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From 5662e5376adcc45da43d7818c8ac1882883c18ac Mon Sep 17 00:00:00 2001
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From: Tyler Baicar <tbaicar@codeaurora.org>
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Date: Tue, 12 Sep 2017 14:58:25 -0600
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Subject: [PATCH 1/2] rasdaemon: add support for ARM events
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Add support to handle the ARM kernel trace events
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which cover RAS ARM processor errors.
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[V4]: fix arm_event_tab usage
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Change-Id: Ife99c97042498d5fad4d9b8e873ecfba6a47947d
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Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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---
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Makefile.am | 3 ++
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configure.ac | 9 ++++++
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ras-arm-handler.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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ras-arm-handler.h | 24 +++++++++++++++
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ras-events.c | 15 ++++++++++
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ras-record.c | 59 ++++++++++++++++++++++++++++++++++++
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ras-record.h | 16 ++++++++++
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ras-report.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++
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ras-report.h | 5 +++-
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9 files changed, 295 insertions(+), 1 deletion(-)
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create mode 100644 ras-arm-handler.c
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create mode 100644 ras-arm-handler.h
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diff --git a/Makefile.am b/Makefile.am
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index 2500772..4aa5543 100644
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--- a/Makefile.am
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+++ b/Makefile.am
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@@ -27,6 +27,9 @@ endif
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if WITH_NON_STANDARD
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rasdaemon_SOURCES += ras-non-standard-handler.c
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endif
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+if WITH_ARM
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+ rasdaemon_SOURCES += ras-arm-handler.c
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+endif
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if WITH_MCE
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rasdaemon_SOURCES += ras-mce-handler.c mce-intel.c mce-amd-k8.c \
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mce-intel-p4-p6.c mce-intel-nehalem.c \
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diff --git a/configure.ac b/configure.ac
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index ecd4b2f..14fc2f2 100644
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--- a/configure.ac
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+++ b/configure.ac
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@@ -53,6 +53,15 @@ AS_IF([test "x$enable_non_standard" = "xyes"], [
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])
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AM_CONDITIONAL([WITH_NON_STANDARD], [test x$enable_non_standard = xyes])
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+AC_ARG_ENABLE([arm],
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+ AS_HELP_STRING([--enable-arm], [enable ARM events (currently experimental)]))
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+
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+AS_IF([test "x$enable_arm" = "xyes"], [
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+ AC_DEFINE(HAVE_ARM,1,"have ARM events collect")
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+ AC_SUBST([WITH_ARM])
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+])
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+AM_CONDITIONAL([WITH_ARM], [test x$enable_arm = xyes])
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+
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AC_ARG_ENABLE([mce],
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AS_HELP_STRING([--enable-mce], [enable MCE events (currently experimental)]))
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diff --git a/ras-arm-handler.c b/ras-arm-handler.c
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new file mode 100644
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index 0000000..a76470d
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--- /dev/null
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+++ b/ras-arm-handler.c
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@@ -0,0 +1,90 @@
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+/*
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+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <stdio.h>
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+#include <stdlib.h>
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+#include <string.h>
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+#include <unistd.h>
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+#include "libtrace/kbuffer.h"
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+#include "ras-arm-handler.h"
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+#include "ras-record.h"
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+#include "ras-logger.h"
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+#include "ras-report.h"
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+
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+int ras_arm_event_handler(struct trace_seq *s,
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+ struct pevent_record *record,
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+ struct event_format *event, void *context)
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+{
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+ unsigned long long val;
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+ struct ras_events *ras = context;
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+ time_t now;
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+ struct tm *tm;
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+ struct ras_arm_event ev;
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+
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+ /*
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+ * Newer kernels (3.10-rc1 or upper) provide an uptime clock.
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+ * On previous kernels, the way to properly generate an event would
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+ * be to inject a fake one, measure its timestamp and diff it against
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+ * gettimeofday. We won't do it here. Instead, let's use uptime,
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+ * falling-back to the event report's time, if "uptime" clock is
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+ * not available (legacy kernels).
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+ */
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+
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+ if (ras->use_uptime)
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+ now = record->ts/user_hz + ras->uptime_diff;
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+ else
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+ now = time(NULL);
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+
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+ tm = localtime(&now;;
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+ if (tm)
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+ strftime(ev.timestamp, sizeof(ev.timestamp),
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+ "%Y-%m-%d %H:%M:%S %z", tm);
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+ trace_seq_printf(s, "%s\n", ev.timestamp);
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+
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+ if (pevent_get_field_val(s, event, "affinity", record, &val, 1) < 0)
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+ return -1;
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+ ev.affinity = val;
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+ trace_seq_printf(s, " affinity: %d", ev.affinity);
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+
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+ if (pevent_get_field_val(s, event, "mpidr", record, &val, 1) < 0)
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+ return -1;
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+ ev.mpidr = val;
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+ trace_seq_printf(s, "\n MPIDR: 0x%llx", (unsigned long long)ev.mpidr);
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+
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+ if (pevent_get_field_val(s, event, "midr", record, &val, 1) < 0)
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+ return -1;
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+ ev.midr = val;
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+ trace_seq_printf(s, "\n MIDR: 0x%llx", (unsigned long long)ev.midr);
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+
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+ if (pevent_get_field_val(s, event, "running_state", record, &val, 1) < 0)
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+ return -1;
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+ ev.running_state = val;
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+ trace_seq_printf(s, "\n running_state: %d", ev.running_state);
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+
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+ if (pevent_get_field_val(s, event, "psci_state", record, &val, 1) < 0)
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+ return -1;
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+ ev.psci_state = val;
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+ trace_seq_printf(s, "\n psci_state: %d", ev.psci_state);
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+
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+ /* Insert data into the SGBD */
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+#ifdef HAVE_SQLITE3
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+ ras_store_arm_record(ras, &ev;;
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+#endif
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+
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+#ifdef HAVE_ABRT_REPORT
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+ /* Report event to ABRT */
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+ ras_report_arm_event(ras, &ev;;
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+#endif
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+
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+ return 0;
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+}
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diff --git a/ras-arm-handler.h b/ras-arm-handler.h
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new file mode 100644
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index 0000000..eae10ec
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--- /dev/null
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+++ b/ras-arm-handler.h
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@@ -0,0 +1,24 @@
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+/*
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+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __RAS_ARM_HANDLER_H
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+#define __RAS_ARM_HANDLER_H
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+
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+#include "ras-events.h"
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+#include "libtrace/event-parse.h"
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+
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+int ras_arm_event_handler(struct trace_seq *s,
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+ struct pevent_record *record,
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+ struct event_format *event, void *context);
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+
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+#endif
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diff --git a/ras-events.c b/ras-events.c
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index 96aa6f1..812d712 100644
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--- a/ras-events.c
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+++ b/ras-events.c
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@@ -30,6 +30,7 @@
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#include "ras-mc-handler.h"
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#include "ras-aer-handler.h"
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#include "ras-non-standard-handler.h"
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+#include "ras-arm-handler.h"
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#include "ras-mce-handler.h"
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#include "ras-extlog-handler.h"
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#include "ras-record.h"
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@@ -213,6 +214,10 @@ int toggle_ras_mc_event(int enable)
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rc |= __toggle_ras_mc_event(ras, "ras", "non_standard_event", enable);
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#endif
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+#ifdef HAVE_ARM
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+ rc |= __toggle_ras_mc_event(ras, "ras", "arm_event", enable);
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+#endif
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+
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free_ras:
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free(ras);
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return rc;
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@@ -691,6 +696,16 @@ int handle_ras_events(int record_events)
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"ras", "non_standard_event");
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#endif
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+#ifdef HAVE_ARM
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+ rc = add_event_handler(ras, pevent, page_size, "ras", "arm_event",
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+ ras_arm_event_handler);
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+ if (!rc)
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+ num_events++;
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+ else
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+ log(ALL, LOG_ERR, "Can't get traces from %s:%s\n",
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+ "ras", "arm_event");
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+#endif
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+
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cpus = get_num_cpus(ras);
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#ifdef HAVE_MCE
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diff --git a/ras-record.c b/ras-record.c
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index 357ab61..c3644cb 100644
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--- a/ras-record.c
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+++ b/ras-record.c
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@@ -209,6 +209,58 @@ int ras_store_non_standard_record(struct ras_events *ras, struct ras_non_standar
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}
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#endif
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+/*
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+ * Table and functions to handle ras:arm
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+ */
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+
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+#ifdef HAVE_ARM
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+static const struct db_fields arm_event_fields[] = {
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+ { .name="id", .type="INTEGER PRIMARY KEY" },
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+ { .name="timestamp", .type="TEXT" },
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+ { .name="error_count", .type="INTEGER" },
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+ { .name="affinity", .type="INTEGER" },
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+ { .name="mpidr", .type="INTEGER" },
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+ { .name="running_state", .type="INTEGER" },
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+ { .name="psci_state", .type="INTEGER" },
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+};
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+
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+static const struct db_table_descriptor arm_event_tab = {
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+ .name = "arm_event",
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+ .fields = arm_event_fields,
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+ .num_fields = ARRAY_SIZE(arm_event_fields),
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+};
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+
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ac32bf |
+int ras_store_arm_record(struct ras_events *ras, struct ras_arm_event *ev)
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+{
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+ int rc;
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+ struct sqlite3_priv *priv = ras->db_priv;
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+
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+ if (!priv || !priv->stmt_arm_record)
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+ return 0;
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+ log(TERM, LOG_INFO, "arm_event store: %p\n", priv->stmt_arm_record);
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+
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+ sqlite3_bind_text (priv->stmt_arm_record, 1, ev->timestamp, -1, NULL);
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+ sqlite3_bind_int (priv->stmt_arm_record, 2, ev->error_count);
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+ sqlite3_bind_int (priv->stmt_arm_record, 3, ev->affinity);
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+ sqlite3_bind_int (priv->stmt_arm_record, 4, ev->mpidr);
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+ sqlite3_bind_int (priv->stmt_arm_record, 5, ev->running_state);
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+ sqlite3_bind_int (priv->stmt_arm_record, 6, ev->psci_state);
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+
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+ rc = sqlite3_step(priv->stmt_arm_record);
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+ if (rc != SQLITE_OK && rc != SQLITE_DONE)
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+ log(TERM, LOG_ERR,
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ac32bf |
+ "Failed to do arm_event step on sqlite: error = %d\n", rc);
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+ rc = sqlite3_reset(priv->stmt_arm_record);
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+ if (rc != SQLITE_OK && rc != SQLITE_DONE)
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+ log(TERM, LOG_ERR,
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ac32bf |
+ "Failed reset arm_event on sqlite: error = %d\n",
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+ rc);
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+ log(TERM, LOG_INFO, "register inserted at db\n");
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+
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+ return rc;
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+}
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+#endif
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+
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#ifdef HAVE_EXTLOG
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static const struct db_fields extlog_event_fields[] = {
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{ .name="id", .type="INTEGER PRIMARY KEY" },
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ac32bf |
@@ -509,6 +561,13 @@ int ras_mc_event_opendb(unsigned cpu, struct ras_events *ras)
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&non_standard_event_tab);
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#endif
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+#ifdef HAVE_ARM
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ac32bf |
+ rc = ras_mc_create_table(priv, &arm_event_tab);
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ac32bf |
+ if (rc == SQLITE_OK)
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|
ac32bf |
+ rc = ras_mc_prepare_stmt(priv, &priv->stmt_arm_record,
|
|
|
ac32bf |
+ &arm_event_tab);
|
|
|
ac32bf |
+#endif
|
|
|
ac32bf |
+
|
|
|
ac32bf |
ras->db_priv = priv;
|
|
|
ac32bf |
return 0;
|
|
|
ac32bf |
}
|
|
|
ac32bf |
diff --git a/ras-record.h b/ras-record.h
|
|
|
ac32bf |
index 473ae40..12c2218 100644
|
|
|
ac32bf |
--- a/ras-record.h
|
|
|
ac32bf |
+++ b/ras-record.h
|
|
|
ac32bf |
@@ -65,10 +65,21 @@ struct ras_non_standard_event {
|
|
|
ac32bf |
uint32_t length;
|
|
|
ac32bf |
};
|
|
|
ac32bf |
|
|
|
ac32bf |
+struct ras_arm_event {
|
|
|
ac32bf |
+ char timestamp[64];
|
|
|
ac32bf |
+ int32_t error_count;
|
|
|
ac32bf |
+ int8_t affinity;
|
|
|
ac32bf |
+ int64_t mpidr;
|
|
|
ac32bf |
+ int64_t midr;
|
|
|
ac32bf |
+ int32_t running_state;
|
|
|
ac32bf |
+ int32_t psci_state;
|
|
|
ac32bf |
+};
|
|
|
ac32bf |
+
|
|
|
ac32bf |
struct ras_mc_event;
|
|
|
ac32bf |
struct ras_aer_event;
|
|
|
ac32bf |
struct ras_extlog_event;
|
|
|
ac32bf |
struct ras_non_standard_event;
|
|
|
ac32bf |
+struct ras_arm_event;
|
|
|
ac32bf |
struct mce_event;
|
|
|
ac32bf |
|
|
|
ac32bf |
#ifdef HAVE_SQLITE3
|
|
|
ac32bf |
@@ -90,6 +101,9 @@ struct sqlite3_priv {
|
|
|
ac32bf |
#ifdef HAVE_NON_STANDARD
|
|
|
ac32bf |
sqlite3_stmt *stmt_non_standard_record;
|
|
|
ac32bf |
#endif
|
|
|
ac32bf |
+#ifdef HAVE_ARM
|
|
|
ac32bf |
+ sqlite3_stmt *stmt_arm_record;
|
|
|
ac32bf |
+#endif
|
|
|
ac32bf |
};
|
|
|
ac32bf |
|
|
|
ac32bf |
int ras_mc_event_opendb(unsigned cpu, struct ras_events *ras);
|
|
|
ac32bf |
@@ -98,6 +112,7 @@ int ras_store_aer_event(struct ras_events *ras, struct ras_aer_event *ev);
|
|
|
ac32bf |
int ras_store_mce_record(struct ras_events *ras, struct mce_event *ev);
|
|
|
ac32bf |
int ras_store_extlog_mem_record(struct ras_events *ras, struct ras_extlog_event *ev);
|
|
|
ac32bf |
int ras_store_non_standard_record(struct ras_events *ras, struct ras_non_standard_event *ev);
|
|
|
ac32bf |
+int ras_store_arm_record(struct ras_events *ras, struct ras_arm_event *ev);
|
|
|
ac32bf |
|
|
|
ac32bf |
#else
|
|
|
ac32bf |
static inline int ras_mc_event_opendb(unsigned cpu, struct ras_events *ras) { return 0; };
|
|
|
ac32bf |
@@ -106,6 +121,7 @@ static inline int ras_store_aer_event(struct ras_events *ras, struct ras_aer_eve
|
|
|
ac32bf |
static inline int ras_store_mce_record(struct ras_events *ras, struct mce_event *ev) { return 0; };
|
|
|
ac32bf |
static inline int ras_store_extlog_mem_record(struct ras_events *ras, struct ras_extlog_event *ev) { return 0; };
|
|
|
ac32bf |
static inline int ras_store_non_standard_record(struct ras_events *ras, struct ras_non_standard_event *ev) { return 0; };
|
|
|
ac32bf |
+static inline int ras_store_arm_record(struct ras_events *ras, struct ras_arm_event *ev) { return 0; };
|
|
|
ac32bf |
|
|
|
ac32bf |
#endif
|
|
|
ac32bf |
|
|
|
ac32bf |
diff --git a/ras-report.c b/ras-report.c
|
|
|
ac32bf |
index 1eb9f79..d4beee0 100644
|
|
|
ac32bf |
--- a/ras-report.c
|
|
|
ac32bf |
+++ b/ras-report.c
|
|
|
ac32bf |
@@ -228,6 +228,33 @@ static int set_non_standard_event_backtrace(char *buf, struct ras_non_standard_e
|
|
|
ac32bf |
return 0;
|
|
|
ac32bf |
}
|
|
|
ac32bf |
|
|
|
ac32bf |
+static int set_arm_event_backtrace(char *buf, struct ras_arm_event *ev){
|
|
|
ac32bf |
+ char bt_buf[MAX_BACKTRACE_SIZE];
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ if(!buf || !ev)
|
|
|
ac32bf |
+ return -1;
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ sprintf(bt_buf, "BACKTRACE=" \
|
|
|
ac32bf |
+ "timestamp=%s\n" \
|
|
|
ac32bf |
+ "error_count=%d\n" \
|
|
|
ac32bf |
+ "affinity=%d\n" \
|
|
|
ac32bf |
+ "mpidr=0x%lx\n" \
|
|
|
ac32bf |
+ "midr=0x%lx\n" \
|
|
|
ac32bf |
+ "running_state=%d\n" \
|
|
|
ac32bf |
+ "psci_state=%d\n", \
|
|
|
ac32bf |
+ ev->timestamp, \
|
|
|
ac32bf |
+ ev->error_count, \
|
|
|
ac32bf |
+ ev->affinity, \
|
|
|
ac32bf |
+ ev->mpidr, \
|
|
|
ac32bf |
+ ev->midr, \
|
|
|
ac32bf |
+ ev->running_state, \
|
|
|
ac32bf |
+ ev->psci_state);
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ strcat(buf, bt_buf);
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ return 0;
|
|
|
ac32bf |
+}
|
|
|
ac32bf |
+
|
|
|
ac32bf |
static int commit_report_backtrace(int sockfd, int type, void *ev){
|
|
|
ac32bf |
char buf[MAX_BACKTRACE_SIZE];
|
|
|
ac32bf |
char *pbuf = buf;
|
|
|
ac32bf |
@@ -253,6 +280,9 @@ static int commit_report_backtrace(int sockfd, int type, void *ev){
|
|
|
ac32bf |
case NON_STANDARD_EVENT:
|
|
|
ac32bf |
rc = set_non_standard_event_backtrace(buf, (struct ras_non_standard_event *)ev);
|
|
|
ac32bf |
break;
|
|
|
ac32bf |
+ case ARM_EVENT:
|
|
|
ac32bf |
+ rc = set_arm_event_backtrace(buf, (struct ras_arm_event *)ev);
|
|
|
ac32bf |
+ break;
|
|
|
ac32bf |
default:
|
|
|
ac32bf |
return -1;
|
|
|
ac32bf |
}
|
|
|
ac32bf |
@@ -425,6 +455,51 @@ non_standard_fail:
|
|
|
ac32bf |
return rc;
|
|
|
ac32bf |
}
|
|
|
ac32bf |
|
|
|
ac32bf |
+int ras_report_arm_event(struct ras_events *ras, struct ras_arm_event *ev){
|
|
|
ac32bf |
+ char buf[MAX_MESSAGE_SIZE];
|
|
|
ac32bf |
+ int sockfd = 0;
|
|
|
ac32bf |
+ int rc = -1;
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ memset(buf, 0, sizeof(buf));
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ sockfd = setup_report_socket();
|
|
|
ac32bf |
+ if(sockfd < 0){
|
|
|
ac32bf |
+ return rc;
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ rc = commit_report_basic(sockfd);
|
|
|
ac32bf |
+ if(rc < 0){
|
|
|
ac32bf |
+ goto arm_fail;
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ rc = commit_report_backtrace(sockfd, ARM_EVENT, ev);
|
|
|
ac32bf |
+ if(rc < 0){
|
|
|
ac32bf |
+ goto arm_fail;
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ sprintf(buf, "ANALYZER=%s", "rasdaemon-arm");
|
|
|
ac32bf |
+ rc = write(sockfd, buf, strlen(buf) + 1);
|
|
|
ac32bf |
+ if(rc < strlen(buf) + 1){
|
|
|
ac32bf |
+ goto arm_fail;
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ sprintf(buf, "REASON=%s", "ARM CPU report problem");
|
|
|
ac32bf |
+ rc = write(sockfd, buf, strlen(buf) + 1);
|
|
|
ac32bf |
+ if(rc < strlen(buf) + 1){
|
|
|
ac32bf |
+ goto arm_fail;
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ rc = 0;
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+arm_fail:
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ if(sockfd > 0){
|
|
|
ac32bf |
+ close(sockfd);
|
|
|
ac32bf |
+ }
|
|
|
ac32bf |
+
|
|
|
ac32bf |
+ return rc;
|
|
|
ac32bf |
+}
|
|
|
ac32bf |
+
|
|
|
ac32bf |
int ras_report_mce_event(struct ras_events *ras, struct mce_event *ev){
|
|
|
ac32bf |
char buf[MAX_MESSAGE_SIZE];
|
|
|
ac32bf |
int sockfd = 0;
|
|
|
ac32bf |
diff --git a/ras-report.h b/ras-report.h
|
|
|
ac32bf |
index c2fcf42..6c466f5 100644
|
|
|
ac32bf |
--- a/ras-report.h
|
|
|
ac32bf |
+++ b/ras-report.h
|
|
|
ac32bf |
@@ -33,7 +33,8 @@ enum {
|
|
|
ac32bf |
MC_EVENT,
|
|
|
ac32bf |
MCE_EVENT,
|
|
|
ac32bf |
AER_EVENT,
|
|
|
ac32bf |
- NON_STANDARD_EVENT
|
|
|
ac32bf |
+ NON_STANDARD_EVENT,
|
|
|
ac32bf |
+ ARM_EVENT
|
|
|
ac32bf |
};
|
|
|
ac32bf |
|
|
|
ac32bf |
#ifdef HAVE_ABRT_REPORT
|
|
|
ac32bf |
@@ -42,6 +43,7 @@ int ras_report_mc_event(struct ras_events *ras, struct ras_mc_event *ev);
|
|
|
ac32bf |
int ras_report_aer_event(struct ras_events *ras, struct ras_aer_event *ev);
|
|
|
ac32bf |
int ras_report_mce_event(struct ras_events *ras, struct mce_event *ev);
|
|
|
ac32bf |
int ras_report_non_standard_event(struct ras_events *ras, struct ras_non_standard_event *ev);
|
|
|
ac32bf |
+int ras_report_arm_event(struct ras_events *ras, struct ras_arm_event *ev);
|
|
|
ac32bf |
|
|
|
ac32bf |
#else
|
|
|
ac32bf |
|
|
|
ac32bf |
@@ -49,6 +51,7 @@ static inline int ras_report_mc_event(struct ras_events *ras, struct ras_mc_even
|
|
|
ac32bf |
static inline int ras_report_aer_event(struct ras_events *ras, struct ras_aer_event *ev) { return 0; };
|
|
|
ac32bf |
static inline int ras_report_mce_event(struct ras_events *ras, struct mce_event *ev) { return 0; };
|
|
|
ac32bf |
static inline int ras_report_non_standard_event(struct ras_events *ras, struct ras_non_standard_event *ev) { return 0; };
|
|
|
ac32bf |
+static inline int ras_report_arm_event(struct ras_events *ras, struct ras_arm_event *ev) { return 0; };
|
|
|
ac32bf |
|
|
|
ac32bf |
#endif
|
|
|
ac32bf |
|
|
|
ac32bf |
--
|
|
|
ac32bf |
1.8.3.1
|
|
|
ac32bf |
|