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From 66588d01b8cb710d746c249a34f31f7f353bc697 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Sat, 22 Sep 2012 23:08:38 +0200
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Subject: [PATCH] tcg/mips: fix MIPS32(R2) detection
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Fix the MIPS32(R2) cpu detection so that it also works with
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-march=octeon. Thanks to Andrew Pinski for the hint.
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Cc: Andrew Pinski <apinski@cavium.com>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/mips/tcg-target.c | 10 +++++-----
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tcg/mips/tcg-target.h | 8 ++++----
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2 files changed, 9 insertions(+), 9 deletions(-)
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diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
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index c272b38..e9a1ffb 100644
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--- a/tcg/mips/tcg-target.c
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+++ b/tcg/mips/tcg-target.c
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@@ -425,7 +425,7 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
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static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
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{
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-#ifdef _MIPS_ARCH_MIPS32R2
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+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
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#else
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/* ret and arg can't be register at */
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@@ -442,7 +442,7 @@ static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
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static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
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{
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-#ifdef _MIPS_ARCH_MIPS32R2
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+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
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tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
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#else
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@@ -460,7 +460,7 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
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static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
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{
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-#ifdef _MIPS_ARCH_MIPS32R2
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+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
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tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
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#else
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@@ -486,7 +486,7 @@ static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
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static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
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{
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-#ifdef _MIPS_ARCH_MIPS32R2
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+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg);
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#else
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tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
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@@ -496,7 +496,7 @@ static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
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static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
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{
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-#ifdef _MIPS_ARCH_MIPS32R2
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+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg);
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#else
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tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16);
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diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
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index d147e70..7020d65 100644
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--- a/tcg/mips/tcg-target.h
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+++ b/tcg/mips/tcg-target.h
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@@ -88,16 +88,16 @@ typedef enum {
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#define TCG_TARGET_HAS_nand_i32 0
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/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
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-#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \
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- defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \
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- defined(_MIPS_ARCH_LOONGSON2F)
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+#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
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+ defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
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+ defined(_MIPS_ARCH_MIPS4)
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#define TCG_TARGET_HAS_movcond_i32 1
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#else
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#define TCG_TARGET_HAS_movcond_i32 0
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#endif
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/* optional instructions only implemented on MIPS32R2 */
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-#ifdef _MIPS_ARCH_MIPS32R2
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+#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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--
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1.7.12.1
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