From 0d087d9d5276866b7a7c17cdb23e71b5636dc529 Mon Sep 17 00:00:00 2001

From: Paolo Bonzini <pbonzini@redhat.com>

Date: Fri, 22 Nov 2019 11:53:43 +0000

Subject: [PATCH 10/16] vmxcap: correct the name of the variables

RH-Author: Paolo Bonzini <pbonzini@redhat.com>

Message-id: <20191122115348.25000-11-pbonzini@redhat.com>

Patchwork-id: 92607

O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 10/15] vmxcap: correct the name of the variables

Bugzilla: 1689270

RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>

RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>

The low bits are 1 if the control must be one, the high bits

are 1 if the control can be one.  Correct the variable names

as they are very confusing.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

(cherry picked from commit 49d51b8927a9ea7267f4677a2e92f5046ce74025)

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 scripts/kvm/vmxcap | 14 +++++++-------

 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap

index 99a8146..2db6832 100755

--- a/scripts/kvm/vmxcap

+++ b/scripts/kvm/vmxcap

@@ -51,15 +51,15 @@ class Control(object):

         return (val & 0xffffffff, val >> 32)

     def show(self):

         print(self.name)

-        mbz, mb1 = self.read2(self.cap_msr)

-        tmbz, tmb1 = 0, 0

+        mb1, cb1 = self.read2(self.cap_msr)

+        tmb1, tcb1 = 0, 0

         if self.true_cap_msr:

-            tmbz, tmb1 = self.read2(self.true_cap_msr)

+            tmb1, tcb1 = self.read2(self.true_cap_msr)

         for bit in sorted(self.bits.keys()):

-            zero = not (mbz & (1 << bit))

-            one = mb1 & (1 << bit)

-            true_zero = not (tmbz & (1 << bit))

-            true_one = tmb1 & (1 << bit)

+            zero = not (mb1 & (1 << bit))

+            one = cb1 & (1 << bit)

+            true_zero = not (tmb1 & (1 << bit))

+            true_one = tcb1 & (1 << bit)

             s= '?'

             if (self.true_cap_msr and true_zero and true_one

                 and one and not zero):

-- 

1.8.3.1