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From f83115d485ef395b751b8d25b56917cf7630d63d Mon Sep 17 00:00:00 2001
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From: Peter Xu <peterx@redhat.com>
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Date: Thu, 8 Nov 2018 06:29:34 +0000
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Subject: [PATCH 06/35] intel-iommu: replace more vtd_err_* traces
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Peter Xu <peterx@redhat.com>
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Message-id: <20181108062938.21143-4-peterx@redhat.com>
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Patchwork-id: 82962
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O-Subject: [RHEL-8 qemu-kvm PATCH 3/7] intel-iommu: replace more vtd_err_* traces
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Bugzilla: 1625173
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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Bugzilla: 1625173
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Replace all the trace_vtd_err_*() hooks with the new error_report_once()
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since they are similar to trace_vtd_err() - dumping the first error
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would be mostly enough, then we have them on by default too.
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Message-Id: <20180815095328.32414-4-peterx@redhat.com>
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[Use "%x" instead of "%" PRIx16 to print uint16_t, whitespace tidied up]
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Signed-off-by: Markus Armbruster <armbru@redhat.com>
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(cherry picked from commit 4e4abd111a2af0179a4467368d695958844bf113)
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Signed-off-by: Peter Xu <peterx@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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hw/i386/intel_iommu.c | 64 ++++++++++++++++++++++++++++++++++++---------------
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hw/i386/trace-events | 12 ----------
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2 files changed, 46 insertions(+), 30 deletions(-)
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diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
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index ab11cc4..aab86e9 100644
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--- a/hw/i386/intel_iommu.c
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+++ b/hw/i386/intel_iommu.c
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@@ -705,7 +705,8 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
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uint64_t access_right_check;
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if (!vtd_iova_range_check(iova, ce, aw_bits)) {
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- trace_vtd_err_dmar_iova_overflow(iova);
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+ error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64 ")",
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+ __func__, iova);
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return -VTD_FR_ADDR_BEYOND_MGAW;
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}
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@@ -717,7 +718,8 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
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slpte = vtd_get_slpte(addr, offset);
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if (slpte == (uint64_t)-1) {
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- trace_vtd_err_dmar_slpte_read_error(iova, level);
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+ error_report_once("%s: detected read error on DMAR slpte "
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+ "(iova=0x%" PRIx64 ")", __func__, iova);
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if (level == vtd_ce_get_level(ce)) {
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/* Invalid programming of context-entry */
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return -VTD_FR_CONTEXT_ENTRY_INV;
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@@ -728,11 +730,17 @@ static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
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*reads = (*reads) && (slpte & VTD_SL_R);
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*writes = (*writes) && (slpte & VTD_SL_W);
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if (!(slpte & access_right_check)) {
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- trace_vtd_err_dmar_slpte_perm_error(iova, level, slpte, is_write);
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+ error_report_once("%s: detected slpte permission error "
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+ "(iova=0x%" PRIx64 ", level=0x%" PRIx32 ", "
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+ "slpte=0x%" PRIx64 ", write=%d)", __func__,
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+ iova, level, slpte, is_write);
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return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
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}
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if (vtd_slpte_nonzero_rsvd(slpte, level)) {
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- trace_vtd_err_dmar_slpte_resv_error(iova, level, slpte);
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+ error_report_once("%s: detected splte reserve non-zero "
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+ "iova=0x%" PRIx64 ", level=0x%" PRIx32
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+ "slpte=0x%" PRIx64 ")", __func__, iova,
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+ level, slpte);
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return -VTD_FR_PAGING_ENTRY_RSVD;
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}
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@@ -1697,7 +1705,10 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
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/* Ok - report back to driver */
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vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
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} else {
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- trace_vtd_err_qi_disable(s->iq_head, s->iq_tail, s->iq_last_desc_type);
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+ error_report_once("%s: detected improper state when disable QI "
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+ "(head=0x%x, tail=0x%x, last_type=%d)",
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+ __func__,
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+ s->iq_head, s->iq_tail, s->iq_last_desc_type);
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}
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}
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}
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@@ -2094,7 +2105,9 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s)
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if (s->iq_tail >= s->iq_size) {
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/* Detects an invalid Tail pointer */
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- trace_vtd_err_qi_tail(s->iq_tail, s->iq_size);
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+ error_report_once("%s: detected invalid QI tail "
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+ "(tail=0x%x, size=0x%x)",
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+ __func__, s->iq_tail, s->iq_size);
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vtd_handle_inv_queue_error(s);
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return;
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}
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@@ -2507,10 +2520,12 @@ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
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iotlb.iova, iotlb.translated_addr,
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iotlb.addr_mask);
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} else {
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- trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus),
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- VTD_PCI_SLOT(vtd_as->devfn),
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- VTD_PCI_FUNC(vtd_as->devfn),
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- iotlb.iova);
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+ error_report_once("%s: detected translation failure "
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+ "(dev=%02x:%02x:%02x, iova=0x%" PRIx64 ")",
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+ __func__, pci_bus_num(vtd_as->bus),
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+ VTD_PCI_SLOT(vtd_as->devfn),
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+ VTD_PCI_FUNC(vtd_as->devfn),
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+ iotlb.iova);
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}
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return iotlb;
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@@ -2626,15 +2641,19 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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le64_to_cpu(entry->data[0]));
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if (!entry->irte.present) {
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- trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
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- le64_to_cpu(entry->data[0]));
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+ error_report_once("%s: detected non-present IRTE "
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+ "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
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+ __func__, index, le64_to_cpu(entry->data[1]),
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+ le64_to_cpu(entry->data[0]));
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return -VTD_FR_IR_ENTRY_P;
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}
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if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
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entry->irte.__reserved_2) {
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- trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
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- le64_to_cpu(entry->data[0]));
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+ error_report_once("%s: detected non-zero reserved IRTE "
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+ "(index=%u, high=0x%" PRIx64 ", low=0x%" PRIx64 ")",
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+ __func__, index, le64_to_cpu(entry->data[1]),
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+ le64_to_cpu(entry->data[0]));
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return -VTD_FR_IR_IRTE_RSVD;
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}
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@@ -2648,7 +2667,9 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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case VTD_SVT_ALL:
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mask = vtd_svt_mask[entry->irte.sid_q];
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if ((source_id & mask) != (sid & mask)) {
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- trace_vtd_err_irte_sid(index, sid, source_id);
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+ error_report_once("%s: invalid IRTE SID "
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+ "(index=%u, sid=%u, source_id=%u)",
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+ __func__, index, sid, source_id);
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return -VTD_FR_IR_SID_ERR;
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}
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break;
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@@ -2658,13 +2679,17 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
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bus_min = source_id & 0xff;
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bus = sid >> 8;
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if (bus > bus_max || bus < bus_min) {
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- trace_vtd_err_irte_sid_bus(index, bus, bus_min, bus_max);
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+ error_report_once("%s: invalid SVT_BUS "
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+ "(index=%u, bus=%u, min=%u, max=%u)",
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+ __func__, index, bus, bus_min, bus_max);
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return -VTD_FR_IR_SID_ERR;
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}
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break;
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default:
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- trace_vtd_err_irte_svt(index, entry->irte.sid_vtype);
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+ error_report_once("%s: detected invalid IRTE SVT "
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+ "(index=%u, type=%d)", __func__,
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+ index, entry->irte.sid_vtype);
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/* Take this as verification failure. */
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return -VTD_FR_IR_SID_ERR;
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break;
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@@ -2786,7 +2811,10 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
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if (addr.addr.sub_valid) {
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trace_vtd_ir_remap_type("MSI");
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if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
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- trace_vtd_err_ir_msi_invalid(sid, origin->address, origin->data);
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+ error_report_once("%s: invalid IR MSI "
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+ "(sid=%u, address=0x%" PRIx64
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+ ", data=0x%" PRIx32 ")",
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+ __func__, sid, origin->address, origin->data);
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return -VTD_FR_IR_REQ_RSVD;
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}
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} else {
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diff --git a/hw/i386/trace-events b/hw/i386/trace-events
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index 922431b..9e6fc4d 100644
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--- a/hw/i386/trace-events
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+++ b/hw/i386/trace-events
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@@ -69,19 +69,7 @@ vtd_ir_remap_msi_req(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" data 0x%"PR
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vtd_fsts_ppf(bool set) "FSTS PPF bit set to %d"
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vtd_fsts_clear_ip(void) ""
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vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64" low 0x%"PRIx64
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-vtd_err_dmar_iova_overflow(uint64_t iova) "iova 0x%"PRIx64
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-vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" level %d"
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-vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bool is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d"
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-vtd_err_dmar_slpte_resv_error(uint64_t iova, int level, uint64_t slpte) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64
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-vtd_err_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova) "dev %02x:%02x.%02x iova 0x%"PRIx64
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vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16
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-vtd_err_qi_disable(uint16_t head, uint16_t tail, int type) "head 0x%"PRIx16" tail 0x%"PRIx16" last_desc_type %d"
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-vtd_err_qi_tail(uint16_t tail, uint16_t size) "tail 0x%"PRIx16" size 0x%"PRIx16
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-vtd_err_irte(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64
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-vtd_err_irte_sid(int index, uint16_t req, uint16_t target) "index %d SVT_ALL sid 0x%"PRIx16" (should be: 0x%"PRIx16")"
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-vtd_err_irte_sid_bus(int index, uint8_t bus, uint8_t min, uint8_t max) "index %d SVT_BUS bus 0x%"PRIx8" (should be: 0x%"PRIx8"-0x%"PRIx8")"
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-vtd_err_irte_svt(int index, int type) "index %d SVT type %d"
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-vtd_err_ir_msi_invalid(uint16_t sid, uint64_t addr, uint64_t data) "sid 0x%"PRIx16" addr 0x%"PRIx64" data 0x%"PRIx64
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vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"PRIx16" index %d vec %d (should be: %d)"
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vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x%"PRIx16" index %d trigger %d (should be: %d)"
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--
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1.8.3.1
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