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From 12623687c4bd5eeb5b3ca8f23cf3b646357e2bc3 Mon Sep 17 00:00:00 2001
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From: Marcelo Tosatti <mtosatti@redhat.com>
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Date: Tue, 20 Aug 2013 21:42:24 +0200
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Subject: [PATCH 25/28] kvm: i386: fix LAPIC TSC deadline timer save/restore
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RH-Author: Marcelo Tosatti <mtosatti@redhat.com>
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Message-id: <20130820214224.GA9334@amt.cnet>
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Patchwork-id: 53623
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O-Subject: [RHEL7 qemu-kvm PATCH] kvm: i386: fix LAPIC TSC deadline timer save/restore
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Bugzilla: 972433
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Gleb Natapov <gleb@redhat.com>
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BZ: 972433
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commit 7477cd3897082d2650d520a4e9aa7f8affa3dd5d of uq/master branch
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of qemu-kvm.git repository
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The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on:
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- APIC LVT Timer register.
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- TSC value.
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Change the order to respect the dependency.
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Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target-i386/kvm.c | 29 ++++++++++++++++++++++++++---
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1 files changed, 26 insertions(+), 3 deletions(-)
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index 8da6a0d..c5a9416 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -1042,6 +1042,26 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
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entry->data = value;
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}
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+static int kvm_put_tscdeadline_msr(X86CPU *cpu)
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+{
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+ CPUX86State *env = &cpu->env;
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+ struct {
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+ struct kvm_msrs info;
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+ struct kvm_msr_entry entries[1];
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+ } msr_data;
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+ struct kvm_msr_entry *msrs = msr_data.entries;
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+
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+ if (!has_msr_tsc_deadline) {
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+ return 0;
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+ }
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+
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+ kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
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+
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+ msr_data.info.nmsrs = 1;
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+
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+ return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
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+}
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+
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static int kvm_put_msrs(X86CPU *cpu, int level)
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{
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CPUX86State *env = &cpu->env;
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@@ -1065,9 +1085,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_tsc_adjust) {
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kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
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}
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- if (has_msr_tsc_deadline) {
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- kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
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- }
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if (has_msr_misc_enable) {
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
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env->msr_ia32_misc_enable);
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@@ -1705,6 +1722,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level)
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return ret;
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}
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}
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+
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+ ret = kvm_put_tscdeadline_msr(x86_cpu);
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+ if (ret < 0) {
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+ return ret;
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+ }
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+
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ret = kvm_put_vcpu_events(x86_cpu, level);
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if (ret < 0) {
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return ret;
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--
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1.7.1
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