From 0a8e2990b83c805fc6cc2421950a938caa9ba8a5 Mon Sep 17 00:00:00 2001

From: "plai@redhat.com" <plai@redhat.com>

Date: Wed, 3 Apr 2019 15:54:29 +0100

Subject: [PATCH 05/10] i386: Add new CPU model Icelake-{Server, Client}

RH-Author: plai@redhat.com

Message-id: <1554306874-28796-6-git-send-email-plai@redhat.com>

Patchwork-id: 85383

O-Subject: [RHEL8.1 qemu-kvm PATCH resend 05/10] i386: Add new CPU model Icelake-{Server, Client}

Bugzilla: 1561761

RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>

RH-Acked-by: Igor Mammedov <imammedo@redhat.com>

RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>

From: Robert Hoo <robert.hu@linux.intel.com>

New CPU models mostly inherit features from ancestor Skylake, while addin new

features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD,

AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG),

Intel PT and 5-level paging (Server only). As well as

IA32_PRED_CMD, SSBD support for speculative execution

side channel mitigations.

Note:

For 5-level paging, Guest physical address width can be configured, with

parameter "phys-bits". Unless explicitly specified, we still use its default

value, even for Icelake-Server cpu model.

At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR

actually presents more than 1 'feature', maintainers are considering expanding current

features presentation of only CPUIDs to MSR bits; 2) a reasonable default value

for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully

beyond Icelake CPU model itself but fundamental. So split these work apart

and do it later.

https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html

https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html

Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>

Message-Id: <1530781798-183214-6-git-send-email-robert.hu@linux.intel.com>

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

(cherry picked from commit 8a11c62da9146dd89aee98947e6bd831e65a970d)

Signed-off-by: Paul Lai <plai@redhat.com>

Resovled Conflicts:

	target/i386/cpu.c

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 target/i386/cpu.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++++

 1 file changed, 115 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c

index 8b9a9f6..d86b744 100644

--- a/target/i386/cpu.c

+++ b/target/i386/cpu.c

@@ -2414,6 +2414,121 @@ static X86CPUDefinition builtin_x86_defs[] = {

         .model_id = "Intel Xeon Processor (Skylake, IBRS)",

     },

     {

+        .name = "Icelake-Client",

+        .level = 0xd,

+        .vendor = CPUID_VENDOR_INTEL,

+        .family = 6,

+        .model = 126,

+        .stepping = 0,

+        .features[FEAT_1_EDX] =

+            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |

+            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |

+            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |

+            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |

+            CPUID_DE | CPUID_FP87,

+        .features[FEAT_1_ECX] =

+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |

+            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |

+            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |

+            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |

+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |

+            CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,

+        .features[FEAT_8000_0001_EDX] =

+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |

+            CPUID_EXT2_SYSCALL,

+        .features[FEAT_8000_0001_ECX] =

+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

+        .features[FEAT_8000_0008_EBX] =

+            CPUID_8000_0008_EBX_WBNOINVD,

+        .features[FEAT_7_0_EBX] =

+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |

+            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |

+            CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,

+        .features[FEAT_7_0_ECX] =

+            CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |

+            CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |

+            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |

+            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |

+            CPUID_7_0_ECX_AVX512_VPOPCNTDQ,

+        .features[FEAT_7_0_EDX] =

+            CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,

+        /* Missing: XSAVES (not supported by some Linux versions,

+                * including v4.1 to v4.12).

+                * KVM doesn't yet expose any XSAVES state save component,

+                * and the only one defined in Skylake (processor tracing)

+                * probably will block migration anyway.

+                */

+        .features[FEAT_XSAVE] =

+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |

+            CPUID_XSAVE_XGETBV1,

+        .features[FEAT_6_EAX] =

+            CPUID_6_EAX_ARAT,

+        .xlevel = 0x80000008,

+        .model_id = "Intel Core Processor (Icelake)",

+    },

+    {

+        .name = "Icelake-Server",

+        .level = 0xd,

+        .vendor = CPUID_VENDOR_INTEL,

+        .family = 6,

+        .model = 134,

+        .stepping = 0,

+        .features[FEAT_1_EDX] =

+            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |

+            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |

+            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |

+            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |

+            CPUID_DE | CPUID_FP87,

+        .features[FEAT_1_ECX] =

+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |

+            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |

+            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |

+            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |

+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |

+            CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,

+        .features[FEAT_8000_0001_EDX] =

+            CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |

+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,

+        .features[FEAT_8000_0001_ECX] =

+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,

+        .features[FEAT_8000_0008_EBX] =

+            CPUID_8000_0008_EBX_WBNOINVD,

+        .features[FEAT_7_0_EBX] =

+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |

+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |

+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |

+            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |

+            CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |

+            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |

+            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |

+            CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |

+            CPUID_7_0_EBX_INTEL_PT,

+        .features[FEAT_7_0_ECX] =

+            CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |

+            CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |

+            CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |

+            CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |

+            CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,

+        .features[FEAT_7_0_EDX] =

+            CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |

+            CPUID_7_0_EDX_SPEC_CTRL_SSBD,

+        /* Missing: XSAVES (not supported by some Linux versions,

+                * including v4.1 to v4.12).

+                * KVM doesn't yet expose any XSAVES state save component,

+                * and the only one defined in Skylake (processor tracing)

+                * probably will block migration anyway.

+                */

+        .features[FEAT_XSAVE] =

+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |

+            CPUID_XSAVE_XGETBV1,

+        .features[FEAT_6_EAX] =

+            CPUID_6_EAX_ARAT,

+        .xlevel = 0x80000008,

+        .model_id = "Intel Xeon Processor (Icelake)",

+    },

+    {

         .name = "Opteron_G1",

         .level = 5,

         .vendor = CPUID_VENDOR_AMD,

-- 

1.8.3.1