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From 1bee5a77b3f999d2933a440021737d0720b32269 Mon Sep 17 00:00:00 2001
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From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
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Date: Wed, 29 Jul 2020 18:56:21 -0400
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Subject: [PATCH 1/4] i386: Add 2nd Generation AMD EPYC processors
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RH-Author: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Message-id: <20200729185621.152427-2-dgilbert@redhat.com>
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Patchwork-id: 98078
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O-Subject: [RHEL-8.3.0 qemu-kvm PATCH 1/1] i386: Add 2nd Generation AMD EPYC processors
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Bugzilla: 1780385
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RH-Acked-by: Danilo de Paula <ddepaula@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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From: "Moger, Babu" <Babu.Moger@amd.com>
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Adds the support for 2nd Gen AMD EPYC Processors. The model display
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name will be EPYC-Rome.
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Adds the following new feature bits on top of the feature bits from the
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first generation EPYC models.
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perfctr-core : core performance counter extensions support. Enables the VM to
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use extended performance counter support. It enables six
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programmable counters instead of four counters.
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clzero : instruction zeroes out the 64 byte cache line specified in RAX.
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xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
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pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
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pointers.
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wbnoinvd : Write back and do not invalidate cache
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ibpb : Indirect Branch Prediction Barrier
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amd-stibp : Single Thread Indirect Branch Predictor
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clwb : Cache Line Write Back and Retain
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xsaves : XSAVES, XRSTORS and IA32_XSS support
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rdpid : Read Processor ID instruction support
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umip : User-Mode Instruction Prevention support
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The Reference documents are available at
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https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
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https://www.amd.com/system/files/TechDocs/24594.pdf
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Depends on following kernel commits:
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40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
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504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
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6d61e3c32248 ("kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID")
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52297436199d ("kvm: svm: Update svm_xsaves_supported")
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Message-Id: <157314966312.23828.17684821666338093910.stgit@naples-babu.amd.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit 143c30d4d346831a09e59e9af45afdca0331e819)
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 102 +++++++++++++++++++++++++++++++++++++++++++++-
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target/i386/cpu.h | 2 +
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2 files changed, 103 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index a343de0c9d..ff39fc9905 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1133,7 +1133,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"clzero", NULL, "xsaveerptr", NULL,
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NULL, NULL, NULL, NULL,
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NULL, "wbnoinvd", NULL, NULL,
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- "ibpb", NULL, NULL, NULL,
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+ "ibpb", NULL, NULL, "amd-stibp",
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
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@@ -1803,6 +1803,56 @@ static CPUCaches epyc_cache_info = {
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},
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};
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+static CPUCaches epyc_rome_cache_info = {
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+ .l1d_cache = &(CPUCacheInfo) {
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+ .type = DATA_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l1i_cache = &(CPUCacheInfo) {
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+ .type = INSTRUCTION_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l2_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 2,
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+ .size = 512 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 1024,
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+ .lines_per_tag = 1,
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+ },
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+ .l3_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 3,
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+ .size = 16 * MiB,
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+ .line_size = 64,
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+ .associativity = 16,
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+ .partitions = 1,
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+ .sets = 16384,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .inclusive = true,
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+ .complex_indexing = true,
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+ },
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+};
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+
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/* The following VMX features are not supported by KVM and are left out in the
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* CPU definitions:
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*
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@@ -4024,6 +4074,56 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "Hygon Dhyana Processor",
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.cache_info = &epyc_cache_info,
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},
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+ {
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+ .name = "EPYC-Rome",
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+ .level = 0xd,
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+ .vendor = CPUID_VENDOR_AMD,
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+ .family = 23,
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+ .model = 49,
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+ .stepping = 0,
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+ .features[FEAT_1_EDX] =
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+ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
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+ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
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+ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
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+ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
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+ CPUID_VME | CPUID_FP87,
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+ .features[FEAT_1_ECX] =
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+ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
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+ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
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+ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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+ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
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+ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
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+ .features[FEAT_8000_0001_EDX] =
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+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
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+ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
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+ CPUID_EXT2_SYSCALL,
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+ .features[FEAT_8000_0001_ECX] =
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+ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
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+ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
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+ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
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+ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
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+ .features[FEAT_8000_0008_EBX] =
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+ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
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+ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
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+ CPUID_8000_0008_EBX_STIBP,
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+ .features[FEAT_7_0_EBX] =
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+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
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+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
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+ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
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+ CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
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+ .features[FEAT_7_0_ECX] =
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+ CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
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+ .features[FEAT_XSAVE] =
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+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
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+ .features[FEAT_6_EAX] =
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+ CPUID_6_EAX_ARAT,
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+ .features[FEAT_SVM] =
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+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
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+ .xlevel = 0x8000001E,
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+ .model_id = "AMD EPYC-Rome Processor",
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+ .cache_info = &epyc_rome_cache_info,
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+ },
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};
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/* KVM-specific features that are automatically added/removed
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 7bfbf2a5e5..f3da25cb8a 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -792,6 +792,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
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/* Indirect Branch Prediction Barrier */
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#define CPUID_8000_0008_EBX_IBPB (1U << 12)
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+/* Single Thread Indirect Branch Predictors */
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+#define CPUID_8000_0008_EBX_STIBP (1U << 15)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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--
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2.27.0
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