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From c4ae2dbb8ee406f0a015b35fb76b3d6d131900d6 Mon Sep 17 00:00:00 2001
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From: eperezma <eperezma@redhat.com>
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Date: Tue, 12 Jan 2021 14:36:31 -0500
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Subject: [PATCH 07/17] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: eperezma <eperezma@redhat.com>
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Message-id: <20210112143638.374060-7-eperezma@redhat.com>
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Patchwork-id: 100599
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O-Subject: [RHEL-8.4.0 qemu-kvm PATCH v2 06/13] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper
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Bugzilla: 1843852
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RH-Acked-by: Xiao Wang <jasowang@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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From: Eric Auger <eric.auger@redhat.com>
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Let's introduce an helper for S1 IOVA range invalidation.
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This will be used for NH_VA and NH_VAA commands. It decodes
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the same fields, trace, calls the UNMAP notifiers and
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invalidate the corresponding IOTLB entries.
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At the moment, we do not support 3.2 range invalidation yet.
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So it reduces to a single IOVA invalidation.
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Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA
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command. At the moment it is only used for tracing.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200728150815.11446-7-eric.auger@redhat.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit c0f9ef70377cfcbd0fa6559d5dc729a930d71b7c)
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Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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hw/arm/smmuv3.c | 36 +++++++++++++++++-------------------
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hw/arm/trace-events | 3 +--
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2 files changed, 18 insertions(+), 21 deletions(-)
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diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
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index 067c9480a03..ae2b769f891 100644
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--- a/hw/arm/smmuv3.c
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+++ b/hw/arm/smmuv3.c
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@@ -824,6 +824,22 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova)
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}
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}
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+static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
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+{
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+ dma_addr_t addr = CMD_ADDR(cmd);
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+ uint8_t type = CMD_TYPE(cmd);
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+ uint16_t vmid = CMD_VMID(cmd);
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+ bool leaf = CMD_LEAF(cmd);
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+ int asid = -1;
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+
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+ if (type == SMMU_CMD_TLBI_NH_VA) {
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+ asid = CMD_ASID(cmd);
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+ }
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+ trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf);
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+ smmuv3_inv_notifiers_iova(s, asid, addr);
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+ smmu_iotlb_inv_iova(s, asid, addr);
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+}
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+
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static int smmuv3_cmdq_consume(SMMUv3State *s)
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{
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SMMUState *bs = ARM_SMMU(s);
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@@ -954,27 +970,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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smmu_iotlb_inv_all(bs);
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break;
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case SMMU_CMD_TLBI_NH_VAA:
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- {
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- dma_addr_t addr = CMD_ADDR(&cmd);
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- uint16_t vmid = CMD_VMID(&cmd);
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-
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- trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr);
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- smmuv3_inv_notifiers_iova(bs, -1, addr);
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- smmu_iotlb_inv_iova(bs, -1, addr);
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- break;
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- }
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case SMMU_CMD_TLBI_NH_VA:
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- {
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- uint16_t asid = CMD_ASID(&cmd);
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- uint16_t vmid = CMD_VMID(&cmd);
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- dma_addr_t addr = CMD_ADDR(&cmd);
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- bool leaf = CMD_LEAF(&cmd);
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-
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- trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf);
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- smmuv3_inv_notifiers_iova(bs, asid, addr);
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- smmu_iotlb_inv_iova(bs, asid, addr);
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+ smmuv3_s1_range_inval(bs, &cmd);
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break;
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- }
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case SMMU_CMD_TLBI_EL3_ALL:
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case SMMU_CMD_TLBI_EL3_VA:
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case SMMU_CMD_TLBI_EL2_ALL:
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diff --git a/hw/arm/trace-events b/hw/arm/trace-events
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index f74d3e920f1..c219fe9e828 100644
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--- a/hw/arm/trace-events
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+++ b/hw/arm/trace-events
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@@ -45,8 +45,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
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smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
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smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
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-smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d"
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-smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64
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+smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d"
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smmuv3_cmdq_tlbi_nh(void) ""
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smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
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--
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2.27.0
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