Blame SOURCES/0189-libcxl-add-a-depth-attribute-to-cxl_port.patch

2eb93d
From 0a43bfdf030b4a84fce562462944a9a44888afaa Mon Sep 17 00:00:00 2001
2eb93d
From: Vishal Verma <vishal.l.verma@intel.com>
2eb93d
Date: Mon, 15 Aug 2022 13:22:04 -0600
2eb93d
Subject: [PATCH 189/217] libcxl: add a depth attribute to cxl_port
2eb93d
2eb93d
Add a depth attribute to the cxl_port structure, that can be used for
2eb93d
calculating its distance from the root port, and will be needed for
2eb93d
interleave granularity calculations during region creation.
2eb93d
2eb93d
Link: https://lore.kernel.org/r/20220815192214.545800-2-vishal.l.verma@intel.com
2eb93d
Suggested-by: Dan Williams <dan.j.williams@intel.com>
2eb93d
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
2eb93d
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
2eb93d
---
2eb93d
 cxl/lib/libcxl.c  | 1 +
2eb93d
 cxl/lib/private.h | 1 +
2eb93d
 2 files changed, 2 insertions(+)
2eb93d
2eb93d
diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
2eb93d
index e52896f..145c6ba 100644
2eb93d
--- a/cxl/lib/libcxl.c
2eb93d
+++ b/cxl/lib/libcxl.c
2eb93d
@@ -744,6 +744,7 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port,
2eb93d
 	port->type = type;
2eb93d
 	port->parent = parent_port;
2eb93d
 	port->type = type;
2eb93d
+	port->depth = parent_port ? parent_port->depth + 1 : 0;
2eb93d
 
2eb93d
 	list_head_init(&port->child_ports);
2eb93d
 	list_head_init(&port->endpoints);
2eb93d
diff --git a/cxl/lib/private.h b/cxl/lib/private.h
2eb93d
index f6d4573..832a815 100644
2eb93d
--- a/cxl/lib/private.h
2eb93d
+++ b/cxl/lib/private.h
2eb93d
@@ -66,6 +66,7 @@ struct cxl_port {
2eb93d
 	int decoders_init;
2eb93d
 	int dports_init;
2eb93d
 	int nr_dports;
2eb93d
+	int depth;
2eb93d
 	struct cxl_ctx *ctx;
2eb93d
 	struct cxl_bus *bus;
2eb93d
 	enum cxl_port_type type;
2eb93d
-- 
2eb93d
2.27.0
2eb93d