From 1b00ec2d7916551eda170e687eb351d40fe346aa Mon Sep 17 00:00:00 2001 From: Joe Lawrence Date: Tue, 3 Jan 2023 11:02:47 -0500 Subject: [KPATCH CVE-2022-4139] kpatch fixes for CVE-2022-4139 Content-type: text/plain Kernels: 4.18.0-425.3.1.el8 Changes since last build: arches: x86_64 intel_gt.o: changed function: intel_gt_invalidate_tlbs --------------------------- Kpatch-MR: https://gitlab.com/redhat/prdsc/rhel/src/kpatch/rhel-8/-/merge_requests/66 Approved-by: Julia Denham (@jdenham) Modifications: none commit 54c6de5154c319e30fddef4fc82a67661525b76e Author: Wander Lairson Costa Date: Thu Dec 1 10:30:34 2022 -0300 drm/i915: fix TLB invalidation for Gen12 video and compute engines Bugzilla: https://bugzilla.redhat.com/2148149 CVE: CVE-2022-4139 Y-Commit: 03abd2e51e4b208b873f7fd749d1af0ebef6658f O-Bugzilla: https://bugzilla.redhat.com/2148150 O-CVE: CVE-2022-4139 commit 04aa64375f48a5d430b5550d9271f8428883e550 Author: Andrzej Hajda Date: Mon Nov 14 11:38:24 2022 +0100 drm/i915: fix TLB invalidation for Gen12 video and compute engines In case of Gen12 video and compute engines, TLB_INV registers are masked - to modify one bit, corresponding bit in upper half of the register must be enabled, otherwise nothing happens. CVE: CVE-2022-4139 Suggested-by: Chris Wilson Signed-off-by: Andrzej Hajda Acked-by: Daniel Vetter Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Cc: stable@vger.kernel.org Signed-off-by: Linus Torvalds Signed-off-by: Wander Lairson Costa Signed-off-by: Jarod Wilson Signed-off-by: Joe Lawrence --- drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f4375479e6f0..1cb9971759d2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1021,6 +1021,11 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) if (!i915_mmio_reg_offset(rb.reg)) continue; + if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || + engine->class == VIDEO_ENHANCEMENT_CLASS || + engine->class == COMPUTE_CLASS)) + rb.bit = _MASKED_BIT_ENABLE(rb.bit); + intel_uncore_write_fw(uncore, rb.reg, rb.bit); } -- 2.39.0