From 56e3f4740a7943a0830b878d1fab594513f83bdc Mon Sep 17 00:00:00 2001 From: CentOS Sources Date: Feb 15 2022 15:33:44 +0000 Subject: import kmod-redhat-rtw89-4.18.0_363_dup8.5-1.el8_5 --- diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d43bf1e --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +SOURCES/rtw89-redhat-4.18.0_363_dup8.5.tar.bz2 diff --git a/.kmod-redhat-rtw89.metadata b/.kmod-redhat-rtw89.metadata new file mode 100644 index 0000000..50a7c72 --- /dev/null +++ b/.kmod-redhat-rtw89.metadata @@ -0,0 +1 @@ +f9a7325c3d3970cb184f7adcd09decfa71c78244 SOURCES/rtw89-redhat-4.18.0_363_dup8.5.tar.bz2 diff --git a/SOURCES/0001-rtw89-add-Realtek-802.11ax-driver.patch b/SOURCES/0001-rtw89-add-Realtek-802.11ax-driver.patch new file mode 100644 index 0000000..51e4403 --- /dev/null +++ b/SOURCES/0001-rtw89-add-Realtek-802.11ax-driver.patch @@ -0,0 +1,91466 @@ +From 922cfd704b4f625f7f5596d0471776327ec713a8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:01 +0100 +Subject: [PATCH 01/36] rtw89: add Realtek 802.11ax driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit e3ec7017f6a20d12ddd9fe23d345ebb7b8c104dd +Author: Ping-Ke Shih +Date: Mon Oct 11 14:47:27 2021 +0300 + + rtw89: add Realtek 802.11ax driver + + This driver named rtw89, which is the next generation of rtw88, supports + Realtek 8852AE 802.11ax 2x2 chip whose new features are OFDMA, DBCC, + Spatial reuse, TWT and BSS coloring; now some of them aren't implemented + though. + + The chip architecture is entirely different from the chips supported by + rtw88 like RTL8822CE 802.11ac chip. First of all, register address ranges + are totally redefined, so it's impossible to reuse register definition. To + communicate with firmware, new H2C/C2H format is proposed. In order to have + better utilization, TX DMA flow is changed to two stages DMA. To provide + rich RX status information, additional RX PPDU packets are added. + + Since there are so many differences mentioned above, we decide to propose + a new driver. It has many authors, they are listed in alphabetic order: + + Chin-Yen Lee + Ping-Ke Shih + Po Hao Huang + Tzu-En Huang + Vincent Fann + Yan-Hsuan Chuang + Zong-Zhe Yang + + Tested-by: Aaron Ma + Tested-by: Brian Norris + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211008035627.19463-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/Kconfig | 1 + + drivers/net/wireless/realtek/Makefile | 1 + + drivers/net/wireless/realtek/rtw89/Kconfig | 50 + + drivers/net/wireless/realtek/rtw89/Makefile | 25 + + drivers/net/wireless/realtek/rtw89/cam.c | 695 + + drivers/net/wireless/realtek/rtw89/cam.h | 165 + + drivers/net/wireless/realtek/rtw89/coex.c | 5716 +++ + drivers/net/wireless/realtek/rtw89/coex.h | 181 + + drivers/net/wireless/realtek/rtw89/core.c | 2502 + + drivers/net/wireless/realtek/rtw89/core.h | 3384 ++ + drivers/net/wireless/realtek/rtw89/debug.c | 2489 + + drivers/net/wireless/realtek/rtw89/debug.h | 77 + + drivers/net/wireless/realtek/rtw89/efuse.c | 188 + + drivers/net/wireless/realtek/rtw89/efuse.h | 13 + + drivers/net/wireless/realtek/rtw89/fw.c | 1641 + + drivers/net/wireless/realtek/rtw89/fw.h | 1378 + + drivers/net/wireless/realtek/rtw89/mac.c | 3838 ++ + drivers/net/wireless/realtek/rtw89/mac.h | 860 + + drivers/net/wireless/realtek/rtw89/mac80211.c | 676 + + drivers/net/wireless/realtek/rtw89/pci.c | 3060 ++ + drivers/net/wireless/realtek/rtw89/pci.h | 635 + + drivers/net/wireless/realtek/rtw89/phy.c | 2868 ++ + drivers/net/wireless/realtek/rtw89/phy.h | 311 + + drivers/net/wireless/realtek/rtw89/ps.c | 150 + + drivers/net/wireless/realtek/rtw89/ps.h | 16 + + drivers/net/wireless/realtek/rtw89/reg.h | 2159 + + drivers/net/wireless/realtek/rtw89/regd.c | 353 + + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 2036 + + drivers/net/wireless/realtek/rtw89/rtw8852a.h | 109 + + drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c | 3911 ++ + drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h | 24 + + .../wireless/realtek/rtw89/rtw8852a_rfk_table.c | 1607 + + .../wireless/realtek/rtw89/rtw8852a_rfk_table.h | 133 + + .../net/wireless/realtek/rtw89/rtw8852a_table.c | 48725 +++++++++++++++++++ + .../net/wireless/realtek/rtw89/rtw8852a_table.h | 28 + + drivers/net/wireless/realtek/rtw89/sar.c | 190 + + drivers/net/wireless/realtek/rtw89/sar.h | 26 + + drivers/net/wireless/realtek/rtw89/ser.c | 491 + + drivers/net/wireless/realtek/rtw89/ser.h | 15 + + drivers/net/wireless/realtek/rtw89/txrx.h | 358 + + drivers/net/wireless/realtek/rtw89/util.h | 17 + + 41 files changed, 91102 insertions(+) + create mode 100644 drivers/net/wireless/realtek/rtw89/Kconfig + create mode 100644 drivers/net/wireless/realtek/rtw89/Makefile + create mode 100644 drivers/net/wireless/realtek/rtw89/cam.c + create mode 100644 drivers/net/wireless/realtek/rtw89/cam.h + create mode 100644 drivers/net/wireless/realtek/rtw89/coex.c + create mode 100644 drivers/net/wireless/realtek/rtw89/coex.h + create mode 100644 drivers/net/wireless/realtek/rtw89/core.c + create mode 100644 drivers/net/wireless/realtek/rtw89/core.h + create mode 100644 drivers/net/wireless/realtek/rtw89/debug.c + create mode 100644 drivers/net/wireless/realtek/rtw89/debug.h + create mode 100644 drivers/net/wireless/realtek/rtw89/efuse.c + create mode 100644 drivers/net/wireless/realtek/rtw89/efuse.h + create mode 100644 drivers/net/wireless/realtek/rtw89/fw.c + create mode 100644 drivers/net/wireless/realtek/rtw89/fw.h + create mode 100644 drivers/net/wireless/realtek/rtw89/mac.c + create mode 100644 drivers/net/wireless/realtek/rtw89/mac.h + create mode 100644 drivers/net/wireless/realtek/rtw89/mac80211.c + create mode 100644 drivers/net/wireless/realtek/rtw89/pci.c + create mode 100644 drivers/net/wireless/realtek/rtw89/pci.h + create mode 100644 drivers/net/wireless/realtek/rtw89/phy.c + create mode 100644 drivers/net/wireless/realtek/rtw89/phy.h + create mode 100644 drivers/net/wireless/realtek/rtw89/ps.c + create mode 100644 drivers/net/wireless/realtek/rtw89/ps.h + create mode 100644 drivers/net/wireless/realtek/rtw89/reg.h + create mode 100644 drivers/net/wireless/realtek/rtw89/regd.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a.h + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_table.c + create mode 100644 drivers/net/wireless/realtek/rtw89/rtw8852a_table.h + create mode 100644 drivers/net/wireless/realtek/rtw89/sar.c + create mode 100644 drivers/net/wireless/realtek/rtw89/sar.h + create mode 100644 drivers/net/wireless/realtek/rtw89/ser.c + create mode 100644 drivers/net/wireless/realtek/rtw89/ser.h + create mode 100644 drivers/net/wireless/realtek/rtw89/txrx.h + create mode 100644 drivers/net/wireless/realtek/rtw89/util.h + +diff --git a/drivers/net/wireless/realtek/rtw89/Kconfig b/drivers/net/wireless/realtek/rtw89/Kconfig +new file mode 100644 +index 000000000000..37e5def24d9f +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/Kconfig +@@ -0,0 +1,50 @@ ++# SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++menuconfig RTW89 ++ tristate "Realtek 802.11ax wireless chips support" ++ depends on MAC80211 ++ help ++ This module adds support for mac80211-based wireless drivers that ++ enables Realtek IEEE 802.11ax wireless chipsets. ++ ++ If you choose to build a module, it'll be called rtw89. ++ ++if RTW89 ++ ++config RTW89_CORE ++ tristate ++ ++config RTW89_PCI ++ tristate ++ ++config RTW89_8852AE ++ tristate "Realtek 8852AE PCI wireless network adapter" ++ depends on PCI ++ select RTW89_CORE ++ select RTW89_PCI ++ help ++ Select this option will enable support for 8852AE chipset ++ ++ 802.11ax PCIe wireless network adapter ++ ++config RTW89_DEBUG ++ bool ++ ++config RTW89_DEBUGMSG ++ bool "Realtek rtw89 debug message support" ++ depends on RTW89_CORE ++ select RTW89_DEBUG ++ help ++ Enable debug message support ++ ++ If unsure, say Y to simplify debug problems ++ ++config RTW89_DEBUGFS ++ bool "Realtek rtw89 debugfs support" ++ depends on RTW89_CORE ++ select RTW89_DEBUG ++ help ++ Enable debugfs support ++ ++ If unsure, say Y to simplify debug problems ++ ++endif +diff --git a/drivers/net/wireless/realtek/rtw89/Makefile b/drivers/net/wireless/realtek/rtw89/Makefile +new file mode 100644 +index 000000000000..077e8fe23f60 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/Makefile +@@ -0,0 +1,25 @@ ++# SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++ ++obj-$(CONFIG_RTW89_CORE) += rtw89_core.o ++rtw89_core-y += core.o \ ++ mac80211.o \ ++ mac.o \ ++ phy.o \ ++ fw.o \ ++ rtw8852a.o \ ++ rtw8852a_table.o \ ++ rtw8852a_rfk.o \ ++ rtw8852a_rfk_table.o \ ++ cam.o \ ++ efuse.o \ ++ regd.o \ ++ sar.o \ ++ coex.o \ ++ ps.o \ ++ ser.o ++ ++rtw89_core-$(CONFIG_RTW89_DEBUG) += debug.o ++ ++obj-$(CONFIG_RTW89_PCI) += rtw89_pci.o ++rtw89_pci-y := pci.o ++ +diff --git a/drivers/net/wireless/realtek/rtw89/cam.c b/drivers/net/wireless/realtek/rtw89/cam.c +new file mode 100644 +index 000000000000..c1e8c76c6aca +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/cam.c +@@ -0,0 +1,695 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++ ++static struct sk_buff * ++rtw89_cam_get_sec_key_cmd(struct rtw89_dev *rtwdev, ++ struct rtw89_sec_cam_entry *sec_cam, ++ bool ext_key) ++{ ++ struct sk_buff *skb; ++ u32 cmd_len = H2C_SEC_CAM_LEN; ++ u32 key32[4]; ++ u8 *cmd; ++ int i, j; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(cmd_len); ++ if (!skb) ++ return NULL; ++ ++ skb_put_zero(skb, cmd_len); ++ ++ for (i = 0; i < 4; i++) { ++ j = i * 4; ++ j += ext_key ? 16 : 0; ++ key32[i] = FIELD_PREP(GENMASK(7, 0), sec_cam->key[j + 0]) | ++ FIELD_PREP(GENMASK(15, 8), sec_cam->key[j + 1]) | ++ FIELD_PREP(GENMASK(23, 16), sec_cam->key[j + 2]) | ++ FIELD_PREP(GENMASK(31, 24), sec_cam->key[j + 3]); ++ } ++ ++ cmd = skb->data; ++ RTW89_SET_FWCMD_SEC_IDX(cmd, sec_cam->sec_cam_idx + (ext_key ? 1 : 0)); ++ RTW89_SET_FWCMD_SEC_OFFSET(cmd, sec_cam->offset); ++ RTW89_SET_FWCMD_SEC_LEN(cmd, sec_cam->len); ++ RTW89_SET_FWCMD_SEC_TYPE(cmd, sec_cam->type); ++ RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, ext_key); ++ RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, sec_cam->spp_mode); ++ RTW89_SET_FWCMD_SEC_KEY0(cmd, key32[0]); ++ RTW89_SET_FWCMD_SEC_KEY1(cmd, key32[1]); ++ RTW89_SET_FWCMD_SEC_KEY2(cmd, key32[2]); ++ RTW89_SET_FWCMD_SEC_KEY3(cmd, key32[3]); ++ ++ return skb; ++} ++ ++static int rtw89_cam_send_sec_key_cmd(struct rtw89_dev *rtwdev, ++ struct rtw89_sec_cam_entry *sec_cam) ++{ ++ struct sk_buff *skb, *ext_skb; ++ int ret; ++ ++ skb = rtw89_cam_get_sec_key_cmd(rtwdev, sec_cam, false); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to get sec key command\n"); ++ return -ENOMEM; ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, ++ FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_SEC_CAM, ++ H2C_FUNC_MAC_SEC_UPD, 1, 0, ++ H2C_SEC_CAM_LEN); ++ ret = rtw89_h2c_tx(rtwdev, skb, false); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send sec key h2c: %d\n", ret); ++ dev_kfree_skb(skb); ++ return ret; ++ } ++ ++ if (!sec_cam->ext_key) ++ return 0; ++ ++ ext_skb = rtw89_cam_get_sec_key_cmd(rtwdev, sec_cam, true); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to get ext sec key command\n"); ++ return -ENOMEM; ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, ext_skb, ++ FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_SEC_CAM, ++ H2C_FUNC_MAC_SEC_UPD, ++ 1, 0, H2C_SEC_CAM_LEN); ++ ret = rtw89_h2c_tx(rtwdev, ext_skb, false); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send ext sec key h2c: %d\n", ret); ++ dev_kfree_skb(ext_skb); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_get_avail_sec_cam(struct rtw89_dev *rtwdev, ++ u8 *sec_cam_idx, bool ext_key) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 sec_cam_num = chip->scam_num; ++ u8 idx = 0; ++ ++ if (!ext_key) { ++ idx = find_first_zero_bit(cam_info->sec_cam_map, sec_cam_num); ++ if (idx >= sec_cam_num) ++ return -EBUSY; ++ ++ set_bit(idx, cam_info->sec_cam_map); ++ *sec_cam_idx = idx; ++ ++ return 0; ++ } ++ ++again: ++ idx = find_next_zero_bit(cam_info->sec_cam_map, sec_cam_num, idx); ++ if (idx >= sec_cam_num - 1) ++ return -EBUSY; ++ /* ext keys need two cam entries for 256-bit key */ ++ if (test_bit(idx + 1, cam_info->sec_cam_map)) { ++ idx++; ++ goto again; ++ } ++ ++ set_bit(idx, cam_info->sec_cam_map); ++ set_bit(idx + 1, cam_info->sec_cam_map); ++ *sec_cam_idx = idx; ++ ++ return 0; ++} ++ ++static int rtw89_cam_get_addr_cam_key_idx(struct rtw89_addr_cam_entry *addr_cam, ++ struct rtw89_sec_cam_entry *sec_cam, ++ struct ieee80211_key_conf *key, ++ u8 *key_idx) ++{ ++ u8 idx; ++ ++ /* RTW89_ADDR_CAM_SEC_NONE : not enabled ++ * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast ++ * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP ++ * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP ++ */ ++ switch (addr_cam->sec_ent_mode) { ++ case RTW89_ADDR_CAM_SEC_NONE: ++ return -EINVAL; ++ case RTW89_ADDR_CAM_SEC_ALL_UNI: ++ if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) ++ return -EINVAL; ++ idx = find_first_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM); ++ if (idx >= RTW89_SEC_CAM_IN_ADDR_CAM) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ case RTW89_ADDR_CAM_SEC_NORMAL: ++ if (sec_cam->type == RTW89_SEC_KEY_TYPE_BIP_CCMP128) { ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 5); ++ if (idx > 6) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 0); ++ if (idx > 1) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ /* Group keys */ ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 2); ++ if (idx > 4) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ case RTW89_ADDR_CAM_SEC_4GROUP: ++ if (sec_cam->type == RTW89_SEC_KEY_TYPE_BIP_CCMP128) { ++ if (test_bit(6, addr_cam->sec_cam_map)) ++ return -EINVAL; ++ *key_idx = 6; ++ break; ++ } ++ ++ if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 0); ++ if (idx > 1) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ /* Group keys */ ++ idx = find_next_zero_bit(addr_cam->sec_cam_map, ++ RTW89_SEC_CAM_IN_ADDR_CAM, 2); ++ if (idx > 5) ++ return -EBUSY; ++ *key_idx = idx; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_attach_sec_cam(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ struct rtw89_sec_cam_entry *sec_cam) ++{ ++ struct rtw89_vif *rtwvif; ++ struct rtw89_addr_cam_entry *addr_cam; ++ u8 key_idx = 0; ++ int ret; ++ ++ if (!vif) { ++ rtw89_err(rtwdev, "No iface for adding sec cam\n"); ++ return -EINVAL; ++ } ++ ++ rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ addr_cam = &rtwvif->addr_cam; ++ ret = rtw89_cam_get_addr_cam_key_idx(addr_cam, sec_cam, key, &key_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get addr cam key idx %d, %d\n", ++ addr_cam->sec_ent_mode, sec_cam->type); ++ return ret; ++ } ++ ++ key->hw_key_idx = key_idx; ++ addr_cam->sec_ent_keyid[key_idx] = key->keyidx; ++ addr_cam->sec_ent[key_idx] = sec_cam->sec_cam_idx; ++ addr_cam->sec_entries[key_idx] = sec_cam; ++ set_bit(key_idx, addr_cam->sec_cam_map); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to update addr cam sec entry: %d\n", ++ ret); ++ clear_bit(key_idx, addr_cam->sec_cam_map); ++ addr_cam->sec_entries[key_idx] = NULL; ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_sec_key_install(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ u8 hw_key_type, bool ext_key) ++{ ++ struct rtw89_sec_cam_entry *sec_cam = NULL; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 sec_cam_idx; ++ int ret; ++ ++ /* maximum key length 256-bit */ ++ if (key->keylen > 32) { ++ rtw89_err(rtwdev, "invalid sec key length %d\n", key->keylen); ++ return -EINVAL; ++ } ++ ++ ret = rtw89_cam_get_avail_sec_cam(rtwdev, &sec_cam_idx, ext_key); ++ if (ret) { ++ rtw89_warn(rtwdev, "no available sec cam: %d ext: %d\n", ++ ret, ext_key); ++ return ret; ++ } ++ ++ sec_cam = kzalloc(sizeof(*sec_cam), GFP_KERNEL); ++ if (!sec_cam) { ++ ret = -ENOMEM; ++ goto err_release_cam; ++ } ++ ++ sec_cam->sec_cam_idx = sec_cam_idx; ++ sec_cam->type = hw_key_type; ++ sec_cam->len = RTW89_SEC_CAM_LEN; ++ sec_cam->ext_key = ext_key; ++ memcpy(sec_cam->key, key->key, key->keylen); ++ ret = rtw89_cam_send_sec_key_cmd(rtwdev, sec_cam); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send sec key cmd: %d\n", ret); ++ goto err_release_cam; ++ } ++ ++ /* associate with addr cam */ ++ ret = rtw89_cam_attach_sec_cam(rtwdev, vif, sta, key, sec_cam); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to attach sec cam: %d\n", ret); ++ goto err_release_cam; ++ } ++ ++ return 0; ++ ++err_release_cam: ++ kfree(sec_cam); ++ clear_bit(sec_cam_idx, cam_info->sec_cam_map); ++ if (ext_key) ++ clear_bit(sec_cam_idx + 1, cam_info->sec_cam_map); ++ ++ return ret; ++} ++ ++int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key) ++{ ++ u8 hw_key_type; ++ bool ext_key = false; ++ int ret; ++ ++ switch (key->cipher) { ++ case WLAN_CIPHER_SUITE_WEP40: ++ hw_key_type = RTW89_SEC_KEY_TYPE_WEP40; ++ break; ++ case WLAN_CIPHER_SUITE_WEP104: ++ hw_key_type = RTW89_SEC_KEY_TYPE_WEP104; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ hw_key_type = RTW89_SEC_KEY_TYPE_CCMP128; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP_256: ++ hw_key_type = RTW89_SEC_KEY_TYPE_CCMP256; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ ext_key = true; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP: ++ hw_key_type = RTW89_SEC_KEY_TYPE_GCMP128; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP_256: ++ hw_key_type = RTW89_SEC_KEY_TYPE_GCMP256; ++ key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; ++ ext_key = true; ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; ++ ++ ret = rtw89_cam_sec_key_install(rtwdev, vif, sta, key, hw_key_type, ++ ext_key); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to install key type %d ext %d: %d\n", ++ hw_key_type, ext_key, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ bool inform_fw) ++{ ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ struct rtw89_vif *rtwvif; ++ struct rtw89_addr_cam_entry *addr_cam; ++ struct rtw89_sec_cam_entry *sec_cam; ++ u8 key_idx = key->hw_key_idx; ++ u8 sec_cam_idx; ++ int ret = 0; ++ ++ if (!vif) { ++ rtw89_err(rtwdev, "No iface for deleting sec cam\n"); ++ return -EINVAL; ++ } ++ ++ rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ addr_cam = &rtwvif->addr_cam; ++ sec_cam = addr_cam->sec_entries[key_idx]; ++ if (!sec_cam) ++ return -EINVAL; ++ ++ /* detach sec cam from addr cam */ ++ clear_bit(key_idx, addr_cam->sec_cam_map); ++ addr_cam->sec_entries[key_idx] = NULL; ++ if (inform_fw) { ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) ++ rtw89_err(rtwdev, "failed to update cam del key: %d\n", ret); ++ } ++ ++ /* clear valid bit in addr cam will disable sec cam, ++ * so we don't need to send H2C command again ++ */ ++ sec_cam_idx = sec_cam->sec_cam_idx; ++ clear_bit(sec_cam_idx, cam_info->sec_cam_map); ++ if (sec_cam->ext_key) ++ clear_bit(sec_cam_idx + 1, cam_info->sec_cam_map); ++ ++ kfree(sec_cam); ++ ++ return ret; ++} ++ ++static void rtw89_cam_reset_key_iter(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ void *data) ++{ ++ struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ rtw89_cam_sec_key_del(rtwdev, vif, sta, key, false); ++ rtw89_cam_deinit(rtwdev, rtwvif); ++} ++ ++void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ ++ addr_cam->valid = false; ++ bssid_cam->valid = false; ++ clear_bit(addr_cam->addr_cam_idx, cam_info->addr_cam_map); ++ clear_bit(bssid_cam->bssid_cam_idx, cam_info->bssid_cam_map); ++} ++ ++void rtw89_cam_reset_keys(struct rtw89_dev *rtwdev) ++{ ++ rcu_read_lock(); ++ ieee80211_iter_keys_rcu(rtwdev->hw, NULL, rtw89_cam_reset_key_iter, rtwdev); ++ rcu_read_unlock(); ++} ++ ++static int rtw89_cam_get_avail_addr_cam(struct rtw89_dev *rtwdev, ++ u8 *addr_cam_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 addr_cam_num = chip->acam_num; ++ u8 idx; ++ ++ idx = find_first_zero_bit(cam_info->addr_cam_map, addr_cam_num); ++ if (idx >= addr_cam_num) ++ return -EBUSY; ++ ++ set_bit(idx, cam_info->addr_cam_map); ++ *addr_cam_idx = idx; ++ ++ return 0; ++} ++ ++static int rtw89_cam_init_addr_cam(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ u8 addr_cam_idx; ++ int i; ++ int ret; ++ ++ ret = rtw89_cam_get_avail_addr_cam(rtwdev, &addr_cam_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get available addr cam\n"); ++ return ret; ++ } ++ ++ addr_cam->addr_cam_idx = addr_cam_idx; ++ addr_cam->len = ADDR_CAM_ENT_SIZE; ++ addr_cam->offset = 0; ++ addr_cam->valid = true; ++ addr_cam->addr_mask = 0; ++ addr_cam->mask_sel = RTW89_NO_MSK; ++ bitmap_zero(addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); ++ ether_addr_copy(addr_cam->sma, rtwvif->mac_addr); ++ ++ for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { ++ addr_cam->sec_ent_keyid[i] = 0; ++ addr_cam->sec_ent[i] = 0; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_cam_get_avail_bssid_cam(struct rtw89_dev *rtwdev, ++ u8 *bssid_cam_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_cam_info *cam_info = &rtwdev->cam_info; ++ u8 bssid_cam_num = chip->bcam_num; ++ u8 idx; ++ ++ idx = find_first_zero_bit(cam_info->bssid_cam_map, bssid_cam_num); ++ if (idx >= bssid_cam_num) ++ return -EBUSY; ++ ++ set_bit(idx, cam_info->bssid_cam_map); ++ *bssid_cam_idx = idx; ++ ++ return 0; ++} ++ ++static int rtw89_cam_init_bssid_cam(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ u8 bssid_cam_idx; ++ int ret; ++ ++ ret = rtw89_cam_get_avail_bssid_cam(rtwdev, &bssid_cam_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get available bssid cam\n"); ++ return ret; ++ } ++ ++ bssid_cam->bssid_cam_idx = bssid_cam_idx; ++ bssid_cam->phy_idx = rtwvif->phy_idx; ++ bssid_cam->len = BSSID_CAM_ENT_SIZE; ++ bssid_cam->offset = 0; ++ bssid_cam->valid = true; ++ ether_addr_copy(bssid_cam->bssid, rtwvif->bssid); ++ ++ return 0; ++} ++ ++void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ ++ if (vif->type == NL80211_IFTYPE_STATION) ++ ether_addr_copy(addr_cam->tma, rtwvif->bssid); ++ ether_addr_copy(bssid_cam->bssid, rtwvif->bssid); ++} ++ ++int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ int ret; ++ ++ ret = rtw89_cam_init_addr_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init addr cam\n"); ++ return ret; ++ } ++ ++ ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init bssid cam\n"); ++ return ret; ++ } ++ ++ /* associate addr cam with bssid cam */ ++ addr_cam->bssid_cam_idx = bssid_cam->bssid_cam_idx; ++ ++ return 0; ++} ++ ++int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u8 *cmd) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; ++ u8 bss_color = vif->bss_conf.he_bss_color.color; ++ ++ FWCMD_SET_ADDR_BSSID_IDX(cmd, bssid_cam->bssid_cam_idx); ++ FWCMD_SET_ADDR_BSSID_OFFSET(cmd, bssid_cam->offset); ++ FWCMD_SET_ADDR_BSSID_LEN(cmd, bssid_cam->len); ++ FWCMD_SET_ADDR_BSSID_VALID(cmd, bssid_cam->valid); ++ FWCMD_SET_ADDR_BSSID_BB_SEL(cmd, bssid_cam->phy_idx); ++ FWCMD_SET_ADDR_BSSID_BSS_COLOR(cmd, bss_color); ++ ++ FWCMD_SET_ADDR_BSSID_BSSID0(cmd, bssid_cam->bssid[0]); ++ FWCMD_SET_ADDR_BSSID_BSSID1(cmd, bssid_cam->bssid[1]); ++ FWCMD_SET_ADDR_BSSID_BSSID2(cmd, bssid_cam->bssid[2]); ++ FWCMD_SET_ADDR_BSSID_BSSID3(cmd, bssid_cam->bssid[3]); ++ FWCMD_SET_ADDR_BSSID_BSSID4(cmd, bssid_cam->bssid[4]); ++ FWCMD_SET_ADDR_BSSID_BSSID5(cmd, bssid_cam->bssid[5]); ++ ++ return 0; ++} ++ ++static u8 rtw89_cam_addr_hash(u8 start, u8 *addr) ++{ ++ u8 hash = 0; ++ u8 i; ++ ++ for (i = start; i < ETH_ALEN; i++) ++ hash ^= addr[i]; ++ ++ return hash; ++} ++ ++void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, ++ u8 *cmd) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct ieee80211_sta *sta; ++ struct rtw89_sta *rtwsta; ++ struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ u8 sma_hash, tma_hash, addr_msk_start; ++ u8 sma_start = 0; ++ u8 tma_start = 0; ++ ++ if (addr_cam->addr_mask != 0) { ++ addr_msk_start = __ffs(addr_cam->addr_mask); ++ if (addr_cam->mask_sel == RTW89_SMA) ++ sma_start = addr_msk_start; ++ else if (addr_cam->mask_sel == RTW89_TMA) ++ tma_start = addr_msk_start; ++ } ++ sma_hash = rtw89_cam_addr_hash(sma_start, rtwvif->mac_addr); ++ tma_hash = rtw89_cam_addr_hash(tma_start, addr_cam->tma); ++ ++ FWCMD_SET_ADDR_IDX(cmd, addr_cam->addr_cam_idx); ++ FWCMD_SET_ADDR_OFFSET(cmd, addr_cam->offset); ++ FWCMD_SET_ADDR_LEN(cmd, addr_cam->len); ++ ++ FWCMD_SET_ADDR_VALID(cmd, addr_cam->valid); ++ FWCMD_SET_ADDR_NET_TYPE(cmd, rtwvif->net_type); ++ FWCMD_SET_ADDR_BCN_HIT_COND(cmd, rtwvif->bcn_hit_cond); ++ FWCMD_SET_ADDR_HIT_RULE(cmd, rtwvif->hit_rule); ++ FWCMD_SET_ADDR_BB_SEL(cmd, rtwvif->phy_idx); ++ FWCMD_SET_ADDR_ADDR_MASK(cmd, addr_cam->addr_mask); ++ FWCMD_SET_ADDR_MASK_SEL(cmd, addr_cam->mask_sel); ++ FWCMD_SET_ADDR_SMA_HASH(cmd, sma_hash); ++ FWCMD_SET_ADDR_TMA_HASH(cmd, tma_hash); ++ ++ FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, addr_cam->bssid_cam_idx); ++ ++ FWCMD_SET_ADDR_SMA0(cmd, rtwvif->mac_addr[0]); ++ FWCMD_SET_ADDR_SMA1(cmd, rtwvif->mac_addr[1]); ++ FWCMD_SET_ADDR_SMA2(cmd, rtwvif->mac_addr[2]); ++ FWCMD_SET_ADDR_SMA3(cmd, rtwvif->mac_addr[3]); ++ FWCMD_SET_ADDR_SMA4(cmd, rtwvif->mac_addr[4]); ++ FWCMD_SET_ADDR_SMA5(cmd, rtwvif->mac_addr[5]); ++ ++ FWCMD_SET_ADDR_TMA0(cmd, addr_cam->tma[0]); ++ FWCMD_SET_ADDR_TMA1(cmd, addr_cam->tma[1]); ++ FWCMD_SET_ADDR_TMA2(cmd, addr_cam->tma[2]); ++ FWCMD_SET_ADDR_TMA3(cmd, addr_cam->tma[3]); ++ FWCMD_SET_ADDR_TMA4(cmd, addr_cam->tma[4]); ++ FWCMD_SET_ADDR_TMA5(cmd, addr_cam->tma[5]); ++ ++ FWCMD_SET_ADDR_PORT_INT(cmd, rtwvif->port); ++ FWCMD_SET_ADDR_TSF_SYNC(cmd, rtwvif->port); ++ FWCMD_SET_ADDR_TF_TRS(cmd, rtwvif->trigger); ++ FWCMD_SET_ADDR_LSIG_TXOP(cmd, rtwvif->lsig_txop); ++ FWCMD_SET_ADDR_TGT_IND(cmd, rtwvif->tgt_ind); ++ FWCMD_SET_ADDR_FRM_TGT_IND(cmd, rtwvif->frm_tgt_ind); ++ ++ if (vif->type == NL80211_IFTYPE_STATION) { ++ sta = rtwvif->mgd.ap; ++ if (sta) { ++ rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ FWCMD_SET_ADDR_MACID(cmd, rtwsta->mac_id); ++ FWCMD_SET_ADDR_AID12(cmd, vif->bss_conf.aid & 0xfff); ++ } ++ } ++ FWCMD_SET_ADDR_WOL_PATTERN(cmd, rtwvif->wowlan_pattern); ++ FWCMD_SET_ADDR_WOL_UC(cmd, rtwvif->wowlan_uc); ++ FWCMD_SET_ADDR_WOL_MAGIC(cmd, rtwvif->wowlan_magic); ++ FWCMD_SET_ADDR_WAPI(cmd, addr_cam->wapi); ++ FWCMD_SET_ADDR_SEC_ENT_MODE(cmd, addr_cam->sec_ent_mode); ++ FWCMD_SET_ADDR_SEC_ENT0_KEYID(cmd, addr_cam->sec_ent_keyid[0]); ++ FWCMD_SET_ADDR_SEC_ENT1_KEYID(cmd, addr_cam->sec_ent_keyid[1]); ++ FWCMD_SET_ADDR_SEC_ENT2_KEYID(cmd, addr_cam->sec_ent_keyid[2]); ++ FWCMD_SET_ADDR_SEC_ENT3_KEYID(cmd, addr_cam->sec_ent_keyid[3]); ++ FWCMD_SET_ADDR_SEC_ENT4_KEYID(cmd, addr_cam->sec_ent_keyid[4]); ++ FWCMD_SET_ADDR_SEC_ENT5_KEYID(cmd, addr_cam->sec_ent_keyid[5]); ++ FWCMD_SET_ADDR_SEC_ENT6_KEYID(cmd, addr_cam->sec_ent_keyid[6]); ++ ++ FWCMD_SET_ADDR_SEC_ENT_VALID(cmd, addr_cam->sec_cam_map[0] & 0xff); ++ FWCMD_SET_ADDR_SEC_ENT0(cmd, addr_cam->sec_ent[0]); ++ FWCMD_SET_ADDR_SEC_ENT1(cmd, addr_cam->sec_ent[1]); ++ FWCMD_SET_ADDR_SEC_ENT2(cmd, addr_cam->sec_ent[2]); ++ FWCMD_SET_ADDR_SEC_ENT3(cmd, addr_cam->sec_ent[3]); ++ FWCMD_SET_ADDR_SEC_ENT4(cmd, addr_cam->sec_ent[4]); ++ FWCMD_SET_ADDR_SEC_ENT5(cmd, addr_cam->sec_ent[5]); ++ FWCMD_SET_ADDR_SEC_ENT6(cmd, addr_cam->sec_ent[6]); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/cam.h b/drivers/net/wireless/realtek/rtw89/cam.h +new file mode 100644 +index 000000000000..90a20a5375c6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/cam.h +@@ -0,0 +1,165 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_CAM_H__ ++#define __RTW89_CAM_H__ ++ ++#include "core.h" ++ ++#define RTW89_SEC_CAM_LEN 20 ++ ++#define FWCMD_SET_ADDR_IDX(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_OFFSET(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_LEN(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_VALID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0)) ++#define FWCMD_SET_ADDR_NET_TYPE(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)) ++#define FWCMD_SET_ADDR_BCN_HIT_COND(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3)) ++#define FWCMD_SET_ADDR_HIT_RULE(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5)) ++#define FWCMD_SET_ADDR_BB_SEL(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(7)) ++#define FWCMD_SET_ADDR_ADDR_MASK(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8)) ++#define FWCMD_SET_ADDR_MASK_SEL(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(15, 14)) ++#define FWCMD_SET_ADDR_SMA_HASH(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_TMA_HASH(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0)) ++#define FWCMD_SET_ADDR_SMA0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SMA1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_SMA2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_SMA3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_SMA4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SMA5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_TMA0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_TMA1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_TMA2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_TMA3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_TMA4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_TMA5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_MACID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_PORT_INT(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(10, 8)) ++#define FWCMD_SET_ADDR_TSF_SYNC(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(13, 11)) ++#define FWCMD_SET_ADDR_TF_TRS(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(14)) ++#define FWCMD_SET_ADDR_LSIG_TXOP(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(15)) ++#define FWCMD_SET_ADDR_TGT_IND(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(26, 24)) ++#define FWCMD_SET_ADDR_FRM_TGT_IND(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(29, 27)) ++#define FWCMD_SET_ADDR_AID12(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 0)) ++#define FWCMD_SET_ADDR_AID12_0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_AID12_1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 8)) ++#define FWCMD_SET_ADDR_WOL_PATTERN(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(12)) ++#define FWCMD_SET_ADDR_WOL_UC(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(13)) ++#define FWCMD_SET_ADDR_WOL_MAGIC(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(14)) ++#define FWCMD_SET_ADDR_WAPI(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(15)) ++#define FWCMD_SET_ADDR_SEC_ENT_MODE(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(17, 16)) ++#define FWCMD_SET_ADDR_SEC_ENT0_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(19, 18)) ++#define FWCMD_SET_ADDR_SEC_ENT1_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(21, 20)) ++#define FWCMD_SET_ADDR_SEC_ENT2_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(23, 22)) ++#define FWCMD_SET_ADDR_SEC_ENT3_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(25, 24)) ++#define FWCMD_SET_ADDR_SEC_ENT4_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(27, 26)) ++#define FWCMD_SET_ADDR_SEC_ENT5_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(29, 28)) ++#define FWCMD_SET_ADDR_SEC_ENT6_KEYID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(31, 30)) ++#define FWCMD_SET_ADDR_SEC_ENT_VALID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SEC_ENT0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_SEC_ENT1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_SEC_ENT2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_SEC_ENT3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_SEC_ENT4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_SEC_ENT5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_SEC_ENT6(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_BSSID_IDX(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_BSSID_OFFSET(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_BSSID_LEN(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_BSSID_VALID(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(0)) ++#define FWCMD_SET_ADDR_BSSID_BB_SEL(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(1)) ++#define FWCMD_SET_ADDR_BSSID_BSS_COLOR(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(13, 8)) ++#define FWCMD_SET_ADDR_BSSID_BSSID0(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_BSSID_BSSID1(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(31, 24)) ++#define FWCMD_SET_ADDR_BSSID_BSSID2(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(7, 0)) ++#define FWCMD_SET_ADDR_BSSID_BSSID3(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(15, 8)) ++#define FWCMD_SET_ADDR_BSSID_BSSID4(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(23, 16)) ++#define FWCMD_SET_ADDR_BSSID_BSSID5(cmd, value) \ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(31, 24)) ++ ++int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *vif, u8 *cmd); ++int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *vif, u8 *cmd); ++int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key); ++int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key, ++ bool inform_fw); ++void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif); ++void rtw89_cam_reset_keys(struct rtw89_dev *rtwdev); ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +new file mode 100644 +index 000000000000..abe4b6549ab2 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -0,0 +1,5716 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++ ++#define FCXDEF_STEP 50 /* MUST <= FCXMAX_STEP and match with wl fw*/ ++ ++enum btc_fbtc_tdma_template { ++ CXTD_OFF = 0x0, ++ CXTD_OFF_B2, ++ CXTD_OFF_EXT, ++ CXTD_FIX, ++ CXTD_PFIX, ++ CXTD_AUTO, ++ CXTD_PAUTO, ++ CXTD_AUTO2, ++ CXTD_PAUTO2, ++ CXTD_MAX, ++}; ++ ++enum btc_fbtc_tdma_type { ++ CXTDMA_OFF = 0x0, ++ CXTDMA_FIX = 0x1, ++ CXTDMA_AUTO = 0x2, ++ CXTDMA_AUTO2 = 0x3, ++ CXTDMA_MAX ++}; ++ ++enum btc_fbtc_tdma_rx_flow_ctrl { ++ CXFLC_OFF = 0x0, ++ CXFLC_NULLP = 0x1, ++ CXFLC_QOSNULL = 0x2, ++ CXFLC_CTS = 0x3, ++ CXFLC_MAX ++}; ++ ++enum btc_fbtc_tdma_wlan_tx_pause { ++ CXTPS_OFF = 0x0, /* no wl tx pause*/ ++ CXTPS_ON = 0x1, ++ CXTPS_MAX ++}; ++ ++enum btc_mlme_state { ++ MLME_NO_LINK, ++ MLME_LINKING, ++ MLME_LINKED, ++}; ++ ++#define FCXONESLOT_VER 1 ++struct btc_fbtc_1slot { ++ u8 fver; ++ u8 sid; /* slot id */ ++ struct rtw89_btc_fbtc_slot slot; ++} __packed; ++ ++static const struct rtw89_btc_fbtc_tdma t_def[] = { ++ [CXTD_OFF] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_OFF_B2] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 1, 0, 0}, ++ [CXTD_OFF_EXT] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 3, 0, 0}, ++ [CXTD_FIX] = { CXTDMA_FIX, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_PFIX] = { CXTDMA_FIX, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, ++ [CXTD_AUTO] = { CXTDMA_AUTO, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_PAUTO] = { CXTDMA_AUTO, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, ++ [CXTD_AUTO2] = {CXTDMA_AUTO2, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, ++ [CXTD_PAUTO2] = {CXTDMA_AUTO2, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0} ++}; ++ ++#define __DEF_FBTC_SLOT(__dur, __cxtbl, __cxtype) \ ++ { .dur = cpu_to_le16(__dur), .cxtbl = cpu_to_le32(__cxtbl), \ ++ .cxtype = cpu_to_le16(__cxtype),} ++ ++static const struct rtw89_btc_fbtc_slot s_def[] = { ++ [CXST_OFF] = __DEF_FBTC_SLOT(100, 0x55555555, SLOT_MIX), ++ [CXST_B2W] = __DEF_FBTC_SLOT(5, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_W1] = __DEF_FBTC_SLOT(70, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_W2] = __DEF_FBTC_SLOT(70, 0x5a5a5aaa, SLOT_ISO), ++ [CXST_W2B] = __DEF_FBTC_SLOT(15, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_B1] = __DEF_FBTC_SLOT(100, 0x55555555, SLOT_MIX), ++ [CXST_B2] = __DEF_FBTC_SLOT(7, 0x6a5a5a5a, SLOT_MIX), ++ [CXST_B3] = __DEF_FBTC_SLOT(5, 0x55555555, SLOT_MIX), ++ [CXST_B4] = __DEF_FBTC_SLOT(50, 0x55555555, SLOT_MIX), ++ [CXST_LK] = __DEF_FBTC_SLOT(20, 0x5a5a5a5a, SLOT_ISO), ++ [CXST_BLK] = __DEF_FBTC_SLOT(250, 0x55555555, SLOT_MIX), ++ [CXST_E2G] = __DEF_FBTC_SLOT(20, 0x6a5a5a5a, SLOT_MIX), ++ [CXST_E5G] = __DEF_FBTC_SLOT(20, 0xffffffff, SLOT_MIX), ++ [CXST_EBT] = __DEF_FBTC_SLOT(20, 0x55555555, SLOT_MIX), ++ [CXST_ENULL] = __DEF_FBTC_SLOT(7, 0xaaaaaaaa, SLOT_ISO), ++ [CXST_WLK] = __DEF_FBTC_SLOT(250, 0x6a5a6a5a, SLOT_MIX), ++ [CXST_W1FDD] = __DEF_FBTC_SLOT(35, 0xfafafafa, SLOT_ISO), ++ [CXST_B1FDD] = __DEF_FBTC_SLOT(100, 0xffffffff, SLOT_MIX), ++}; ++ ++static const u32 cxtbl[] = { ++ 0xffffffff, /* 0 */ ++ 0xaaaaaaaa, /* 1 */ ++ 0x55555555, /* 2 */ ++ 0x66555555, /* 3 */ ++ 0x66556655, /* 4 */ ++ 0x5a5a5a5a, /* 5 */ ++ 0x5a5a5aaa, /* 6 */ ++ 0xaa5a5a5a, /* 7 */ ++ 0x6a5a5a5a, /* 8 */ ++ 0x6a5a5aaa, /* 9 */ ++ 0x6a5a6a5a, /* 10 */ ++ 0x6a5a6aaa, /* 11 */ ++ 0x6afa5afa, /* 12 */ ++ 0xaaaa5aaa, /* 13 */ ++ 0xaaffffaa, /* 14 */ ++ 0xaa5555aa, /* 15 */ ++ 0xfafafafa, /* 16 */ ++ 0xffffddff, /* 17 */ ++ 0xdaffdaff, /* 18 */ ++ 0xfafadafa /* 19 */ ++}; ++ ++struct rtw89_btc_btf_tlv { ++ u8 type; ++ u8 len; ++ u8 val[1]; ++} __packed; ++ ++enum btc_btf_set_report_en { ++ RPT_EN_TDMA = BIT(0), ++ RPT_EN_CYCLE = BIT(1), ++ RPT_EN_MREG = BIT(2), ++ RPT_EN_BT_VER_INFO = BIT(3), ++ RPT_EN_BT_SCAN_INFO = BIT(4), ++ RPT_EN_BT_AFH_MAP = BIT(5), ++ RPT_EN_BT_DEVICE_INFO = BIT(6), ++ RPT_EN_WL_ALL = GENMASK(2, 0), ++ RPT_EN_BT_ALL = GENMASK(6, 3), ++ RPT_EN_ALL = GENMASK(6, 0), ++}; ++ ++#define BTF_SET_REPORT_VER 1 ++struct rtw89_btc_btf_set_report { ++ u8 fver; ++ __le32 enable; ++ __le32 para; ++} __packed; ++ ++#define BTF_SET_SLOT_TABLE_VER 1 ++struct rtw89_btc_btf_set_slot_table { ++ u8 fver; ++ u8 tbl_num; ++ u8 buf[]; ++} __packed; ++ ++#define BTF_SET_MON_REG_VER 1 ++struct rtw89_btc_btf_set_mon_reg { ++ u8 fver; ++ u8 reg_num; ++ u8 buf[]; ++} __packed; ++ ++enum btc_btf_set_cx_policy { ++ CXPOLICY_TDMA = 0x0, ++ CXPOLICY_SLOT = 0x1, ++ CXPOLICY_TYPE = 0x2, ++ CXPOLICY_MAX, ++}; ++ ++enum btc_b2w_scoreboard { ++ BTC_BSCB_ACT = BIT(0), ++ BTC_BSCB_ON = BIT(1), ++ BTC_BSCB_WHQL = BIT(2), ++ BTC_BSCB_BT_S1 = BIT(3), ++ BTC_BSCB_A2DP_ACT = BIT(4), ++ BTC_BSCB_RFK_RUN = BIT(5), ++ BTC_BSCB_RFK_REQ = BIT(6), ++ BTC_BSCB_LPS = BIT(7), ++ BTC_BSCB_WLRFK = BIT(11), ++ BTC_BSCB_BT_HILNA = BIT(13), ++ BTC_BSCB_BT_CONNECT = BIT(16), ++ BTC_BSCB_PATCH_CODE = BIT(30), ++ BTC_BSCB_ALL = GENMASK(30, 0), ++}; ++ ++enum btc_phymap { ++ BTC_PHY_0 = BIT(0), ++ BTC_PHY_1 = BIT(1), ++ BTC_PHY_ALL = BIT(0) | BIT(1), ++}; ++ ++enum btc_cx_state_map { ++ BTC_WIDLE = 0, ++ BTC_WBUSY_BNOSCAN, ++ BTC_WBUSY_BSCAN, ++ BTC_WSCAN_BNOSCAN, ++ BTC_WSCAN_BSCAN, ++ BTC_WLINKING ++}; ++ ++enum btc_ant_phase { ++ BTC_ANT_WPOWERON = 0, ++ BTC_ANT_WINIT, ++ BTC_ANT_WONLY, ++ BTC_ANT_WOFF, ++ BTC_ANT_W2G, ++ BTC_ANT_W5G, ++ BTC_ANT_W25G, ++ BTC_ANT_FREERUN, ++ BTC_ANT_WRFK, ++ BTC_ANT_BRFK, ++ BTC_ANT_MAX ++}; ++ ++enum btc_plt { ++ BTC_PLT_NONE = 0, ++ BTC_PLT_LTE_RX = BIT(0), ++ BTC_PLT_GNT_BT_TX = BIT(1), ++ BTC_PLT_GNT_BT_RX = BIT(2), ++ BTC_PLT_GNT_WL = BIT(3), ++ BTC_PLT_BT = BIT(1) | BIT(2), ++ BTC_PLT_ALL = 0xf ++}; ++ ++enum btc_cx_poicy_main_type { ++ BTC_CXP_OFF = 0, ++ BTC_CXP_OFFB, ++ BTC_CXP_OFFE, ++ BTC_CXP_FIX, ++ BTC_CXP_PFIX, ++ BTC_CXP_AUTO, ++ BTC_CXP_PAUTO, ++ BTC_CXP_AUTO2, ++ BTC_CXP_PAUTO2, ++ BTC_CXP_MANUAL, ++ BTC_CXP_USERDEF0, ++ BTC_CXP_MAIN_MAX ++}; ++ ++enum btc_cx_poicy_type { ++ /* TDMA off + pri: BT > WL */ ++ BTC_CXP_OFF_BT = (BTC_CXP_OFF << 8) | 0, ++ ++ /* TDMA off + pri: WL > BT */ ++ BTC_CXP_OFF_WL = (BTC_CXP_OFF << 8) | 1, ++ ++ /* TDMA off + pri: BT = WL */ ++ BTC_CXP_OFF_EQ0 = (BTC_CXP_OFF << 8) | 2, ++ ++ /* TDMA off + pri: BT = WL > BT_Lo */ ++ BTC_CXP_OFF_EQ1 = (BTC_CXP_OFF << 8) | 3, ++ ++ /* TDMA off + pri: WL = BT, BT_Rx > WL_Lo_Tx */ ++ BTC_CXP_OFF_EQ2 = (BTC_CXP_OFF << 8) | 4, ++ ++ /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ ++ BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5, ++ ++ /* TDMA off + pri: BT_Hi > WL > BT_Lo */ ++ BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 6, ++ ++ /* TDMA off + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */ ++ BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 7, ++ ++ /* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/ ++ BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0, ++ ++ /* TDMA off + Ext-Ctrl + pri: default */ ++ BTC_CXP_OFFE_DEF = (BTC_CXP_OFFE << 8) | 0, ++ ++ /* TDMA off + Ext-Ctrl + pri: E2G-slot block all BT */ ++ BTC_CXP_OFFE_DEF2 = (BTC_CXP_OFFE << 8) | 1, ++ ++ /* TDMA Fix slot-0: W1:B1 = 30:30 */ ++ BTC_CXP_FIX_TD3030 = (BTC_CXP_FIX << 8) | 0, ++ ++ /* TDMA Fix slot-1: W1:B1 = 50:50 */ ++ BTC_CXP_FIX_TD5050 = (BTC_CXP_FIX << 8) | 1, ++ ++ /* TDMA Fix slot-2: W1:B1 = 20:30 */ ++ BTC_CXP_FIX_TD2030 = (BTC_CXP_FIX << 8) | 2, ++ ++ /* TDMA Fix slot-3: W1:B1 = 40:10 */ ++ BTC_CXP_FIX_TD4010 = (BTC_CXP_FIX << 8) | 3, ++ ++ /* TDMA Fix slot-4: W1:B1 = 70:10 */ ++ BTC_CXP_FIX_TD7010 = (BTC_CXP_FIX << 8) | 4, ++ ++ /* TDMA Fix slot-5: W1:B1 = 20:60 */ ++ BTC_CXP_FIX_TD2060 = (BTC_CXP_FIX << 8) | 5, ++ ++ /* TDMA Fix slot-6: W1:B1 = 30:60 */ ++ BTC_CXP_FIX_TD3060 = (BTC_CXP_FIX << 8) | 6, ++ ++ /* TDMA Fix slot-7: W1:B1 = 20:80 */ ++ BTC_CXP_FIX_TD2080 = (BTC_CXP_FIX << 8) | 7, ++ ++ /* TDMA Fix slot-8: W1:B1 = user-define */ ++ BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8, ++ ++ /* TDMA Fix slot-9: W1:B1 = 40:20 */ ++ BTC_CXP_FIX_TD4020 = (BTC_CXP_FIX << 8) | 9, ++ ++ /* PS-TDMA Fix slot-0: W1:B1 = 30:30 */ ++ BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0, ++ ++ /* PS-TDMA Fix slot-1: W1:B1 = 50:50 */ ++ BTC_CXP_PFIX_TD5050 = (BTC_CXP_PFIX << 8) | 1, ++ ++ /* PS-TDMA Fix slot-2: W1:B1 = 20:30 */ ++ BTC_CXP_PFIX_TD2030 = (BTC_CXP_PFIX << 8) | 2, ++ ++ /* PS-TDMA Fix slot-3: W1:B1 = 20:60 */ ++ BTC_CXP_PFIX_TD2060 = (BTC_CXP_PFIX << 8) | 3, ++ ++ /* PS-TDMA Fix slot-4: W1:B1 = 30:70 */ ++ BTC_CXP_PFIX_TD3070 = (BTC_CXP_PFIX << 8) | 4, ++ ++ /* PS-TDMA Fix slot-5: W1:B1 = 20:80 */ ++ BTC_CXP_PFIX_TD2080 = (BTC_CXP_PFIX << 8) | 5, ++ ++ /* PS-TDMA Fix slot-6: W1:B1 = user-define */ ++ BTC_CXP_PFIX_TDW1B1 = (BTC_CXP_PFIX << 8) | 6, ++ ++ /* TDMA Auto slot-0: W1:B1 = 50:200 */ ++ BTC_CXP_AUTO_TD50200 = (BTC_CXP_AUTO << 8) | 0, ++ ++ /* TDMA Auto slot-1: W1:B1 = 60:200 */ ++ BTC_CXP_AUTO_TD60200 = (BTC_CXP_AUTO << 8) | 1, ++ ++ /* TDMA Auto slot-2: W1:B1 = 20:200 */ ++ BTC_CXP_AUTO_TD20200 = (BTC_CXP_AUTO << 8) | 2, ++ ++ /* TDMA Auto slot-3: W1:B1 = user-define */ ++ BTC_CXP_AUTO_TDW1B1 = (BTC_CXP_AUTO << 8) | 3, ++ ++ /* PS-TDMA Auto slot-0: W1:B1 = 50:200 */ ++ BTC_CXP_PAUTO_TD50200 = (BTC_CXP_PAUTO << 8) | 0, ++ ++ /* PS-TDMA Auto slot-1: W1:B1 = 60:200 */ ++ BTC_CXP_PAUTO_TD60200 = (BTC_CXP_PAUTO << 8) | 1, ++ ++ /* PS-TDMA Auto slot-2: W1:B1 = 20:200 */ ++ BTC_CXP_PAUTO_TD20200 = (BTC_CXP_PAUTO << 8) | 2, ++ ++ /* PS-TDMA Auto slot-3: W1:B1 = user-define */ ++ BTC_CXP_PAUTO_TDW1B1 = (BTC_CXP_PAUTO << 8) | 3, ++ ++ /* TDMA Auto slot2-0: W1:B4 = 30:50 */ ++ BTC_CXP_AUTO2_TD3050 = (BTC_CXP_AUTO2 << 8) | 0, ++ ++ /* TDMA Auto slot2-1: W1:B4 = 30:70 */ ++ BTC_CXP_AUTO2_TD3070 = (BTC_CXP_AUTO2 << 8) | 1, ++ ++ /* TDMA Auto slot2-2: W1:B4 = 50:50 */ ++ BTC_CXP_AUTO2_TD5050 = (BTC_CXP_AUTO2 << 8) | 2, ++ ++ /* TDMA Auto slot2-3: W1:B4 = 60:60 */ ++ BTC_CXP_AUTO2_TD6060 = (BTC_CXP_AUTO2 << 8) | 3, ++ ++ /* TDMA Auto slot2-4: W1:B4 = 20:80 */ ++ BTC_CXP_AUTO2_TD2080 = (BTC_CXP_AUTO2 << 8) | 4, ++ ++ /* TDMA Auto slot2-5: W1:B4 = user-define */ ++ BTC_CXP_AUTO2_TDW1B4 = (BTC_CXP_AUTO2 << 8) | 5, ++ ++ /* PS-TDMA Auto slot2-0: W1:B4 = 30:50 */ ++ BTC_CXP_PAUTO2_TD3050 = (BTC_CXP_PAUTO2 << 8) | 0, ++ ++ /* PS-TDMA Auto slot2-1: W1:B4 = 30:70 */ ++ BTC_CXP_PAUTO2_TD3070 = (BTC_CXP_PAUTO2 << 8) | 1, ++ ++ /* PS-TDMA Auto slot2-2: W1:B4 = 50:50 */ ++ BTC_CXP_PAUTO2_TD5050 = (BTC_CXP_PAUTO2 << 8) | 2, ++ ++ /* PS-TDMA Auto slot2-3: W1:B4 = 60:60 */ ++ BTC_CXP_PAUTO2_TD6060 = (BTC_CXP_PAUTO2 << 8) | 3, ++ ++ /* PS-TDMA Auto slot2-4: W1:B4 = 20:80 */ ++ BTC_CXP_PAUTO2_TD2080 = (BTC_CXP_PAUTO2 << 8) | 4, ++ ++ /* PS-TDMA Auto slot2-5: W1:B4 = user-define */ ++ BTC_CXP_PAUTO2_TDW1B4 = (BTC_CXP_PAUTO2 << 8) | 5, ++ ++ BTC_CXP_MAX = 0xffff ++}; ++ ++enum btc_wl_rfk_result { ++ BTC_WRFK_REJECT = 0, ++ BTC_WRFK_ALLOW = 1, ++}; ++ ++enum btc_coex_info_map_en { ++ BTC_COEX_INFO_CX = BIT(0), ++ BTC_COEX_INFO_WL = BIT(1), ++ BTC_COEX_INFO_BT = BIT(2), ++ BTC_COEX_INFO_DM = BIT(3), ++ BTC_COEX_INFO_MREG = BIT(4), ++ BTC_COEX_INFO_SUMMARY = BIT(5), ++ BTC_COEX_INFO_ALL = GENMASK(7, 0), ++}; ++ ++#define BTC_CXP_MASK GENMASK(15, 8) ++ ++enum btc_w2b_scoreboard { ++ BTC_WSCB_ACTIVE = BIT(0), ++ BTC_WSCB_ON = BIT(1), ++ BTC_WSCB_SCAN = BIT(2), ++ BTC_WSCB_UNDERTEST = BIT(3), ++ BTC_WSCB_RXGAIN = BIT(4), ++ BTC_WSCB_WLBUSY = BIT(7), ++ BTC_WSCB_EXTFEM = BIT(8), ++ BTC_WSCB_TDMA = BIT(9), ++ BTC_WSCB_FIX2M = BIT(10), ++ BTC_WSCB_WLRFK = BIT(11), ++ BTC_WSCB_BTRFK_GNT = BIT(12), /* not used, use mailbox to inform BT */ ++ BTC_WSCB_BT_HILNA = BIT(13), ++ BTC_WSCB_BTLOG = BIT(14), ++ BTC_WSCB_ALL = GENMASK(23, 0), ++}; ++ ++enum btc_wl_link_mode { ++ BTC_WLINK_NOLINK = 0x0, ++ BTC_WLINK_2G_STA, ++ BTC_WLINK_2G_AP, ++ BTC_WLINK_2G_GO, ++ BTC_WLINK_2G_GC, ++ BTC_WLINK_2G_SCC, ++ BTC_WLINK_2G_MCC, ++ BTC_WLINK_25G_MCC, ++ BTC_WLINK_25G_DBCC, ++ BTC_WLINK_5G, ++ BTC_WLINK_2G_NAN, ++ BTC_WLINK_OTHER, ++ BTC_WLINK_MAX ++}; ++ ++enum btc_bt_hid_type { ++ BTC_HID_218 = BIT(0), ++ BTC_HID_418 = BIT(1), ++ BTC_HID_BLE = BIT(2), ++ BTC_HID_RCU = BIT(3), ++ BTC_HID_RCU_VOICE = BIT(4), ++ BTC_HID_OTHER_LEGACY = BIT(5) ++}; ++ ++enum btc_reset_module { ++ BTC_RESET_CX = BIT(0), ++ BTC_RESET_DM = BIT(1), ++ BTC_RESET_CTRL = BIT(2), ++ BTC_RESET_CXDM = BIT(0) | BIT(1), ++ BTC_RESET_BTINFO = BIT(3), ++ BTC_RESET_MDINFO = BIT(4), ++ BTC_RESET_ALL = GENMASK(7, 0), ++}; ++ ++enum btc_gnt_state { ++ BTC_GNT_HW = 0, ++ BTC_GNT_SW_LO, ++ BTC_GNT_SW_HI, ++ BTC_GNT_MAX ++}; ++ ++enum btc_wl_max_tx_time { ++ BTC_MAX_TX_TIME_L1 = 500, ++ BTC_MAX_TX_TIME_L2 = 1000, ++ BTC_MAX_TX_TIME_L3 = 2000, ++ BTC_MAX_TX_TIME_DEF = 5280 ++}; ++ ++enum btc_wl_max_tx_retry { ++ BTC_MAX_TX_RETRY_L1 = 7, ++ BTC_MAX_TX_RETRY_L2 = 15, ++ BTC_MAX_TX_RETRY_DEF = 31, ++}; ++ ++enum btc_reason_and_action { ++ BTC_RSN_NONE, ++ BTC_RSN_NTFY_INIT, ++ BTC_RSN_NTFY_SWBAND, ++ BTC_RSN_NTFY_WL_STA, ++ BTC_RSN_NTFY_RADIO_STATE, ++ BTC_RSN_UPDATE_BT_SCBD, ++ BTC_RSN_NTFY_WL_RFK, ++ BTC_RSN_UPDATE_BT_INFO, ++ BTC_RSN_NTFY_SCAN_START, ++ BTC_RSN_NTFY_SCAN_FINISH, ++ BTC_RSN_NTFY_SPECIFIC_PACKET, ++ BTC_RSN_NTFY_POWEROFF, ++ BTC_RSN_NTFY_ROLE_INFO, ++ BTC_RSN_CMD_SET_COEX, ++ BTC_RSN_ACT1_WORK, ++ BTC_RSN_BT_DEVINFO_WORK, ++ BTC_RSN_RFK_CHK_WORK, ++ BTC_RSN_NUM, ++ BTC_ACT_NONE = 100, ++ BTC_ACT_WL_ONLY, ++ BTC_ACT_WL_5G, ++ BTC_ACT_WL_OTHER, ++ BTC_ACT_WL_IDLE, ++ BTC_ACT_WL_NC, ++ BTC_ACT_WL_RFK, ++ BTC_ACT_WL_INIT, ++ BTC_ACT_WL_OFF, ++ BTC_ACT_FREERUN, ++ BTC_ACT_BT_WHQL, ++ BTC_ACT_BT_RFK, ++ BTC_ACT_BT_OFF, ++ BTC_ACT_BT_IDLE, ++ BTC_ACT_BT_HFP, ++ BTC_ACT_BT_HID, ++ BTC_ACT_BT_A2DP, ++ BTC_ACT_BT_A2DPSINK, ++ BTC_ACT_BT_PAN, ++ BTC_ACT_BT_A2DP_HID, ++ BTC_ACT_BT_A2DP_PAN, ++ BTC_ACT_BT_PAN_HID, ++ BTC_ACT_BT_A2DP_PAN_HID, ++ BTC_ACT_WL_25G_MCC, ++ BTC_ACT_WL_2G_MCC, ++ BTC_ACT_WL_2G_SCC, ++ BTC_ACT_WL_2G_AP, ++ BTC_ACT_WL_2G_GO, ++ BTC_ACT_WL_2G_GC, ++ BTC_ACT_WL_2G_NAN, ++ BTC_ACT_LAST, ++ BTC_ACT_NUM = BTC_ACT_LAST - BTC_ACT_NONE, ++ BTC_ACT_EXT_BIT = BIT(14), ++ BTC_POLICY_EXT_BIT = BIT(15), ++}; ++ ++#define BTC_FREERUN_ANTISO_MIN 30 ++#define BTC_TDMA_BTHID_MAX 2 ++#define BTC_BLINK_NOCONNECT 0 ++ ++static void _run_coex(struct rtw89_dev *rtwdev, ++ enum btc_reason_and_action reason); ++static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state); ++static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update); ++ ++static void _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, ++ void *param, u16 len) ++{ ++ rtw89_fw_h2c_raw_with_hdr(rtwdev, h2c_class, h2c_func, param, len, ++ false, true); ++} ++ ++static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s\n", __func__); ++ ++ if (type & BTC_RESET_CX) ++ memset(cx, 0, sizeof(*cx)); ++ else if (type & BTC_RESET_BTINFO) /* only for BT enable */ ++ memset(bt, 0, sizeof(*bt)); ++ ++ if (type & BTC_RESET_CTRL) { ++ memset(&btc->ctrl, 0, sizeof(btc->ctrl)); ++ btc->ctrl.trace_step = FCXDEF_STEP; ++ } ++ ++ /* Init Coex variables that are not zero */ ++ if (type & BTC_RESET_DM) { ++ memset(&btc->dm, 0, sizeof(btc->dm)); ++ memset(bt_linfo->rssi_state, 0, sizeof(bt_linfo->rssi_state)); ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) ++ memset(wl_linfo[i].rssi_state, 0, ++ sizeof(wl_linfo[i].rssi_state)); ++ ++ /* set the slot_now table to original */ ++ btc->dm.tdma_now = t_def[CXTD_OFF]; ++ btc->dm.tdma = t_def[CXTD_OFF]; ++ memcpy(&btc->dm.slot_now, s_def, sizeof(btc->dm.slot_now)); ++ memcpy(&btc->dm.slot, s_def, sizeof(btc->dm.slot)); ++ ++ btc->policy_len = 0; ++ btc->bt_req_len = 0; ++ ++ btc->dm.coex_info_map = BTC_COEX_INFO_ALL; ++ btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF; ++ btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF; ++ } ++ ++ if (type & BTC_RESET_MDINFO) ++ memset(&btc->mdinfo, 0, sizeof(btc->mdinfo)); ++} ++ ++#define BTC_FWINFO_BUF 1024 ++ ++#define BTC_RPT_HDR_SIZE 3 ++#define BTC_CHK_WLSLOT_DRIFT_MAX 15 ++#define BTC_CHK_HANG_MAX 3 ++ ++static void _chk_btc_err(struct rtw89_dev *rtwdev, u8 type, u32 cnt) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): type:%d cnt:%d\n", ++ __func__, type, cnt); ++ ++ switch (type) { ++ case BTC_DCNT_RPT_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_RPT] == cnt && btc->fwinfo.rpt_en_map) ++ dm->cnt_dm[BTC_DCNT_RPT_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_RPT_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_RPT_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.wl_fw_hang = true; ++ else ++ dm->error.map.wl_fw_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_RPT] = cnt; ++ break; ++ case BTC_DCNT_CYCLE_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_CYCLE] == cnt && ++ (dm->tdma_now.type != CXTDMA_OFF || ++ dm->tdma_now.ext_ctrl == CXECTL_EXT)) ++ dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_CYCLE_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.cycle_hang = true; ++ else ++ dm->error.map.cycle_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_CYCLE] = cnt; ++ break; ++ case BTC_DCNT_W1_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_W1] == cnt && ++ dm->tdma_now.type != CXTDMA_OFF) ++ dm->cnt_dm[BTC_DCNT_W1_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_W1_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_W1_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.w1_hang = true; ++ else ++ dm->error.map.w1_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_W1] = cnt; ++ break; ++ case BTC_DCNT_B1_FREEZE: ++ if (dm->cnt_dm[BTC_DCNT_B1] == cnt && ++ dm->tdma_now.type != CXTDMA_OFF) ++ dm->cnt_dm[BTC_DCNT_B1_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_B1_FREEZE] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_B1_FREEZE] >= BTC_CHK_HANG_MAX) ++ dm->error.map.b1_hang = true; ++ else ++ dm->error.map.b1_hang = false; ++ ++ dm->cnt_dm[BTC_DCNT_B1] = cnt; ++ break; ++ case BTC_DCNT_TDMA_NONSYNC: ++ if (cnt != 0) /* if tdma not sync between drv/fw */ ++ dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC]++; ++ else ++ dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] >= BTC_CHK_HANG_MAX) ++ dm->error.map.tdma_no_sync = true; ++ else ++ dm->error.map.tdma_no_sync = false; ++ break; ++ case BTC_DCNT_SLOT_NONSYNC: ++ if (cnt != 0) /* if slot not sync between drv/fw */ ++ dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC]++; ++ else ++ dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] >= BTC_CHK_HANG_MAX) ++ dm->error.map.tdma_no_sync = true; ++ else ++ dm->error.map.tdma_no_sync = false; ++ break; ++ case BTC_DCNT_BTCNT_FREEZE: ++ cnt = cx->cnt_bt[BTC_BCNT_HIPRI_RX] + ++ cx->cnt_bt[BTC_BCNT_HIPRI_TX] + ++ cx->cnt_bt[BTC_BCNT_LOPRI_RX] + ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX]; ++ ++ if (cnt == 0) ++ dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE]++; ++ else ++ dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] = 0; ++ ++ if ((dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX && ++ bt->enable.now) || (!dm->cnt_dm[BTC_DCNT_BTCNT_FREEZE] && ++ !bt->enable.now)) ++ _update_bt_scbd(rtwdev, false); ++ break; ++ case BTC_DCNT_WL_SLOT_DRIFT: ++ if (cnt >= BTC_CHK_WLSLOT_DRIFT_MAX) ++ dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT]++; ++ else ++ dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] = 0; ++ ++ if (dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] >= BTC_CHK_HANG_MAX) ++ dm->error.map.wl_slot_drift = true; ++ else ++ dm->error.map.wl_slot_drift = false; ++ break; ++ } ++} ++ ++static void _update_bt_report(struct rtw89_dev *rtwdev, u8 rpt_type, u8 *pfinfo) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &bt_linfo->a2dp_desc; ++ struct rtw89_btc_fbtc_btver *pver = NULL; ++ struct rtw89_btc_fbtc_btscan *pscan = NULL; ++ struct rtw89_btc_fbtc_btafh *pafh = NULL; ++ struct rtw89_btc_fbtc_btdevinfo *pdev = NULL; ++ ++ pver = (struct rtw89_btc_fbtc_btver *)pfinfo; ++ pscan = (struct rtw89_btc_fbtc_btscan *)pfinfo; ++ pafh = (struct rtw89_btc_fbtc_btafh *)pfinfo; ++ pdev = (struct rtw89_btc_fbtc_btdevinfo *)pfinfo; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_type:%d\n", ++ __func__, rpt_type); ++ ++ switch (rpt_type) { ++ case BTC_RPT_TYPE_BT_VER: ++ bt->ver_info.fw = le32_to_cpu(pver->fw_ver); ++ bt->ver_info.fw_coex = le32_get_bits(pver->coex_ver, GENMASK(7, 0)); ++ bt->feature = le32_to_cpu(pver->feature); ++ break; ++ case BTC_RPT_TYPE_BT_SCAN: ++ memcpy(bt->scan_info, pscan->scan, BTC_SCAN_MAX1); ++ break; ++ case BTC_RPT_TYPE_BT_AFH: ++ memcpy(&bt_linfo->afh_map[0], pafh->afh_l, 4); ++ memcpy(&bt_linfo->afh_map[4], pafh->afh_m, 4); ++ memcpy(&bt_linfo->afh_map[8], pafh->afh_h, 2); ++ break; ++ case BTC_RPT_TYPE_BT_DEVICE: ++ a2dp->device_name = le32_to_cpu(pdev->dev_name); ++ a2dp->vendor_id = le16_to_cpu(pdev->vendor_id); ++ a2dp->flush_time = le32_to_cpu(pdev->flush_time); ++ break; ++ default: ++ break; ++ } ++} ++ ++struct rtw89_btc_fbtc_cysta_cpu { ++ u8 fver; ++ u8 rsvd; ++ u16 cycles; ++ u16 cycles_a2dp[CXT_FLCTRL_MAX]; ++ u16 a2dpept; ++ u16 a2dpeptto; ++ u16 tavg_cycle[CXT_MAX]; ++ u16 tmax_cycle[CXT_MAX]; ++ u16 tmaxdiff_cycle[CXT_MAX]; ++ u16 tavg_a2dp[CXT_FLCTRL_MAX]; ++ u16 tmax_a2dp[CXT_FLCTRL_MAX]; ++ u16 tavg_a2dpept; ++ u16 tmax_a2dpept; ++ u16 tavg_lk; ++ u16 tmax_lk; ++ u32 slot_cnt[CXST_MAX]; ++ u32 bcn_cnt[CXBCN_MAX]; ++ u32 leakrx_cnt; ++ u32 collision_cnt; ++ u32 skip_cnt; ++ u32 exception; ++ u32 except_cnt; ++ u16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; ++}; ++ ++static void rtw89_btc_fbtc_cysta_to_cpu(const struct rtw89_btc_fbtc_cysta *src, ++ struct rtw89_btc_fbtc_cysta_cpu *dst) ++{ ++ static_assert(sizeof(*src) == sizeof(*dst)); ++ ++#define __CPY_U8(_x) ({dst->_x = src->_x; }) ++#define __CPY_LE16(_x) ({dst->_x = le16_to_cpu(src->_x); }) ++#define __CPY_LE16S(_x) ({int _i; for (_i = 0; _i < ARRAY_SIZE(dst->_x); _i++) \ ++ dst->_x[_i] = le16_to_cpu(src->_x[_i]); }) ++#define __CPY_LE32(_x) ({dst->_x = le32_to_cpu(src->_x); }) ++#define __CPY_LE32S(_x) ({int _i; for (_i = 0; _i < ARRAY_SIZE(dst->_x); _i++) \ ++ dst->_x[_i] = le32_to_cpu(src->_x[_i]); }) ++ ++ __CPY_U8(fver); ++ __CPY_U8(rsvd); ++ __CPY_LE16(cycles); ++ __CPY_LE16S(cycles_a2dp); ++ __CPY_LE16(a2dpept); ++ __CPY_LE16(a2dpeptto); ++ __CPY_LE16S(tavg_cycle); ++ __CPY_LE16S(tmax_cycle); ++ __CPY_LE16S(tmaxdiff_cycle); ++ __CPY_LE16S(tavg_a2dp); ++ __CPY_LE16S(tmax_a2dp); ++ __CPY_LE16(tavg_a2dpept); ++ __CPY_LE16(tmax_a2dpept); ++ __CPY_LE16(tavg_lk); ++ __CPY_LE16(tmax_lk); ++ __CPY_LE32S(slot_cnt); ++ __CPY_LE32S(bcn_cnt); ++ __CPY_LE32(leakrx_cnt); ++ __CPY_LE32(collision_cnt); ++ __CPY_LE32(skip_cnt); ++ __CPY_LE32(exception); ++ __CPY_LE32(except_cnt); ++ __CPY_LE16S(tslot_cycle); ++ ++#undef __CPY_U8 ++#undef __CPY_LE16 ++#undef __CPY_LE16S ++#undef __CPY_LE32 ++#undef __CPY_LE32S ++} ++ ++#define BTC_LEAK_AP_TH 10 ++#define BTC_CYSTA_CHK_PERIOD 100 ++ ++struct rtw89_btc_prpt { ++ u8 type; ++ __le16 len; ++ u8 content[]; ++} __packed; ++ ++static u32 _chk_btc_report(struct rtw89_dev *rtwdev, ++ struct rtw89_btc_btf_fwinfo *pfwinfo, ++ u8 *prptbuf, u32 index) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_fbtc_rpt_ctrl *prpt = NULL; ++ struct rtw89_btc_fbtc_cysta *pcysta_le32 = NULL; ++ struct rtw89_btc_fbtc_cysta_cpu pcysta[1]; ++ struct rtw89_btc_prpt *btc_prpt = NULL; ++ struct rtw89_btc_fbtc_slot *rtp_slot = NULL; ++ u8 rpt_type = 0, *rpt_content = NULL, *pfinfo = NULL; ++ u16 wl_slot_set = 0; ++ u32 trace_step = btc->ctrl.trace_step, rpt_len = 0, diff_t; ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): index:%d\n", ++ __func__, index); ++ ++ if (!prptbuf) { ++ pfwinfo->err[BTFRE_INVALID_INPUT]++; ++ return 0; ++ } ++ ++ btc_prpt = (struct rtw89_btc_prpt *)&prptbuf[index]; ++ rpt_type = btc_prpt->type; ++ rpt_len = le16_to_cpu(btc_prpt->len); ++ rpt_content = btc_prpt->content; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_type:%d\n", ++ __func__, rpt_type); ++ ++ switch (rpt_type) { ++ case BTC_RPT_TYPE_CTRL: ++ pcinfo = &pfwinfo->rpt_ctrl.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_ctrl.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo); ++ pcinfo->req_fver = BTCRPT_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_TDMA: ++ pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_tdma.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_tdma.finfo); ++ pcinfo->req_fver = FCXTDMA_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_SLOT: ++ pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_slots.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_slots.finfo); ++ pcinfo->req_fver = FCXSLOTS_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_CYSTA: ++ pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_cysta.finfo); ++ pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo; ++ rtw89_btc_fbtc_cysta_to_cpu(pcysta_le32, pcysta); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo); ++ pcinfo->req_fver = FCXCYSTA_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_STEP: ++ pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_step.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_step.finfo.step[0]) * ++ trace_step + 8; ++ pcinfo->req_fver = FCXSTEP_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_NULLSTA: ++ pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_nullsta.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_nullsta.finfo); ++ pcinfo->req_fver = FCXNULLSTA_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_MREG: ++ pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_mregval.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_mregval.finfo); ++ pcinfo->req_fver = FCXMREG_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_GPIO_DBG: ++ pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_gpio_dbg.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_gpio_dbg.finfo); ++ pcinfo->req_fver = FCXGPIODBG_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_VER: ++ pcinfo = &pfwinfo->rpt_fbtc_btver.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btver.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btver.finfo); ++ pcinfo->req_fver = FCX_BTVER_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_SCAN: ++ pcinfo = &pfwinfo->rpt_fbtc_btscan.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btscan.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btscan.finfo); ++ pcinfo->req_fver = FCX_BTSCAN_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_AFH: ++ pcinfo = &pfwinfo->rpt_fbtc_btafh.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btafh.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btafh.finfo); ++ pcinfo->req_fver = FCX_BTAFH_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ case BTC_RPT_TYPE_BT_DEVICE: ++ pcinfo = &pfwinfo->rpt_fbtc_btdev.cinfo; ++ pfinfo = (u8 *)(&pfwinfo->rpt_fbtc_btdev.finfo); ++ pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btdev.finfo); ++ pcinfo->req_fver = FCX_BTDEVINFO_VER; ++ pcinfo->rx_len = rpt_len; ++ pcinfo->rx_cnt++; ++ break; ++ default: ++ pfwinfo->err[BTFRE_UNDEF_TYPE]++; ++ return 0; ++ } ++ ++ if (rpt_len != pcinfo->req_len) { ++ if (rpt_type < BTC_RPT_TYPE_MAX) ++ pfwinfo->len_mismch |= (0x1 << rpt_type); ++ else ++ pfwinfo->len_mismch |= BIT(31); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d rpt_len:%d!=req_len:%d\n", ++ __func__, rpt_type, rpt_len, pcinfo->req_len); ++ ++ pcinfo->valid = 0; ++ return 0; ++ } else if (!pfinfo || !rpt_content || !pcinfo->req_len) { ++ pfwinfo->err[BTFRE_EXCEPTION]++; ++ pcinfo->valid = 0; ++ return 0; ++ } ++ ++ memcpy(pfinfo, rpt_content, pcinfo->req_len); ++ pcinfo->valid = 1; ++ ++ if (rpt_type == BTC_RPT_TYPE_TDMA) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): check %d %zu\n", __func__, ++ BTC_DCNT_TDMA_NONSYNC, sizeof(dm->tdma_now)); ++ ++ if (memcmp(&dm->tdma_now, &pfwinfo->rpt_fbtc_tdma.finfo, ++ sizeof(dm->tdma_now)) != 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d tdma_now %x %x %x %x %x %x %x %x\n", ++ __func__, BTC_DCNT_TDMA_NONSYNC, ++ dm->tdma_now.type, dm->tdma_now.rxflctrl, ++ dm->tdma_now.txpause, dm->tdma_now.wtgle_n, ++ dm->tdma_now.leak_n, dm->tdma_now.ext_ctrl, ++ dm->tdma_now.rsvd0, dm->tdma_now.rsvd1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d rpt_fbtc_tdma %x %x %x %x %x %x %x %x\n", ++ __func__, BTC_DCNT_TDMA_NONSYNC, ++ pfwinfo->rpt_fbtc_tdma.finfo.type, ++ pfwinfo->rpt_fbtc_tdma.finfo.rxflctrl, ++ pfwinfo->rpt_fbtc_tdma.finfo.txpause, ++ pfwinfo->rpt_fbtc_tdma.finfo.wtgle_n, ++ pfwinfo->rpt_fbtc_tdma.finfo.leak_n, ++ pfwinfo->rpt_fbtc_tdma.finfo.ext_ctrl, ++ pfwinfo->rpt_fbtc_tdma.finfo.rsvd0, ++ pfwinfo->rpt_fbtc_tdma.finfo.rsvd1); ++ } ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_TDMA_NONSYNC, ++ memcmp(&dm->tdma_now, ++ &pfwinfo->rpt_fbtc_tdma.finfo, ++ sizeof(dm->tdma_now))); ++ } ++ ++ if (rpt_type == BTC_RPT_TYPE_SLOT) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): check %d %zu\n", ++ __func__, BTC_DCNT_SLOT_NONSYNC, ++ sizeof(dm->slot_now)); ++ ++ if (memcmp(dm->slot_now, pfwinfo->rpt_fbtc_slots.finfo.slot, ++ sizeof(dm->slot_now)) != 0) { ++ for (i = 0; i < CXST_MAX; i++) { ++ rtp_slot = ++ &pfwinfo->rpt_fbtc_slots.finfo.slot[i]; ++ if (memcmp(&dm->slot_now[i], rtp_slot, ++ sizeof(dm->slot_now[i])) != 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d slot_now[%d] dur=0x%04x tbl=%08x type=0x%04x\n", ++ __func__, ++ BTC_DCNT_SLOT_NONSYNC, i, ++ dm->slot_now[i].dur, ++ dm->slot_now[i].cxtbl, ++ dm->slot_now[i].cxtype); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): %d rpt_fbtc_slots[%d] dur=0x%04x tbl=%08x type=0x%04x\n", ++ __func__, ++ BTC_DCNT_SLOT_NONSYNC, i, ++ rtp_slot->dur, ++ rtp_slot->cxtbl, ++ rtp_slot->cxtype); ++ } ++ } ++ } ++ _chk_btc_err(rtwdev, BTC_DCNT_SLOT_NONSYNC, ++ memcmp(dm->slot_now, ++ pfwinfo->rpt_fbtc_slots.finfo.slot, ++ sizeof(dm->slot_now))); ++ } ++ ++ if (rpt_type == BTC_RPT_TYPE_CYSTA && ++ pcysta->cycles >= BTC_CYSTA_CHK_PERIOD) { ++ /* Check Leak-AP */ ++ if (pcysta->slot_cnt[CXST_LK] != 0 && ++ pcysta->leakrx_cnt != 0 && dm->tdma_now.rxflctrl) { ++ if (pcysta->slot_cnt[CXST_LK] < ++ BTC_LEAK_AP_TH * pcysta->leakrx_cnt) ++ dm->leak_ap = 1; ++ } ++ ++ /* Check diff time between WL slot and W1/E2G slot */ ++ if (dm->tdma_now.type == CXTDMA_OFF && ++ dm->tdma_now.ext_ctrl == CXECTL_EXT) ++ wl_slot_set = le16_to_cpu(dm->slot_now[CXST_E2G].dur); ++ else ++ wl_slot_set = le16_to_cpu(dm->slot_now[CXST_W1].dur); ++ ++ if (pcysta->tavg_cycle[CXT_WL] > wl_slot_set) { ++ diff_t = pcysta->tavg_cycle[CXT_WL] - wl_slot_set; ++ _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t); ++ } ++ } ++ ++ if (rpt_type == BTC_RPT_TYPE_CTRL) { ++ prpt = &pfwinfo->rpt_ctrl.finfo; ++ btc->fwinfo.rpt_en_map = prpt->rpt_enable; ++ wl->ver_info.fw_coex = prpt->wl_fw_coex_ver; ++ wl->ver_info.fw = prpt->wl_fw_ver; ++ dm->wl_fw_cx_offload = !!(prpt->wl_fw_cx_offload); ++ } ++ ++ if (rpt_type >= BTC_RPT_TYPE_BT_VER && ++ rpt_type <= BTC_RPT_TYPE_BT_DEVICE) ++ _update_bt_report(rtwdev, rpt_type, pfinfo); ++ ++ return (rpt_len + BTC_RPT_HDR_SIZE); ++} ++ ++static void _parse_btc_report(struct rtw89_dev *rtwdev, ++ struct rtw89_btc_btf_fwinfo *pfwinfo, ++ u8 *pbuf, u32 buf_len) ++{ ++ struct rtw89_btc_prpt *btc_prpt = NULL; ++ u32 index = 0, rpt_len = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): buf_len:%d\n", ++ __func__, buf_len); ++ ++ while (pbuf) { ++ btc_prpt = (struct rtw89_btc_prpt *)&pbuf[index]; ++ if (index + 2 >= BTC_FWINFO_BUF) ++ break; ++ /* At least 3 bytes: type(1) & len(2) */ ++ rpt_len = le16_to_cpu(btc_prpt->len); ++ if ((index + rpt_len + BTC_RPT_HDR_SIZE) > buf_len) ++ break; ++ ++ rpt_len = _chk_btc_report(rtwdev, pfwinfo, pbuf, index); ++ if (!rpt_len) ++ break; ++ index += rpt_len; ++ } ++} ++ ++#define BTC_TLV_HDR_LEN 2 ++ ++static void _append_tdma(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_btf_tlv *tlv = NULL; ++ struct rtw89_btc_fbtc_tdma *v = NULL; ++ u16 len = btc->policy_len; ++ ++ if (!btc->update_policy_force && ++ !memcmp(&dm->tdma, &dm->tdma_now, sizeof(dm->tdma))) { ++ rtw89_debug(rtwdev, ++ RTW89_DBG_BTC, "[BTC], %s(): tdma no change!\n", ++ __func__); ++ return; ++ } ++ ++ tlv = (struct rtw89_btc_btf_tlv *)&btc->policy[len]; ++ v = (struct rtw89_btc_fbtc_tdma *)&tlv->val[0]; ++ tlv->type = CXPOLICY_TDMA; ++ tlv->len = sizeof(*v); ++ ++ memcpy(v, &dm->tdma, sizeof(*v)); ++ btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): type:%d, rxflctrl=%d, txpause=%d, wtgle_n=%d, leak_n=%d, ext_ctrl=%d\n", ++ __func__, dm->tdma.type, dm->tdma.rxflctrl, ++ dm->tdma.txpause, dm->tdma.wtgle_n, dm->tdma.leak_n, ++ dm->tdma.ext_ctrl); ++} ++ ++static void _append_slot(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_btf_tlv *tlv = NULL; ++ struct btc_fbtc_1slot *v = NULL; ++ u16 len = 0; ++ u8 i, cnt = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): A:btc->policy_len = %d\n", ++ __func__, btc->policy_len); ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ if (!btc->update_policy_force && ++ !memcmp(&dm->slot[i], &dm->slot_now[i], ++ sizeof(dm->slot[i]))) ++ continue; ++ ++ len = btc->policy_len; ++ ++ tlv = (struct rtw89_btc_btf_tlv *)&btc->policy[len]; ++ v = (struct btc_fbtc_1slot *)&tlv->val[0]; ++ tlv->type = CXPOLICY_SLOT; ++ tlv->len = sizeof(*v); ++ ++ v->fver = FCXONESLOT_VER; ++ v->sid = i; ++ v->slot = dm->slot[i]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): slot-%d: dur=%d, table=0x%08x, type=%d\n", ++ __func__, i, dm->slot[i].dur, dm->slot[i].cxtbl, ++ dm->slot[i].cxtype); ++ cnt++; ++ ++ btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v); ++ } ++ ++ if (cnt > 0) ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): slot update (cnt=%d)!!\n", ++ __func__, cnt); ++} ++ ++static void rtw89_btc_fw_en_rpt(struct rtw89_dev *rtwdev, ++ u32 rpt_map, bool rpt_state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *fwinfo = &btc->fwinfo; ++ struct rtw89_btc_btf_set_report r = {0}; ++ u32 val = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_map=%x, rpt_state=%x\n", ++ __func__, rpt_map, rpt_state); ++ ++ if (rpt_state) ++ val = fwinfo->rpt_en_map | rpt_map; ++ else ++ val = fwinfo->rpt_en_map & ~rpt_map; ++ ++ if (val == fwinfo->rpt_en_map) ++ return; ++ ++ fwinfo->rpt_en_map = val; ++ ++ r.fver = BTF_SET_REPORT_VER; ++ r.enable = cpu_to_le32(val); ++ r.para = cpu_to_le32(rpt_state); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r, sizeof(r)); ++} ++ ++static void rtw89_btc_fw_set_slots(struct rtw89_dev *rtwdev, u8 num, ++ struct rtw89_btc_fbtc_slot *s) ++{ ++ struct rtw89_btc_btf_set_slot_table *tbl = NULL; ++ u8 *ptr = NULL; ++ u16 n = 0; ++ ++ n = sizeof(*s) * num + sizeof(*tbl); ++ tbl = kmalloc(n, GFP_KERNEL); ++ if (!tbl) ++ return; ++ ++ tbl->fver = BTF_SET_SLOT_TABLE_VER; ++ tbl->tbl_num = num; ++ ptr = &tbl->buf[0]; ++ memcpy(ptr, s, num * sizeof(*s)); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_SLOT_TABLE, tbl, n); ++ ++ kfree(tbl); ++} ++ ++static void btc_fw_set_monreg(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc_btf_set_mon_reg *monreg = NULL; ++ u8 n, *ptr = NULL, ulen; ++ u16 sz = 0; ++ ++ n = chip->mon_reg_num; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): mon_reg_num=%d\n", __func__, n); ++ if (n > CXMREG_MAX) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): mon reg count %d > %d\n", ++ __func__, n, CXMREG_MAX); ++ return; ++ } ++ ++ ulen = sizeof(struct rtw89_btc_fbtc_mreg); ++ sz = (ulen * n) + sizeof(*monreg); ++ monreg = kmalloc(sz, GFP_KERNEL); ++ if (!monreg) ++ return; ++ ++ monreg->fver = BTF_SET_MON_REG_VER; ++ monreg->reg_num = n; ++ ptr = &monreg->buf[0]; ++ memcpy(ptr, chip->mon_reg, n * ulen); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): sz=%d ulen=%d n=%d\n", ++ __func__, sz, ulen, n); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_MREG_TABLE, (u8 *)monreg, sz); ++ kfree(monreg); ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_MREG, 1); ++} ++ ++static void _update_dm_step(struct rtw89_dev *rtwdev, ++ enum btc_reason_and_action reason_or_action) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ /* use ring-structure to store dm step */ ++ dm->dm_step.step[dm->dm_step.step_pos] = reason_or_action; ++ dm->dm_step.step_pos++; ++ ++ if (dm->dm_step.step_pos >= ARRAY_SIZE(dm->dm_step.step)) { ++ dm->dm_step.step_pos = 0; ++ dm->dm_step.step_ov = true; ++ } ++} ++ ++static void _fw_set_policy(struct rtw89_dev *rtwdev, u16 policy_type, ++ enum btc_reason_and_action action) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ dm->run_action = action; ++ ++ _update_dm_step(rtwdev, action | BTC_ACT_EXT_BIT); ++ _update_dm_step(rtwdev, policy_type | BTC_POLICY_EXT_BIT); ++ ++ btc->policy_len = 0; ++ btc->policy_type = policy_type; ++ ++ _append_tdma(rtwdev); ++ _append_slot(rtwdev); ++ ++ if (btc->policy_len == 0 || btc->policy_len > RTW89_BTC_POLICY_MAXLEN) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): action = %d -> policy type/len: 0x%04x/%d\n", ++ __func__, action, policy_type, btc->policy_len); ++ ++ if (dm->tdma.rxflctrl == CXFLC_NULLP || ++ dm->tdma.rxflctrl == CXFLC_QOSNULL) ++ btc->lps = 1; ++ else ++ btc->lps = 0; ++ ++ if (btc->lps == 1) ++ rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_CX_POLICY, ++ btc->policy, btc->policy_len); ++ ++ memcpy(&dm->tdma_now, &dm->tdma, sizeof(dm->tdma_now)); ++ memcpy(&dm->slot_now, &dm->slot, sizeof(dm->slot_now)); ++ ++ if (btc->update_policy_force) ++ btc->update_policy_force = false; ++ ++ if (btc->lps == 0) ++ rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); ++} ++ ++static void _fw_set_drv_info(struct rtw89_dev *rtwdev, u8 type) ++{ ++ switch (type) { ++ case CXDRVINFO_INIT: ++ rtw89_fw_h2c_cxdrv_init(rtwdev); ++ break; ++ case CXDRVINFO_ROLE: ++ rtw89_fw_h2c_cxdrv_role(rtwdev); ++ break; ++ case CXDRVINFO_CTRL: ++ rtw89_fw_h2c_cxdrv_ctrl(rtwdev); ++ break; ++ case CXDRVINFO_RFK: ++ rtw89_fw_h2c_cxdrv_rfk(rtwdev); ++ break; ++ default: ++ break; ++ } ++} ++ ++static ++void btc_fw_event(struct rtw89_dev *rtwdev, u8 evt_id, void *data, u32 len) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): evt_id:%d len:%d\n", ++ __func__, evt_id, len); ++ ++ if (!len || !data) ++ return; ++ ++ switch (evt_id) { ++ case BTF_EVNT_RPT: ++ _parse_btc_report(rtwdev, pfwinfo, data, len); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _set_gnt_wl(struct rtw89_dev *rtwdev, u8 phy_map, u8 state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_mac_ax_gnt *g = dm->gnt.band; ++ u8 i; ++ ++ if (phy_map > BTC_PHY_ALL) ++ return; ++ ++ for (i = 0; i < RTW89_PHY_MAX; i++) { ++ if (!(phy_map & BIT(i))) ++ continue; ++ ++ switch (state) { ++ case BTC_GNT_HW: ++ g[i].gnt_wl_sw_en = 0; ++ g[i].gnt_wl = 0; ++ break; ++ case BTC_GNT_SW_LO: ++ g[i].gnt_wl_sw_en = 1; ++ g[i].gnt_wl = 0; ++ break; ++ case BTC_GNT_SW_HI: ++ g[i].gnt_wl_sw_en = 1; ++ g[i].gnt_wl = 1; ++ break; ++ } ++ } ++ ++ rtw89_mac_cfg_gnt(rtwdev, &dm->gnt); ++} ++ ++#define BTC_TDMA_WLROLE_MAX 2 ++ ++static void _set_bt_ignore_wlan_act(struct rtw89_dev *rtwdev, u8 enable) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): set bt %s wlan_act\n", __func__, ++ enable ? "ignore" : "do not ignore"); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_IGNORE_WLAN_ACT, &enable, 1); ++} ++ ++#define WL_TX_POWER_NO_BTC_CTRL GENMASK(31, 0) ++#define WL_TX_POWER_ALL_TIME GENMASK(15, 0) ++#define WL_TX_POWER_WITH_BT GENMASK(31, 16) ++#define WL_TX_POWER_INT_PART GENMASK(8, 2) ++#define WL_TX_POWER_FRA_PART GENMASK(1, 0) ++#define B_BTC_WL_TX_POWER_SIGN BIT(7) ++#define B_TSSI_WL_TX_POWER_SIGN BIT(8) ++ ++static void _set_wl_tx_power(struct rtw89_dev *rtwdev, u32 level) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ u32 pwr_val; ++ ++ if (wl->rf_para.tx_pwr_freerun == level) ++ return; ++ ++ wl->rf_para.tx_pwr_freerun = level; ++ btc->dm.rf_trx_para.wl_tx_power = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ if (level == RTW89_BTC_WL_DEF_TX_PWR) { ++ pwr_val = WL_TX_POWER_NO_BTC_CTRL; ++ } else { /* only apply "force tx power" */ ++ pwr_val = FIELD_PREP(WL_TX_POWER_INT_PART, level); ++ if (pwr_val > RTW89_BTC_WL_DEF_TX_PWR) ++ pwr_val = RTW89_BTC_WL_DEF_TX_PWR; ++ ++ if (level & B_BTC_WL_TX_POWER_SIGN) ++ pwr_val |= B_TSSI_WL_TX_POWER_SIGN; ++ pwr_val |= WL_TX_POWER_WITH_BT; ++ } ++ ++ chip->ops->btc_set_wl_txpwr_ctrl(rtwdev, pwr_val); ++} ++ ++static void _set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ if (wl->rf_para.rx_gain_freerun == level) ++ return; ++ ++ wl->rf_para.rx_gain_freerun = level; ++ btc->dm.rf_trx_para.wl_rx_gain = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++} ++ ++static void _set_bt_tx_power(struct rtw89_dev *rtwdev, u8 level) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ u8 buf; ++ ++ if (bt->rf_para.tx_pwr_freerun == level) ++ return; ++ ++ bt->rf_para.tx_pwr_freerun = level; ++ btc->dm.rf_trx_para.bt_tx_power = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ buf = (s8)(-level); ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_TX_PWR, &buf, 1); ++} ++ ++#define BTC_BT_RX_NORMAL_LVL 7 ++ ++static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ ++ if (bt->rf_para.rx_gain_freerun == level || ++ level > BTC_BT_RX_NORMAL_LVL) ++ return; ++ ++ bt->rf_para.rx_gain_freerun = level; ++ btc->dm.rf_trx_para.bt_rx_gain = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): level = %d\n", ++ __func__, level); ++ ++ if (level == BTC_BT_RX_NORMAL_LVL) ++ _write_scbd(rtwdev, BTC_WSCB_RXGAIN, false); ++ else ++ _write_scbd(rtwdev, BTC_WSCB_RXGAIN, true); ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_LNA_CONSTRAIN, &level, 1); ++} ++ ++static void _set_rf_trx_para(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_rf_trx_para para; ++ u32 wl_stb_chg = 0; ++ u8 level_id = 0; ++ ++ if (!dm->freerun) { ++ dm->trx_para_level = 0; ++ chip->ops->btc_bt_aci_imp(rtwdev); ++ } ++ ++ level_id = (u8)dm->trx_para_level; ++ ++ if (level_id >= chip->rf_para_dlink_num || ++ level_id >= chip->rf_para_ulink_num) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): invalid level_id: %d\n", ++ __func__, level_id); ++ return; ++ } ++ ++ if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) ++ para = chip->rf_para_ulink[level_id]; ++ else ++ para = chip->rf_para_dlink[level_id]; ++ ++ if (para.wl_tx_power != RTW89_BTC_WL_DEF_TX_PWR) ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): wl_tx_power=%d\n", ++ __func__, para.wl_tx_power); ++ _set_wl_tx_power(rtwdev, para.wl_tx_power); ++ _set_wl_rx_gain(rtwdev, para.wl_rx_gain); ++ _set_bt_tx_power(rtwdev, para.bt_tx_power); ++ _set_bt_rx_gain(rtwdev, para.bt_rx_gain); ++ ++ if (bt->enable.now == 0 || wl->status.map.rf_off == 1 || ++ wl->status.map.lps == 1) ++ wl_stb_chg = 0; ++ else ++ wl_stb_chg = 1; ++ ++ if (wl_stb_chg != dm->wl_stb_chg) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): wl_stb_chg=%d\n", ++ __func__, wl_stb_chg); ++ dm->wl_stb_chg = wl_stb_chg; ++ chip->ops->btc_wl_s1_standby(rtwdev, dm->wl_stb_chg); ++ } ++} ++ ++static void _update_btc_state_map(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ ++ if (wl->status.map.connecting || wl->status.map._4way || ++ wl->status.map.roaming) { ++ cx->state_map = BTC_WLINKING; ++ } else if (wl->status.map.scan) { /* wl scan */ ++ if (bt_linfo->status.map.inq_pag) ++ cx->state_map = BTC_WSCAN_BSCAN; ++ else ++ cx->state_map = BTC_WSCAN_BNOSCAN; ++ } else if (wl->status.map.busy) { /* only busy */ ++ if (bt_linfo->status.map.inq_pag) ++ cx->state_map = BTC_WBUSY_BSCAN; ++ else ++ cx->state_map = BTC_WBUSY_BNOSCAN; ++ } else { /* wl idle */ ++ cx->state_map = BTC_WIDLE; ++ } ++} ++ ++static void _set_bt_afh_info(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ u8 en = 0, i, ch = 0, bw = 0; ++ ++ if (btc->ctrl.manual || wl->status.map.scan) ++ return; ++ ++ /* TODO if include module->ant.type == BTC_ANT_SHARED */ ++ if (wl->status.map.rf_off || bt->whql_test || ++ wl_rinfo->link_mode == BTC_WLINK_NOLINK || ++ wl_rinfo->link_mode == BTC_WLINK_5G || ++ wl_rinfo->connect_cnt > BTC_TDMA_WLROLE_MAX) { ++ en = false; ++ } else if (wl_rinfo->link_mode == BTC_WLINK_2G_MCC || ++ wl_rinfo->link_mode == BTC_WLINK_2G_SCC) { ++ en = true; ++ /* get p2p channel */ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ if (wl_rinfo->active_role[i].role == ++ RTW89_WIFI_ROLE_P2P_GO || ++ wl_rinfo->active_role[i].role == ++ RTW89_WIFI_ROLE_P2P_CLIENT) { ++ ch = wl_rinfo->active_role[i].ch; ++ bw = wl_rinfo->active_role[i].bw; ++ break; ++ } ++ } ++ } else { ++ en = true; ++ /* get 2g channel */ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ if (wl_rinfo->active_role[i].connected && ++ wl_rinfo->active_role[i].band == RTW89_BAND_2G) { ++ ch = wl_rinfo->active_role[i].ch; ++ bw = wl_rinfo->active_role[i].bw; ++ break; ++ } ++ } ++ } ++ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_20: ++ bw = 20 + chip->afh_guard_ch * 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ bw = 40 + chip->afh_guard_ch * 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_5: ++ bw = 5 + chip->afh_guard_ch * 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_10: ++ bw = 10 + chip->afh_guard_ch * 2; ++ break; ++ default: ++ bw = 0; ++ en = false; /* turn off AFH info if BW > 40 */ ++ break; ++ } ++ ++ if (wl->afh_info.en == en && ++ wl->afh_info.ch == ch && ++ wl->afh_info.bw == bw && ++ b->profile_cnt.last == b->profile_cnt.now) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return because no change!\n", ++ __func__); ++ return; ++ } ++ ++ wl->afh_info.en = en; ++ wl->afh_info.ch = ch; ++ wl->afh_info.bw = bw; ++ ++ _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_WL_CH_INFO, &wl->afh_info, 3); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): en=%d, ch=%d, bw=%d\n", ++ __func__, en, ch, bw); ++ btc->cx.cnt_wl[BTC_WCNT_CH_UPDATE]++; ++} ++ ++static bool _check_freerun(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_bt_hid_desc *hid = &bt_linfo->hid_desc; ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ btc->dm.trx_para_level = 0; ++ return false; ++ } ++ ++ /* The below is dedicated antenna case */ ++ if (wl_rinfo->connect_cnt > BTC_TDMA_WLROLE_MAX) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ if (bt_linfo->profile_cnt.now == 0) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ if (hid->pair_cnt > BTC_TDMA_BTHID_MAX) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ /* TODO get isolation by BT psd */ ++ if (btc->mdinfo.ant.isolation >= BTC_FREERUN_ANTISO_MIN) { ++ btc->dm.trx_para_level = 5; ++ return true; ++ } ++ ++ if (!wl->status.map.busy) {/* wl idle -> freerun */ ++ btc->dm.trx_para_level = 5; ++ return true; ++ } else if (wl->rssi_level > 1) {/* WL rssi < 50% (-60dBm) */ ++ btc->dm.trx_para_level = 0; ++ return false; ++ } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { ++ if (wl->rssi_level == 0 && bt_linfo->rssi > 31) { ++ btc->dm.trx_para_level = 6; ++ return true; ++ } else if (wl->rssi_level == 1 && bt_linfo->rssi > 36) { ++ btc->dm.trx_para_level = 7; ++ return true; ++ } ++ btc->dm.trx_para_level = 0; ++ return false; ++ } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_DL)) { ++ if (bt_linfo->rssi > 28) { ++ btc->dm.trx_para_level = 6; ++ return true; ++ } ++ } ++ ++ btc->dm.trx_para_level = 0; ++ return false; ++} ++ ++#define _tdma_set_flctrl(btc, flc) ({(btc)->dm.tdma.rxflctrl = flc; }) ++#define _tdma_set_tog(btc, wtg) ({(btc)->dm.tdma.wtgle_n = wtg; }) ++#define _tdma_set_lek(btc, lek) ({(btc)->dm.tdma.leak_n = lek; }) ++ ++#define _slot_set(btc, sid, dura, tbl, type) \ ++ do { \ ++ typeof(sid) _sid = (sid); \ ++ typeof(btc) _btc = (btc); \ ++ _btc->dm.slot[_sid].dur = cpu_to_le16(dura);\ ++ _btc->dm.slot[_sid].cxtbl = cpu_to_le32(tbl); \ ++ _btc->dm.slot[_sid].cxtype = cpu_to_le16(type); \ ++ } while (0) ++ ++#define _slot_set_dur(btc, sid, dura) (btc)->dm.slot[sid].dur = cpu_to_le16(dura) ++#define _slot_set_tbl(btc, sid, tbl) (btc)->dm.slot[sid].cxtbl = cpu_to_le32(tbl) ++#define _slot_set_type(btc, sid, type) (btc)->dm.slot[sid].cxtype = cpu_to_le16(type) ++ ++struct btc_btinfo_lb2 { ++ u8 connect: 1; ++ u8 sco_busy: 1; ++ u8 inq_pag: 1; ++ u8 acl_busy: 1; ++ u8 hfp: 1; ++ u8 hid: 1; ++ u8 a2dp: 1; ++ u8 pan: 1; ++}; ++ ++struct btc_btinfo_lb3 { ++ u8 retry: 4; ++ u8 cqddr: 1; ++ u8 inq: 1; ++ u8 mesh_busy: 1; ++ u8 pag: 1; ++}; ++ ++struct btc_btinfo_hb0 { ++ s8 rssi; ++}; ++ ++struct btc_btinfo_hb1 { ++ u8 ble_connect: 1; ++ u8 reinit: 1; ++ u8 relink: 1; ++ u8 igno_wl: 1; ++ u8 voice: 1; ++ u8 ble_scan: 1; ++ u8 role_sw: 1; ++ u8 multi_link: 1; ++}; ++ ++struct btc_btinfo_hb2 { ++ u8 pan_active: 1; ++ u8 afh_update: 1; ++ u8 a2dp_active: 1; ++ u8 slave: 1; ++ u8 hid_slot: 2; ++ u8 hid_cnt: 2; ++}; ++ ++struct btc_btinfo_hb3 { ++ u8 a2dp_bitpool: 6; ++ u8 tx_3m: 1; ++ u8 a2dp_sink: 1; ++}; ++ ++union btc_btinfo { ++ u8 val; ++ struct btc_btinfo_lb2 lb2; ++ struct btc_btinfo_lb3 lb3; ++ struct btc_btinfo_hb0 hb0; ++ struct btc_btinfo_hb1 hb1; ++ struct btc_btinfo_hb2 hb2; ++ struct btc_btinfo_hb3 hb3; ++}; ++ ++static void _set_policy(struct rtw89_dev *rtwdev, u16 policy_type, ++ enum btc_reason_and_action action) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_fbtc_tdma *t = &dm->tdma; ++ struct rtw89_btc_fbtc_slot *s = dm->slot; ++ u8 type; ++ u32 tbl_w1, tbl_b1, tbl_b4; ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.wl.status.map._4way) ++ tbl_w1 = cxtbl[1]; ++ else ++ tbl_w1 = cxtbl[8]; ++ tbl_b1 = cxtbl[3]; ++ tbl_b4 = cxtbl[3]; ++ } else { ++ tbl_w1 = cxtbl[16]; ++ tbl_b1 = cxtbl[17]; ++ tbl_b4 = cxtbl[17]; ++ } ++ ++ type = (u8)((policy_type & BTC_CXP_MASK) >> 8); ++ btc->bt_req_en = false; ++ ++ switch (type) { ++ case BTC_CXP_USERDEF0: ++ *t = t_def[CXTD_OFF]; ++ s[CXST_OFF] = s_def[CXST_OFF]; ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); ++ btc->update_policy_force = true; ++ break; ++ case BTC_CXP_OFF: /* TDMA off */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, false); ++ *t = t_def[CXTD_OFF]; ++ s[CXST_OFF] = s_def[CXST_OFF]; ++ ++ switch (policy_type) { ++ case BTC_CXP_OFF_BT: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); ++ break; ++ case BTC_CXP_OFF_WL: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[1]); ++ break; ++ case BTC_CXP_OFF_EQ0: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[0]); ++ break; ++ case BTC_CXP_OFF_EQ1: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[16]); ++ break; ++ case BTC_CXP_OFF_EQ2: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[17]); ++ break; ++ case BTC_CXP_OFF_EQ3: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[18]); ++ break; ++ case BTC_CXP_OFF_BWB0: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[5]); ++ break; ++ case BTC_CXP_OFF_BWB1: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); ++ break; ++ } ++ break; ++ case BTC_CXP_OFFB: /* TDMA off + beacon protect */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, false); ++ *t = t_def[CXTD_OFF_B2]; ++ s[CXST_OFF] = s_def[CXST_OFF]; ++ switch (policy_type) { ++ case BTC_CXP_OFFB_BWB0: ++ _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); ++ break; ++ } ++ break; ++ case BTC_CXP_OFFE: /* TDMA off + beacon protect + Ext_control */ ++ btc->bt_req_en = true; ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_OFF_EXT]; ++ switch (policy_type) { ++ case BTC_CXP_OFFE_DEF: ++ s[CXST_E2G] = s_def[CXST_E2G]; ++ s[CXST_E5G] = s_def[CXST_E5G]; ++ s[CXST_EBT] = s_def[CXST_EBT]; ++ s[CXST_ENULL] = s_def[CXST_ENULL]; ++ break; ++ case BTC_CXP_OFFE_DEF2: ++ _slot_set(btc, CXST_E2G, 20, cxtbl[1], SLOT_ISO); ++ s[CXST_E5G] = s_def[CXST_E5G]; ++ s[CXST_EBT] = s_def[CXST_EBT]; ++ s[CXST_ENULL] = s_def[CXST_ENULL]; ++ break; ++ } ++ break; ++ case BTC_CXP_FIX: /* TDMA Fix-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_FIX]; ++ switch (policy_type) { ++ case BTC_CXP_FIX_TD3030: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD2030: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD4010: ++ _slot_set(btc, CXST_W1, 40, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD4020: ++ _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_MIX); ++ _slot_set(btc, CXST_B1, 20, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD7010: ++ _slot_set(btc, CXST_W1, 70, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD2060: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD3060: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_FIX_TDW1B1: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], ++ tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_PFIX: /* PS-TDMA Fix-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_PFIX]; ++ if (btc->cx.wl.role_info.role_map.role.ap) ++ _tdma_set_flctrl(btc, CXFLC_QOSNULL); ++ ++ switch (policy_type) { ++ case BTC_CXP_PFIX_TD3030: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD2030: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD2060: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD3070: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PFIX_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_AUTO: /* TDMA Auto-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_AUTO]; ++ switch (policy_type) { ++ case BTC_CXP_AUTO_TD50200: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO_TD60200: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO_TD20200: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO_TDW1B1: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], ++ tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_PAUTO: /* PS-TDMA Auto-Slot */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_PAUTO]; ++ switch (policy_type) { ++ case BTC_CXP_PAUTO_TD50200: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO_TD60200: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO_TD20200: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO_TDW1B1: ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], ++ tbl_b1, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_AUTO2: /* TDMA Auto-Slot2 */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_AUTO2]; ++ switch (policy_type) { ++ case BTC_CXP_AUTO2_TD3050: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD3070: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD6060: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_AUTO2_TDW1B4: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], ++ tbl_b4, SLOT_MIX); ++ break; ++ } ++ break; ++ case BTC_CXP_PAUTO2: /* PS-TDMA Auto-Slot2 */ ++ _write_scbd(rtwdev, BTC_WSCB_TDMA, true); ++ *t = t_def[CXTD_PAUTO2]; ++ switch (policy_type) { ++ case BTC_CXP_PAUTO2_TD3050: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD3070: ++ _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD5050: ++ _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD6060: ++ _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TD2080: ++ _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B1, 200, tbl_b1, SLOT_MIX); ++ _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); ++ break; ++ case BTC_CXP_PAUTO2_TDW1B4: /* W1:B1 = user-define */ ++ _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], ++ tbl_w1, SLOT_ISO); ++ _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], ++ tbl_b4, SLOT_MIX); ++ break; ++ } ++ break; ++ } ++ ++ _fw_set_policy(rtwdev, policy_type, action); ++} ++ ++static void _set_gnt_bt(struct rtw89_dev *rtwdev, u8 phy_map, u8 state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_mac_ax_gnt *g = dm->gnt.band; ++ u8 i; ++ ++ if (phy_map > BTC_PHY_ALL) ++ return; ++ ++ for (i = 0; i < RTW89_PHY_MAX; i++) { ++ if (!(phy_map & BIT(i))) ++ continue; ++ ++ switch (state) { ++ case BTC_GNT_HW: ++ g[i].gnt_bt_sw_en = 0; ++ g[i].gnt_bt = 0; ++ break; ++ case BTC_GNT_SW_LO: ++ g[i].gnt_bt_sw_en = 1; ++ g[i].gnt_bt = 0; ++ break; ++ case BTC_GNT_SW_HI: ++ g[i].gnt_bt_sw_en = 1; ++ g[i].gnt_bt = 1; ++ break; ++ } ++ } ++ ++ rtw89_mac_cfg_gnt(rtwdev, &dm->gnt); ++} ++ ++static void _set_bt_plut(struct rtw89_dev *rtwdev, u8 phy_map, ++ u8 tx_val, u8 rx_val) ++{ ++ struct rtw89_mac_ax_plt plt; ++ ++ plt.band = RTW89_MAC_0; ++ plt.tx = tx_val; ++ plt.rx = rx_val; ++ ++ if (phy_map & BTC_PHY_0) ++ rtw89_mac_cfg_plt(rtwdev, &plt); ++ ++ if (!rtwdev->dbcc_en) ++ return; ++ ++ plt.band = RTW89_MAC_1; ++ if (phy_map & BTC_PHY_1) ++ rtw89_mac_cfg_plt(rtwdev, &plt); ++} ++ ++static void _set_ant(struct rtw89_dev *rtwdev, bool force_exec, ++ u8 phy_map, u8 type) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ u8 gnt_wl_ctrl, gnt_bt_ctrl, plt_ctrl, i, b2g = 0; ++ u32 ant_path_type; ++ ++ ant_path_type = ((phy_map << 8) + type); ++ ++ if (btc->dm.run_reason == BTC_RSN_NTFY_POWEROFF || ++ btc->dm.run_reason == BTC_RSN_NTFY_RADIO_STATE || ++ btc->dm.run_reason == BTC_RSN_CMD_SET_COEX) ++ force_exec = FC_EXEC; ++ ++ if (!force_exec && ant_path_type == dm->set_ant_path) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by no change!!\n", ++ __func__); ++ return; ++ } else if (bt->rfk_info.map.run) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by bt rfk!!\n", __func__); ++ return; ++ } else if (btc->dm.run_reason != BTC_RSN_NTFY_WL_RFK && ++ wl->rfk_info.state != BTC_WRFK_STOP) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by wl rfk!!\n", __func__); ++ return; ++ } ++ ++ dm->set_ant_path = ant_path_type; ++ ++ rtw89_debug(rtwdev, ++ RTW89_DBG_BTC, ++ "[BTC], %s(): path=0x%x, set_type=0x%x\n", ++ __func__, phy_map, dm->set_ant_path & 0xff); ++ ++ switch (type) { ++ case BTC_ANT_WPOWERON: ++ rtw89_mac_cfg_ctrl_path(rtwdev, false); ++ break; ++ case BTC_ANT_WINIT: ++ if (bt->enable.now) { ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_LO); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_HI); ++ } else { ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_LO); ++ } ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_BT, BTC_PLT_BT); ++ break; ++ case BTC_ANT_WONLY: ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_LO); ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_WOFF: ++ rtw89_mac_cfg_ctrl_path(rtwdev, false); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_W2G: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ if (rtwdev->dbcc_en) { ++ for (i = 0; i < RTW89_PHY_MAX; i++) { ++ b2g = (wl_dinfo->real_band[i] == RTW89_BAND_2G); ++ ++ gnt_wl_ctrl = b2g ? BTC_GNT_HW : BTC_GNT_SW_HI; ++ _set_gnt_wl(rtwdev, BIT(i), gnt_wl_ctrl); ++ ++ gnt_bt_ctrl = b2g ? BTC_GNT_HW : BTC_GNT_SW_HI; ++ /* BT should control by GNT_BT if WL_2G at S0 */ ++ if (i == 1 && ++ wl_dinfo->real_band[0] == RTW89_BAND_2G && ++ wl_dinfo->real_band[1] == RTW89_BAND_5G) ++ gnt_bt_ctrl = BTC_GNT_HW; ++ _set_gnt_bt(rtwdev, BIT(i), gnt_bt_ctrl); ++ ++ plt_ctrl = b2g ? BTC_PLT_BT : BTC_PLT_NONE; ++ _set_bt_plut(rtwdev, BIT(i), ++ plt_ctrl, plt_ctrl); ++ } ++ } else { ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_HW); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_HW); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, ++ BTC_PLT_BT, BTC_PLT_BT); ++ } ++ break; ++ case BTC_ANT_W5G: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_HW); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_W25G: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_HW); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_HW); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, ++ BTC_PLT_GNT_WL, BTC_PLT_GNT_WL); ++ break; ++ case BTC_ANT_FREERUN: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_WRFK: ++ rtw89_mac_cfg_ctrl_path(rtwdev, true); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_LO); ++ _set_bt_plut(rtwdev, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ case BTC_ANT_BRFK: ++ rtw89_mac_cfg_ctrl_path(rtwdev, false); ++ _set_gnt_wl(rtwdev, phy_map, BTC_GNT_SW_LO); ++ _set_gnt_bt(rtwdev, phy_map, BTC_GNT_SW_HI); ++ _set_bt_plut(rtwdev, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _action_wl_only(struct rtw89_dev *rtwdev) ++{ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_ONLY); ++} ++ ++static void _action_wl_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WINIT); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_INIT); ++} ++ ++static void _action_wl_off(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ if (wl->status.map.rf_off || btc->dm.bt_only) ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_WOFF); ++ ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); ++} ++ ++static void _action_freerun(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_FREERUN); ++ ++ btc->dm.freerun = true; ++} ++ ++static void _action_bt_whql(struct rtw89_dev *rtwdev) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_BT_WHQL); ++} ++ ++static void _action_bt_off(struct rtw89_dev *rtwdev) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_BT_OFF); ++} ++ ++static void _action_bt_idle(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *b = &btc->cx.bt.link_info; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /*wl-busy + bt idle*/ ++ if (b->profile_cnt.now > 0) ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4010, ++ BTC_ACT_BT_IDLE); ++ else ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4020, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WBUSY_BSCAN: /*wl-busy + bt-inq */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ ++ if (b->profile_cnt.now > 0) ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4010, ++ BTC_ACT_BT_IDLE); ++ else ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4020, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD5050, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-inq or bt-idle */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD7010, ++ BTC_ACT_BT_IDLE); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-idle */ ++ _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_IDLE); ++ break; ++ } ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_BT_IDLE); ++ } ++} ++ ++static void _action_bt_hfp(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.wl.status.map._4way) ++ _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_BT_HFP); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFF_BWB0, BTC_ACT_BT_HFP); ++ } else { ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ2, BTC_ACT_BT_HFP); ++ } ++} ++ ++static void _action_bt_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) /* shared-antenna */ ++ if (btc->cx.wl.status.map._4way) ++ _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_BT_HID); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFF_BWB0, BTC_ACT_BT_HID); ++ else /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ3, BTC_ACT_BT_HID); ++} ++ ++static void _action_bt_a2dp(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TDW1B1, BTC_ACT_BT_A2DP); ++ } else { ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TD50200, BTC_ACT_BT_A2DP); ++ } ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3050, BTC_ACT_BT_A2DP); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */ ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, BTC_CXP_AUTO_TDW1B1, ++ BTC_ACT_BT_A2DP); ++ } else { ++ _set_policy(rtwdev, BTC_CXP_AUTO_TD50200, ++ BTC_ACT_BT_A2DP); ++ } ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2DP */ ++ _set_policy(rtwdev, BTC_CXP_AUTO_TD20200, BTC_ACT_BT_A2DP); ++ break; ++ } ++} ++ ++static void _action_bt_a2dpsink(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2030, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2060, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD2030, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD2060, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_A2DPSINK); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2dp_Sink */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD2080, BTC_ACT_BT_A2DPSINK); ++ break; ++ } ++} ++ ++static void _action_bt_pan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD3070, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-PAN */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4020, BTC_ACT_BT_PAN); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-pan */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN); ++ break; ++ } ++} ++ ++static void _action_bt_a2dp_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+HID */ ++ case BTC_WIDLE: /* wl-idle + bt-A2DP */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TDW1B1, BTC_ACT_BT_A2DP_HID); ++ } else { ++ _set_policy(rtwdev, ++ BTC_CXP_PAUTO_TD50200, BTC_ACT_BT_A2DP_HID); ++ } ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3050, BTC_ACT_BT_A2DP_HID); ++ break; ++ ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+HID */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP_HID); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+HID */ ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP+HID */ ++ if (a2dp.vendor_id == 0x4c || dm->leak_ap) { ++ dm->slot_dur[CXST_W1] = 40; ++ dm->slot_dur[CXST_B1] = 200; ++ _set_policy(rtwdev, BTC_CXP_AUTO_TDW1B1, ++ BTC_ACT_BT_A2DP_HID); ++ } else { ++ _set_policy(rtwdev, BTC_CXP_AUTO_TD50200, ++ BTC_ACT_BT_A2DP_HID); ++ } ++ break; ++ } ++} ++ ++static void _action_bt_a2dp_pan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD5050, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP_PAN); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD2080, BTC_ACT_BT_A2DP_PAN); ++ break; ++ } ++} ++ ++static void _action_bt_pan_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD3030, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD3070, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WLINKING: /* wl-connecting + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_FIX_TD4010, BTC_ACT_BT_PAN_HID); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN_HID); ++ break; ++ } ++} ++ ++static void _action_bt_a2dp_pan_hid(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ switch (btc->cx.state_map) { ++ case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3070, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN+HID */ ++ case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN+HID */ ++ _set_policy(rtwdev, BTC_CXP_PAUTO2_TD2080, ++ BTC_ACT_BT_A2DP_PAN_HID); ++ break; ++ } ++} ++ ++static void _action_wl_5g(struct rtw89_dev *rtwdev) ++{ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_5G); ++} ++ ++static void _action_wl_other(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) ++ _set_policy(rtwdev, BTC_CXP_OFFB_BWB0, BTC_ACT_WL_OTHER); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_OTHER); ++} ++ ++static void _action_wl_nc(struct rtw89_dev *rtwdev) ++{ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_NC); ++} ++ ++static void _action_wl_rfk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_rfk_info rfk = btc->cx.wl.rfk_info; ++ ++ if (rfk.state != BTC_WRFK_START) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): band = %d\n", ++ __func__, rfk.band); ++ ++ _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK); ++ _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_WL_RFK); ++} ++ ++static void _set_btg_ctrl(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ bool is_btg = false; ++ ++ if (btc->ctrl.manual) ++ return; ++ ++ /* notify halbb ignore GNT_BT or not for WL BB Rx-AGC control */ ++ if (wl_rinfo->link_mode == BTC_WLINK_5G) /* always 0 if 5G */ ++ is_btg = false; ++ else if (wl_rinfo->link_mode == BTC_WLINK_25G_DBCC && ++ wl_dinfo->real_band[RTW89_PHY_1] != RTW89_BAND_2G) ++ is_btg = false; ++ else ++ is_btg = true; ++ ++ if (btc->dm.run_reason != BTC_RSN_NTFY_INIT && ++ is_btg == btc->dm.wl_btg_rx) ++ return; ++ ++ btc->dm.wl_btg_rx = is_btg; ++ ++ if (wl_rinfo->link_mode == BTC_WLINK_25G_MCC) ++ return; ++ ++ rtw89_ctrl_btg(rtwdev, is_btg); ++} ++ ++struct rtw89_txtime_data { ++ struct rtw89_dev *rtwdev; ++ int type; ++ u32 tx_time; ++ u8 tx_retry; ++ u16 enable; ++ bool reenable; ++}; ++ ++static void rtw89_tx_time_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_txtime_data *iter_data = ++ (struct rtw89_txtime_data *)data; ++ struct rtw89_dev *rtwdev = iter_data->rtwdev; ++ struct rtw89_vif *rtwvif = rtwsta->rtwvif; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_wl_link_info *plink = NULL; ++ u8 port = rtwvif->port; ++ u32 tx_time = iter_data->tx_time; ++ u8 tx_retry = iter_data->tx_retry; ++ u16 enable = iter_data->enable; ++ bool reenable = iter_data->reenable; ++ ++ plink = &wl->link_info[port]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): port = %d\n", __func__, port); ++ ++ if (!plink->connected) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): connected = %d\n", ++ __func__, plink->connected); ++ return; ++ } ++ ++ /* backup the original tx time before tx-limit on */ ++ if (reenable) { ++ rtw89_mac_get_tx_time(rtwdev, rtwsta, &plink->tx_time); ++ rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta, &plink->tx_retry); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): reenable, tx_time=%d tx_retry= %d\n", ++ __func__, plink->tx_time, plink->tx_retry); ++ } ++ ++ /* restore the original tx time if no tx-limit */ ++ if (!enable) { ++ rtw89_mac_set_tx_time(rtwdev, rtwsta, true, plink->tx_time); ++ rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta, true, ++ plink->tx_retry); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): restore, tx_time=%d tx_retry= %d\n", ++ __func__, plink->tx_time, plink->tx_retry); ++ ++ } else { ++ rtw89_mac_set_tx_time(rtwdev, rtwsta, false, tx_time); ++ rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta, false, tx_retry); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): set, tx_time=%d tx_retry= %d\n", ++ __func__, tx_time, tx_retry); ++ } ++} ++ ++static void _set_wl_tx_limit(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; ++ struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_txtime_data data = {.rtwdev = rtwdev}; ++ u8 mode = wl_rinfo->link_mode; ++ u8 tx_retry = 0; ++ u32 tx_time = 0; ++ u16 enable = 0; ++ bool reenable = false; ++ ++ if (btc->ctrl.manual) ++ return; ++ ++ if (btc->dm.freerun || btc->ctrl.igno_bt || b->profile_cnt.now == 0 || ++ mode == BTC_WLINK_5G || mode == BTC_WLINK_NOLINK) { ++ enable = 0; ++ tx_time = BTC_MAX_TX_TIME_DEF; ++ tx_retry = BTC_MAX_TX_RETRY_DEF; ++ } else if ((hfp->exist && hid->exist) || hid->pair_cnt > 1) { ++ enable = 1; ++ tx_time = BTC_MAX_TX_TIME_L2; ++ tx_retry = BTC_MAX_TX_RETRY_L1; ++ } else if (hfp->exist || hid->exist) { ++ enable = 1; ++ tx_time = BTC_MAX_TX_TIME_L3; ++ tx_retry = BTC_MAX_TX_RETRY_L1; ++ } else { ++ enable = 0; ++ tx_time = BTC_MAX_TX_TIME_DEF; ++ tx_retry = BTC_MAX_TX_RETRY_DEF; ++ } ++ ++ if (dm->wl_tx_limit.enable == enable && ++ dm->wl_tx_limit.tx_time == tx_time && ++ dm->wl_tx_limit.tx_retry == tx_retry) ++ return; ++ ++ if (!dm->wl_tx_limit.enable && enable) ++ reenable = true; ++ ++ dm->wl_tx_limit.enable = enable; ++ dm->wl_tx_limit.tx_time = tx_time; ++ dm->wl_tx_limit.tx_retry = tx_retry; ++ ++ data.enable = enable; ++ data.tx_time = tx_time; ++ data.tx_retry = tx_retry; ++ data.reenable = reenable; ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_tx_time_iter, ++ &data); ++} ++ ++static void _set_bt_rx_agc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ bool bt_hi_lna_rx = false; ++ ++ if (wl_rinfo->link_mode != BTC_WLINK_NOLINK && btc->dm.wl_btg_rx) ++ bt_hi_lna_rx = true; ++ ++ if (bt_hi_lna_rx == bt->hi_lna_rx) ++ return; ++ ++ _write_scbd(rtwdev, BTC_WSCB_BT_HILNA, bt_hi_lna_rx); ++} ++ ++/* TODO add these functions */ ++static void _action_common(struct rtw89_dev *rtwdev) ++{ ++ _set_btg_ctrl(rtwdev); ++ _set_wl_tx_limit(rtwdev); ++ _set_bt_afh_info(rtwdev); ++ _set_bt_rx_agc(rtwdev); ++ _set_rf_trx_para(rtwdev); ++} ++ ++static void _action_by_bt(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ struct rtw89_btc_bt_hid_desc hid = bt_linfo->hid_desc; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; ++ u8 profile_map = 0; ++ ++ if (bt_linfo->hfp_desc.exist) ++ profile_map |= BTC_BT_HFP; ++ ++ if (bt_linfo->hid_desc.exist) ++ profile_map |= BTC_BT_HID; ++ ++ if (bt_linfo->a2dp_desc.exist) ++ profile_map |= BTC_BT_A2DP; ++ ++ if (bt_linfo->pan_desc.exist) ++ profile_map |= BTC_BT_PAN; ++ ++ switch (profile_map) { ++ case BTC_BT_NOPROFILE: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else if (a2dp.active || pan.active) ++ _action_bt_pan(rtwdev); ++ else ++ _action_bt_idle(rtwdev); ++ break; ++ case BTC_BT_HFP: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else ++ _action_bt_hfp(rtwdev); ++ break; ++ case BTC_BT_HFP | BTC_BT_HID: ++ case BTC_BT_HID: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else ++ _action_bt_hid(rtwdev); ++ break; ++ case BTC_BT_A2DP: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else if (a2dp.sink) ++ _action_bt_a2dpsink(rtwdev); ++ else if (bt_linfo->multi_link.now && !hid.pair_cnt) ++ _action_bt_a2dp_pan(rtwdev); ++ else ++ _action_bt_a2dp(rtwdev); ++ break; ++ case BTC_BT_PAN: ++ _action_bt_pan(rtwdev); ++ break; ++ case BTC_BT_A2DP | BTC_BT_HFP: ++ case BTC_BT_A2DP | BTC_BT_HID: ++ case BTC_BT_A2DP | BTC_BT_HFP | BTC_BT_HID: ++ if (_check_freerun(rtwdev)) ++ _action_freerun(rtwdev); ++ else ++ _action_bt_a2dp_hid(rtwdev); ++ break; ++ case BTC_BT_A2DP | BTC_BT_PAN: ++ _action_bt_a2dp_pan(rtwdev); ++ break; ++ case BTC_BT_PAN | BTC_BT_HFP: ++ case BTC_BT_PAN | BTC_BT_HID: ++ case BTC_BT_PAN | BTC_BT_HFP | BTC_BT_HID: ++ _action_bt_pan_hid(rtwdev); ++ break; ++ case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HID: ++ case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HFP: ++ default: ++ _action_bt_a2dp_pan_hid(rtwdev); ++ break; ++ } ++} ++ ++static void _action_wl_2g_sta(struct rtw89_dev *rtwdev) ++{ ++ _action_by_bt(rtwdev); ++} ++ ++static void _action_wl_scan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ ++ if (rtwdev->dbcc_en) { ++ if (wl_dinfo->real_band[RTW89_PHY_0] != RTW89_BAND_2G && ++ wl_dinfo->real_band[RTW89_PHY_1] != RTW89_BAND_2G) ++ _action_wl_5g(rtwdev); ++ else ++ _action_by_bt(rtwdev); ++ } else { ++ if (wl->scan_info.band[RTW89_PHY_0] != RTW89_BAND_2G) ++ _action_wl_5g(rtwdev); ++ else ++ _action_by_bt(rtwdev); ++ } ++} ++ ++static void _action_wl_25g_mcc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, ++ BTC_ACT_WL_25G_MCC); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF, ++ BTC_ACT_WL_25G_MCC); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_25G_MCC); ++ } ++} ++ ++static void _action_wl_2g_mcc(struct rtw89_dev *rtwdev) ++{ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, ++ BTC_ACT_WL_2G_MCC); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF, ++ BTC_ACT_WL_2G_MCC); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_MCC); ++ } ++} ++ ++static void _action_wl_2g_scc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_SCC); ++ else ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_SCC); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_SCC); ++ } ++} ++ ++static void _action_wl_2g_ap(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, ++ BTC_ACT_WL_2G_AP); ++ else ++ _set_policy(rtwdev, BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_AP); ++ } else {/* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_AP); ++ } ++} ++ ++static void _action_wl_2g_go(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_GO); ++ else ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_GO); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GO); ++ } ++} ++ ++static void _action_wl_2g_gc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ _action_by_bt(rtwdev); ++ } else {/* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GC); ++ } ++} ++ ++static void _action_wl_2g_nan(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ ++ if (btc->cx.bt.link_info.profile_cnt.now == 0) ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_NAN); ++ else ++ _set_policy(rtwdev, ++ BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_NAN); ++ } else { /* dedicated-antenna */ ++ _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_NAN); ++ } ++} ++ ++static u32 _read_scbd(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ u32 scbd_val = 0; ++ ++ if (!chip->scbd) ++ return 0; ++ ++ scbd_val = rtw89_mac_get_sb(rtwdev); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], read scbd: 0x%08x\n", ++ scbd_val); ++ ++ btc->cx.cnt_bt[BTC_BCNT_SCBDREAD]++; ++ return scbd_val; ++} ++ ++static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ u32 scbd_val = 0; ++ ++ if (!chip->scbd) ++ return; ++ ++ scbd_val = state ? wl->scbd | val : wl->scbd & ~val; ++ ++ if (scbd_val == wl->scbd) ++ return; ++ rtw89_mac_cfg_sb(rtwdev, scbd_val); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], write scbd: 0x%08x\n", ++ scbd_val); ++ wl->scbd = scbd_val; ++ ++ btc->cx.cnt_wl[BTC_WCNT_SCBDUPDATE]++; ++} ++ ++static u8 ++_update_rssi_state(struct rtw89_dev *rtwdev, u8 pre_state, u8 rssi, u8 thresh) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 next_state, tol = chip->rssi_tol; ++ ++ if (pre_state == BTC_RSSI_ST_LOW || ++ pre_state == BTC_RSSI_ST_STAY_LOW) { ++ if (rssi >= (thresh + tol)) ++ next_state = BTC_RSSI_ST_HIGH; ++ else ++ next_state = BTC_RSSI_ST_STAY_LOW; ++ } else { ++ if (rssi < thresh) ++ next_state = BTC_RSSI_ST_LOW; ++ else ++ next_state = BTC_RSSI_ST_STAY_HIGH; ++ } ++ ++ return next_state; ++} ++ ++static ++void _update_dbcc_band(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ btc->cx.wl.dbcc_info.real_band[phy_idx] = ++ btc->cx.wl.scan_info.phy_map & BIT(phy_idx) ? ++ btc->cx.wl.dbcc_info.scan_band[phy_idx] : ++ btc->cx.wl.dbcc_info.op_band[phy_idx]; ++} ++ ++static void _update_wl_info(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ u8 i, cnt_connect = 0, cnt_connecting = 0, cnt_active = 0; ++ u8 cnt_2g = 0, cnt_5g = 0, phy; ++ u32 wl_2g_ch[2] = {0}, wl_5g_ch[2] = {0}; ++ bool b2g = false, b5g = false, client_joined = false; ++ ++ memset(wl_rinfo, 0, sizeof(*wl_rinfo)); ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ /* check if role active? */ ++ if (!wl_linfo[i].active) ++ continue; ++ ++ cnt_active++; ++ wl_rinfo->active_role[cnt_active - 1].role = wl_linfo[i].role; ++ wl_rinfo->active_role[cnt_active - 1].pid = wl_linfo[i].pid; ++ wl_rinfo->active_role[cnt_active - 1].phy = wl_linfo[i].phy; ++ wl_rinfo->active_role[cnt_active - 1].band = wl_linfo[i].band; ++ wl_rinfo->active_role[cnt_active - 1].noa = (u8)wl_linfo[i].noa; ++ wl_rinfo->active_role[cnt_active - 1].connected = 0; ++ ++ wl->port_id[wl_linfo[i].role] = wl_linfo[i].pid; ++ ++ phy = wl_linfo[i].phy; ++ ++ /* check dbcc role */ ++ if (rtwdev->dbcc_en && phy < RTW89_PHY_MAX) { ++ wl_dinfo->role[phy] = wl_linfo[i].role; ++ wl_dinfo->op_band[phy] = wl_linfo[i].band; ++ _update_dbcc_band(rtwdev, phy); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ ++ if (wl_linfo[i].connected == MLME_NO_LINK) { ++ continue; ++ } else if (wl_linfo[i].connected == MLME_LINKING) { ++ cnt_connecting++; ++ } else { ++ cnt_connect++; ++ if ((wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || ++ wl_linfo[i].role == RTW89_WIFI_ROLE_AP) && ++ wl_linfo[i].client_cnt > 1) ++ client_joined = true; ++ } ++ ++ wl_rinfo->role_map.val |= BIT(wl_linfo[i].role); ++ wl_rinfo->active_role[cnt_active - 1].ch = wl_linfo[i].ch; ++ wl_rinfo->active_role[cnt_active - 1].bw = wl_linfo[i].bw; ++ wl_rinfo->active_role[cnt_active - 1].connected = 1; ++ ++ /* only care 2 roles + BT coex */ ++ if (wl_linfo[i].band != RTW89_BAND_2G) { ++ if (cnt_5g <= ARRAY_SIZE(wl_5g_ch) - 1) ++ wl_5g_ch[cnt_5g] = wl_linfo[i].ch; ++ cnt_5g++; ++ b5g = true; ++ } else { ++ if (cnt_2g <= ARRAY_SIZE(wl_2g_ch) - 1) ++ wl_2g_ch[cnt_2g] = wl_linfo[i].ch; ++ cnt_2g++; ++ b2g = true; ++ } ++ } ++ ++ wl_rinfo->connect_cnt = cnt_connect; ++ ++ /* Be careful to change the following sequence!! */ ++ if (cnt_connect == 0) { ++ wl_rinfo->link_mode = BTC_WLINK_NOLINK; ++ wl_rinfo->role_map.role.none = 1; ++ } else if (!b2g && b5g) { ++ wl_rinfo->link_mode = BTC_WLINK_5G; ++ } else if (wl_rinfo->role_map.role.nan) { ++ wl_rinfo->link_mode = BTC_WLINK_2G_NAN; ++ } else if (cnt_connect > BTC_TDMA_WLROLE_MAX) { ++ wl_rinfo->link_mode = BTC_WLINK_OTHER; ++ } else if (b2g && b5g && cnt_connect == 2) { ++ if (rtwdev->dbcc_en) { ++ switch (wl_dinfo->role[RTW89_PHY_0]) { ++ case RTW89_WIFI_ROLE_STATION: ++ wl_rinfo->link_mode = BTC_WLINK_2G_STA; ++ break; ++ case RTW89_WIFI_ROLE_P2P_GO: ++ wl_rinfo->link_mode = BTC_WLINK_2G_GO; ++ break; ++ case RTW89_WIFI_ROLE_P2P_CLIENT: ++ wl_rinfo->link_mode = BTC_WLINK_2G_GC; ++ break; ++ case RTW89_WIFI_ROLE_AP: ++ wl_rinfo->link_mode = BTC_WLINK_2G_AP; ++ break; ++ default: ++ wl_rinfo->link_mode = BTC_WLINK_OTHER; ++ break; ++ } ++ } else { ++ wl_rinfo->link_mode = BTC_WLINK_25G_MCC; ++ } ++ } else if (!b5g && cnt_connect == 2) { ++ if (wl_rinfo->role_map.role.station && ++ (wl_rinfo->role_map.role.p2p_go || ++ wl_rinfo->role_map.role.p2p_gc || ++ wl_rinfo->role_map.role.ap)) { ++ if (wl_2g_ch[0] == wl_2g_ch[1]) ++ wl_rinfo->link_mode = BTC_WLINK_2G_SCC; ++ else ++ wl_rinfo->link_mode = BTC_WLINK_2G_MCC; ++ } else { ++ wl_rinfo->link_mode = BTC_WLINK_2G_MCC; ++ } ++ } else if (!b5g && cnt_connect == 1) { ++ if (wl_rinfo->role_map.role.station) ++ wl_rinfo->link_mode = BTC_WLINK_2G_STA; ++ else if (wl_rinfo->role_map.role.ap) ++ wl_rinfo->link_mode = BTC_WLINK_2G_AP; ++ else if (wl_rinfo->role_map.role.p2p_go) ++ wl_rinfo->link_mode = BTC_WLINK_2G_GO; ++ else if (wl_rinfo->role_map.role.p2p_gc) ++ wl_rinfo->link_mode = BTC_WLINK_2G_GC; ++ else ++ wl_rinfo->link_mode = BTC_WLINK_OTHER; ++ } ++ ++ /* if no client_joined, don't care P2P-GO/AP role */ ++ if (wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) { ++ if (!client_joined) { ++ if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || ++ wl_rinfo->link_mode == BTC_WLINK_2G_MCC) { ++ wl_rinfo->link_mode = BTC_WLINK_2G_STA; ++ wl_rinfo->connect_cnt = 1; ++ } else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO || ++ wl_rinfo->link_mode == BTC_WLINK_2G_AP) { ++ wl_rinfo->link_mode = BTC_WLINK_NOLINK; ++ wl_rinfo->connect_cnt = 0; ++ } ++ } ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], cnt_connect = %d, link_mode = %d\n", ++ cnt_connect, wl_rinfo->link_mode); ++ ++ _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); ++} ++ ++#define BTC_CHK_HANG_MAX 3 ++#define BTC_SCB_INV_VALUE GENMASK(31, 0) ++ ++void rtw89_coex_act1_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ coex_act1_work.work); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); ++ dm->cnt_notify[BTC_NCNT_TIMER]++; ++ if (wl->status.map._4way) ++ wl->status.map._4way = false; ++ if (wl->status.map.connecting) ++ wl->status.map.connecting = false; ++ ++ _run_coex(rtwdev, BTC_RSN_ACT1_WORK); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_coex_bt_devinfo_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ coex_bt_devinfo_work.work); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); ++ dm->cnt_notify[BTC_NCNT_TIMER]++; ++ a2dp->play_latency = 0; ++ _run_coex(rtwdev, BTC_RSN_BT_DEVINFO_WORK); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_coex_rfk_chk_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ coex_rfk_chk_work.work); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); ++ dm->cnt_notify[BTC_NCNT_TIMER]++; ++ if (wl->rfk_info.state != BTC_WRFK_STOP) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): RFK timeout\n", __func__); ++ cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]++; ++ dm->error.map.wl_rfk_timeout = true; ++ wl->rfk_info.state = BTC_WRFK_STOP; ++ _write_scbd(rtwdev, BTC_WSCB_WLRFK, false); ++ _run_coex(rtwdev, BTC_RSN_RFK_CHK_WORK); ++ } ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ u32 val; ++ bool status_change = false; ++ ++ if (!chip->scbd) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s\n", __func__); ++ ++ val = _read_scbd(rtwdev); ++ if (val == BTC_SCB_INV_VALUE) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by invalid scbd value\n", ++ __func__); ++ return; ++ } ++ ++ if (!(val & BTC_BSCB_ON) || ++ btc->dm.cnt_dm[BTC_DCNT_BTCNT_FREEZE] >= BTC_CHK_HANG_MAX) ++ bt->enable.now = 0; ++ else ++ bt->enable.now = 1; ++ ++ if (bt->enable.now != bt->enable.last) ++ status_change = true; ++ ++ /* reset bt info if bt re-enable */ ++ if (bt->enable.now && !bt->enable.last) { ++ _reset_btc_var(rtwdev, BTC_RESET_BTINFO); ++ cx->cnt_bt[BTC_BCNT_REENABLE]++; ++ bt->enable.now = 1; ++ } ++ ++ bt->enable.last = bt->enable.now; ++ bt->scbd = val; ++ bt->mbx_avl = !!(val & BTC_BSCB_ACT); ++ ++ if (bt->whql_test != !!(val & BTC_BSCB_WHQL)) ++ status_change = true; ++ ++ bt->whql_test = !!(val & BTC_BSCB_WHQL); ++ bt->btg_type = val & BTC_BSCB_BT_S1 ? BTC_BT_BTG : BTC_BT_ALONE; ++ bt->link_info.a2dp_desc.active = !!(val & BTC_BSCB_A2DP_ACT); ++ ++ /* if rfk run 1->0 */ ++ if (bt->rfk_info.map.run && !(val & BTC_BSCB_RFK_RUN)) ++ status_change = true; ++ ++ bt->rfk_info.map.run = !!(val & BTC_BSCB_RFK_RUN); ++ bt->rfk_info.map.req = !!(val & BTC_BSCB_RFK_REQ); ++ bt->hi_lna_rx = !!(val & BTC_BSCB_BT_HILNA); ++ bt->link_info.status.map.connect = !!(val & BTC_BSCB_BT_CONNECT); ++ bt->run_patch_code = !!(val & BTC_BSCB_PATCH_CODE); ++ ++ if (!only_update && status_change) ++ _run_coex(rtwdev, BTC_RSN_UPDATE_BT_SCBD); ++} ++ ++static bool _chk_wl_rfk_request(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ ++ _update_bt_scbd(rtwdev, true); ++ ++ cx->cnt_wl[BTC_WCNT_RFK_REQ]++; ++ ++ if ((bt->rfk_info.map.run || bt->rfk_info.map.req) && ++ !bt->rfk_info.map.timeout) { ++ cx->cnt_wl[BTC_WCNT_RFK_REJECT]++; ++ } else { ++ cx->cnt_wl[BTC_WCNT_RFK_GO]++; ++ return true; ++ } ++ return false; ++} ++ ++static ++void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ u8 mode = wl_rinfo->link_mode; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): reason=%d, mode=%d\n", ++ __func__, reason, mode); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): wl_only=%d, bt_only=%d\n", ++ __func__, dm->wl_only, dm->bt_only); ++ ++ dm->run_reason = reason; ++ _update_dm_step(rtwdev, reason); ++ _update_btc_state_map(rtwdev); ++ ++ /* Be careful to change the following function sequence!! */ ++ if (btc->ctrl.manual) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for Manual CTRL!!\n", ++ __func__); ++ return; ++ } ++ ++ if (btc->ctrl.igno_bt && ++ (reason == BTC_RSN_UPDATE_BT_INFO || ++ reason == BTC_RSN_UPDATE_BT_SCBD)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for Stop Coex DM!!\n", ++ __func__); ++ return; ++ } ++ ++ if (!wl->status.map.init_ok) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for WL init fail!!\n", ++ __func__); ++ return; ++ } ++ ++ if (wl->status.map.rf_off_pre == wl->status.map.rf_off && ++ wl->status.map.lps_pre == wl->status.map.lps && ++ (reason == BTC_RSN_NTFY_POWEROFF || ++ reason == BTC_RSN_NTFY_RADIO_STATE)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for WL rf off state no change!!\n", ++ __func__); ++ return; ++ } ++ ++ dm->cnt_dm[BTC_DCNT_RUN]++; ++ ++ if (btc->ctrl.always_freerun) { ++ _action_freerun(rtwdev); ++ btc->ctrl.igno_bt = true; ++ goto exit; ++ } ++ ++ if (dm->wl_only) { ++ _action_wl_only(rtwdev); ++ btc->ctrl.igno_bt = true; ++ goto exit; ++ } ++ ++ if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) { ++ _action_wl_off(rtwdev); ++ btc->ctrl.igno_bt = true; ++ goto exit; ++ } ++ ++ btc->ctrl.igno_bt = false; ++ dm->freerun = false; ++ ++ if (reason == BTC_RSN_NTFY_INIT) { ++ _action_wl_init(rtwdev); ++ goto exit; ++ } ++ ++ if (!cx->bt.enable.now && !cx->other.type) { ++ _action_bt_off(rtwdev); ++ goto exit; ++ } ++ ++ if (cx->bt.whql_test) { ++ _action_bt_whql(rtwdev); ++ goto exit; ++ } ++ ++ if (wl->rfk_info.state != BTC_WRFK_STOP) { ++ _action_wl_rfk(rtwdev); ++ goto exit; ++ } ++ ++ if (cx->state_map == BTC_WLINKING) { ++ if (mode == BTC_WLINK_NOLINK || mode == BTC_WLINK_2G_STA || ++ mode == BTC_WLINK_5G) { ++ _action_wl_scan(rtwdev); ++ goto exit; ++ } ++ } ++ ++ if (wl->status.map.scan) { ++ _action_wl_scan(rtwdev); ++ goto exit; ++ } ++ ++ switch (mode) { ++ case BTC_WLINK_NOLINK: ++ _action_wl_nc(rtwdev); ++ break; ++ case BTC_WLINK_2G_STA: ++ _action_wl_2g_sta(rtwdev); ++ break; ++ case BTC_WLINK_2G_AP: ++ _action_wl_2g_ap(rtwdev); ++ break; ++ case BTC_WLINK_2G_GO: ++ _action_wl_2g_go(rtwdev); ++ break; ++ case BTC_WLINK_2G_GC: ++ _action_wl_2g_gc(rtwdev); ++ break; ++ case BTC_WLINK_2G_SCC: ++ _action_wl_2g_scc(rtwdev); ++ break; ++ case BTC_WLINK_2G_MCC: ++ _action_wl_2g_mcc(rtwdev); ++ break; ++ case BTC_WLINK_25G_MCC: ++ _action_wl_25g_mcc(rtwdev); ++ break; ++ case BTC_WLINK_5G: ++ _action_wl_5g(rtwdev); ++ break; ++ case BTC_WLINK_2G_NAN: ++ _action_wl_2g_nan(rtwdev); ++ break; ++ default: ++ _action_wl_other(rtwdev); ++ break; ++ } ++ ++exit: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): exit\n", __func__); ++ _action_common(rtwdev); ++} ++ ++void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ btc->dm.cnt_notify[BTC_NCNT_POWER_ON]++; ++} ++ ++void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); ++ btc->dm.cnt_notify[BTC_NCNT_POWER_OFF]++; ++ ++ btc->cx.wl.status.map.rf_off = 1; ++ ++ _write_scbd(rtwdev, BTC_WSCB_ALL, false); ++ _run_coex(rtwdev, BTC_RSN_NTFY_POWEROFF); ++ ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, 0); ++ ++ btc->cx.wl.status.map.rf_off_pre = btc->cx.wl.status.map.rf_off; ++} ++ ++static void _set_init_info(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ dm->init_info.wl_only = (u8)dm->wl_only; ++ dm->init_info.bt_only = (u8)dm->bt_only; ++ dm->init_info.wl_init_ok = (u8)wl->status.map.init_ok; ++ dm->init_info.dbcc_en = rtwdev->dbcc_en; ++ dm->init_info.cx_other = btc->cx.other.type; ++ dm->init_info.wl_guard_ch = chip->afh_guard_ch; ++ dm->init_info.module = btc->mdinfo; ++} ++ ++void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &rtwdev->btc.dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ _reset_btc_var(rtwdev, BTC_RESET_ALL); ++ btc->dm.run_reason = BTC_RSN_NONE; ++ btc->dm.run_action = BTC_ACT_NONE; ++ btc->ctrl.igno_bt = true; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): mode=%d\n", __func__, mode); ++ ++ dm->cnt_notify[BTC_NCNT_INIT_COEX]++; ++ dm->wl_only = mode == BTC_MODE_WL ? 1 : 0; ++ dm->bt_only = mode == BTC_MODE_BT ? 1 : 0; ++ wl->status.map.rf_off = mode == BTC_MODE_WLOFF ? 1 : 0; ++ ++ chip->ops->btc_set_rfe(rtwdev); ++ chip->ops->btc_init_cfg(rtwdev); ++ ++ if (!wl->status.map.init_ok) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return for WL init fail!!\n", ++ __func__); ++ dm->error.map.init = true; ++ return; ++ } ++ ++ _write_scbd(rtwdev, ++ BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true); ++ _update_bt_scbd(rtwdev, true); ++ if (rtw89_mac_get_ctrl_path(rtwdev)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): PTA owner warning!!\n", ++ __func__); ++ dm->error.map.pta_owner = true; ++ } ++ ++ _set_init_info(rtwdev); ++ _set_wl_tx_power(rtwdev, RTW89_BTC_WL_DEF_TX_PWR); ++ rtw89_btc_fw_set_slots(rtwdev, CXST_MAX, dm->slot); ++ btc_fw_set_monreg(rtwdev); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_INIT); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_CTRL); ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_INIT); ++} ++ ++void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): phy_idx=%d, band=%d\n", ++ __func__, phy_idx, band); ++ btc->dm.cnt_notify[BTC_NCNT_SCAN_START]++; ++ wl->status.map.scan = true; ++ wl->scan_info.band[phy_idx] = band; ++ wl->scan_info.phy_map |= BIT(phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); ++ ++ if (rtwdev->dbcc_en) { ++ wl->dbcc_info.scan_band[phy_idx] = band; ++ _update_dbcc_band(rtwdev, phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_SCAN_START); ++} ++ ++void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): phy_idx=%d\n", __func__, phy_idx); ++ btc->dm.cnt_notify[BTC_NCNT_SCAN_FINISH]++; ++ ++ wl->status.map.scan = false; ++ wl->scan_info.phy_map &= ~BIT(phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); ++ ++ if (rtwdev->dbcc_en) { ++ _update_dbcc_band(rtwdev, phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_SCAN_FINISH); ++} ++ ++void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): phy_idx=%d, band=%d\n", ++ __func__, phy_idx, band); ++ btc->dm.cnt_notify[BTC_NCNT_SWITCH_BAND]++; ++ ++ wl->scan_info.band[phy_idx] = band; ++ wl->scan_info.phy_map |= BIT(phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); ++ ++ if (rtwdev->dbcc_en) { ++ wl->dbcc_info.scan_band[phy_idx] = band; ++ _update_dbcc_band(rtwdev, phy_idx); ++ _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); ++ } ++ _run_coex(rtwdev, BTC_RSN_NTFY_SWBAND); ++} ++ ++void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev, ++ enum btc_pkt_type pkt_type) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_link_info *b = &cx->bt.link_info; ++ struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; ++ struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; ++ u32 cnt; ++ u32 delay = RTW89_COEX_ACT1_WORK_PERIOD; ++ bool delay_work = false; ++ ++ switch (pkt_type) { ++ case PACKET_DHCP: ++ cnt = ++cx->cnt_wl[BTC_WCNT_DHCP]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): DHCP cnt=%d\n", __func__, cnt); ++ wl->status.map.connecting = true; ++ delay_work = true; ++ break; ++ case PACKET_EAPOL: ++ cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): EAPOL cnt=%d\n", __func__, cnt); ++ wl->status.map._4way = true; ++ delay_work = true; ++ if (hfp->exist || hid->exist) ++ delay /= 2; ++ break; ++ case PACKET_EAPOL_END: ++ cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): EAPOL_End cnt=%d\n", ++ __func__, cnt); ++ wl->status.map._4way = false; ++ cancel_delayed_work(&rtwdev->coex_act1_work); ++ break; ++ case PACKET_ARP: ++ cnt = ++cx->cnt_wl[BTC_WCNT_ARP]; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): ARP cnt=%d\n", __func__, cnt); ++ return; ++ case PACKET_ICMP: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): ICMP pkt\n", __func__); ++ return; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): unknown packet type %d\n", ++ __func__, pkt_type); ++ return; ++ } ++ ++ if (delay_work) { ++ cancel_delayed_work(&rtwdev->coex_act1_work); ++ ieee80211_queue_delayed_work(rtwdev->hw, ++ &rtwdev->coex_act1_work, delay); ++ } ++ ++ btc->dm.cnt_notify[BTC_NCNT_SPECIAL_PACKET]++; ++ _run_coex(rtwdev, BTC_RSN_NTFY_SPECIFIC_PACKET); ++} ++ ++void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.eapol_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_EAPOL); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.arp_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_ARP); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.dhcp_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_DHCP); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_btc_ntfy_icmp_packet_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ btc.icmp_notify_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_ICMP); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void _update_bt_info(struct rtw89_dev *rtwdev, u8 *buf, u32 len) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; ++ struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &b->a2dp_desc; ++ struct rtw89_btc_bt_pan_desc *pan = &b->pan_desc; ++ union btc_btinfo btinfo; ++ ++ if (buf[BTC_BTINFO_L1] != 6) ++ return; ++ ++ if (!memcmp(bt->raw_info, buf, BTC_BTINFO_MAX)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by bt-info duplicate!!\n", ++ __func__); ++ cx->cnt_bt[BTC_BCNT_INFOSAME]++; ++ return; ++ } ++ ++ memcpy(bt->raw_info, buf, BTC_BTINFO_MAX); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): bt_info[2]=0x%02x\n", ++ __func__, bt->raw_info[2]); ++ ++ /* reset to mo-connect before update */ ++ b->status.val = BTC_BLINK_NOCONNECT; ++ b->profile_cnt.last = b->profile_cnt.now; ++ b->relink.last = b->relink.now; ++ a2dp->exist_last = a2dp->exist; ++ b->multi_link.last = b->multi_link.now; ++ bt->inq_pag.last = bt->inq_pag.now; ++ b->profile_cnt.now = 0; ++ hid->type = 0; ++ ++ /* parse raw info low-Byte2 */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_L2]; ++ b->status.map.connect = btinfo.lb2.connect; ++ b->status.map.sco_busy = btinfo.lb2.sco_busy; ++ b->status.map.acl_busy = btinfo.lb2.acl_busy; ++ b->status.map.inq_pag = btinfo.lb2.inq_pag; ++ bt->inq_pag.now = btinfo.lb2.inq_pag; ++ cx->cnt_bt[BTC_BCNT_INQPAG] += !!(bt->inq_pag.now && !bt->inq_pag.last); ++ ++ hfp->exist = btinfo.lb2.hfp; ++ b->profile_cnt.now += (u8)hfp->exist; ++ hid->exist = btinfo.lb2.hid; ++ b->profile_cnt.now += (u8)hid->exist; ++ a2dp->exist = btinfo.lb2.a2dp; ++ b->profile_cnt.now += (u8)a2dp->exist; ++ pan->active = btinfo.lb2.pan; ++ ++ /* parse raw info low-Byte3 */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_L3]; ++ if (btinfo.lb3.retry != 0) ++ cx->cnt_bt[BTC_BCNT_RETRY]++; ++ b->cqddr = btinfo.lb3.cqddr; ++ cx->cnt_bt[BTC_BCNT_INQ] += !!(btinfo.lb3.inq && !bt->inq); ++ bt->inq = btinfo.lb3.inq; ++ cx->cnt_bt[BTC_BCNT_PAGE] += !!(btinfo.lb3.pag && !bt->pag); ++ bt->pag = btinfo.lb3.pag; ++ ++ b->status.map.mesh_busy = btinfo.lb3.mesh_busy; ++ /* parse raw info high-Byte0 */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H0]; ++ /* raw val is dBm unit, translate from -100~ 0dBm to 0~100%*/ ++ b->rssi = chip->ops->btc_get_bt_rssi(rtwdev, btinfo.hb0.rssi); ++ ++ /* parse raw info high-Byte1 */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H1]; ++ b->status.map.ble_connect = btinfo.hb1.ble_connect; ++ if (btinfo.hb1.ble_connect) ++ hid->type |= (hid->exist ? BTC_HID_BLE : BTC_HID_RCU); ++ ++ cx->cnt_bt[BTC_BCNT_REINIT] += !!(btinfo.hb1.reinit && !bt->reinit); ++ bt->reinit = btinfo.hb1.reinit; ++ cx->cnt_bt[BTC_BCNT_RELINK] += !!(btinfo.hb1.relink && !b->relink.now); ++ b->relink.now = btinfo.hb1.relink; ++ cx->cnt_bt[BTC_BCNT_IGNOWL] += !!(btinfo.hb1.igno_wl && !bt->igno_wl); ++ bt->igno_wl = btinfo.hb1.igno_wl; ++ ++ if (bt->igno_wl && !cx->wl.status.map.rf_off) ++ _set_bt_ignore_wlan_act(rtwdev, false); ++ ++ hid->type |= (btinfo.hb1.voice ? BTC_HID_RCU_VOICE : 0); ++ bt->ble_scan_en = btinfo.hb1.ble_scan; ++ ++ cx->cnt_bt[BTC_BCNT_ROLESW] += !!(btinfo.hb1.role_sw && !b->role_sw); ++ b->role_sw = btinfo.hb1.role_sw; ++ ++ b->multi_link.now = btinfo.hb1.multi_link; ++ ++ /* parse raw info high-Byte2 */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H2]; ++ pan->exist = btinfo.hb2.pan_active; ++ b->profile_cnt.now += (u8)pan->exist; ++ ++ cx->cnt_bt[BTC_BCNT_AFH] += !!(btinfo.hb2.afh_update && !b->afh_update); ++ b->afh_update = btinfo.hb2.afh_update; ++ a2dp->active = btinfo.hb2.a2dp_active; ++ b->slave_role = btinfo.hb2.slave; ++ hid->slot_info = btinfo.hb2.hid_slot; ++ hid->pair_cnt = btinfo.hb2.hid_cnt; ++ hid->type |= (hid->slot_info == BTC_HID_218 ? ++ BTC_HID_218 : BTC_HID_418); ++ /* parse raw info high-Byte3 */ ++ btinfo.val = bt->raw_info[BTC_BTINFO_H3]; ++ a2dp->bitpool = btinfo.hb3.a2dp_bitpool; ++ ++ if (b->tx_3m != (u32)btinfo.hb3.tx_3m) ++ cx->cnt_bt[BTC_BCNT_RATECHG]++; ++ b->tx_3m = (u32)btinfo.hb3.tx_3m; ++ ++ a2dp->sink = btinfo.hb3.a2dp_sink; ++ ++ if (b->profile_cnt.now || b->status.map.ble_connect) ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP, 1); ++ else ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP, 0); ++ ++ if (!a2dp->exist_last && a2dp->exist) { ++ a2dp->vendor_id = 0; ++ a2dp->flush_time = 0; ++ a2dp->play_latency = 1; ++ ieee80211_queue_delayed_work(rtwdev->hw, ++ &rtwdev->coex_bt_devinfo_work, ++ RTW89_COEX_BT_DEVINFO_WORK_PERIOD); ++ } ++ ++ if (a2dp->exist && (a2dp->flush_time == 0 || a2dp->vendor_id == 0 || ++ a2dp->play_latency == 1)) ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_DEVICE_INFO, 1); ++ else ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_DEVICE_INFO, 0); ++ ++ _run_coex(rtwdev, BTC_RSN_UPDATE_BT_INFO); ++} ++ ++enum btc_wl_mode { ++ BTC_WL_MODE_HT = 0, ++ BTC_WL_MODE_VHT = 1, ++ BTC_WL_MODE_HE = 2, ++ BTC_WL_MODE_NUM, ++}; ++ ++void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ struct rtw89_sta *rtwsta, enum btc_role_state state) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_link_info r = {0}; ++ struct rtw89_btc_wl_link_info *wlinfo = NULL; ++ u8 mode = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], state=%d\n", state); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], role is STA=%d\n", ++ vif->type == NL80211_IFTYPE_STATION); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], port=%d\n", rtwvif->port); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], band=%d ch=%d bw=%d\n", ++ hal->current_band_type, hal->current_channel, ++ hal->current_band_width); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], associated=%d\n", ++ state == BTC_ROLE_MSTS_STA_CONN_END); ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], bcn_period=%d dtim_period=%d\n", ++ vif->bss_conf.beacon_int, vif->bss_conf.dtim_period); ++ ++ if (rtwsta) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], STA mac_id=%d\n", ++ rtwsta->mac_id); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], STA support HE=%d VHT=%d HT=%d\n", ++ sta->he_cap.has_he, ++ sta->vht_cap.vht_supported, ++ sta->ht_cap.ht_supported); ++ if (sta->he_cap.has_he) ++ mode |= BIT(BTC_WL_MODE_HE); ++ if (sta->vht_cap.vht_supported) ++ mode |= BIT(BTC_WL_MODE_VHT); ++ if (sta->ht_cap.ht_supported) ++ mode |= BIT(BTC_WL_MODE_HT); ++ ++ r.mode = mode; ++ } ++ ++ if (rtwvif->wifi_role >= RTW89_WIFI_ROLE_MLME_MAX) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], wifi_role=%d\n", rtwvif->wifi_role); ++ ++ r.role = rtwvif->wifi_role; ++ r.phy = rtwvif->phy_idx; ++ r.pid = rtwvif->port; ++ r.active = true; ++ r.connected = MLME_LINKED; ++ r.bcn_period = vif->bss_conf.beacon_int; ++ r.dtim_period = vif->bss_conf.dtim_period; ++ r.band = hal->current_band_type; ++ r.ch = hal->current_channel; ++ r.bw = hal->current_band_width; ++ ether_addr_copy(r.mac_addr, rtwvif->mac_addr); ++ ++ if (rtwsta && vif->type == NL80211_IFTYPE_STATION) ++ r.mac_id = rtwsta->mac_id; ++ ++ btc->dm.cnt_notify[BTC_NCNT_ROLE_INFO]++; ++ ++ wlinfo = &wl->link_info[r.pid]; ++ ++ memcpy(wlinfo, &r, sizeof(*wlinfo)); ++ _update_wl_info(rtwdev); ++ ++ if (wlinfo->role == RTW89_WIFI_ROLE_STATION && ++ wlinfo->connected == MLME_NO_LINK) ++ btc->dm.leak_ap = 0; ++ ++ if (state == BTC_ROLE_MSTS_STA_CONN_START) ++ wl->status.map.connecting = 1; ++ else ++ wl->status.map.connecting = 0; ++ ++ if (state == BTC_ROLE_MSTS_STA_DIS_CONN) ++ wl->status.map._4way = false; ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_ROLE_INFO); ++} ++ ++void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): rf_state = %d\n", ++ __func__, rf_state); ++ btc->dm.cnt_notify[BTC_NCNT_RADIO_STATE]++; ++ ++ switch (rf_state) { ++ case BTC_RFCTRL_WL_OFF: ++ wl->status.map.rf_off = 1; ++ wl->status.map.lps = 0; ++ break; ++ case BTC_RFCTRL_FW_CTRL: ++ wl->status.map.rf_off = 0; ++ wl->status.map.lps = 1; ++ break; ++ case BTC_RFCTRL_WL_ON: ++ default: ++ wl->status.map.rf_off = 0; ++ wl->status.map.lps = 0; ++ break; ++ } ++ ++ if (rf_state == BTC_RFCTRL_WL_ON) { ++ rtw89_btc_fw_en_rpt(rtwdev, ++ RPT_EN_MREG | RPT_EN_BT_VER_INFO, true); ++ _write_scbd(rtwdev, BTC_WSCB_ACTIVE, true); ++ _update_bt_scbd(rtwdev, true); ++ chip->ops->btc_init_cfg(rtwdev); ++ } else { ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, false); ++ _write_scbd(rtwdev, BTC_WSCB_ACTIVE | BTC_WSCB_WLBUSY, false); ++ } ++ ++ _run_coex(rtwdev, BTC_RSN_NTFY_RADIO_STATE); ++ ++ wl->status.map.rf_off_pre = wl->status.map.rf_off; ++ wl->status.map.lps_pre = wl->status.map.lps; ++} ++ ++static bool _ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_path, ++ enum btc_wl_rfk_type type, ++ enum btc_wl_rfk_state state) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ bool result = BTC_WRFK_REJECT; ++ ++ wl->rfk_info.type = type; ++ wl->rfk_info.path_map = FIELD_GET(BTC_RFK_PATH_MAP, phy_path); ++ wl->rfk_info.phy_map = FIELD_GET(BTC_RFK_PHY_MAP, phy_path); ++ wl->rfk_info.band = FIELD_GET(BTC_RFK_BAND_MAP, phy_path); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s()_start: phy=0x%x, path=0x%x, type=%d, state=%d\n", ++ __func__, wl->rfk_info.phy_map, wl->rfk_info.path_map, ++ type, state); ++ ++ switch (state) { ++ case BTC_WRFK_START: ++ result = _chk_wl_rfk_request(rtwdev); ++ wl->rfk_info.state = result ? BTC_WRFK_START : BTC_WRFK_STOP; ++ ++ _write_scbd(rtwdev, BTC_WSCB_WLRFK, result); ++ ++ btc->dm.cnt_notify[BTC_NCNT_WL_RFK]++; ++ break; ++ case BTC_WRFK_ONESHOT_START: ++ case BTC_WRFK_ONESHOT_STOP: ++ if (wl->rfk_info.state == BTC_WRFK_STOP) { ++ result = BTC_WRFK_REJECT; ++ } else { ++ result = BTC_WRFK_ALLOW; ++ wl->rfk_info.state = state; ++ } ++ break; ++ case BTC_WRFK_STOP: ++ result = BTC_WRFK_ALLOW; ++ wl->rfk_info.state = BTC_WRFK_STOP; ++ ++ _write_scbd(rtwdev, BTC_WSCB_WLRFK, false); ++ cancel_delayed_work(&rtwdev->coex_rfk_chk_work); ++ break; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s() warning state=%d\n", __func__, state); ++ break; ++ } ++ ++ if (result == BTC_WRFK_ALLOW) { ++ if (wl->rfk_info.state == BTC_WRFK_START || ++ wl->rfk_info.state == BTC_WRFK_STOP) ++ _run_coex(rtwdev, BTC_RSN_NTFY_WL_RFK); ++ ++ if (wl->rfk_info.state == BTC_WRFK_START) ++ ieee80211_queue_delayed_work(rtwdev->hw, ++ &rtwdev->coex_rfk_chk_work, ++ RTW89_COEX_RFK_CHK_WORK_PERIOD); ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s()_finish: rfk_cnt=%d, result=%d\n", ++ __func__, btc->dm.cnt_notify[BTC_NCNT_WL_RFK], result); ++ ++ return result == BTC_WRFK_ALLOW; ++} ++ ++void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map, ++ enum btc_wl_rfk_type type, ++ enum btc_wl_rfk_state state) ++{ ++ u8 band; ++ bool allow; ++ int ret; ++ ++ band = FIELD_GET(BTC_RFK_BAND_MAP, phy_map); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RFK] RFK notify (%s / PHY%u / K_type = %u / path_idx = %lu / process = %s)\n", ++ band == RTW89_BAND_2G ? "2G" : ++ band == RTW89_BAND_5G ? "5G" : "6G", ++ !!(FIELD_GET(BTC_RFK_PHY_MAP, phy_map) & BIT(RTW89_PHY_1)), ++ type, ++ FIELD_GET(BTC_RFK_PATH_MAP, phy_map), ++ state == BTC_WRFK_STOP ? "RFK_STOP" : ++ state == BTC_WRFK_START ? "RFK_START" : ++ state == BTC_WRFK_ONESHOT_START ? "ONE-SHOT_START" : ++ "ONE-SHOT_STOP"); ++ ++ if (state != BTC_WRFK_START || rtwdev->is_bt_iqk_timeout) { ++ _ntfy_wl_rfk(rtwdev, phy_map, type, state); ++ return; ++ } ++ ++ ret = read_poll_timeout(_ntfy_wl_rfk, allow, allow, 40, 100000, false, ++ rtwdev, phy_map, type, state); ++ if (ret) { ++ rtw89_warn(rtwdev, "RFK notify timeout\n"); ++ rtwdev->is_bt_iqk_timeout = true; ++ } ++} ++ ++struct rtw89_btc_wl_sta_iter_data { ++ struct rtw89_dev *rtwdev; ++ u8 busy_all; ++ u8 dir_all; ++ u8 rssi_map_all; ++ bool is_sta_change; ++ bool is_traffic_change; ++}; ++ ++static void rtw89_btc_ntfy_wl_sta_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_btc_wl_sta_iter_data *iter_data = ++ (struct rtw89_btc_wl_sta_iter_data *)data; ++ struct rtw89_dev *rtwdev = iter_data->rtwdev; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_link_info *link_info = NULL; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_traffic_stats *link_info_t = NULL; ++ struct rtw89_vif *rtwvif = rtwsta->rtwvif; ++ struct rtw89_traffic_stats *stats = &rtwvif->stats; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u32 last_tx_rate, last_rx_rate; ++ u16 last_tx_lvl, last_rx_lvl; ++ u8 port = rtwvif->port; ++ u8 rssi; ++ u8 busy = 0; ++ u8 dir = 0; ++ u8 rssi_map = 0; ++ u8 i = 0; ++ bool is_sta_change = false, is_traffic_change = false; ++ ++ rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], rssi=%d\n", rssi); ++ ++ link_info = &wl->link_info[port]; ++ link_info->stat.traffic = rtwvif->stats; ++ link_info_t = &link_info->stat.traffic; ++ ++ if (link_info->connected == MLME_NO_LINK) { ++ link_info->rx_rate_drop_cnt = 0; ++ return; ++ } ++ ++ link_info->stat.rssi = rssi; ++ for (i = 0; i < BTC_WL_RSSI_THMAX; i++) { ++ link_info->rssi_state[i] = ++ _update_rssi_state(rtwdev, ++ link_info->rssi_state[i], ++ link_info->stat.rssi, ++ chip->wl_rssi_thres[i]); ++ if (BTC_RSSI_LOW(link_info->rssi_state[i])) ++ rssi_map |= BIT(i); ++ ++ if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED && ++ BTC_RSSI_CHANGE(link_info->rssi_state[i])) ++ is_sta_change = true; ++ } ++ iter_data->rssi_map_all |= rssi_map; ++ ++ last_tx_rate = link_info_t->tx_rate; ++ last_rx_rate = link_info_t->rx_rate; ++ last_tx_lvl = (u16)link_info_t->tx_tfc_lv; ++ last_rx_lvl = (u16)link_info_t->rx_tfc_lv; ++ ++ if (stats->tx_tfc_lv != RTW89_TFC_IDLE || ++ stats->rx_tfc_lv != RTW89_TFC_IDLE) ++ busy = 1; ++ ++ if (stats->tx_tfc_lv > stats->rx_tfc_lv) ++ dir = RTW89_TFC_UL; ++ else ++ dir = RTW89_TFC_DL; ++ ++ link_info = &wl->link_info[port]; ++ if (link_info->busy != busy || link_info->dir != dir) { ++ is_sta_change = true; ++ link_info->busy = busy; ++ link_info->dir = dir; ++ } ++ ++ iter_data->busy_all |= busy; ++ iter_data->dir_all |= BIT(dir); ++ ++ if (rtwsta->rx_hw_rate <= RTW89_HW_RATE_CCK2 && ++ last_rx_rate > RTW89_HW_RATE_CCK2 && ++ link_info_t->rx_tfc_lv > RTW89_TFC_IDLE) ++ link_info->rx_rate_drop_cnt++; ++ ++ if (last_tx_rate != rtwsta->ra_report.hw_rate || ++ last_rx_rate != rtwsta->rx_hw_rate || ++ last_tx_lvl != link_info_t->tx_tfc_lv || ++ last_rx_lvl != link_info_t->rx_tfc_lv) ++ is_traffic_change = true; ++ ++ link_info_t->tx_rate = rtwsta->ra_report.hw_rate; ++ link_info_t->rx_rate = rtwsta->rx_hw_rate; ++ ++ wl->role_info.active_role[port].tx_lvl = (u16)stats->tx_tfc_lv; ++ wl->role_info.active_role[port].rx_lvl = (u16)stats->rx_tfc_lv; ++ wl->role_info.active_role[port].tx_rate = rtwsta->ra_report.hw_rate; ++ wl->role_info.active_role[port].rx_rate = rtwsta->rx_hw_rate; ++ ++ if (is_sta_change) ++ iter_data->is_sta_change = true; ++ ++ if (is_traffic_change) ++ iter_data->is_traffic_change = true; ++} ++ ++#define BTC_NHM_CHK_INTVL 20 ++ ++void rtw89_btc_ntfy_wl_sta(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_sta_iter_data data = {.rtwdev = rtwdev}; ++ u8 i; ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_btc_ntfy_wl_sta_iter, ++ &data); ++ ++ wl->rssi_level = 0; ++ btc->dm.cnt_notify[BTC_NCNT_WL_STA]++; ++ for (i = BTC_WL_RSSI_THMAX; i > 0; i--) { ++ /* set RSSI level 4 ~ 0 if rssi bit map match */ ++ if (data.rssi_map_all & BIT(i - 1)) { ++ wl->rssi_level = i; ++ break; ++ } ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): busy=%d\n", ++ __func__, !!wl->status.map.busy); ++ ++ _write_scbd(rtwdev, BTC_WSCB_WLBUSY, (!!wl->status.map.busy)); ++ ++ if (data.is_traffic_change) ++ _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); ++ if (data.is_sta_change) { ++ wl->status.map.busy = data.busy_all; ++ wl->status.map.traffic_dir = data.dir_all; ++ _run_coex(rtwdev, BTC_RSN_NTFY_WL_STA); ++ } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] >= ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] + BTC_NHM_CHK_INTVL) { ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = ++ btc->dm.cnt_notify[BTC_NCNT_WL_STA]; ++ } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] < ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST]) { ++ btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = ++ btc->dm.cnt_notify[BTC_NCNT_WL_STA]; ++ } ++} ++ ++void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ u8 *buf = &skb->data[RTW89_C2H_HEADER_LEN]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): C2H BT len:%d class:%d fun:%d\n", ++ __func__, len, class, func); ++ ++ if (class != BTFC_FW_EVENT) ++ return; ++ ++ switch (func) { ++ case BTF_EVNT_RPT: ++ case BTF_EVNT_BUF_OVERFLOW: ++ pfwinfo->event[func]++; ++ /* Don't need rtw89_leave_ps_mode() */ ++ btc_fw_event(rtwdev, func, buf, len); ++ break; ++ case BTF_EVNT_BT_INFO: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], handle C2H BT INFO with data %8ph\n", buf); ++ btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE]++; ++ rtw89_leave_ps_mode(rtwdev); ++ _update_bt_info(rtwdev, buf, len); ++ break; ++ case BTF_EVNT_BT_SCBD: ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], handle C2H BT SCBD with data %8ph\n", buf); ++ btc->cx.cnt_bt[BTC_BCNT_SCBDUPDATE]++; ++ rtw89_leave_ps_mode(rtwdev); ++ _update_bt_scbd(rtwdev, false); ++ break; ++ case BTF_EVNT_BT_PSD: ++ break; ++ case BTF_EVNT_BT_REG: ++ btc->dbg.rb_done = true; ++ btc->dbg.rb_val = le32_to_cpu(*((__le32 *)buf)); ++ ++ break; ++ case BTF_EVNT_C2H_LOOPBACK: ++ btc->dbg.rb_done = true; ++ btc->dbg.rb_val = buf[0]; ++ break; ++ case BTF_EVNT_CX_RUNINFO: ++ btc->dm.cnt_dm[BTC_DCNT_CX_RUNINFO]++; ++ break; ++ } ++} ++ ++#define BTC_CX_FW_OFFLOAD 0 ++ ++static void _show_cx_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ u32 ver_main = 0, ver_sub = 0, ver_hotfix = 0, id_branch = 0; ++ ++ if (!(dm->coex_info_map & BTC_COEX_INFO_CX)) ++ return; ++ ++ dm->cnt_notify[BTC_NCNT_SHOW_COEX_INFO]++; ++ ++ seq_printf(m, "========== [BTC COEX INFO (%d)] ==========\n", ++ chip->chip_id); ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), chip->para_ver); ++ ver_sub = FIELD_GET(GENMASK(23, 16), chip->para_ver); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), chip->para_ver); ++ id_branch = FIELD_GET(GENMASK(7, 0), chip->para_ver); ++ seq_printf(m, " %-15s : Coex:%d.%d.%d(branch:%d), ", ++ "[coex_version]", ver_main, ver_sub, ver_hotfix, id_branch); ++ ++ if (dm->wl_fw_cx_offload != BTC_CX_FW_OFFLOAD) ++ dm->error.map.offload_mismatch = true; ++ else ++ dm->error.map.offload_mismatch = false; ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw_coex); ++ ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw_coex); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw_coex); ++ id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw_coex); ++ seq_printf(m, "WL_FW_coex:%d.%d.%d(branch:%d)", ++ ver_main, ver_sub, ver_hotfix, id_branch); ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), chip->wlcx_desired); ++ ver_sub = FIELD_GET(GENMASK(23, 16), chip->wlcx_desired); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), chip->wlcx_desired); ++ seq_printf(m, "(%s, desired:%d.%d.%d), ", ++ (wl->ver_info.fw_coex >= chip->wlcx_desired ? ++ "Match" : "Mis-Match"), ver_main, ver_sub, ver_hotfix); ++ ++ seq_printf(m, "BT_FW_coex:%d(%s, desired:%d)\n", ++ bt->ver_info.fw_coex, ++ (bt->ver_info.fw_coex >= chip->btcx_desired ? ++ "Match" : "Mis-Match"), chip->btcx_desired); ++ ++ if (bt->enable.now && bt->ver_info.fw == 0) ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, true); ++ else ++ rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, false); ++ ++ ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw); ++ ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw); ++ ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw); ++ id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw); ++ seq_printf(m, " %-15s : WL_FW:%d.%d.%d.%d, BT_FW:0x%x(%s)\n", ++ "[sub_module]", ++ ver_main, ver_sub, ver_hotfix, id_branch, ++ bt->ver_info.fw, bt->run_patch_code ? "patch" : "ROM"); ++ ++ seq_printf(m, " %-15s : cv:%x, rfe_type:0x%x, ant_iso:%d, ant_pg:%d, %s", ++ "[hw_info]", btc->mdinfo.cv, btc->mdinfo.rfe_type, ++ btc->mdinfo.ant.isolation, btc->mdinfo.ant.num, ++ (btc->mdinfo.ant.num > 1 ? "" : (btc->mdinfo.ant.single_pos ? ++ "1Ant_Pos:S1, " : "1Ant_Pos:S0, "))); ++ ++ seq_printf(m, "3rd_coex:%d, dbcc:%d, tx_num:%d, rx_num:%d\n", ++ btc->cx.other.type, rtwdev->dbcc_en, hal->tx_nss, ++ hal->rx_nss); ++} ++ ++static void _show_wl_role_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_link_info *plink = NULL; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; ++ struct rtw89_traffic_stats *t; ++ u8 i; ++ ++ if (rtwdev->dbcc_en) { ++ seq_printf(m, ++ " %-15s : PHY0_band(op:%d/scan:%d/real:%d), ", ++ "[dbcc_info]", wl_dinfo->op_band[RTW89_PHY_0], ++ wl_dinfo->scan_band[RTW89_PHY_0], ++ wl_dinfo->real_band[RTW89_PHY_0]); ++ seq_printf(m, ++ "PHY1_band(op:%d/scan:%d/real:%d)\n", ++ wl_dinfo->op_band[RTW89_PHY_1], ++ wl_dinfo->scan_band[RTW89_PHY_1], ++ wl_dinfo->real_band[RTW89_PHY_1]); ++ } ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++) { ++ plink = &btc->cx.wl.link_info[i]; ++ ++ if (!plink->active) ++ continue; ++ ++ seq_printf(m, ++ " [port_%d] : role=%d(phy-%d), connect=%d(client_cnt=%d), mode=%d, center_ch=%d, bw=%d", ++ plink->pid, (u32)plink->role, plink->phy, ++ (u32)plink->connected, plink->client_cnt - 1, ++ (u32)plink->mode, plink->ch, (u32)plink->bw); ++ ++ if (plink->connected == MLME_NO_LINK) ++ continue; ++ ++ seq_printf(m, ++ ", mac_id=%d, max_tx_time=%dus, max_tx_retry=%d\n", ++ plink->mac_id, plink->tx_time, plink->tx_retry); ++ ++ seq_printf(m, ++ " [port_%d] : rssi=-%ddBm(%d), busy=%d, dir=%s, ", ++ plink->pid, 110 - plink->stat.rssi, ++ plink->stat.rssi, plink->busy, ++ plink->dir == RTW89_TFC_UL ? "UL" : "DL"); ++ ++ t = &plink->stat.traffic; ++ ++ seq_printf(m, ++ "tx[rate:%d/busy_level:%d], ", ++ (u32)t->tx_rate, t->tx_tfc_lv); ++ ++ seq_printf(m, "rx[rate:%d/busy_level:%d/drop:%d]\n", ++ (u32)t->rx_rate, ++ t->rx_tfc_lv, plink->rx_rate_drop_cnt); ++ } ++} ++ ++static void _show_wl_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_WL)) ++ return; ++ ++ seq_puts(m, "========== [WL Status] ==========\n"); ++ ++ seq_printf(m, " %-15s : link_mode:%d, ", ++ "[status]", (u32)wl_rinfo->link_mode); ++ ++ seq_printf(m, ++ "rf_off:%s, power_save:%s, scan:%s(band:%d/phy_map:0x%x), ", ++ wl->status.map.rf_off ? "Y" : "N", ++ wl->status.map.lps ? "Y" : "N", ++ wl->status.map.scan ? "Y" : "N", ++ wl->scan_info.band[RTW89_PHY_0], wl->scan_info.phy_map); ++ ++ seq_printf(m, ++ "connecting:%s, roam:%s, 4way:%s, init_ok:%s\n", ++ wl->status.map.connecting ? "Y" : "N", ++ wl->status.map.roaming ? "Y" : "N", ++ wl->status.map._4way ? "Y" : "N", ++ wl->status.map.init_ok ? "Y" : "N"); ++ ++ _show_wl_role_info(rtwdev, m); ++} ++ ++enum btc_bt_a2dp_type { ++ BTC_A2DP_LEGACY = 0, ++ BTC_A2DP_TWS_SNIFF = 1, ++ BTC_A2DP_TWS_RELAY = 2, ++}; ++ ++static void _show_bt_profile_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; ++ struct rtw89_btc_bt_hfp_desc hfp = bt_linfo->hfp_desc; ++ struct rtw89_btc_bt_hid_desc hid = bt_linfo->hid_desc; ++ struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; ++ struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; ++ ++ if (hfp.exist) { ++ seq_printf(m, " %-15s : type:%s, sut_pwr:%d, golden-rx:%d", ++ "[HFP]", (hfp.type == 0 ? "SCO" : "eSCO"), ++ bt_linfo->sut_pwr_level[0], ++ bt_linfo->golden_rx_shift[0]); ++ } ++ ++ if (hid.exist) { ++ seq_printf(m, ++ "\n\r %-15s : type:%s%s%s%s%s pair-cnt:%d, sut_pwr:%d, golden-rx:%d\n", ++ "[HID]", ++ hid.type & BTC_HID_218 ? "2/18," : "", ++ hid.type & BTC_HID_418 ? "4/18," : "", ++ hid.type & BTC_HID_BLE ? "BLE," : "", ++ hid.type & BTC_HID_RCU ? "RCU," : "", ++ hid.type & BTC_HID_RCU_VOICE ? "RCU-Voice," : "", ++ hid.pair_cnt, bt_linfo->sut_pwr_level[1], ++ bt_linfo->golden_rx_shift[1]); ++ } ++ ++ if (a2dp.exist) { ++ seq_printf(m, ++ " %-15s : type:%s, bit-pool:%d, flush-time:%d, ", ++ "[A2DP]", ++ a2dp.type == BTC_A2DP_LEGACY ? "Legacy" : "TWS", ++ a2dp.bitpool, a2dp.flush_time); ++ ++ seq_printf(m, ++ "vid:0x%x, Dev-name:0x%x, sut_pwr:%d, golden-rx:%d\n", ++ a2dp.vendor_id, a2dp.device_name, ++ bt_linfo->sut_pwr_level[2], ++ bt_linfo->golden_rx_shift[2]); ++ } ++ ++ if (pan.exist) { ++ seq_printf(m, " %-15s : sut_pwr:%d, golden-rx:%d\n", ++ "[PAN]", ++ bt_linfo->sut_pwr_level[3], ++ bt_linfo->golden_rx_shift[3]); ++ } ++} ++ ++static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; ++ u8 *afh = bt_linfo->afh_map; ++ u16 polt_cnt = 0; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT)) ++ return; ++ ++ seq_puts(m, "========== [BT Status] ==========\n"); ++ ++ seq_printf(m, " %-15s : enable:%s, btg:%s%s, connect:%s, ", ++ "[status]", bt->enable.now ? "Y" : "N", ++ bt->btg_type ? "Y" : "N", ++ (bt->enable.now && (bt->btg_type != module->bt_pos) ? ++ "(efuse-mismatch!!)" : ""), ++ (bt_linfo->status.map.connect ? "Y" : "N")); ++ ++ seq_printf(m, "igno_wl:%s, mailbox_avl:%s, rfk_state:0x%x\n", ++ bt->igno_wl ? "Y" : "N", ++ bt->mbx_avl ? "Y" : "N", bt->rfk_info.val); ++ ++ seq_printf(m, " %-15s : profile:%s%s%s%s%s ", ++ "[profile]", ++ (bt_linfo->profile_cnt.now == 0) ? "None," : "", ++ bt_linfo->hfp_desc.exist ? "HFP," : "", ++ bt_linfo->hid_desc.exist ? "HID," : "", ++ bt_linfo->a2dp_desc.exist ? ++ (bt_linfo->a2dp_desc.sink ? "A2DP_sink," : "A2DP,") : "", ++ bt_linfo->pan_desc.exist ? "PAN," : ""); ++ ++ seq_printf(m, ++ "multi-link:%s, role:%s, ble-connect:%s, CQDDR:%s, A2DP_active:%s, PAN_active:%s\n", ++ bt_linfo->multi_link.now ? "Y" : "N", ++ bt_linfo->slave_role ? "Slave" : "Master", ++ bt_linfo->status.map.ble_connect ? "Y" : "N", ++ bt_linfo->cqddr ? "Y" : "N", ++ bt_linfo->a2dp_desc.active ? "Y" : "N", ++ bt_linfo->pan_desc.active ? "Y" : "N"); ++ ++ seq_printf(m, ++ " %-15s : rssi:%ddBm, tx_rate:%dM, %s%s%s", ++ "[link]", bt_linfo->rssi - 100, ++ bt_linfo->tx_3m ? 3 : 2, ++ bt_linfo->status.map.inq_pag ? " inq-page!!" : "", ++ bt_linfo->status.map.acl_busy ? " acl_busy!!" : "", ++ bt_linfo->status.map.mesh_busy ? " mesh_busy!!" : ""); ++ ++ seq_printf(m, ++ "%s afh_map[%02x%02x_%02x%02x_%02x%02x_%02x%02x_%02x%02x], ", ++ bt_linfo->relink.now ? " ReLink!!" : "", ++ afh[0], afh[1], afh[2], afh[3], afh[4], ++ afh[5], afh[6], afh[7], afh[8], afh[9]); ++ ++ seq_printf(m, "wl_ch_map[en:%d/ch:%d/bw:%d]\n", ++ wl->afh_info.en, wl->afh_info.ch, wl->afh_info.bw); ++ ++ seq_printf(m, ++ " %-15s : retry:%d, relink:%d, rate_chg:%d, reinit:%d, reenable:%d, ", ++ "[stat_cnt]", cx->cnt_bt[BTC_BCNT_RETRY], ++ cx->cnt_bt[BTC_BCNT_RELINK], cx->cnt_bt[BTC_BCNT_RATECHG], ++ cx->cnt_bt[BTC_BCNT_REINIT], cx->cnt_bt[BTC_BCNT_REENABLE]); ++ ++ seq_printf(m, ++ "role-switch:%d, afh:%d, inq_page:%d(inq:%d/page:%d), igno_wl:%d\n", ++ cx->cnt_bt[BTC_BCNT_ROLESW], cx->cnt_bt[BTC_BCNT_AFH], ++ cx->cnt_bt[BTC_BCNT_INQPAG], cx->cnt_bt[BTC_BCNT_INQ], ++ cx->cnt_bt[BTC_BCNT_PAGE], cx->cnt_bt[BTC_BCNT_IGNOWL]); ++ ++ _show_bt_profile_info(rtwdev, m); ++ ++ seq_printf(m, ++ " %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)\n", ++ "[bt_info]", bt->raw_info[2], bt->raw_info[3], ++ bt->raw_info[4], bt->raw_info[5], bt->raw_info[6], ++ bt->raw_info[7], ++ bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply", ++ cx->cnt_bt[BTC_BCNT_INFOUPDATE], ++ cx->cnt_bt[BTC_BCNT_INFOSAME]); ++ ++ if (wl->status.map.lps || wl->status.map.rf_off) ++ return; ++ ++ chip->ops->btc_update_bt_cnt(rtwdev); ++ _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_FREEZE, 0); ++ ++ seq_printf(m, ++ " %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)\n", ++ "[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX], ++ cx->cnt_bt[BTC_BCNT_HIPRI_TX], cx->cnt_bt[BTC_BCNT_LOPRI_RX], ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX], polt_cnt); ++} ++ ++#define CASE_BTC_RSN_STR(e) case BTC_RSN_ ## e: return #e ++#define CASE_BTC_ACT_STR(e) case BTC_ACT_ ## e | BTC_ACT_EXT_BIT: return #e ++#define CASE_BTC_POLICY_STR(e) \ ++ case BTC_CXP_ ## e | BTC_POLICY_EXT_BIT: return #e ++ ++static const char *steps_to_str(u16 step) ++{ ++ switch (step) { ++ CASE_BTC_RSN_STR(NONE); ++ CASE_BTC_RSN_STR(NTFY_INIT); ++ CASE_BTC_RSN_STR(NTFY_SWBAND); ++ CASE_BTC_RSN_STR(NTFY_WL_STA); ++ CASE_BTC_RSN_STR(NTFY_RADIO_STATE); ++ CASE_BTC_RSN_STR(UPDATE_BT_SCBD); ++ CASE_BTC_RSN_STR(NTFY_WL_RFK); ++ CASE_BTC_RSN_STR(UPDATE_BT_INFO); ++ CASE_BTC_RSN_STR(NTFY_SCAN_START); ++ CASE_BTC_RSN_STR(NTFY_SCAN_FINISH); ++ CASE_BTC_RSN_STR(NTFY_SPECIFIC_PACKET); ++ CASE_BTC_RSN_STR(NTFY_POWEROFF); ++ CASE_BTC_RSN_STR(NTFY_ROLE_INFO); ++ CASE_BTC_RSN_STR(CMD_SET_COEX); ++ CASE_BTC_RSN_STR(ACT1_WORK); ++ CASE_BTC_RSN_STR(BT_DEVINFO_WORK); ++ CASE_BTC_RSN_STR(RFK_CHK_WORK); ++ ++ CASE_BTC_ACT_STR(NONE); ++ CASE_BTC_ACT_STR(WL_ONLY); ++ CASE_BTC_ACT_STR(WL_5G); ++ CASE_BTC_ACT_STR(WL_OTHER); ++ CASE_BTC_ACT_STR(WL_IDLE); ++ CASE_BTC_ACT_STR(WL_NC); ++ CASE_BTC_ACT_STR(WL_RFK); ++ CASE_BTC_ACT_STR(WL_INIT); ++ CASE_BTC_ACT_STR(WL_OFF); ++ CASE_BTC_ACT_STR(FREERUN); ++ CASE_BTC_ACT_STR(BT_WHQL); ++ CASE_BTC_ACT_STR(BT_RFK); ++ CASE_BTC_ACT_STR(BT_OFF); ++ CASE_BTC_ACT_STR(BT_IDLE); ++ CASE_BTC_ACT_STR(BT_HFP); ++ CASE_BTC_ACT_STR(BT_HID); ++ CASE_BTC_ACT_STR(BT_A2DP); ++ CASE_BTC_ACT_STR(BT_A2DPSINK); ++ CASE_BTC_ACT_STR(BT_PAN); ++ CASE_BTC_ACT_STR(BT_A2DP_HID); ++ CASE_BTC_ACT_STR(BT_A2DP_PAN); ++ CASE_BTC_ACT_STR(BT_PAN_HID); ++ CASE_BTC_ACT_STR(BT_A2DP_PAN_HID); ++ CASE_BTC_ACT_STR(WL_25G_MCC); ++ CASE_BTC_ACT_STR(WL_2G_MCC); ++ CASE_BTC_ACT_STR(WL_2G_SCC); ++ CASE_BTC_ACT_STR(WL_2G_AP); ++ CASE_BTC_ACT_STR(WL_2G_GO); ++ CASE_BTC_ACT_STR(WL_2G_GC); ++ CASE_BTC_ACT_STR(WL_2G_NAN); ++ ++ CASE_BTC_POLICY_STR(OFF_BT); ++ CASE_BTC_POLICY_STR(OFF_WL); ++ CASE_BTC_POLICY_STR(OFF_EQ0); ++ CASE_BTC_POLICY_STR(OFF_EQ1); ++ CASE_BTC_POLICY_STR(OFF_EQ2); ++ CASE_BTC_POLICY_STR(OFF_EQ3); ++ CASE_BTC_POLICY_STR(OFF_BWB0); ++ CASE_BTC_POLICY_STR(OFF_BWB1); ++ CASE_BTC_POLICY_STR(OFFB_BWB0); ++ CASE_BTC_POLICY_STR(OFFE_DEF); ++ CASE_BTC_POLICY_STR(OFFE_DEF2); ++ CASE_BTC_POLICY_STR(FIX_TD3030); ++ CASE_BTC_POLICY_STR(FIX_TD5050); ++ CASE_BTC_POLICY_STR(FIX_TD2030); ++ CASE_BTC_POLICY_STR(FIX_TD4010); ++ CASE_BTC_POLICY_STR(FIX_TD7010); ++ CASE_BTC_POLICY_STR(FIX_TD2060); ++ CASE_BTC_POLICY_STR(FIX_TD3060); ++ CASE_BTC_POLICY_STR(FIX_TD2080); ++ CASE_BTC_POLICY_STR(FIX_TDW1B1); ++ CASE_BTC_POLICY_STR(FIX_TD4020); ++ CASE_BTC_POLICY_STR(PFIX_TD3030); ++ CASE_BTC_POLICY_STR(PFIX_TD5050); ++ CASE_BTC_POLICY_STR(PFIX_TD2030); ++ CASE_BTC_POLICY_STR(PFIX_TD2060); ++ CASE_BTC_POLICY_STR(PFIX_TD3070); ++ CASE_BTC_POLICY_STR(PFIX_TD2080); ++ CASE_BTC_POLICY_STR(PFIX_TDW1B1); ++ CASE_BTC_POLICY_STR(AUTO_TD50200); ++ CASE_BTC_POLICY_STR(AUTO_TD60200); ++ CASE_BTC_POLICY_STR(AUTO_TD20200); ++ CASE_BTC_POLICY_STR(AUTO_TDW1B1); ++ CASE_BTC_POLICY_STR(PAUTO_TD50200); ++ CASE_BTC_POLICY_STR(PAUTO_TD60200); ++ CASE_BTC_POLICY_STR(PAUTO_TD20200); ++ CASE_BTC_POLICY_STR(PAUTO_TDW1B1); ++ CASE_BTC_POLICY_STR(AUTO2_TD3050); ++ CASE_BTC_POLICY_STR(AUTO2_TD3070); ++ CASE_BTC_POLICY_STR(AUTO2_TD5050); ++ CASE_BTC_POLICY_STR(AUTO2_TD6060); ++ CASE_BTC_POLICY_STR(AUTO2_TD2080); ++ CASE_BTC_POLICY_STR(AUTO2_TDW1B4); ++ CASE_BTC_POLICY_STR(PAUTO2_TD3050); ++ CASE_BTC_POLICY_STR(PAUTO2_TD3070); ++ CASE_BTC_POLICY_STR(PAUTO2_TD5050); ++ CASE_BTC_POLICY_STR(PAUTO2_TD6060); ++ CASE_BTC_POLICY_STR(PAUTO2_TD2080); ++ CASE_BTC_POLICY_STR(PAUTO2_TDW1B4); ++ default: ++ return "unknown step"; ++ } ++} ++ ++static ++void seq_print_segment(struct seq_file *m, const char *prefix, u16 *data, ++ u8 len, u8 seg_len, u8 start_idx, u8 ring_len) ++{ ++ u8 i; ++ u8 cur_index; ++ ++ for (i = 0; i < len ; i++) { ++ if ((i % seg_len) == 0) ++ seq_printf(m, " %-15s : ", prefix); ++ cur_index = (start_idx + i) % ring_len; ++ if (i % 3 == 0) ++ seq_printf(m, "-> %-20s", ++ steps_to_str(*(data + cur_index))); ++ else if (i % 3 == 1) ++ seq_printf(m, "-> %-15s", ++ steps_to_str(*(data + cur_index))); ++ else ++ seq_printf(m, "-> %-13s", ++ steps_to_str(*(data + cur_index))); ++ if (i == (len - 1) || (i % seg_len) == (seg_len - 1)) ++ seq_puts(m, "\n"); ++ } ++} ++ ++static void _show_dm_step(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ u8 start_idx; ++ u8 len; ++ ++ len = dm->dm_step.step_ov ? RTW89_BTC_DM_MAXSTEP : dm->dm_step.step_pos; ++ start_idx = dm->dm_step.step_ov ? dm->dm_step.step_pos : 0; ++ ++ seq_print_segment(m, "[dm_steps]", dm->dm_step.step, len, 6, start_idx, ++ ARRAY_SIZE(dm->dm_step.step)); ++} ++ ++static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ ++ if (!(dm->coex_info_map & BTC_COEX_INFO_DM)) ++ return; ++ ++ seq_printf(m, "========== [Mechanism Status %s] ==========\n", ++ (btc->ctrl.manual ? "(Manual)" : "(Auto)")); ++ ++ seq_printf(m, ++ " %-15s : type:%s, reason:%s(), action:%s(), ant_path:%ld, run_cnt:%d\n", ++ "[status]", ++ module->ant.type == BTC_ANT_SHARED ? "shared" : "dedicated", ++ steps_to_str(dm->run_reason), ++ steps_to_str(dm->run_action | BTC_ACT_EXT_BIT), ++ FIELD_GET(GENMASK(7, 0), dm->set_ant_path), ++ dm->cnt_dm[BTC_DCNT_RUN]); ++ ++ _show_dm_step(rtwdev, m); ++ ++ seq_printf(m, " %-15s : wl_only:%d, bt_only:%d, igno_bt:%d, free_run:%d, wl_ps_ctrl:%d, wl_mimo_ps:%d, ", ++ "[dm_flag]", dm->wl_only, dm->bt_only, btc->ctrl.igno_bt, ++ dm->freerun, btc->lps, dm->wl_mimo_ps); ++ ++ seq_printf(m, "leak_ap:%d, fw_offload:%s%s\n", dm->leak_ap, ++ (BTC_CX_FW_OFFLOAD ? "Y" : "N"), ++ (dm->wl_fw_cx_offload == BTC_CX_FW_OFFLOAD ? ++ "" : "(Mis-Match!!)")); ++ ++ if (dm->rf_trx_para.wl_tx_power == 0xff) ++ seq_printf(m, ++ " %-15s : wl_rssi_lvl:%d, para_lvl:%d, wl_tx_pwr:orig, ", ++ "[trx_ctrl]", wl->rssi_level, dm->trx_para_level); ++ ++ else ++ seq_printf(m, ++ " %-15s : wl_rssi_lvl:%d, para_lvl:%d, wl_tx_pwr:%d, ", ++ "[trx_ctrl]", wl->rssi_level, dm->trx_para_level, ++ dm->rf_trx_para.wl_tx_power); ++ ++ seq_printf(m, ++ "wl_rx_lvl:%d, bt_tx_pwr_dec:%d, bt_rx_lna:%d(%s-tbl), wl_btg_rx:%d\n", ++ dm->rf_trx_para.wl_rx_gain, dm->rf_trx_para.bt_tx_power, ++ dm->rf_trx_para.bt_rx_gain, ++ (bt->hi_lna_rx ? "Hi" : "Ori"), dm->wl_btg_rx); ++ ++ seq_printf(m, ++ " %-15s : wl_tx_limit[en:%d/max_t:%dus/max_retry:%d], bt_slot_reg:%d-TU\n", ++ "[dm_ctrl]", dm->wl_tx_limit.enable, dm->wl_tx_limit.tx_time, ++ dm->wl_tx_limit.tx_retry, btc->bt_req_len); ++} ++ ++static void _show_error(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_fbtc_cysta *pcysta = NULL; ++ ++ pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; ++ ++ if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW] == 0 && ++ pcysta->except_cnt == 0 && ++ !pfwinfo->len_mismch && !pfwinfo->fver_mismch) ++ return; ++ ++ seq_printf(m, " %-15s : ", "[error]"); ++ ++ if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]) { ++ seq_printf(m, ++ "overflow-cnt: %d, ", ++ pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]); ++ } ++ ++ if (pfwinfo->len_mismch) { ++ seq_printf(m, ++ "len-mismatch: 0x%x, ", ++ pfwinfo->len_mismch); ++ } ++ ++ if (pfwinfo->fver_mismch) { ++ seq_printf(m, ++ "fver-mismatch: 0x%x, ", ++ pfwinfo->fver_mismch); ++ } ++ ++ /* cycle statistics exceptions */ ++ if (pcysta->exception || pcysta->except_cnt) { ++ seq_printf(m, ++ "exception-type: 0x%x, exception-cnt = %d", ++ pcysta->exception, pcysta->except_cnt); ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_fbtc_tdma(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_tdma *t = NULL; ++ struct rtw89_btc_fbtc_slot *s = NULL; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ u8 i, cnt = 0; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ t = &pfwinfo->rpt_fbtc_tdma.finfo; ++ ++ seq_printf(m, ++ " %-15s : ", "[tdma_policy]"); ++ seq_printf(m, ++ "type:%d, rx_flow_ctrl:%d, tx_pause:%d, ", ++ (u32)t->type, ++ t->rxflctrl, t->txpause); ++ ++ seq_printf(m, ++ "wl_toggle_n:%d, leak_n:%d, ext_ctrl:%d, ", ++ t->wtgle_n, t->leak_n, t->ext_ctrl); ++ ++ seq_printf(m, ++ "policy_type:%d", ++ (u32)btc->policy_type); ++ ++ s = pfwinfo->rpt_fbtc_slots.finfo.slot; ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ if (dm->update_slot_map == BIT(CXST_MAX) - 1) ++ break; ++ ++ if (!(dm->update_slot_map & BIT(i))) ++ continue; ++ ++ if (cnt % 6 == 0) ++ seq_printf(m, ++ " %-15s : %d[%d/0x%x/%d]", ++ "[slot_policy]", ++ (u32)i, ++ s[i].dur, s[i].cxtbl, s[i].cxtype); ++ else ++ seq_printf(m, ++ ", %d[%d/0x%x/%d]", ++ (u32)i, ++ s[i].dur, s[i].cxtbl, s[i].cxtype); ++ if (cnt % 6 == 5) ++ seq_puts(m, "\n"); ++ cnt++; ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_fbtc_slots(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_slots *pslots = NULL; ++ struct rtw89_btc_fbtc_slot s; ++ u8 i = 0; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ pslots = &pfwinfo->rpt_fbtc_slots.finfo; ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ s = pslots->slot[i]; ++ if (i % 6 == 0) ++ seq_printf(m, ++ " %-15s : %02d[%03d/0x%x/%d]", ++ "[slot_list]", ++ (u32)i, ++ s.dur, s.cxtbl, s.cxtype); ++ else ++ seq_printf(m, ++ ", %02d[%03d/0x%x/%d]", ++ (u32)i, ++ s.dur, s.cxtbl, s.cxtype); ++ if (i % 6 == 5) ++ seq_puts(m, "\n"); ++ } ++} ++ ++static void _show_fbtc_cysta(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_cysta *pcysta_le32 = NULL; ++ struct rtw89_btc_fbtc_cysta_cpu pcysta[1]; ++ union rtw89_btc_fbtc_rxflct r; ++ u8 i, cnt = 0, slot_pair; ++ u16 cycle, c_begin, c_end, store_index; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo; ++ rtw89_btc_fbtc_cysta_to_cpu(pcysta_le32, pcysta); ++ seq_printf(m, ++ " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", ++ "[cycle_cnt]", pcysta->cycles, pcysta->bcn_cnt[CXBCN_ALL], ++ pcysta->bcn_cnt[CXBCN_ALL_OK], ++ pcysta->bcn_cnt[CXBCN_BT_SLOT], ++ pcysta->bcn_cnt[CXBCN_BT_OK]); ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles); ++ ++ for (i = 0; i < CXST_MAX; i++) { ++ if (!pcysta->slot_cnt[i]) ++ continue; ++ seq_printf(m, ++ ", %d:%d", (u32)i, pcysta->slot_cnt[i]); ++ } ++ ++ if (dm->tdma_now.rxflctrl) { ++ seq_printf(m, ++ ", leak_rx:%d", pcysta->leakrx_cnt); ++ } ++ ++ if (pcysta->collision_cnt) { ++ seq_printf(m, ++ ", collision:%d", pcysta->collision_cnt); ++ } ++ ++ if (pcysta->skip_cnt) { ++ seq_printf(m, ++ ", skip:%d", pcysta->skip_cnt); ++ } ++ seq_puts(m, "\n"); ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]); ++ _chk_btc_err(rtwdev, BTC_DCNT_B1_FREEZE, pcysta->slot_cnt[CXST_B1]); ++ ++ seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", ++ "[cycle_time]", ++ pcysta->tavg_cycle[CXT_WL], ++ pcysta->tavg_cycle[CXT_BT], ++ pcysta->tavg_lk / 1000, pcysta->tavg_lk % 1000); ++ seq_printf(m, ++ ", max_t[wl:%d/bt:%d/lk:%d.%03d]", ++ pcysta->tmax_cycle[CXT_WL], ++ pcysta->tmax_cycle[CXT_BT], ++ pcysta->tmax_lk / 1000, pcysta->tmax_lk % 1000); ++ seq_printf(m, ++ ", maxdiff_t[wl:%d/bt:%d]\n", ++ pcysta->tmaxdiff_cycle[CXT_WL], ++ pcysta->tmaxdiff_cycle[CXT_BT]); ++ ++ if (pcysta->cycles == 0) ++ return; ++ ++ /* 1 cycle record 1 wl-slot and 1 bt-slot */ ++ slot_pair = BTC_CYCLE_SLOT_MAX / 2; ++ ++ if (pcysta->cycles <= slot_pair) ++ c_begin = 1; ++ else ++ c_begin = pcysta->cycles - slot_pair + 1; ++ ++ c_end = pcysta->cycles; ++ ++ for (cycle = c_begin; cycle <= c_end; cycle++) { ++ cnt++; ++ store_index = ((cycle - 1) % slot_pair) * 2; ++ ++ if (cnt % (BTC_CYCLE_SLOT_MAX / 4) == 1) ++ seq_printf(m, ++ " %-15s : ->b%02d->w%02d", "[cycle_step]", ++ pcysta->tslot_cycle[store_index], ++ pcysta->tslot_cycle[store_index + 1]); ++ else ++ seq_printf(m, ++ "->b%02d->w%02d", ++ pcysta->tslot_cycle[store_index], ++ pcysta->tslot_cycle[store_index + 1]); ++ if (cnt % (BTC_CYCLE_SLOT_MAX / 4) == 0 || cnt == c_end) ++ seq_puts(m, "\n"); ++ } ++ ++ if (a2dp->exist) { ++ seq_printf(m, ++ " %-15s : a2dp_ept:%d, a2dp_late:%d", ++ "[a2dp_t_sta]", ++ pcysta->a2dpept, pcysta->a2dpeptto); ++ ++ seq_printf(m, ++ ", avg_t:%d, max_t:%d", ++ pcysta->tavg_a2dpept, pcysta->tmax_a2dpept); ++ r.val = dm->tdma_now.rxflctrl; ++ ++ if (r.type && r.tgln_n) { ++ seq_printf(m, ++ ", cycle[PSTDMA:%d/TDMA:%d], ", ++ pcysta->cycles_a2dp[CXT_FLCTRL_ON], ++ pcysta->cycles_a2dp[CXT_FLCTRL_OFF]); ++ ++ seq_printf(m, ++ "avg_t[PSTDMA:%d/TDMA:%d], ", ++ pcysta->tavg_a2dp[CXT_FLCTRL_ON], ++ pcysta->tavg_a2dp[CXT_FLCTRL_OFF]); ++ ++ seq_printf(m, ++ "max_t[PSTDMA:%d/TDMA:%d]", ++ pcysta->tmax_a2dp[CXT_FLCTRL_ON], ++ pcysta->tmax_a2dp[CXT_FLCTRL_OFF]); ++ } ++ seq_puts(m, "\n"); ++ } ++} ++ ++static void _show_fbtc_nullsta(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_cynullsta *ns = NULL; ++ u8 i = 0; ++ ++ if (!btc->dm.tdma_now.rxflctrl) ++ return; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ ns = &pfwinfo->rpt_fbtc_nullsta.finfo; ++ ++ seq_printf(m, " %-15s : ", "[null_sta]"); ++ ++ for (i = 0; i < 2; i++) { ++ if (i != 0) ++ seq_printf(m, ", null-%d", i); ++ else ++ seq_printf(m, "null-%d", i); ++ seq_printf(m, "[ok:%d/", le32_to_cpu(ns->result[i][1])); ++ seq_printf(m, "fail:%d/", le32_to_cpu(ns->result[i][0])); ++ seq_printf(m, "on_time:%d/", le32_to_cpu(ns->result[i][2])); ++ seq_printf(m, "retry:%d/", le32_to_cpu(ns->result[i][3])); ++ seq_printf(m, "avg_t:%d.%03d/", ++ le32_to_cpu(ns->avg_t[i]) / 1000, ++ le32_to_cpu(ns->avg_t[i]) % 1000); ++ seq_printf(m, "max_t:%d.%03d]", ++ le32_to_cpu(ns->max_t[i]) / 1000, ++ le32_to_cpu(ns->max_t[i]) % 1000); ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_fbtc_step(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_steps *pstep = NULL; ++ u8 type, val, cnt = 0, state = 0; ++ bool outloop = false; ++ u16 i, diff_t, n_start = 0, n_stop = 0; ++ u16 pos_old, pos_new; ++ ++ pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; ++ if (!pcinfo->valid) ++ return; ++ ++ pstep = &pfwinfo->rpt_fbtc_step.finfo; ++ pos_old = le16_to_cpu(pstep->pos_old); ++ pos_new = le16_to_cpu(pstep->pos_new); ++ ++ if (pcinfo->req_fver != pstep->fver) ++ return; ++ ++ /* store step info by using ring instead of FIFO*/ ++ do { ++ switch (state) { ++ case 0: ++ n_start = pos_old; ++ if (pos_new >= pos_old) ++ n_stop = pos_new; ++ else ++ n_stop = btc->ctrl.trace_step - 1; ++ ++ state = 1; ++ break; ++ case 1: ++ for (i = n_start; i <= n_stop; i++) { ++ type = pstep->step[i].type; ++ val = pstep->step[i].val; ++ diff_t = le16_to_cpu(pstep->step[i].difft); ++ ++ if (type == CXSTEP_NONE || type >= CXSTEP_MAX) ++ continue; ++ ++ if (cnt % 10 == 0) ++ seq_printf(m, " %-15s : ", "[steps]"); ++ ++ seq_printf(m, "-> %s(%02d)(%02d)", ++ (type == CXSTEP_SLOT ? "SLT" : ++ "EVT"), (u32)val, diff_t); ++ if (cnt % 10 == 9) ++ seq_puts(m, "\n"); ++ cnt++; ++ } ++ ++ state = 2; ++ break; ++ case 2: ++ if (pos_new < pos_old && n_start != 0) { ++ n_start = 0; ++ n_stop = pos_new; ++ state = 1; ++ } else { ++ outloop = true; ++ } ++ break; ++ } ++ } while (!outloop); ++} ++ ++static void _show_fw_dm_msg(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_DM)) ++ return; ++ ++ _show_error(rtwdev, m); ++ _show_fbtc_tdma(rtwdev, m); ++ _show_fbtc_slots(rtwdev, m); ++ _show_fbtc_cysta(rtwdev, m); ++ _show_fbtc_nullsta(rtwdev, m); ++ _show_fbtc_step(rtwdev, m); ++} ++ ++static void _show_mreg(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_mreg_val *pmreg = NULL; ++ struct rtw89_btc_fbtc_gpio_dbg *gdbg = NULL; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_mac_ax_gnt gnt[2] = {0}; ++ u8 i = 0, type = 0, cnt = 0; ++ u32 val, offset; ++ ++ if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG)) ++ return; ++ ++ seq_puts(m, "========== [HW Status] ==========\n"); ++ ++ seq_printf(m, ++ " %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)\n", ++ "[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE], ++ bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], ++ cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); ++ ++ /* To avoid I/O if WL LPS or power-off */ ++ if (!wl->status.map.lps && !wl->status.map.rf_off) { ++ rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); ++ if (val & (B_AX_GNT_BT_RFC_S0_SW_VAL | ++ B_AX_GNT_BT_BB_S0_SW_VAL)) ++ gnt[0].gnt_bt = true; ++ if (val & (B_AX_GNT_BT_RFC_S0_SW_CTRL | ++ B_AX_GNT_BT_BB_S0_SW_CTRL)) ++ gnt[0].gnt_bt_sw_en = true; ++ if (val & (B_AX_GNT_WL_RFC_S0_SW_VAL | ++ B_AX_GNT_WL_BB_S0_SW_VAL)) ++ gnt[0].gnt_wl = true; ++ if (val & (B_AX_GNT_WL_RFC_S0_SW_CTRL | ++ B_AX_GNT_WL_BB_S0_SW_CTRL)) ++ gnt[0].gnt_wl_sw_en = true; ++ ++ if (val & (B_AX_GNT_BT_RFC_S1_SW_VAL | ++ B_AX_GNT_BT_BB_S1_SW_VAL)) ++ gnt[1].gnt_bt = true; ++ if (val & (B_AX_GNT_BT_RFC_S1_SW_CTRL | ++ B_AX_GNT_BT_BB_S1_SW_CTRL)) ++ gnt[1].gnt_bt_sw_en = true; ++ if (val & (B_AX_GNT_WL_RFC_S1_SW_VAL | ++ B_AX_GNT_WL_BB_S1_SW_VAL)) ++ gnt[1].gnt_wl = true; ++ if (val & (B_AX_GNT_WL_RFC_S1_SW_CTRL | ++ B_AX_GNT_WL_BB_S1_SW_CTRL)) ++ gnt[1].gnt_wl_sw_en = true; ++ ++ seq_printf(m, ++ " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", ++ "[gnt_status]", ++ (rtw89_mac_get_ctrl_path(rtwdev) ? "WL" : "BT"), ++ (gnt[0].gnt_wl_sw_en ? "SW" : "HW"), gnt[0].gnt_wl, ++ (gnt[0].gnt_bt_sw_en ? "SW" : "HW"), gnt[0].gnt_bt); ++ ++ seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", ++ (gnt[1].gnt_wl_sw_en ? "SW" : "HW"), gnt[1].gnt_wl, ++ (gnt[1].gnt_bt_sw_en ? "SW" : "HW"), gnt[1].gnt_bt); ++ } ++ ++ pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; ++ if (!pcinfo->valid) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): stop due rpt_fbtc_mregval.cinfo\n", ++ __func__); ++ return; ++ } ++ ++ pmreg = &pfwinfo->rpt_fbtc_mregval.finfo; ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): rpt_fbtc_mregval reg_num = %d\n", ++ __func__, pmreg->reg_num); ++ ++ for (i = 0; i < pmreg->reg_num; i++) { ++ type = (u8)le16_to_cpu(chip->mon_reg[i].type); ++ offset = le32_to_cpu(chip->mon_reg[i].offset); ++ val = le32_to_cpu(pmreg->mreg_val[i]); ++ ++ if (cnt % 6 == 0) ++ seq_printf(m, " %-15s : %d_0x%04x=0x%08x", ++ "[reg]", (u32)type, offset, val); ++ else ++ seq_printf(m, ", %d_0x%04x=0x%08x", (u32)type, ++ offset, val); ++ if (cnt % 6 == 5) ++ seq_puts(m, "\n"); ++ cnt++; ++ } ++ ++ pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; ++ if (!pcinfo->valid) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): stop due rpt_fbtc_gpio_dbg.cinfo\n", ++ __func__); ++ return; ++ } ++ ++ gdbg = &pfwinfo->rpt_fbtc_gpio_dbg.finfo; ++ if (!gdbg->en_map) ++ return; ++ ++ seq_printf(m, " %-15s : enable_map:0x%08x", ++ "[gpio_dbg]", gdbg->en_map); ++ ++ for (i = 0; i < BTC_DBG_MAX1; i++) { ++ if (!(gdbg->en_map & BIT(i))) ++ continue; ++ seq_printf(m, ", %d->GPIO%d", (u32)i, gdbg->gpio_map[i]); ++ } ++ seq_puts(m, "\n"); ++} ++ ++static void _show_summary(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; ++ struct rtw89_btc_fbtc_rpt_ctrl *prptctrl = NULL; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; ++ u8 i; ++ ++ if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) ++ return; ++ ++ seq_puts(m, "========== [Statistics] ==========\n"); ++ ++ pcinfo = &pfwinfo->rpt_ctrl.cinfo; ++ if (pcinfo->valid && !wl->status.map.lps && !wl->status.map.rf_off) { ++ prptctrl = &pfwinfo->rpt_ctrl.finfo; ++ ++ seq_printf(m, ++ " %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d), ", ++ "[summary]", pfwinfo->cnt_h2c, ++ pfwinfo->cnt_h2c_fail, prptctrl->h2c_cnt, ++ pfwinfo->cnt_c2h, prptctrl->c2h_cnt); ++ ++ seq_printf(m, ++ "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x, dm_error_map:0x%x", ++ pfwinfo->event[BTF_EVNT_RPT], prptctrl->rpt_cnt, ++ prptctrl->rpt_enable, dm->error.val); ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_RPT_FREEZE, ++ pfwinfo->event[BTF_EVNT_RPT]); ++ ++ if (dm->error.map.wl_fw_hang) ++ seq_puts(m, " (WL FW Hang!!)"); ++ seq_puts(m, "\n"); ++ seq_printf(m, ++ " %-15s : send_ok:%d, send_fail:%d, recv:%d", ++ "[mailbox]", prptctrl->mb_send_ok_cnt, ++ prptctrl->mb_send_fail_cnt, prptctrl->mb_recv_cnt); ++ ++ seq_printf(m, ++ "(A2DP_empty:%d, A2DP_flowstop:%d, A2DP_full:%d)\n", ++ prptctrl->mb_a2dp_empty_cnt, ++ prptctrl->mb_a2dp_flct_cnt, ++ prptctrl->mb_a2dp_full_cnt); ++ ++ seq_printf(m, ++ " %-15s : wl_rfk[req:%d/go:%d/reject:%d/timeout:%d]", ++ "[RFK]", cx->cnt_wl[BTC_WCNT_RFK_REQ], ++ cx->cnt_wl[BTC_WCNT_RFK_GO], ++ cx->cnt_wl[BTC_WCNT_RFK_REJECT], ++ cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); ++ ++ seq_printf(m, ++ ", bt_rfk[req:%d/go:%d/reject:%d/timeout:%d/fail:%d]\n", ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REQ], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_GO], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REJECT], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT], ++ prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_FAIL]); ++ ++ if (prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT] > 0) ++ bt->rfk_info.map.timeout = 1; ++ else ++ bt->rfk_info.map.timeout = 0; ++ ++ dm->error.map.wl_rfk_timeout = bt->rfk_info.map.timeout; ++ } else { ++ seq_printf(m, ++ " %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d, rpt_cnt=%d, rpt_map=0x%x", ++ "[summary]", pfwinfo->cnt_h2c, ++ pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h, ++ pfwinfo->event[BTF_EVNT_RPT], ++ btc->fwinfo.rpt_en_map); ++ seq_puts(m, " (WL FW report invalid!!)\n"); ++ } ++ ++ for (i = 0; i < BTC_NCNT_NUM; i++) ++ cnt_sum += dm->cnt_notify[i]; ++ ++ seq_printf(m, ++ " %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", ++ "[notify_cnt]", cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], ++ cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); ++ ++ seq_printf(m, ++ "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d\n", ++ cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], ++ cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], ++ cnt[BTC_NCNT_WL_STA]); ++ ++ seq_printf(m, ++ " %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", ++ "[notify_cnt]", cnt[BTC_NCNT_SCAN_START], ++ cnt[BTC_NCNT_SCAN_FINISH], cnt[BTC_NCNT_SWITCH_BAND], ++ cnt[BTC_NCNT_SPECIAL_PACKET]); ++ ++ seq_printf(m, ++ "timer=%d, control=%d, customerize=%d\n", ++ cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], ++ cnt[BTC_NCNT_CUSTOMERIZE]); ++} ++ ++void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m) ++{ ++ struct rtw89_fw_suit *fw_suit = &rtwdev->fw.normal; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_bt_info *bt = &cx->bt; ++ ++ seq_puts(m, "=========================================\n"); ++ seq_printf(m, "WL FW / BT FW %d.%d.%d.%d / NA\n", ++ fw_suit->major_ver, fw_suit->minor_ver, ++ fw_suit->sub_ver, fw_suit->sub_idex); ++ seq_printf(m, "manual %d\n", btc->ctrl.manual); ++ ++ seq_puts(m, "=========================================\n"); ++ ++ seq_printf(m, "\n\r %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)", ++ "[bt_info]", ++ bt->raw_info[2], bt->raw_info[3], ++ bt->raw_info[4], bt->raw_info[5], ++ bt->raw_info[6], bt->raw_info[7], ++ bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply", ++ cx->cnt_bt[BTC_BCNT_INFOUPDATE], ++ cx->cnt_bt[BTC_BCNT_INFOSAME]); ++ ++ seq_puts(m, "\n=========================================\n"); ++ ++ _show_cx_info(rtwdev, m); ++ _show_wl_info(rtwdev, m); ++ _show_bt_info(rtwdev, m); ++ _show_dm_info(rtwdev, m); ++ _show_fw_dm_msg(rtwdev, m); ++ _show_mreg(rtwdev, m); ++ _show_summary(rtwdev, m); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/coex.h b/drivers/net/wireless/realtek/rtw89/coex.h +new file mode 100644 +index 000000000000..4b4565d15c9e +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/coex.h +@@ -0,0 +1,181 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_COEX_H__ ++#define __RTW89_COEX_H__ ++ ++#include "core.h" ++ ++enum btc_mode { ++ BTC_MODE_NORMAL, ++ BTC_MODE_WL, ++ BTC_MODE_BT, ++ BTC_MODE_WLOFF, ++ BTC_MODE_MAX ++}; ++ ++enum btc_wl_rfk_type { ++ BTC_WRFKT_IQK = 0, ++ BTC_WRFKT_LCK = 1, ++ BTC_WRFKT_DPK = 2, ++ BTC_WRFKT_TXGAPK = 3, ++ BTC_WRFKT_DACK = 4, ++ BTC_WRFKT_RXDCK = 5, ++ BTC_WRFKT_TSSI = 6, ++}; ++ ++#define NM_EXEC false ++#define FC_EXEC true ++ ++#define RTW89_COEX_ACT1_WORK_PERIOD round_jiffies_relative(HZ * 4) ++#define RTW89_COEX_BT_DEVINFO_WORK_PERIOD round_jiffies_relative(HZ * 16) ++#define RTW89_COEX_RFK_CHK_WORK_PERIOD msecs_to_jiffies(300) ++#define BTC_RFK_PATH_MAP GENMASK(3, 0) ++#define BTC_RFK_PHY_MAP GENMASK(5, 4) ++#define BTC_RFK_BAND_MAP GENMASK(7, 6) ++ ++enum btc_wl_rfk_state { ++ BTC_WRFK_STOP = 0, ++ BTC_WRFK_START = 1, ++ BTC_WRFK_ONESHOT_START = 2, ++ BTC_WRFK_ONESHOT_STOP = 3, ++}; ++ ++enum btc_pri { ++ BTC_PRI_MASK_RX_RESP = 0, ++ BTC_PRI_MASK_TX_RESP, ++ BTC_PRI_MASK_BEACON, ++ BTC_PRI_MASK_RX_CCK, ++ BTC_PRI_MASK_TX_MNGQ, ++ BTC_PRI_MASK_MAX, ++}; ++ ++enum btc_bt_trs { ++ BTC_BT_SS_GROUP = 0x0, ++ BTC_BT_TX_GROUP = 0x2, ++ BTC_BT_RX_GROUP = 0x3, ++ BTC_BT_MAX_GROUP, ++}; ++ ++enum btc_rssi_st { ++ BTC_RSSI_ST_LOW = 0x0, ++ BTC_RSSI_ST_HIGH, ++ BTC_RSSI_ST_STAY_LOW, ++ BTC_RSSI_ST_STAY_HIGH, ++ BTC_RSSI_ST_MAX ++}; ++ ++#define BTC_RSSI_HIGH(_rssi_) \ ++ ({typeof(_rssi_) __rssi = (_rssi_); \ ++ ((__rssi == BTC_RSSI_ST_HIGH || \ ++ __rssi == BTC_RSSI_ST_STAY_HIGH) ? 1 : 0); }) ++ ++#define BTC_RSSI_LOW(_rssi_) \ ++ ({typeof(_rssi_) __rssi = (_rssi_); \ ++ ((__rssi == BTC_RSSI_ST_LOW || \ ++ __rssi == BTC_RSSI_ST_STAY_LOW) ? 1 : 0); }) ++ ++#define BTC_RSSI_CHANGE(_rssi_) \ ++ ({typeof(_rssi_) __rssi = (_rssi_); \ ++ ((__rssi == BTC_RSSI_ST_LOW || \ ++ __rssi == BTC_RSSI_ST_HIGH) ? 1 : 0); }) ++ ++enum btc_ant { ++ BTC_ANT_SHARED = 0, ++ BTC_ANT_DEDICATED, ++ BTC_ANTTYPE_MAX ++}; ++ ++enum btc_bt_btg { ++ BTC_BT_ALONE = 0, ++ BTC_BT_BTG ++}; ++ ++enum btc_switch { ++ BTC_SWITCH_INTERNAL = 0, ++ BTC_SWITCH_EXTERNAL ++}; ++ ++enum btc_pkt_type { ++ PACKET_DHCP, ++ PACKET_ARP, ++ PACKET_EAPOL, ++ PACKET_EAPOL_END, ++ PACKET_ICMP, ++ PACKET_MAX ++}; ++ ++enum btc_bt_mailbox_id { ++ BTC_BTINFO_REPLY = 0x23, ++ BTC_BTINFO_AUTO = 0x27 ++}; ++ ++enum btc_role_state { ++ BTC_ROLE_START, ++ BTC_ROLE_STOP, ++ BTC_ROLE_CHG_TYPE, ++ BTC_ROLE_MSTS_STA_CONN_START, ++ BTC_ROLE_MSTS_STA_CONN_END, ++ BTC_ROLE_MSTS_STA_DIS_CONN, ++ BTC_ROLE_MSTS_AP_START, ++ BTC_ROLE_MSTS_AP_STOP, ++ BTC_ROLE_STATE_UNKNOWN ++}; ++ ++enum btc_rfctrl { ++ BTC_RFCTRL_WL_OFF, ++ BTC_RFCTRL_WL_ON, ++ BTC_RFCTRL_FW_CTRL, ++ BTC_RFCTRL_MAX ++}; ++ ++void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev); ++void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev); ++void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode); ++void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band); ++void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx); ++void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band); ++void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev, ++ enum btc_pkt_type pkt_type); ++void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_icmp_packet_work(struct work_struct *work); ++void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ struct rtw89_sta *rtwsta, enum btc_role_state state); ++void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state); ++void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map, ++ enum btc_wl_rfk_type type, ++ enum btc_wl_rfk_state state); ++void rtw89_btc_ntfy_wl_sta(struct rtw89_dev *rtwdev); ++void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func); ++void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m); ++void rtw89_coex_act1_work(struct work_struct *work); ++void rtw89_coex_bt_devinfo_work(struct work_struct *work); ++void rtw89_coex_rfk_chk_work(struct work_struct *work); ++void rtw89_coex_power_on(struct rtw89_dev *rtwdev); ++ ++static inline u8 rtw89_btc_phymap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ enum rtw89_rf_path_bit paths) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u8 phy_map; ++ ++ phy_map = FIELD_PREP(BTC_RFK_PATH_MAP, paths) | ++ FIELD_PREP(BTC_RFK_PHY_MAP, BIT(phy_idx)) | ++ FIELD_PREP(BTC_RFK_BAND_MAP, hal->current_band_type); ++ ++ return phy_map; ++} ++ ++static inline u8 rtw89_btc_path_phymap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ enum rtw89_rf_path path) ++{ ++ return rtw89_btc_phymap(rtwdev, phy_idx, BIT(path)); ++} ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +new file mode 100644 +index 000000000000..06fb6e5b1b37 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -0,0 +1,2502 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "core.h" ++#include "efuse.h" ++#include "fw.h" ++#include "mac.h" ++#include "phy.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++#include "ser.h" ++#include "txrx.h" ++#include "util.h" ++ ++static bool rtw89_disable_ps_mode; ++module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); ++MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); ++ ++static struct ieee80211_channel rtw89_channels_2ghz[] = { ++ { .center_freq = 2412, .hw_value = 1, }, ++ { .center_freq = 2417, .hw_value = 2, }, ++ { .center_freq = 2422, .hw_value = 3, }, ++ { .center_freq = 2427, .hw_value = 4, }, ++ { .center_freq = 2432, .hw_value = 5, }, ++ { .center_freq = 2437, .hw_value = 6, }, ++ { .center_freq = 2442, .hw_value = 7, }, ++ { .center_freq = 2447, .hw_value = 8, }, ++ { .center_freq = 2452, .hw_value = 9, }, ++ { .center_freq = 2457, .hw_value = 10, }, ++ { .center_freq = 2462, .hw_value = 11, }, ++ { .center_freq = 2467, .hw_value = 12, }, ++ { .center_freq = 2472, .hw_value = 13, }, ++ { .center_freq = 2484, .hw_value = 14, }, ++}; ++ ++static struct ieee80211_channel rtw89_channels_5ghz[] = { ++ {.center_freq = 5180, .hw_value = 36,}, ++ {.center_freq = 5200, .hw_value = 40,}, ++ {.center_freq = 5220, .hw_value = 44,}, ++ {.center_freq = 5240, .hw_value = 48,}, ++ {.center_freq = 5260, .hw_value = 52,}, ++ {.center_freq = 5280, .hw_value = 56,}, ++ {.center_freq = 5300, .hw_value = 60,}, ++ {.center_freq = 5320, .hw_value = 64,}, ++ {.center_freq = 5500, .hw_value = 100,}, ++ {.center_freq = 5520, .hw_value = 104,}, ++ {.center_freq = 5540, .hw_value = 108,}, ++ {.center_freq = 5560, .hw_value = 112,}, ++ {.center_freq = 5580, .hw_value = 116,}, ++ {.center_freq = 5600, .hw_value = 120,}, ++ {.center_freq = 5620, .hw_value = 124,}, ++ {.center_freq = 5640, .hw_value = 128,}, ++ {.center_freq = 5660, .hw_value = 132,}, ++ {.center_freq = 5680, .hw_value = 136,}, ++ {.center_freq = 5700, .hw_value = 140,}, ++ {.center_freq = 5720, .hw_value = 144,}, ++ {.center_freq = 5745, .hw_value = 149,}, ++ {.center_freq = 5765, .hw_value = 153,}, ++ {.center_freq = 5785, .hw_value = 157,}, ++ {.center_freq = 5805, .hw_value = 161,}, ++ {.center_freq = 5825, .hw_value = 165, ++ .flags = IEEE80211_CHAN_NO_HT40MINUS}, ++}; ++ ++static struct ieee80211_rate rtw89_bitrates[] = { ++ { .bitrate = 10, .hw_value = 0x00, }, ++ { .bitrate = 20, .hw_value = 0x01, }, ++ { .bitrate = 55, .hw_value = 0x02, }, ++ { .bitrate = 110, .hw_value = 0x03, }, ++ { .bitrate = 60, .hw_value = 0x04, }, ++ { .bitrate = 90, .hw_value = 0x05, }, ++ { .bitrate = 120, .hw_value = 0x06, }, ++ { .bitrate = 180, .hw_value = 0x07, }, ++ { .bitrate = 240, .hw_value = 0x08, }, ++ { .bitrate = 360, .hw_value = 0x09, }, ++ { .bitrate = 480, .hw_value = 0x0a, }, ++ { .bitrate = 540, .hw_value = 0x0b, }, ++}; ++ ++u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate) ++{ ++ struct ieee80211_rate rate; ++ ++ if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { ++ rtw89_info(rtwdev, "invalid rpt rate %d\n", rpt_rate); ++ return 0; ++ } ++ ++ rate = rtw89_bitrates[rpt_rate]; ++ ++ return rate.bitrate; ++} ++ ++static struct ieee80211_supported_band rtw89_sband_2ghz = { ++ .band = NL80211_BAND_2GHZ, ++ .channels = rtw89_channels_2ghz, ++ .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), ++ .bitrates = rtw89_bitrates, ++ .n_bitrates = ARRAY_SIZE(rtw89_bitrates), ++ .ht_cap = {0}, ++ .vht_cap = {0}, ++}; ++ ++static struct ieee80211_supported_band rtw89_sband_5ghz = { ++ .band = NL80211_BAND_5GHZ, ++ .channels = rtw89_channels_5ghz, ++ .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), ++ ++ /* 5G has no CCK rates, 1M/2M/5.5M/11M */ ++ .bitrates = rtw89_bitrates + 4, ++ .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, ++ .ht_cap = {0}, ++ .vht_cap = {0}, ++}; ++ ++static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats, ++ struct sk_buff *skb, bool tx) ++{ ++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; ++ ++ if (!ieee80211_is_data(hdr->frame_control)) ++ return; ++ ++ if (is_broadcast_ether_addr(hdr->addr1) || ++ is_multicast_ether_addr(hdr->addr1)) ++ return; ++ ++ if (tx) { ++ stats->tx_cnt++; ++ stats->tx_unicast += skb->len; ++ } else { ++ stats->rx_cnt++; ++ stats->rx_unicast += skb->len; ++ } ++} ++ ++static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, ++ struct rtw89_channel_params *chan_param) ++{ ++ struct ieee80211_channel *channel = chandef->chan; ++ enum nl80211_chan_width width = chandef->width; ++ u8 *cch_by_bw = chan_param->cch_by_bw; ++ u32 primary_freq, center_freq; ++ u8 center_chan; ++ u8 bandwidth = RTW89_CHANNEL_WIDTH_20; ++ u8 primary_chan_idx = 0; ++ u8 i; ++ ++ center_chan = channel->hw_value; ++ primary_freq = channel->center_freq; ++ center_freq = chandef->center_freq1; ++ ++ /* assign the center channel used while 20M bw is selected */ ++ cch_by_bw[RTW89_CHANNEL_WIDTH_20] = channel->hw_value; ++ ++ switch (width) { ++ case NL80211_CHAN_WIDTH_20_NOHT: ++ case NL80211_CHAN_WIDTH_20: ++ bandwidth = RTW89_CHANNEL_WIDTH_20; ++ primary_chan_idx = RTW89_SC_DONT_CARE; ++ break; ++ case NL80211_CHAN_WIDTH_40: ++ bandwidth = RTW89_CHANNEL_WIDTH_40; ++ if (primary_freq > center_freq) { ++ primary_chan_idx = RTW89_SC_20_UPPER; ++ center_chan -= 2; ++ } else { ++ primary_chan_idx = RTW89_SC_20_LOWER; ++ center_chan += 2; ++ } ++ break; ++ case NL80211_CHAN_WIDTH_80: ++ bandwidth = RTW89_CHANNEL_WIDTH_80; ++ if (primary_freq > center_freq) { ++ if (primary_freq - center_freq == 10) { ++ primary_chan_idx = RTW89_SC_20_UPPER; ++ center_chan -= 2; ++ } else { ++ primary_chan_idx = RTW89_SC_20_UPMOST; ++ center_chan -= 6; ++ } ++ /* assign the center channel used ++ * while 40M bw is selected ++ */ ++ cch_by_bw[RTW89_CHANNEL_WIDTH_40] = center_chan + 4; ++ } else { ++ if (center_freq - primary_freq == 10) { ++ primary_chan_idx = RTW89_SC_20_LOWER; ++ center_chan += 2; ++ } else { ++ primary_chan_idx = RTW89_SC_20_LOWEST; ++ center_chan += 6; ++ } ++ /* assign the center channel used ++ * while 40M bw is selected ++ */ ++ cch_by_bw[RTW89_CHANNEL_WIDTH_40] = center_chan - 4; ++ } ++ break; ++ default: ++ center_chan = 0; ++ break; ++ } ++ ++ chan_param->center_chan = center_chan; ++ chan_param->primary_chan = channel->hw_value; ++ chan_param->bandwidth = bandwidth; ++ chan_param->pri_ch_idx = primary_chan_idx; ++ ++ /* assign the center channel used while current bw is selected */ ++ cch_by_bw[bandwidth] = center_chan; ++ ++ for (i = bandwidth + 1; i <= RTW89_MAX_CHANNEL_WIDTH; i++) ++ cch_by_bw[i] = 0; ++} ++ ++void rtw89_set_channel(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct rtw89_channel_params ch_param; ++ struct rtw89_channel_help_params bak; ++ u8 center_chan, bandwidth; ++ u8 band_type; ++ bool band_changed; ++ u8 i; ++ ++ rtw89_get_channel_params(&hw->conf.chandef, &ch_param); ++ if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) ++ return; ++ ++ center_chan = ch_param.center_chan; ++ bandwidth = ch_param.bandwidth; ++ band_type = center_chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; ++ band_changed = hal->current_band_type != band_type || ++ hal->current_channel == 0; ++ ++ hal->current_band_width = bandwidth; ++ hal->current_channel = center_chan; ++ hal->current_primary_channel = ch_param.primary_chan; ++ hal->current_band_type = band_type; ++ ++ switch (center_chan) { ++ case 1 ... 14: ++ hal->current_subband = RTW89_CH_2G; ++ break; ++ case 36 ... 64: ++ hal->current_subband = RTW89_CH_5G_BAND_1; ++ break; ++ case 100 ... 144: ++ hal->current_subband = RTW89_CH_5G_BAND_3; ++ break; ++ case 149 ... 177: ++ hal->current_subband = RTW89_CH_5G_BAND_4; ++ break; ++ } ++ ++ for (i = RTW89_CHANNEL_WIDTH_20; i <= RTW89_MAX_CHANNEL_WIDTH; i++) ++ hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; ++ ++ rtw89_chip_set_channel_prepare(rtwdev, &bak); ++ ++ chip->ops->set_channel(rtwdev, &ch_param); ++ ++ rtw89_chip_set_txpwr(rtwdev); ++ ++ rtw89_chip_set_channel_done(rtwdev, &bak); ++ ++ if (band_changed) { ++ rtw89_btc_ntfy_switch_band(rtwdev, RTW89_PHY_0, hal->current_band_type); ++ rtw89_chip_rfk_band_changed(rtwdev); ++ } ++} ++ ++static enum rtw89_core_tx_type ++rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ __le16 fc = hdr->frame_control; ++ ++ if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) ++ return RTW89_CORE_TX_TYPE_MGMT; ++ ++ return RTW89_CORE_TX_TYPE_DATA; ++} ++ ++static void ++rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req, u8 tid) ++{ ++ struct ieee80211_sta *sta = tx_req->sta; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct rtw89_sta *rtwsta; ++ u8 ampdu_num; ++ ++ if (!sta) { ++ rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); ++ return; ++ } ++ ++ rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? ++ rtwsta->ampdu_params[tid].agg_num : ++ 4 << sta->ht_cap.ampdu_factor) - 1); ++ ++ desc_info->agg_en = true; ++ desc_info->ampdu_density = sta->ht_cap.ampdu_density; ++ desc_info->ampdu_num = ampdu_num; ++} ++ ++static void ++rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct ieee80211_vif *vif = tx_req->vif; ++ struct ieee80211_tx_info *info; ++ struct ieee80211_key_conf *key; ++ struct rtw89_vif *rtwvif; ++ struct rtw89_addr_cam_entry *addr_cam; ++ struct rtw89_sec_cam_entry *sec_cam; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct sk_buff *skb = tx_req->skb; ++ u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; ++ ++ if (!vif) { ++ rtw89_warn(rtwdev, "cannot set sec key without vif\n"); ++ return; ++ } ++ ++ rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ addr_cam = &rtwvif->addr_cam; ++ ++ info = IEEE80211_SKB_CB(skb); ++ key = info->control.hw_key; ++ sec_cam = addr_cam->sec_entries[key->hw_key_idx]; ++ if (!sec_cam) { ++ rtw89_warn(rtwdev, "sec cam entry is empty\n"); ++ return; ++ } ++ ++ switch (key->cipher) { ++ case WLAN_CIPHER_SUITE_WEP40: ++ sec_type = RTW89_SEC_KEY_TYPE_WEP40; ++ break; ++ case WLAN_CIPHER_SUITE_WEP104: ++ sec_type = RTW89_SEC_KEY_TYPE_WEP104; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ sec_type = RTW89_SEC_KEY_TYPE_TKIP; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ sec_type = RTW89_SEC_KEY_TYPE_CCMP128; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP_256: ++ sec_type = RTW89_SEC_KEY_TYPE_CCMP256; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP: ++ sec_type = RTW89_SEC_KEY_TYPE_GCMP128; ++ break; ++ case WLAN_CIPHER_SUITE_GCMP_256: ++ sec_type = RTW89_SEC_KEY_TYPE_GCMP256; ++ break; ++ default: ++ rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); ++ return; ++ } ++ ++ desc_info->sec_en = true; ++ desc_info->sec_type = sec_type; ++ desc_info->sec_cam_idx = sec_cam->sec_cam_idx; ++} ++ ++static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); ++ struct ieee80211_vif *vif = tx_info->control.vif; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u16 lowest_rate = hal->current_band_type == RTW89_BAND_2G ? ++ RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6; ++ ++ if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) ++ return lowest_rate; ++ ++ return __ffs(vif->bss_conf.basic_rates) + lowest_rate; ++} ++ ++static void ++rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ u8 qsel, ch_dma; ++ ++ qsel = RTW89_TX_QSEL_B0_MGMT; ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ desc_info->qsel = RTW89_TX_QSEL_B0_MGMT; ++ desc_info->ch_dma = ch_dma; ++ ++ /* fixed data rate for mgmt frames */ ++ desc_info->en_wd_info = true; ++ desc_info->use_rate = true; ++ desc_info->dis_data_fb = true; ++ desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "tx mgmt frame with rate 0x%x on channel %d (bw %d)\n", ++ desc_info->data_rate, rtwdev->hal.current_channel, ++ rtwdev->hal.current_band_width); ++} ++ ++static void ++rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ ++ desc_info->is_bmc = false; ++ desc_info->wd_page = false; ++ desc_info->ch_dma = RTW89_DMA_H2C; ++} ++ ++static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) ++{ ++ static const u8 rtw89_bandwidth_to_om[] = { ++ [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, ++ [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, ++ [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, ++ [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, ++ [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, ++ }; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u8 om_bandwidth; ++ ++ if (!chip->dis_2g_40m_ul_ofdma || ++ hal->current_band_type != RTW89_BAND_2G || ++ hal->current_band_width != RTW89_CHANNEL_WIDTH_40) ++ return; ++ ++ om_bandwidth = hal->current_band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? ++ rtw89_bandwidth_to_om[hal->current_band_width] : 0; ++ *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | ++ le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | ++ le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | ++ le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | ++ le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | ++ le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | ++ le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | ++ le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | ++ le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); ++} ++ ++static bool ++__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req, ++ enum btc_pkt_type pkt_type) ++{ ++ struct ieee80211_sta *sta = tx_req->sta; ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ __le16 fc = hdr->frame_control; ++ ++ /* AP IOT issue with EAPoL, ARP and DHCP */ ++ if (pkt_type < PACKET_MAX) ++ return false; ++ ++ if (!sta || !sta->he_cap.has_he) ++ return false; ++ ++ if (!ieee80211_is_data_qos(fc)) ++ return false; ++ ++ if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) ++ return false; ++ ++ return true; ++} ++ ++static void ++__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct ieee80211_sta *sta = tx_req->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ __le16 fc = hdr->frame_control; ++ void *data; ++ __le32 *htc; ++ u8 *qc; ++ int hdr_len; ++ ++ hdr_len = ieee80211_has_a4(fc) ? 32 : 26; ++ data = skb_push(skb, IEEE80211_HT_CTL_LEN); ++ memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); ++ ++ hdr = data; ++ htc = data + hdr_len; ++ hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); ++ *htc = rtwsta->htc_template ? rtwsta->htc_template : ++ le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | ++ le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); ++ ++ qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; ++ qc[0] |= IEEE80211_QOS_CTL_EOSP; ++} ++ ++static void ++rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req, ++ enum btc_pkt_type pkt_type) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct ieee80211_vif *vif = tx_req->vif; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) ++ goto desc_bk; ++ ++ __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); ++ ++ desc_info->pkt_size += IEEE80211_HT_CTL_LEN; ++ desc_info->a_ctrl_bsr = true; ++ ++desc_bk: ++ if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) ++ return; ++ ++ rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; ++ desc_info->bk = true; ++} ++ ++static void ++rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct ieee80211_vif *vif = tx_req->vif; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct sk_buff *skb = tx_req->skb; ++ u8 tid, tid_indicate; ++ u8 qsel, ch_dma; ++ ++ tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; ++ tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); ++ qsel = rtw89_core_get_qsel(rtwdev, tid); ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ desc_info->ch_dma = ch_dma; ++ desc_info->tid_indicate = tid_indicate; ++ desc_info->qsel = qsel; ++ ++ /* enable wd_info for AMPDU */ ++ desc_info->en_wd_info = true; ++ ++ if (IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU) ++ rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, tid); ++ if (IEEE80211_SKB_CB(skb)->control.hw_key) ++ rtw89_core_tx_update_sec_key(rtwdev, tx_req); ++ ++ if (rate_pattern->enable) ++ desc_info->data_retry_lowest_rate = rate_pattern->rate; ++ else if (hal->current_band_type == RTW89_BAND_2G) ++ desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1; ++ else ++ desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; ++} ++ ++static enum btc_pkt_type ++rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct sk_buff *skb = tx_req->skb; ++ struct udphdr *udphdr; ++ ++ if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); ++ return PACKET_EAPOL; ++ } ++ ++ if (skb->protocol == htons(ETH_P_ARP)) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); ++ return PACKET_ARP; ++ } ++ ++ if (skb->protocol == htons(ETH_P_IP) && ++ ip_hdr(skb)->protocol == IPPROTO_UDP) { ++ udphdr = udp_hdr(skb); ++ if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || ++ (udphdr->source == htons(68) && udphdr->dest == htons(67))) && ++ skb->len > 282) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); ++ return PACKET_DHCP; ++ } ++ } ++ ++ if (skb->protocol == htons(ETH_P_IP) && ++ ip_hdr(skb)->protocol == IPPROTO_ICMP) { ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); ++ return PACKET_ICMP; ++ } ++ ++ return PACKET_MAX; ++} ++ ++static void ++rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct sk_buff *skb = tx_req->skb; ++ struct ieee80211_hdr *hdr = (void *)skb->data; ++ enum rtw89_core_tx_type tx_type; ++ enum btc_pkt_type pkt_type; ++ bool is_bmc; ++ u16 seq; ++ ++ seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; ++ if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { ++ tx_type = rtw89_core_get_tx_type(rtwdev, skb); ++ tx_req->tx_type = tx_type; ++ } ++ is_bmc = (is_broadcast_ether_addr(hdr->addr1) || ++ is_multicast_ether_addr(hdr->addr1)); ++ ++ desc_info->seq = seq; ++ desc_info->pkt_size = skb->len; ++ desc_info->is_bmc = is_bmc; ++ desc_info->wd_page = true; ++ ++ switch (tx_req->tx_type) { ++ case RTW89_CORE_TX_TYPE_MGMT: ++ rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); ++ break; ++ case RTW89_CORE_TX_TYPE_DATA: ++ rtw89_core_tx_update_data_info(rtwdev, tx_req); ++ pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); ++ rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); ++ break; ++ case RTW89_CORE_TX_TYPE_FWCMD: ++ rtw89_core_tx_update_h2c_info(rtwdev, tx_req); ++ break; ++ } ++} ++ ++void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) ++{ ++ u8 ch_dma; ++ ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ rtw89_hci_tx_kick_off(rtwdev, ch_dma); ++} ++ ++int rtw89_h2c_tx(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, bool fwdl) ++{ ++ struct rtw89_core_tx_request tx_req = {0}; ++ u32 cnt; ++ int ret; ++ ++ tx_req.skb = skb; ++ tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; ++ if (fwdl) ++ tx_req.desc_info.fw_dl = true; ++ ++ rtw89_core_tx_update_desc_info(rtwdev, &tx_req); ++ ++ if (!fwdl) ++ rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); ++ ++ cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); ++ if (cnt == 0) { ++ rtw89_err(rtwdev, "no tx fwcmd resource\n"); ++ return -ENOSPC; ++ } ++ ++ ret = rtw89_hci_tx_write(rtwdev, &tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); ++ return ret; ++ } ++ rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); ++ ++ return 0; ++} ++ ++int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) ++{ ++ struct rtw89_core_tx_request tx_req = {0}; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ int ret; ++ ++ tx_req.skb = skb; ++ tx_req.sta = sta; ++ tx_req.vif = vif; ++ ++ rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); ++ rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); ++ rtw89_core_tx_update_desc_info(rtwdev, &tx_req); ++ ret = rtw89_hci_tx_write(rtwdev, &tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); ++ return ret; ++ } ++ ++ if (qsel) ++ *qsel = tx_req.desc_info.qsel; ++ ++ return 0; ++} ++ ++static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | ++ FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | ++ FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | ++ FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | ++ FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | ++ FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); ++ ++ return cpu_to_le32(dword); ++} ++ ++static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | ++ FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | ++ FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size); ++ ++ return cpu_to_le32(dword); ++} ++ ++static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | ++ FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | ++ FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); ++ ++ return cpu_to_le32(dword); ++} ++ ++static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | ++ FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | ++ FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb); ++ ++ return cpu_to_le32(dword); ++} ++ ++static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | ++ FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | ++ FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, ++ desc_info->data_retry_lowest_rate); ++ ++ return cpu_to_le32(dword); ++} ++ ++static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | ++ FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | ++ FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | ++ FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); ++ ++ return cpu_to_le32(dword); ++} ++ ++static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) ++{ ++ u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | ++ FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); ++ ++ return cpu_to_le32(dword); ++} ++ ++void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_tx_desc_info *desc_info, ++ void *txdesc) ++{ ++ struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; ++ struct rtw89_txwd_info *txwd_info; ++ ++ txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); ++ txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); ++ txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); ++ ++ if (!desc_info->en_wd_info) ++ return; ++ ++ txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); ++ txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); ++ txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); ++ txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); ++ txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); ++ ++} ++EXPORT_SYMBOL(rtw89_core_fill_txdesc); ++ ++static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ bool rx_cnt_valid = false; ++ u8 plcp_size = 0; ++ u8 usr_num = 0; ++ u8 *phy_sts; ++ ++ rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); ++ plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; ++ usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); ++ if (usr_num > RTW89_PPDU_MAX_USR) { ++ rtw89_warn(rtwdev, "Invalid user number in mac info\n"); ++ return -EINVAL; ++ } ++ ++ phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; ++ phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; ++ /* 8-byte alignment */ ++ if (usr_num & BIT(0)) ++ phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; ++ if (rx_cnt_valid) ++ phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; ++ phy_sts += plcp_size; ++ ++ phy_ppdu->buf = phy_sts; ++ phy_ppdu->len = skb->data + skb->len - phy_sts; ++ ++ return 0; ++} ++ ++static void rtw89_core_rx_process_phy_ppdu_iter(void *data, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; ++ ++ if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) ++ ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); ++} ++ ++#define VAR_LEN 0xff ++#define VAR_LEN_UNIT 8 ++static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) ++{ ++ static const u8 physts_ie_len_tab[32] = { ++ 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, ++ VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, ++ VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 ++ }; ++ u16 ie_len; ++ u8 ie; ++ ++ ie = RTW89_GET_PHY_STS_IE_TYPE(addr); ++ if (physts_ie_len_tab[ie] != VAR_LEN) ++ ie_len = physts_ie_len_tab[ie]; ++ else ++ ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; ++ ++ return ie_len; ++} ++ ++static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ s16 cfo; ++ ++ /* sign conversion for S(12,2) */ ++ cfo = sign_extend32(RTW89_GET_PHY_STS_IE0_CFO(addr), 11); ++ rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); ++} ++ ++static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ u8 ie; ++ ++ ie = RTW89_GET_PHY_STS_IE_TYPE(addr); ++ switch (ie) { ++ case RTW89_PHYSTS_IE01_CMN_OFDM: ++ rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ s8 *rssi = phy_ppdu->rssi; ++ u8 *buf = phy_ppdu->buf; ++ ++ phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); ++ rssi[RF_PATH_A] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_A(buf)); ++ rssi[RF_PATH_B] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_B(buf)); ++ rssi[RF_PATH_C] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_C(buf)); ++ rssi[RF_PATH_D] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_D(buf)); ++} ++ ++static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { ++ rtw89_warn(rtwdev, "phy ppdu len mismatch\n"); ++ return -EINVAL; ++ } ++ rtw89_core_update_phy_ppdu(phy_ppdu); ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_core_rx_process_phy_ppdu_iter, ++ phy_ppdu); ++ ++ return 0; ++} ++ ++static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ u16 ie_len; ++ u8 *pos, *end; ++ ++ if (!phy_ppdu->to_self) ++ return 0; ++ ++ pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; ++ end = (u8 *)phy_ppdu->buf + phy_ppdu->len; ++ while (pos < end) { ++ ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); ++ rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); ++ pos += ie_len; ++ if (pos > end || ie_len == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "phy status parse failed\n"); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ int ret; ++ ++ ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); ++ else ++ phy_ppdu->valid = true; ++} ++ ++static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, ++ const struct rtw89_rx_desc_info *desc_info, ++ bool rx_status) ++{ ++ switch (desc_info->gi_ltf) { ++ case RTW89_GILTF_SGI_4XHE08: ++ case RTW89_GILTF_2XHE08: ++ case RTW89_GILTF_1XHE08: ++ return NL80211_RATE_INFO_HE_GI_0_8; ++ case RTW89_GILTF_2XHE16: ++ case RTW89_GILTF_1XHE16: ++ return NL80211_RATE_INFO_HE_GI_1_6; ++ case RTW89_GILTF_LGI_4XHE32: ++ return NL80211_RATE_INFO_HE_GI_3_2; ++ default: ++ rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); ++ return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; ++ } ++} ++ ++static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct ieee80211_rx_status *status) ++{ ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; ++ u16 data_rate; ++ bool ret; ++ ++ data_rate = desc_info->data_rate; ++ data_rate_mode = GET_DATA_RATE_MODE(data_rate); ++ if (data_rate_mode == DATA_RATE_MODE_NON_HT) { ++ rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); ++ /* No 4 CCK rates for 5G */ ++ if (status->band == NL80211_BAND_5GHZ) ++ rate_idx -= 4; ++ } else if (data_rate_mode == DATA_RATE_MODE_HT) { ++ rate_idx = GET_DATA_RATE_HT_IDX(data_rate); ++ } else if (data_rate_mode == DATA_RATE_MODE_VHT) { ++ rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ } else if (data_rate_mode == DATA_RATE_MODE_HE) { ++ rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ } else { ++ rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); ++ } ++ ++ if (desc_info->bw == RTW89_CHANNEL_WIDTH_80) ++ bw = RATE_INFO_BW_80; ++ else if (desc_info->bw == RTW89_CHANNEL_WIDTH_40) ++ bw = RATE_INFO_BW_40; ++ else ++ bw = RATE_INFO_BW_20; ++ ++ gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); ++ ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && ++ status->rate_idx == rate_idx && ++ status->he_gi == gi_ltf && ++ status->bw == bw; ++ ++ return ret; ++} ++ ++struct rtw89_vif_rx_stats_iter_data { ++ struct rtw89_dev *rtwdev; ++ struct rtw89_rx_phy_ppdu *phy_ppdu; ++ struct rtw89_rx_desc_info *desc_info; ++ struct sk_buff *skb; ++ const u8 *bssid; ++}; ++ ++static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_vif_rx_stats_iter_data *iter_data = data; ++ struct rtw89_dev *rtwdev = iter_data->rtwdev; ++ struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; ++ struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; ++ struct sk_buff *skb = iter_data->skb; ++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; ++ const u8 *bssid = iter_data->bssid; ++ ++ if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) ++ return; ++ ++ if (ieee80211_is_beacon(hdr->frame_control)) ++ pkt_stat->beacon_nr++; ++ ++ if (!ether_addr_equal(vif->addr, hdr->addr1)) ++ return; ++ ++ if (desc_info->data_rate < RTW89_HW_RATE_NR) ++ pkt_stat->rx_rate_cnt[desc_info->data_rate]++; ++ ++ rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); ++} ++ ++static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ struct rtw89_vif_rx_stats_iter_data iter_data; ++ ++ rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); ++ ++ iter_data.rtwdev = rtwdev; ++ iter_data.phy_ppdu = phy_ppdu; ++ iter_data.desc_info = desc_info; ++ iter_data.skb = skb; ++ iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); ++ rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); ++} ++ ++static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; ++ struct sk_buff *skb_ppdu = NULL, *tmp; ++ struct ieee80211_rx_status *rx_status; ++ ++ if (curr > RTW89_MAX_PPDU_CNT) ++ return; ++ ++ skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { ++ skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); ++ rx_status = IEEE80211_SKB_RXCB(skb_ppdu); ++ if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) ++ rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); ++ rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); ++ ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, &rtwdev->napi); ++ rtwdev->napi_budget_countdown--; ++ } ++} ++ ++static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, ++ .len = skb->len, ++ .to_self = desc_info->addr1_match, ++ .mac_id = desc_info->mac_id}; ++ int ret; ++ ++ if (desc_info->mac_info_valid) ++ rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); ++ ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); ++ ++ rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); ++ rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); ++ dev_kfree_skb_any(skb); ++} ++ ++static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ switch (desc_info->pkt_type) { ++ case RTW89_CORE_RX_TYPE_C2H: ++ rtw89_fw_c2h_irqsafe(rtwdev, skb); ++ break; ++ case RTW89_CORE_RX_TYPE_PPDU_STAT: ++ rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); ++ break; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", ++ desc_info->pkt_type); ++ dev_kfree_skb_any(skb); ++ break; ++ } ++} ++ ++void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ u8 *data, u32 data_offset) ++{ ++ struct rtw89_rxdesc_short *rxd_s; ++ struct rtw89_rxdesc_long *rxd_l; ++ u8 shift_len, drv_info_len; ++ ++ rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); ++ desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); ++ desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); ++ desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); ++ desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); ++ desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); ++ desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); ++ desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); ++ desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); ++ desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); ++ desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); ++ desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); ++ desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); ++ desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); ++ desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); ++ desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); ++ desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); ++ desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); ++ desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); ++ ++ shift_len = desc_info->shift << 1; /* 2-byte unit */ ++ drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ ++ desc_info->offset = data_offset + shift_len + drv_info_len; ++ desc_info->ready = true; ++ ++ if (!desc_info->long_rxdesc) ++ return; ++ ++ rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); ++ desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); ++ desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); ++ desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); ++ desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); ++ desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); ++ desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); ++} ++EXPORT_SYMBOL(rtw89_core_query_rxdesc); ++ ++struct rtw89_core_iter_rx_status { ++ struct rtw89_dev *rtwdev; ++ struct ieee80211_rx_status *rx_status; ++ struct rtw89_rx_desc_info *desc_info; ++ u8 mac_id; ++}; ++ ++static ++void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_core_iter_rx_status *iter_data = ++ (struct rtw89_core_iter_rx_status *)data; ++ struct ieee80211_rx_status *rx_status = iter_data->rx_status; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; ++ u8 mac_id = iter_data->mac_id; ++ ++ if (mac_id != rtwsta->mac_id) ++ return; ++ ++ rtwsta->rx_status = *rx_status; ++ rtwsta->rx_hw_rate = desc_info->data_rate; ++} ++ ++static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct ieee80211_rx_status *rx_status) ++{ ++ struct rtw89_core_iter_rx_status iter_data; ++ ++ if (!desc_info->addr1_match || !desc_info->long_rxdesc) ++ return; ++ ++ if (desc_info->frame_type != RTW89_RX_TYPE_DATA) ++ return; ++ ++ iter_data.rtwdev = rtwdev; ++ iter_data.rx_status = rx_status; ++ iter_data.desc_info = desc_info; ++ iter_data.mac_id = desc_info->mac_id; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_core_stats_sta_rx_status_iter, ++ &iter_data); ++} ++ ++static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct ieee80211_rx_status *rx_status) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ u16 data_rate; ++ u8 data_rate_mode; ++ ++ /* currently using single PHY */ ++ rx_status->freq = hw->conf.chandef.chan->center_freq; ++ rx_status->band = hw->conf.chandef.chan->band; ++ ++ if (desc_info->icv_err || desc_info->crc32_err) ++ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; ++ ++ if (desc_info->hw_dec && ++ !(desc_info->sw_dec || desc_info->icv_err)) ++ rx_status->flag |= RX_FLAG_DECRYPTED; ++ ++ if (desc_info->bw == RTW89_CHANNEL_WIDTH_80) ++ rx_status->bw = RATE_INFO_BW_80; ++ else if (desc_info->bw == RTW89_CHANNEL_WIDTH_40) ++ rx_status->bw = RATE_INFO_BW_40; ++ else ++ rx_status->bw = RATE_INFO_BW_20; ++ ++ data_rate = desc_info->data_rate; ++ data_rate_mode = GET_DATA_RATE_MODE(data_rate); ++ if (data_rate_mode == DATA_RATE_MODE_NON_HT) { ++ rx_status->encoding = RX_ENC_LEGACY; ++ rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); ++ /* No 4 CCK rates for 5G */ ++ if (rx_status->band == NL80211_BAND_5GHZ) ++ rx_status->rate_idx -= 4; ++ if (rtwdev->scanning) ++ rx_status->rate_idx = min_t(u8, rx_status->rate_idx, ++ ARRAY_SIZE(rtw89_bitrates) - 5); ++ } else if (data_rate_mode == DATA_RATE_MODE_HT) { ++ rx_status->encoding = RX_ENC_HT; ++ rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); ++ if (desc_info->gi_ltf) ++ rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; ++ } else if (data_rate_mode == DATA_RATE_MODE_VHT) { ++ rx_status->encoding = RX_ENC_VHT; ++ rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; ++ if (desc_info->gi_ltf) ++ rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; ++ } else if (data_rate_mode == DATA_RATE_MODE_HE) { ++ rx_status->encoding = RX_ENC_HE; ++ rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); ++ rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; ++ } else { ++ rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); ++ } ++ ++ /* he_gi is used to match ppdu, so we always fill it. */ ++ rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); ++ rx_status->flag |= RX_FLAG_MACTIME_START; ++ rx_status->mactime = desc_info->free_run_cnt; ++ ++ rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); ++} ++ ++static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (rtw89_disable_ps_mode || !chip->ps_mode_supported) ++ return RTW89_PS_MODE_NONE; ++ ++ if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) ++ return RTW89_PS_MODE_PWR_GATED; ++ ++ if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) ++ return RTW89_PS_MODE_CLK_GATED; ++ ++ if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) ++ return RTW89_PS_MODE_RFOFF; ++ ++ return RTW89_PS_MODE_NONE; ++} ++ ++static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info) ++{ ++ struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ struct sk_buff *skb_ppdu, *tmp; ++ ++ skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { ++ skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); ++ rtw89_core_rx_stats(rtwdev, NULL, desc_info, skb_ppdu); ++ ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, &rtwdev->napi); ++ rtwdev->napi_budget_countdown--; ++ } ++} ++ ++void rtw89_core_rx(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_rx_status *rx_status; ++ struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; ++ u8 ppdu_cnt = desc_info->ppdu_cnt; ++ u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ ++ if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { ++ rtw89_core_rx_process_report(rtwdev, desc_info, skb); ++ return; ++ } ++ ++ if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { ++ rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); ++ ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; ++ } ++ ++ rx_status = IEEE80211_SKB_RXCB(skb); ++ memset(rx_status, 0, sizeof(*rx_status)); ++ rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); ++ if (desc_info->long_rxdesc && ++ BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) { ++ skb_queue_tail(&ppdu_sts->rx_queue[band], skb); ++ } else { ++ rtw89_core_rx_stats(rtwdev, NULL, desc_info, skb); ++ ieee80211_rx_napi(rtwdev->hw, NULL, skb, &rtwdev->napi); ++ rtwdev->napi_budget_countdown--; ++ } ++} ++EXPORT_SYMBOL(rtw89_core_rx); ++ ++void rtw89_core_napi_start(struct rtw89_dev *rtwdev) ++{ ++ if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) ++ return; ++ ++ napi_enable(&rtwdev->napi); ++} ++EXPORT_SYMBOL(rtw89_core_napi_start); ++ ++void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) ++{ ++ if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) ++ return; ++ ++ napi_synchronize(&rtwdev->napi); ++ napi_disable(&rtwdev->napi); ++} ++EXPORT_SYMBOL(rtw89_core_napi_stop); ++ ++void rtw89_core_napi_init(struct rtw89_dev *rtwdev) ++{ ++ init_dummy_netdev(&rtwdev->netdev); ++ netif_napi_add(&rtwdev->netdev, &rtwdev->napi, ++ rtwdev->hci.ops->napi_poll, NAPI_POLL_WEIGHT); ++} ++EXPORT_SYMBOL(rtw89_core_napi_init); ++ ++void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) ++{ ++ rtw89_core_napi_stop(rtwdev); ++ netif_napi_del(&rtwdev->napi); ++} ++EXPORT_SYMBOL(rtw89_core_napi_deinit); ++ ++static void rtw89_core_ba_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = ++ container_of(work, struct rtw89_dev, ba_work); ++ struct rtw89_txq *rtwtxq, *tmp; ++ int ret; ++ ++ spin_lock_bh(&rtwdev->ba_lock); ++ list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ struct ieee80211_sta *sta = txq->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ u8 tid = txq->tid; ++ ++ if (!sta) { ++ rtw89_warn(rtwdev, "cannot start BA without sta\n"); ++ goto skip_ba_work; ++ } ++ ++ if (rtwsta->disassoc) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "cannot start BA with disassoc sta\n"); ++ goto skip_ba_work; ++ } ++ ++ ret = ieee80211_start_tx_ba_session(sta, tid, 0); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "failed to setup BA session for %pM:%2d: %d\n", ++ sta->addr, tid, ret); ++ if (ret == -EINVAL) ++ set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); ++ } ++skip_ba_work: ++ list_del_init(&rtwtxq->list); ++ } ++ spin_unlock_bh(&rtwdev->ba_lock); ++} ++ ++static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_txq *rtwtxq, *tmp; ++ ++ spin_lock_bh(&rtwdev->ba_lock); ++ list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ ++ if (sta == txq->sta) ++ list_del_init(&rtwtxq->list); ++ } ++ spin_unlock_bh(&rtwdev->ba_lock); ++} ++ ++static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, ++ struct rtw89_txq *rtwtxq, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ struct ieee80211_sta *sta = txq->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ if (unlikely(skb_get_queue_mapping(skb) == IEEE80211_AC_VO)) ++ return; ++ ++ if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) ++ return; ++ ++ if (unlikely(!sta)) ++ return; ++ ++ if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) ++ return; ++ ++ if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { ++ IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; ++ return; ++ } ++ ++ spin_lock_bh(&rtwdev->ba_lock); ++ if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { ++ list_add_tail(&rtwtxq->list, &rtwdev->ba_list); ++ ieee80211_queue_work(hw, &rtwdev->ba_work); ++ } ++ spin_unlock_bh(&rtwdev->ba_lock); ++} ++ ++static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, ++ struct rtw89_txq *rtwtxq, ++ unsigned long frame_cnt, ++ unsigned long byte_cnt) ++{ ++ struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); ++ struct ieee80211_vif *vif = txq->vif; ++ struct ieee80211_sta *sta = txq->sta; ++ struct sk_buff *skb; ++ unsigned long i; ++ int ret; ++ ++ for (i = 0; i < frame_cnt; i++) { ++ skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); ++ if (!skb) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); ++ return; ++ } ++ rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); ++ ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to push txq: %d\n", ret); ++ ieee80211_free_txskb(rtwdev->hw, skb); ++ break; ++ } ++ } ++} ++ ++static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) ++{ ++ u8 qsel, ch_dma; ++ ++ qsel = rtw89_core_get_qsel(rtwdev, tid); ++ ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); ++} ++ ++static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, ++ struct ieee80211_txq *txq, ++ unsigned long *frame_cnt, ++ bool *sched_txq, bool *reinvoke) ++{ ++ struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ struct ieee80211_sta *sta = txq->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ if (!sta || rtwsta->max_agg_wait <= 0) ++ return false; ++ ++ if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) ++ return false; ++ ++ if (*frame_cnt > 1) { ++ *frame_cnt -= 1; ++ *sched_txq = true; ++ *reinvoke = true; ++ rtwtxq->wait_cnt = 1; ++ return false; ++ } ++ ++ if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { ++ *reinvoke = true; ++ rtwtxq->wait_cnt++; ++ return true; ++ } ++ ++ rtwtxq->wait_cnt = 0; ++ return false; ++} ++ ++static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct ieee80211_txq *txq; ++ struct rtw89_txq *rtwtxq; ++ unsigned long frame_cnt; ++ unsigned long byte_cnt; ++ u32 tx_resource; ++ bool sched_txq; ++ ++ ieee80211_txq_schedule_start(hw, ac); ++ while ((txq = ieee80211_next_txq(hw, ac))) { ++ rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); ++ sched_txq = false; ++ ++ ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); ++ if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { ++ ieee80211_return_txq(hw, txq, true); ++ continue; ++ } ++ frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); ++ rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); ++ ieee80211_return_txq(hw, txq, sched_txq); ++ if (frame_cnt != 0) ++ rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); ++ } ++ ieee80211_txq_schedule_end(hw, ac); ++} ++ ++static void rtw89_core_txq_work(struct work_struct *w) ++{ ++ struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); ++ bool reinvoke = false; ++ u8 ac; ++ ++ for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) ++ rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); ++ ++ if (reinvoke) { ++ /* reinvoke to process the last frame */ ++ mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); ++ } ++} ++ ++static void rtw89_core_txq_reinvoke_work(struct work_struct *w) ++{ ++ struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, ++ txq_reinvoke_work.work); ++ ++ queue_work(rtwdev->txq_wq, &rtwdev->txq_work); ++} ++ ++static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, ++ u32 throughput, u64 cnt) ++{ ++ if (cnt < 100) ++ return RTW89_TFC_IDLE; ++ if (throughput > 50) ++ return RTW89_TFC_HIGH; ++ if (throughput > 10) ++ return RTW89_TFC_MID; ++ if (throughput > 2) ++ return RTW89_TFC_LOW; ++ return RTW89_TFC_ULTRA_LOW; ++} ++ ++static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats) ++{ ++ enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; ++ enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; ++ ++ stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); ++ stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); ++ ++ ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); ++ ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); ++ ++ stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); ++ stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); ++ stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, ++ stats->tx_cnt); ++ stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, ++ stats->rx_cnt); ++ stats->tx_avg_len = stats->tx_cnt ? ++ DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; ++ stats->rx_avg_len = stats->rx_cnt ? ++ DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; ++ ++ stats->tx_unicast = 0; ++ stats->rx_unicast = 0; ++ stats->tx_cnt = 0; ++ stats->rx_cnt = 0; ++ ++ if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) ++ return true; ++ ++ return false; ++} ++ ++static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ bool tfc_changed; ++ ++ tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); ++ ++ return tfc_changed; ++} ++ ++static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) ++ return; ++ ++ if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && ++ rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) ++ rtw89_enter_lps(rtwdev, rtwvif->mac_id); ++} ++ ++static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_vif_enter_lps(rtwdev, rtwvif); ++} ++ ++void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats) ++{ ++ stats->tx_unicast = 0; ++ stats->rx_unicast = 0; ++ stats->tx_cnt = 0; ++ stats->rx_cnt = 0; ++ ewma_tp_init(&stats->tx_ewma_tp); ++ ewma_tp_init(&stats->rx_ewma_tp); ++} ++ ++static void rtw89_track_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ track_work.work); ++ bool tfc_changed; ++ ++ mutex_lock(&rtwdev->mutex); ++ ++ if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) ++ goto out; ++ ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, ++ RTW89_TRACK_WORK_PERIOD); ++ ++ tfc_changed = rtw89_traffic_stats_track(rtwdev); ++ if (rtwdev->scanning) ++ goto out; ++ ++ rtw89_leave_lps(rtwdev); ++ ++ if (tfc_changed) { ++ rtw89_hci_recalc_int_mit(rtwdev); ++ rtw89_btc_ntfy_wl_sta(rtwdev); ++ } ++ rtw89_mac_bf_monitor_track(rtwdev); ++ rtw89_phy_stat_track(rtwdev); ++ rtw89_phy_env_monitor_track(rtwdev); ++ rtw89_phy_dig(rtwdev); ++ rtw89_chip_rfk_track(rtwdev); ++ rtw89_phy_ra_update(rtwdev); ++ rtw89_phy_cfo_track(rtwdev); ++ ++ if (rtwdev->lps_enabled && !rtwdev->btc.lps) ++ rtw89_enter_lps_track(rtwdev); ++ ++out: ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) ++{ ++ unsigned long bit; ++ ++ bit = find_first_zero_bit(addr, size); ++ if (bit < size) ++ set_bit(bit, addr); ++ ++ return bit; ++} ++ ++void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) ++{ ++ clear_bit(bit, addr); ++} ++ ++void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) ++{ ++ bitmap_zero(addr, nbits); ++} ++ ++#define RTW89_TYPE_MAPPING(_type) \ ++ case NL80211_IFTYPE_ ## _type: \ ++ rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ ++ break ++void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ switch (vif->type) { ++ RTW89_TYPE_MAPPING(ADHOC); ++ RTW89_TYPE_MAPPING(STATION); ++ RTW89_TYPE_MAPPING(AP); ++ RTW89_TYPE_MAPPING(MONITOR); ++ RTW89_TYPE_MAPPING(MESH_POINT); ++ default: ++ WARN_ON(1); ++ break; ++ } ++ ++ switch (vif->type) { ++ case NL80211_IFTYPE_AP: ++ case NL80211_IFTYPE_MESH_POINT: ++ rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; ++ rtwvif->self_role = RTW89_SELF_ROLE_AP; ++ break; ++ case NL80211_IFTYPE_ADHOC: ++ rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; ++ rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; ++ break; ++ case NL80211_IFTYPE_STATION: ++ if (assoc) { ++ rtwvif->net_type = RTW89_NET_TYPE_INFRA; ++ rtwvif->trigger = vif->bss_conf.he_support; ++ } else { ++ rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; ++ rtwvif->trigger = false; ++ } ++ rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; ++ rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; ++ break; ++ default: ++ WARN_ON(1); ++ break; ++ } ++} ++ ++int rtw89_core_sta_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ int i; ++ ++ rtwsta->rtwvif = rtwvif; ++ rtwsta->prev_rssi = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(sta->txq); i++) ++ rtw89_core_txq_init(rtwdev, sta->txq[i]); ++ ++ ewma_rssi_init(&rtwsta->avg_rssi); ++ ++ if (vif->type == NL80211_IFTYPE_STATION) { ++ rtwvif->mgd.ap = sta; ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, ++ BTC_ROLE_MSTS_STA_CONN_START); ++ rtw89_chip_rfk_channel(rtwdev); ++ } ++ ++ return 0; ++} ++ ++int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ rtwdev->total_sta_assoc--; ++ rtwsta->disassoc = true; ++ ++ return 0; ++} ++ ++int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ int ret; ++ ++ rtw89_mac_bf_monitor_calc(rtwdev, sta, true); ++ rtw89_mac_bf_disassoc(rtwdev, vif, sta); ++ rtw89_core_free_sta_pending_ba(rtwdev, sta); ++ ++ rtw89_vif_type_mapping(vif, false); ++ ++ ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); ++ return ret; ++ } ++ ++ ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, 1); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c join info\n"); ++ return ret; ++ } ++ ++ /* update cam aid mac_id net_type */ ++ rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cam\n"); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ int ret; ++ ++ rtw89_vif_type_mapping(vif, true); ++ ++ ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); ++ return ret; ++ } ++ ++ /* for station mode, assign the mac_id from itself */ ++ if (vif->type == NL80211_IFTYPE_STATION) ++ rtwsta->mac_id = rtwvif->mac_id; ++ ++ ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, 0); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c join info\n"); ++ return ret; ++ } ++ ++ /* update cam aid mac_id net_type */ ++ rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c cam\n"); ++ return ret; ++ } ++ ++ ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwsta->mac_id); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to send h2c general packet\n"); ++ return ret; ++ } ++ ++ rtwdev->total_sta_assoc++; ++ rtw89_phy_ra_assoc(rtwdev, sta); ++ rtw89_mac_bf_assoc(rtwdev, vif, sta); ++ rtw89_mac_bf_monitor_calc(rtwdev, sta, false); ++ ++ if (vif->type == NL80211_IFTYPE_STATION) { ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, ++ BTC_ROLE_MSTS_STA_CONN_END); ++ rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); ++ } ++ ++ return ret; ++} ++ ++int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ if (vif->type == NL80211_IFTYPE_STATION) ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, ++ BTC_ROLE_MSTS_STA_DIS_CONN); ++ ++ return 0; ++} ++ ++static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta_ht_cap *ht_cap) ++{ ++ static const __le16 highest[RF_PATH_MAX] = { ++ cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), ++ }; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u8 nss = hal->rx_nss; ++ int i; ++ ++ ht_cap->ht_supported = true; ++ ht_cap->cap = 0; ++ ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_MAX_AMSDU | ++ IEEE80211_HT_CAP_TX_STBC | ++ (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); ++ ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; ++ ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | ++ IEEE80211_HT_CAP_DSSSCCK40 | ++ IEEE80211_HT_CAP_SGI_40; ++ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; ++ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; ++ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; ++ for (i = 0; i < nss; i++) ++ ht_cap->mcs.rx_mask[i] = 0xFF; ++ ht_cap->mcs.rx_mask[4] = 0x01; ++ ht_cap->mcs.rx_highest = highest[nss - 1]; ++} ++ ++static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta_vht_cap *vht_cap) ++{ ++ static const __le16 highest[RF_PATH_MAX] = { ++ cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), ++ }; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u16 tx_mcs_map = 0, rx_mcs_map = 0; ++ u8 sts_cap = 3; ++ int i; ++ ++ for (i = 0; i < 8; i++) { ++ if (i < hal->tx_nss) ++ tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); ++ else ++ tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); ++ if (i < hal->rx_nss) ++ rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); ++ else ++ rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); ++ } ++ ++ vht_cap->vht_supported = true; ++ vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | ++ IEEE80211_VHT_CAP_SHORT_GI_80 | ++ IEEE80211_VHT_CAP_RXSTBC_1 | ++ IEEE80211_VHT_CAP_HTC_VHT | ++ IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | ++ 0; ++ vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; ++ vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; ++ vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | ++ IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; ++ vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; ++ vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); ++ vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); ++ vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; ++ vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; ++} ++ ++#define RTW89_SBAND_IFTYPES_NR 2 ++ ++static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, ++ enum nl80211_band band, ++ struct ieee80211_supported_band *sband) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct ieee80211_sband_iftype_data *iftype_data; ++ bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || ++ (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); ++ u16 mcs_map = 0; ++ int i; ++ int nss = hal->rx_nss; ++ int idx = 0; ++ ++ iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); ++ if (!iftype_data) ++ return; ++ ++ for (i = 0; i < 8; i++) { ++ if (i < nss) ++ mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); ++ else ++ mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); ++ } ++ ++ for (i = 0; i < NUM_NL80211_IFTYPES; i++) { ++ struct ieee80211_sta_he_cap *he_cap; ++ u8 *mac_cap_info; ++ u8 *phy_cap_info; ++ ++ switch (i) { ++ case NL80211_IFTYPE_STATION: ++ case NL80211_IFTYPE_AP: ++ break; ++ default: ++ continue; ++ } ++ ++ if (idx >= RTW89_SBAND_IFTYPES_NR) { ++ rtw89_warn(rtwdev, "run out of iftype_data\n"); ++ break; ++ } ++ ++ iftype_data[idx].types_mask = BIT(i); ++ he_cap = &iftype_data[idx].he_cap; ++ mac_cap_info = he_cap->he_cap_elem.mac_cap_info; ++ phy_cap_info = he_cap->he_cap_elem.phy_cap_info; ++ ++ he_cap->has_he = true; ++ if (i == NL80211_IFTYPE_AP) ++ mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; ++ if (i == NL80211_IFTYPE_STATION) ++ mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; ++ mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | ++ IEEE80211_HE_MAC_CAP2_BSR; ++ mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; ++ if (i == NL80211_IFTYPE_AP) ++ mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; ++ mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | ++ IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; ++ if (i == NL80211_IFTYPE_STATION) ++ mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; ++ phy_cap_info[0] = IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; ++ phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | ++ IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | ++ IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; ++ phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | ++ IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | ++ IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | ++ IEEE80211_HE_PHY_CAP2_DOPPLER_TX; ++ phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; ++ if (i == NL80211_IFTYPE_STATION) ++ phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | ++ IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; ++ if (i == NL80211_IFTYPE_AP) ++ phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; ++ phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | ++ IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; ++ phy_cap_info[5] = no_ng16 ? 0 : ++ IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | ++ IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; ++ phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | ++ IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | ++ IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | ++ IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; ++ phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | ++ IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | ++ IEEE80211_HE_PHY_CAP7_MAX_NC_1; ++ phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | ++ IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | ++ IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; ++ phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | ++ IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | ++ IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | ++ IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | ++ IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US; ++ if (i == NL80211_IFTYPE_STATION) ++ phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; ++ he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); ++ he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); ++ ++ idx++; ++ } ++ ++ sband->iftype_data = iftype_data; ++ sband->n_iftype_data = idx; ++} ++ ++static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; ++ u32 size = sizeof(struct ieee80211_supported_band); ++ ++ sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); ++ if (!sband_2ghz) ++ goto err; ++ rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); ++ rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); ++ hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; ++ ++ sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); ++ if (!sband_5ghz) ++ goto err; ++ rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); ++ rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); ++ rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); ++ hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; ++ ++ return 0; ++ ++err: ++ hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; ++ hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; ++ if (sband_2ghz) ++ kfree(sband_2ghz->iftype_data); ++ if (sband_5ghz) ++ kfree(sband_5ghz->iftype_data); ++ kfree(sband_2ghz); ++ kfree(sband_5ghz); ++ return -ENOMEM; ++} ++ ++static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ ++ kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); ++ kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); ++ kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); ++ kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); ++ hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; ++ hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; ++} ++ ++static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) ++{ ++ int i; ++ ++ for (i = 0; i < RTW89_PHY_MAX; i++) ++ skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); ++ for (i = 0; i < RTW89_PHY_MAX; i++) ++ rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; ++} ++ ++int rtw89_core_start(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ rtwdev->mac.qta_mode = RTW89_QTA_SCC; ++ ret = rtw89_mac_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); ++ return ret; ++ } ++ ++ rtw89_btc_ntfy_poweron(rtwdev); ++ ++ /* efuse process */ ++ ++ /* pre-config BB/RF, BB reset/RFC reset */ ++ rtw89_mac_disable_bb_rf(rtwdev); ++ rtw89_mac_enable_bb_rf(rtwdev); ++ rtw89_phy_init_bb_reg(rtwdev); ++ rtw89_phy_init_rf_reg(rtwdev); ++ ++ rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); ++ ++ rtw89_phy_dm_init(rtwdev); ++ ++ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); ++ rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); ++ ++ ret = rtw89_hci_start(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to start hci\n"); ++ return ret; ++ } ++ ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, ++ RTW89_TRACK_WORK_PERIOD); ++ ++ set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); ++ rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); ++ ++ return 0; ++} ++ ++void rtw89_core_stop(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ ++ /* Prvent to stop twice; enter_ips and ops_stop */ ++ if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) ++ return; ++ ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); ++ ++ clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ ++ mutex_unlock(&rtwdev->mutex); ++ ++ cancel_work_sync(&rtwdev->c2h_work); ++ cancel_work_sync(&btc->eapol_notify_work); ++ cancel_work_sync(&btc->arp_notify_work); ++ cancel_work_sync(&btc->dhcp_notify_work); ++ cancel_work_sync(&btc->icmp_notify_work); ++ cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); ++ cancel_delayed_work_sync(&rtwdev->track_work); ++ cancel_delayed_work_sync(&rtwdev->coex_act1_work); ++ cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); ++ cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); ++ cancel_delayed_work_sync(&rtwdev->cfo_track_work); ++ ++ mutex_lock(&rtwdev->mutex); ++ ++ rtw89_btc_ntfy_poweroff(rtwdev); ++ rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); ++ rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); ++ rtw89_hci_stop(rtwdev); ++ rtw89_hci_deinit(rtwdev); ++ rtw89_mac_pwr_off(rtwdev); ++ rtw89_hci_reset(rtwdev); ++} ++ ++int rtw89_core_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ int ret; ++ ++ INIT_LIST_HEAD(&rtwdev->ba_list); ++ INIT_LIST_HEAD(&rtwdev->rtwvifs_list); ++ INIT_LIST_HEAD(&rtwdev->early_h2c_list); ++ INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); ++ INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); ++ INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); ++ INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); ++ INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); ++ INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); ++ INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); ++ INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); ++ rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); ++ spin_lock_init(&rtwdev->ba_lock); ++ mutex_init(&rtwdev->mutex); ++ mutex_init(&rtwdev->rf_mutex); ++ rtwdev->total_sta_assoc = 0; ++ ++ INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); ++ skb_queue_head_init(&rtwdev->c2h_queue); ++ rtw89_core_ppdu_sts_init(rtwdev); ++ rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); ++ ++ rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); ++ rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; ++ ++ INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); ++ INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); ++ INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); ++ INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); ++ ++ ret = rtw89_load_firmware(rtwdev); ++ if (ret) { ++ rtw89_warn(rtwdev, "no firmware loaded\n"); ++ return ret; ++ } ++ rtw89_ser_init(rtwdev); ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_core_init); ++ ++void rtw89_core_deinit(struct rtw89_dev *rtwdev) ++{ ++ rtw89_ser_deinit(rtwdev); ++ rtw89_unload_firmware(rtwdev); ++ rtw89_fw_free_all_early_h2c(rtwdev); ++ ++ destroy_workqueue(rtwdev->txq_wq); ++ mutex_destroy(&rtwdev->rf_mutex); ++ mutex_destroy(&rtwdev->mutex); ++} ++EXPORT_SYMBOL(rtw89_core_deinit); ++ ++static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) ++{ ++ u8 cv; ++ ++ cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); ++ if (cv <= CHIP_CBV) { ++ if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) ++ cv = CHIP_CAV; ++ else ++ cv = CHIP_CBV; ++ } ++ ++ rtwdev->hal.cv = cv; ++} ++ ++static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_partial_init(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_parse_efuse_map(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_parse_phycap_map(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_setup_phycap(rtwdev); ++ if (ret) ++ return ret; ++ ++ rtw89_mac_pwr_off(rtwdev); ++ ++ return 0; ++} ++ ++static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) ++{ ++ rtw89_chip_fem_setup(rtwdev); ++ ++ return 0; ++} ++ ++int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ rtw89_read_chip_ver(rtwdev); ++ ++ ret = rtw89_wait_firmware_completion(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to wait firmware completion\n"); ++ return ret; ++ } ++ ++ ret = rtw89_fw_recognize(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to recognize firmware\n"); ++ return ret; ++ } ++ ++ ret = rtw89_chip_efuse_info_setup(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_chip_board_info_setup(rtwdev); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_chip_info_setup); ++ ++static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ int ret; ++ int tx_headroom = IEEE80211_HT_CTL_LEN; ++ ++ hw->vif_data_size = sizeof(struct rtw89_vif); ++ hw->sta_data_size = sizeof(struct rtw89_sta); ++ hw->txq_data_size = sizeof(struct rtw89_txq); ++ ++ SET_IEEE80211_PERM_ADDR(hw, efuse->addr); ++ ++ hw->extra_tx_headroom = tx_headroom; ++ hw->queues = IEEE80211_NUM_ACS; ++ hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; ++ hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; ++ ++ ieee80211_hw_set(hw, SIGNAL_DBM); ++ ieee80211_hw_set(hw, HAS_RATE_CONTROL); ++ ieee80211_hw_set(hw, MFP_CAPABLE); ++ ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); ++ ieee80211_hw_set(hw, AMPDU_AGGREGATION); ++ ieee80211_hw_set(hw, RX_INCLUDES_FCS); ++ ieee80211_hw_set(hw, TX_AMSDU); ++ ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); ++ ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); ++ ieee80211_hw_set(hw, SUPPORTS_PS); ++ ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); ++ ++ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); ++ hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; ++ hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; ++ ++ hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; ++ ++ wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); ++ ++ ret = rtw89_core_set_supported_band(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to set supported band\n"); ++ return ret; ++ } ++ ++ hw->wiphy->reg_notifier = rtw89_regd_notifier; ++ hw->wiphy->sar_capa = &rtw89_sar_capa; ++ ++ ret = ieee80211_register_hw(hw); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to register hw\n"); ++ goto err; ++ } ++ ++ ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init regd\n"); ++ goto err; ++ } ++ ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) ++{ ++ struct ieee80211_hw *hw = rtwdev->hw; ++ ++ ieee80211_unregister_hw(hw); ++ rtw89_core_clr_supported_band(rtwdev); ++} ++ ++int rtw89_core_register(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_core_register_hw(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to register core hw\n"); ++ return ret; ++ } ++ ++ rtw89_debugfs_init(rtwdev); ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_core_register); ++ ++void rtw89_core_unregister(struct rtw89_dev *rtwdev) ++{ ++ rtw89_core_unregister_hw(rtwdev); ++} ++EXPORT_SYMBOL(rtw89_core_unregister); ++ ++MODULE_AUTHOR("Realtek Corporation"); ++MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +new file mode 100644 +index 000000000000..c2885e4dd882 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -0,0 +1,3384 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_CORE_H__ ++#define __RTW89_CORE_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rtw89_dev; ++ ++extern const struct ieee80211_ops rtw89_ops; ++extern const struct rtw89_chip_info rtw8852a_chip_info; ++ ++#define MASKBYTE0 0xff ++#define MASKBYTE1 0xff00 ++#define MASKBYTE2 0xff0000 ++#define MASKBYTE3 0xff000000 ++#define MASKBYTE4 0xff00000000ULL ++#define MASKHWORD 0xffff0000 ++#define MASKLWORD 0x0000ffff ++#define MASKDWORD 0xffffffff ++#define RFREG_MASK 0xfffff ++#define INV_RF_DATA 0xffffffff ++ ++#define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) ++#define CFO_TRACK_MAX_USER 64 ++#define MAX_RSSI 110 ++#define RSSI_FACTOR 1 ++#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) ++#define RTW89_MAX_HW_PORT_NUM 5 ++ ++#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) ++#define RTW89_HTC_VARIANT_HE 3 ++#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) ++#define RTW89_HTC_VARIANT_HE_CID_OM 1 ++#define RTW89_HTC_VARIANT_HE_CID_CAS 6 ++#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) ++ ++#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) ++enum htc_om_channel_width { ++ HTC_OM_CHANNEL_WIDTH_20 = 0, ++ HTC_OM_CHANNEL_WIDTH_40 = 1, ++ HTC_OM_CHANNEL_WIDTH_80 = 2, ++ HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, ++}; ++#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) ++#define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) ++#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) ++#define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) ++#define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) ++#define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) ++ ++enum rtw89_subband { ++ RTW89_CH_2G = 0, ++ RTW89_CH_5G_BAND_1 = 1, ++ /* RTW89_CH_5G_BAND_2 = 2, unused */ ++ RTW89_CH_5G_BAND_3 = 3, ++ RTW89_CH_5G_BAND_4 = 4, ++ ++ RTW89_SUBBAND_NR, ++}; ++ ++enum rtw89_hci_type { ++ RTW89_HCI_TYPE_PCIE, ++ RTW89_HCI_TYPE_USB, ++ RTW89_HCI_TYPE_SDIO, ++}; ++ ++enum rtw89_core_chip_id { ++ RTL8852A, ++ RTL8852B, ++ RTL8852C, ++}; ++ ++enum rtw89_cv { ++ CHIP_CAV, ++ CHIP_CBV, ++ CHIP_CCV, ++ CHIP_CDV, ++ CHIP_CEV, ++ CHIP_CFV, ++ CHIP_CV_MAX, ++ CHIP_CV_INVALID = CHIP_CV_MAX, ++}; ++ ++enum rtw89_core_tx_type { ++ RTW89_CORE_TX_TYPE_DATA, ++ RTW89_CORE_TX_TYPE_MGMT, ++ RTW89_CORE_TX_TYPE_FWCMD, ++}; ++ ++enum rtw89_core_rx_type { ++ RTW89_CORE_RX_TYPE_WIFI = 0, ++ RTW89_CORE_RX_TYPE_PPDU_STAT = 1, ++ RTW89_CORE_RX_TYPE_CHAN_INFO = 2, ++ RTW89_CORE_RX_TYPE_BB_SCOPE = 3, ++ RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, ++ RTW89_CORE_RX_TYPE_SS2FW = 5, ++ RTW89_CORE_RX_TYPE_TX_REPORT = 6, ++ RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, ++ RTW89_CORE_RX_TYPE_DFS_REPORT = 8, ++ RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, ++ RTW89_CORE_RX_TYPE_C2H = 10, ++ RTW89_CORE_RX_TYPE_CSI = 11, ++ RTW89_CORE_RX_TYPE_CQI = 12, ++}; ++ ++enum rtw89_txq_flags { ++ RTW89_TXQ_F_AMPDU = 0, ++ RTW89_TXQ_F_BLOCK_BA = 1, ++}; ++ ++enum rtw89_net_type { ++ RTW89_NET_TYPE_NO_LINK = 0, ++ RTW89_NET_TYPE_AD_HOC = 1, ++ RTW89_NET_TYPE_INFRA = 2, ++ RTW89_NET_TYPE_AP_MODE = 3, ++}; ++ ++enum rtw89_wifi_role { ++ RTW89_WIFI_ROLE_NONE, ++ RTW89_WIFI_ROLE_STATION, ++ RTW89_WIFI_ROLE_AP, ++ RTW89_WIFI_ROLE_AP_VLAN, ++ RTW89_WIFI_ROLE_ADHOC, ++ RTW89_WIFI_ROLE_ADHOC_MASTER, ++ RTW89_WIFI_ROLE_MESH_POINT, ++ RTW89_WIFI_ROLE_MONITOR, ++ RTW89_WIFI_ROLE_P2P_DEVICE, ++ RTW89_WIFI_ROLE_P2P_CLIENT, ++ RTW89_WIFI_ROLE_P2P_GO, ++ RTW89_WIFI_ROLE_NAN, ++ RTW89_WIFI_ROLE_MLME_MAX ++}; ++ ++enum rtw89_upd_mode { ++ RTW89_VIF_CREATE, ++ RTW89_VIF_REMOVE, ++ RTW89_VIF_TYPE_CHANGE, ++ RTW89_VIF_INFO_CHANGE, ++ RTW89_VIF_CON_DISCONN ++}; ++ ++enum rtw89_self_role { ++ RTW89_SELF_ROLE_CLIENT, ++ RTW89_SELF_ROLE_AP, ++ RTW89_SELF_ROLE_AP_CLIENT ++}; ++ ++enum rtw89_msk_sO_el { ++ RTW89_NO_MSK, ++ RTW89_SMA, ++ RTW89_TMA, ++ RTW89_BSSID ++}; ++ ++enum rtw89_sch_tx_sel { ++ RTW89_SCH_TX_SEL_ALL, ++ RTW89_SCH_TX_SEL_HIQ, ++ RTW89_SCH_TX_SEL_MG0, ++ RTW89_SCH_TX_SEL_MACID, ++}; ++ ++/* RTW89_ADDR_CAM_SEC_NONE : not enabled ++ * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast ++ * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP ++ * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP ++ */ ++enum rtw89_add_cam_sec_mode { ++ RTW89_ADDR_CAM_SEC_NONE = 0, ++ RTW89_ADDR_CAM_SEC_ALL_UNI = 1, ++ RTW89_ADDR_CAM_SEC_NORMAL = 2, ++ RTW89_ADDR_CAM_SEC_4GROUP = 3, ++}; ++ ++enum rtw89_sec_key_type { ++ RTW89_SEC_KEY_TYPE_NONE = 0, ++ RTW89_SEC_KEY_TYPE_WEP40 = 1, ++ RTW89_SEC_KEY_TYPE_WEP104 = 2, ++ RTW89_SEC_KEY_TYPE_TKIP = 3, ++ RTW89_SEC_KEY_TYPE_WAPI = 4, ++ RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, ++ RTW89_SEC_KEY_TYPE_CCMP128 = 6, ++ RTW89_SEC_KEY_TYPE_CCMP256 = 7, ++ RTW89_SEC_KEY_TYPE_GCMP128 = 8, ++ RTW89_SEC_KEY_TYPE_GCMP256 = 9, ++ RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, ++}; ++ ++enum rtw89_port { ++ RTW89_PORT_0 = 0, ++ RTW89_PORT_1 = 1, ++ RTW89_PORT_2 = 2, ++ RTW89_PORT_3 = 3, ++ RTW89_PORT_4 = 4, ++ RTW89_PORT_NUM ++}; ++ ++enum rtw89_band { ++ RTW89_BAND_2G = 0, ++ RTW89_BAND_5G = 1, ++ RTW89_BAND_MAX, ++}; ++ ++enum rtw89_hw_rate { ++ RTW89_HW_RATE_CCK1 = 0x0, ++ RTW89_HW_RATE_CCK2 = 0x1, ++ RTW89_HW_RATE_CCK5_5 = 0x2, ++ RTW89_HW_RATE_CCK11 = 0x3, ++ RTW89_HW_RATE_OFDM6 = 0x4, ++ RTW89_HW_RATE_OFDM9 = 0x5, ++ RTW89_HW_RATE_OFDM12 = 0x6, ++ RTW89_HW_RATE_OFDM18 = 0x7, ++ RTW89_HW_RATE_OFDM24 = 0x8, ++ RTW89_HW_RATE_OFDM36 = 0x9, ++ RTW89_HW_RATE_OFDM48 = 0xA, ++ RTW89_HW_RATE_OFDM54 = 0xB, ++ RTW89_HW_RATE_MCS0 = 0x80, ++ RTW89_HW_RATE_MCS1 = 0x81, ++ RTW89_HW_RATE_MCS2 = 0x82, ++ RTW89_HW_RATE_MCS3 = 0x83, ++ RTW89_HW_RATE_MCS4 = 0x84, ++ RTW89_HW_RATE_MCS5 = 0x85, ++ RTW89_HW_RATE_MCS6 = 0x86, ++ RTW89_HW_RATE_MCS7 = 0x87, ++ RTW89_HW_RATE_MCS8 = 0x88, ++ RTW89_HW_RATE_MCS9 = 0x89, ++ RTW89_HW_RATE_MCS10 = 0x8A, ++ RTW89_HW_RATE_MCS11 = 0x8B, ++ RTW89_HW_RATE_MCS12 = 0x8C, ++ RTW89_HW_RATE_MCS13 = 0x8D, ++ RTW89_HW_RATE_MCS14 = 0x8E, ++ RTW89_HW_RATE_MCS15 = 0x8F, ++ RTW89_HW_RATE_MCS16 = 0x90, ++ RTW89_HW_RATE_MCS17 = 0x91, ++ RTW89_HW_RATE_MCS18 = 0x92, ++ RTW89_HW_RATE_MCS19 = 0x93, ++ RTW89_HW_RATE_MCS20 = 0x94, ++ RTW89_HW_RATE_MCS21 = 0x95, ++ RTW89_HW_RATE_MCS22 = 0x96, ++ RTW89_HW_RATE_MCS23 = 0x97, ++ RTW89_HW_RATE_MCS24 = 0x98, ++ RTW89_HW_RATE_MCS25 = 0x99, ++ RTW89_HW_RATE_MCS26 = 0x9A, ++ RTW89_HW_RATE_MCS27 = 0x9B, ++ RTW89_HW_RATE_MCS28 = 0x9C, ++ RTW89_HW_RATE_MCS29 = 0x9D, ++ RTW89_HW_RATE_MCS30 = 0x9E, ++ RTW89_HW_RATE_MCS31 = 0x9F, ++ RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, ++ RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, ++ RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, ++ RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, ++ RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, ++ RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, ++ RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, ++ RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, ++ RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, ++ RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, ++ RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, ++ RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, ++ RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, ++ RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, ++ RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, ++ RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, ++ RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, ++ RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, ++ RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, ++ RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, ++ RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, ++ RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, ++ RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, ++ RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, ++ RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, ++ RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, ++ RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, ++ RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, ++ RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, ++ RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, ++ RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, ++ RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, ++ RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, ++ RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, ++ RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, ++ RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, ++ RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, ++ RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, ++ RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, ++ RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, ++ RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, ++ RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, ++ RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, ++ RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, ++ RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, ++ RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, ++ RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, ++ RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, ++ RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, ++ RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, ++ RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, ++ RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, ++ RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, ++ RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, ++ RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, ++ RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, ++ RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, ++ RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, ++ RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, ++ RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, ++ RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, ++ RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, ++ RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, ++ RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, ++ RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, ++ RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, ++ RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, ++ RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, ++ RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, ++ RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, ++ RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, ++ RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, ++ RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, ++ RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, ++ RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, ++ RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, ++ RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, ++ RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, ++ RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, ++ RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, ++ RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, ++ RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, ++ RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, ++ RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, ++ RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, ++ RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, ++ RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, ++ RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, ++ RTW89_HW_RATE_NR, ++ ++ RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), ++ RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), ++}; ++ ++/* 2G channels, ++ * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 ++ */ ++#define RTW89_2G_CH_NUM 14 ++ ++/* 5G channels, ++ * 36, 38, 40, 42, 44, 46, 48, 50, ++ * 52, 54, 56, 58, 60, 62, 64, ++ * 100, 102, 104, 106, 108, 110, 112, 114, ++ * 116, 118, 120, 122, 124, 126, 128, 130, ++ * 132, 134, 136, 138, 140, 142, 144, ++ * 149, 151, 153, 155, 157, 159, 161, 163, ++ * 165, 167, 169, 171, 173, 175, 177 ++ */ ++#define RTW89_5G_CH_NUM 53 ++ ++enum rtw89_rate_section { ++ RTW89_RS_CCK, ++ RTW89_RS_OFDM, ++ RTW89_RS_MCS, /* for HT/VHT/HE */ ++ RTW89_RS_HEDCM, ++ RTW89_RS_OFFSET, ++ RTW89_RS_MAX, ++ RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, ++}; ++ ++enum rtw89_rate_max { ++ RTW89_RATE_CCK_MAX = 4, ++ RTW89_RATE_OFDM_MAX = 8, ++ RTW89_RATE_MCS_MAX = 12, ++ RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ ++ RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ ++}; ++ ++enum rtw89_nss { ++ RTW89_NSS_1 = 0, ++ RTW89_NSS_2 = 1, ++ /* HE DCM only support 1ss and 2ss */ ++ RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, ++ RTW89_NSS_3 = 2, ++ RTW89_NSS_4 = 3, ++ RTW89_NSS_MAX, ++}; ++ ++enum rtw89_ntx { ++ RTW89_1TX = 0, ++ RTW89_2TX = 1, ++ RTW89_NTX_NUM, ++}; ++ ++enum rtw89_beamforming_type { ++ RTW89_NONBF = 0, ++ RTW89_BF = 1, ++ RTW89_BF_NUM, ++}; ++ ++enum rtw89_regulation_type { ++ RTW89_WW = 0, ++ RTW89_ETSI = 1, ++ RTW89_FCC = 2, ++ RTW89_MKK = 3, ++ RTW89_NA = 4, ++ RTW89_IC = 5, ++ RTW89_KCC = 6, ++ RTW89_NCC = 7, ++ RTW89_CHILE = 8, ++ RTW89_ACMA = 9, ++ RTW89_MEXICO = 10, ++ RTW89_UKRAINE = 11, ++ RTW89_CN = 12, ++ RTW89_REGD_NUM, ++}; ++ ++extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX]; ++extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX]; ++ ++struct rtw89_txpwr_byrate { ++ s8 cck[RTW89_RATE_CCK_MAX]; ++ s8 ofdm[RTW89_RATE_OFDM_MAX]; ++ s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; ++ s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; ++ s8 offset[RTW89_RATE_OFFSET_MAX]; ++}; ++ ++enum rtw89_bandwidth_section_num { ++ RTW89_BW20_SEC_NUM = 8, ++ RTW89_BW40_SEC_NUM = 4, ++ RTW89_BW80_SEC_NUM = 2, ++}; ++ ++struct rtw89_txpwr_limit { ++ s8 cck_20m[RTW89_BF_NUM]; ++ s8 cck_40m[RTW89_BF_NUM]; ++ s8 ofdm[RTW89_BF_NUM]; ++ s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; ++ s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; ++ s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; ++ s8 mcs_160m[RTW89_BF_NUM]; ++ s8 mcs_40m_0p5[RTW89_BF_NUM]; ++ s8 mcs_40m_2p5[RTW89_BF_NUM]; ++}; ++ ++#define RTW89_RU_SEC_NUM 8 ++ ++struct rtw89_txpwr_limit_ru { ++ s8 ru26[RTW89_RU_SEC_NUM]; ++ s8 ru52[RTW89_RU_SEC_NUM]; ++ s8 ru106[RTW89_RU_SEC_NUM]; ++}; ++ ++struct rtw89_rate_desc { ++ enum rtw89_nss nss; ++ enum rtw89_rate_section rs; ++ u8 idx; ++}; ++ ++#define PHY_STS_HDR_LEN 8 ++#define RF_PATH_MAX 4 ++#define RTW89_MAX_PPDU_CNT 8 ++struct rtw89_rx_phy_ppdu { ++ u8 *buf; ++ u32 len; ++ u8 rssi_avg; ++ s8 rssi[RF_PATH_MAX]; ++ u8 mac_id; ++ bool to_self; ++ bool valid; ++}; ++ ++enum rtw89_mac_idx { ++ RTW89_MAC_0 = 0, ++ RTW89_MAC_1 = 1, ++}; ++ ++enum rtw89_phy_idx { ++ RTW89_PHY_0 = 0, ++ RTW89_PHY_1 = 1, ++ RTW89_PHY_MAX ++}; ++ ++enum rtw89_rf_path { ++ RF_PATH_A = 0, ++ RF_PATH_B = 1, ++ RF_PATH_C = 2, ++ RF_PATH_D = 3, ++ RF_PATH_AB, ++ RF_PATH_AC, ++ RF_PATH_AD, ++ RF_PATH_BC, ++ RF_PATH_BD, ++ RF_PATH_CD, ++ RF_PATH_ABC, ++ RF_PATH_ABD, ++ RF_PATH_ACD, ++ RF_PATH_BCD, ++ RF_PATH_ABCD, ++}; ++ ++enum rtw89_rf_path_bit { ++ RF_A = BIT(0), ++ RF_B = BIT(1), ++ RF_C = BIT(2), ++ RF_D = BIT(3), ++ ++ RF_AB = (RF_A | RF_B), ++ RF_AC = (RF_A | RF_C), ++ RF_AD = (RF_A | RF_D), ++ RF_BC = (RF_B | RF_C), ++ RF_BD = (RF_B | RF_D), ++ RF_CD = (RF_C | RF_D), ++ ++ RF_ABC = (RF_A | RF_B | RF_C), ++ RF_ABD = (RF_A | RF_B | RF_D), ++ RF_ACD = (RF_A | RF_C | RF_D), ++ RF_BCD = (RF_B | RF_C | RF_D), ++ ++ RF_ABCD = (RF_A | RF_B | RF_C | RF_D), ++}; ++ ++enum rtw89_bandwidth { ++ RTW89_CHANNEL_WIDTH_20 = 0, ++ RTW89_CHANNEL_WIDTH_40 = 1, ++ RTW89_CHANNEL_WIDTH_80 = 2, ++ RTW89_CHANNEL_WIDTH_160 = 3, ++ RTW89_CHANNEL_WIDTH_80_80 = 4, ++ RTW89_CHANNEL_WIDTH_5 = 5, ++ RTW89_CHANNEL_WIDTH_10 = 6, ++}; ++ ++enum rtw89_ps_mode { ++ RTW89_PS_MODE_NONE = 0, ++ RTW89_PS_MODE_RFOFF = 1, ++ RTW89_PS_MODE_CLK_GATED = 2, ++ RTW89_PS_MODE_PWR_GATED = 3, ++}; ++ ++#define RTW89_MAX_CHANNEL_WIDTH RTW89_CHANNEL_WIDTH_80 ++#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) ++#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) ++#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) ++ ++enum rtw89_ru_bandwidth { ++ RTW89_RU26 = 0, ++ RTW89_RU52 = 1, ++ RTW89_RU106 = 2, ++ RTW89_RU_NUM, ++}; ++ ++enum rtw89_sc_offset { ++ RTW89_SC_DONT_CARE = 0, ++ RTW89_SC_20_UPPER = 1, ++ RTW89_SC_20_LOWER = 2, ++ RTW89_SC_20_UPMOST = 3, ++ RTW89_SC_20_LOWEST = 4, ++ RTW89_SC_40_UPPER = 9, ++ RTW89_SC_40_LOWER = 10, ++}; ++ ++struct rtw89_channel_params { ++ u8 center_chan; ++ u8 primary_chan; ++ u8 bandwidth; ++ u8 pri_ch_idx; ++ u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1]; ++}; ++ ++struct rtw89_channel_help_params { ++ u16 tx_en; ++}; ++ ++struct rtw89_port_reg { ++ u32 port_cfg; ++ u32 tbtt_prohib; ++ u32 bcn_area; ++ u32 bcn_early; ++ u32 tbtt_early; ++ u32 tbtt_agg; ++ u32 bcn_space; ++ u32 bcn_forcetx; ++ u32 bcn_err_cnt; ++ u32 bcn_err_flag; ++ u32 dtim_ctrl; ++ u32 tbtt_shift; ++ u32 bcn_cnt_tmr; ++ u32 tsftr_l; ++ u32 tsftr_h; ++}; ++ ++struct rtw89_txwd_body { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++ __le32 dword4; ++ __le32 dword5; ++} __packed; ++ ++struct rtw89_txwd_info { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++ __le32 dword4; ++ __le32 dword5; ++} __packed; ++ ++struct rtw89_rx_desc_info { ++ u16 pkt_size; ++ u8 pkt_type; ++ u8 drv_info_size; ++ u8 shift; ++ u8 wl_hd_iv_len; ++ bool long_rxdesc; ++ bool bb_sel; ++ bool mac_info_valid; ++ u16 data_rate; ++ u8 gi_ltf; ++ u8 bw; ++ u32 free_run_cnt; ++ u8 user_id; ++ bool sr_en; ++ u8 ppdu_cnt; ++ u8 ppdu_type; ++ bool icv_err; ++ bool crc32_err; ++ bool hw_dec; ++ bool sw_dec; ++ bool addr1_match; ++ u8 frag; ++ u16 seq; ++ u8 frame_type; ++ u8 rx_pl_id; ++ bool addr_cam_valid; ++ u8 addr_cam_id; ++ u8 sec_cam_id; ++ u8 mac_id; ++ u16 offset; ++ bool ready; ++}; ++ ++struct rtw89_rxdesc_short { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++} __packed; ++ ++struct rtw89_rxdesc_long { ++ __le32 dword0; ++ __le32 dword1; ++ __le32 dword2; ++ __le32 dword3; ++ __le32 dword4; ++ __le32 dword5; ++ __le32 dword6; ++ __le32 dword7; ++} __packed; ++ ++struct rtw89_tx_desc_info { ++ u16 pkt_size; ++ u8 wp_offset; ++ u8 qsel; ++ u8 ch_dma; ++ u8 hdr_llc_len; ++ bool is_bmc; ++ bool en_wd_info; ++ bool wd_page; ++ bool use_rate; ++ bool dis_data_fb; ++ bool tid_indicate; ++ bool agg_en; ++ bool bk; ++ u8 ampdu_density; ++ u8 ampdu_num; ++ bool sec_en; ++ u8 sec_type; ++ u8 sec_cam_idx; ++ u16 data_rate; ++ u16 data_retry_lowest_rate; ++ bool fw_dl; ++ u16 seq; ++ bool a_ctrl_bsr; ++}; ++ ++struct rtw89_core_tx_request { ++ enum rtw89_core_tx_type tx_type; ++ ++ struct sk_buff *skb; ++ struct ieee80211_vif *vif; ++ struct ieee80211_sta *sta; ++ struct rtw89_tx_desc_info desc_info; ++}; ++ ++struct rtw89_txq { ++ struct list_head list; ++ unsigned long flags; ++ int wait_cnt; ++}; ++ ++struct rtw89_mac_ax_gnt { ++ u8 gnt_bt_sw_en; ++ u8 gnt_bt; ++ u8 gnt_wl_sw_en; ++ u8 gnt_wl; ++}; ++ ++#define RTW89_MAC_AX_COEX_GNT_NR 2 ++struct rtw89_mac_ax_coex_gnt { ++ struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; ++}; ++ ++enum rtw89_btc_ncnt { ++ BTC_NCNT_POWER_ON = 0x0, ++ BTC_NCNT_POWER_OFF, ++ BTC_NCNT_INIT_COEX, ++ BTC_NCNT_SCAN_START, ++ BTC_NCNT_SCAN_FINISH, ++ BTC_NCNT_SPECIAL_PACKET, ++ BTC_NCNT_SWITCH_BAND, ++ BTC_NCNT_RFK_TIMEOUT, ++ BTC_NCNT_SHOW_COEX_INFO, ++ BTC_NCNT_ROLE_INFO, ++ BTC_NCNT_CONTROL, ++ BTC_NCNT_RADIO_STATE, ++ BTC_NCNT_CUSTOMERIZE, ++ BTC_NCNT_WL_RFK, ++ BTC_NCNT_WL_STA, ++ BTC_NCNT_FWINFO, ++ BTC_NCNT_TIMER, ++ BTC_NCNT_NUM ++}; ++ ++enum rtw89_btc_btinfo { ++ BTC_BTINFO_L0 = 0, ++ BTC_BTINFO_L1, ++ BTC_BTINFO_L2, ++ BTC_BTINFO_L3, ++ BTC_BTINFO_H0, ++ BTC_BTINFO_H1, ++ BTC_BTINFO_H2, ++ BTC_BTINFO_H3, ++ BTC_BTINFO_MAX ++}; ++ ++enum rtw89_btc_dcnt { ++ BTC_DCNT_RUN = 0x0, ++ BTC_DCNT_CX_RUNINFO, ++ BTC_DCNT_RPT, ++ BTC_DCNT_RPT_FREEZE, ++ BTC_DCNT_CYCLE, ++ BTC_DCNT_CYCLE_FREEZE, ++ BTC_DCNT_W1, ++ BTC_DCNT_W1_FREEZE, ++ BTC_DCNT_B1, ++ BTC_DCNT_B1_FREEZE, ++ BTC_DCNT_TDMA_NONSYNC, ++ BTC_DCNT_SLOT_NONSYNC, ++ BTC_DCNT_BTCNT_FREEZE, ++ BTC_DCNT_WL_SLOT_DRIFT, ++ BTC_DCNT_WL_STA_LAST, ++ BTC_DCNT_NUM, ++}; ++ ++enum rtw89_btc_wl_state_cnt { ++ BTC_WCNT_SCANAP = 0x0, ++ BTC_WCNT_DHCP, ++ BTC_WCNT_EAPOL, ++ BTC_WCNT_ARP, ++ BTC_WCNT_SCBDUPDATE, ++ BTC_WCNT_RFK_REQ, ++ BTC_WCNT_RFK_GO, ++ BTC_WCNT_RFK_REJECT, ++ BTC_WCNT_RFK_TIMEOUT, ++ BTC_WCNT_CH_UPDATE, ++ BTC_WCNT_NUM ++}; ++ ++enum rtw89_btc_bt_state_cnt { ++ BTC_BCNT_RETRY = 0x0, ++ BTC_BCNT_REINIT, ++ BTC_BCNT_REENABLE, ++ BTC_BCNT_SCBDREAD, ++ BTC_BCNT_RELINK, ++ BTC_BCNT_IGNOWL, ++ BTC_BCNT_INQPAG, ++ BTC_BCNT_INQ, ++ BTC_BCNT_PAGE, ++ BTC_BCNT_ROLESW, ++ BTC_BCNT_AFH, ++ BTC_BCNT_INFOUPDATE, ++ BTC_BCNT_INFOSAME, ++ BTC_BCNT_SCBDUPDATE, ++ BTC_BCNT_HIPRI_TX, ++ BTC_BCNT_HIPRI_RX, ++ BTC_BCNT_LOPRI_TX, ++ BTC_BCNT_LOPRI_RX, ++ BTC_BCNT_RATECHG, ++ BTC_BCNT_NUM ++}; ++ ++enum rtw89_btc_bt_profile { ++ BTC_BT_NOPROFILE = 0, ++ BTC_BT_HFP = BIT(0), ++ BTC_BT_HID = BIT(1), ++ BTC_BT_A2DP = BIT(2), ++ BTC_BT_PAN = BIT(3), ++ BTC_PROFILE_MAX = 4, ++}; ++ ++struct rtw89_btc_ant_info { ++ u8 type; /* shared, dedicated */ ++ u8 num; ++ u8 isolation; ++ ++ u8 single_pos: 1;/* Single antenna at S0 or S1 */ ++ u8 diversity: 1; ++}; ++ ++enum rtw89_tfc_dir { ++ RTW89_TFC_UL, ++ RTW89_TFC_DL, ++}; ++ ++struct rtw89_btc_wl_smap { ++ u32 busy: 1; ++ u32 scan: 1; ++ u32 connecting: 1; ++ u32 roaming: 1; ++ u32 _4way: 1; ++ u32 rf_off: 1; ++ u32 lps: 1; ++ u32 ips: 1; ++ u32 init_ok: 1; ++ u32 traffic_dir : 2; ++ u32 rf_off_pre: 1; ++ u32 lps_pre: 1; ++}; ++ ++enum rtw89_tfc_lv { ++ RTW89_TFC_IDLE, ++ RTW89_TFC_ULTRA_LOW, ++ RTW89_TFC_LOW, ++ RTW89_TFC_MID, ++ RTW89_TFC_HIGH, ++}; ++ ++#define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ ++DECLARE_EWMA(tp, 10, 2); ++ ++struct rtw89_traffic_stats { ++ /* units in bytes */ ++ u64 tx_unicast; ++ u64 rx_unicast; ++ u32 tx_avg_len; ++ u32 rx_avg_len; ++ ++ /* count for packets */ ++ u64 tx_cnt; ++ u64 rx_cnt; ++ ++ /* units in Mbps */ ++ u32 tx_throughput; ++ u32 rx_throughput; ++ u32 tx_throughput_raw; ++ u32 rx_throughput_raw; ++ enum rtw89_tfc_lv tx_tfc_lv; ++ enum rtw89_tfc_lv rx_tfc_lv; ++ struct ewma_tp tx_ewma_tp; ++ struct ewma_tp rx_ewma_tp; ++ ++ u16 tx_rate; ++ u16 rx_rate; ++}; ++ ++struct rtw89_btc_statistic { ++ u8 rssi; /* 0%~110% (dBm = rssi -110) */ ++ struct rtw89_traffic_stats traffic; ++}; ++ ++#define BTC_WL_RSSI_THMAX 4 ++ ++struct rtw89_btc_wl_link_info { ++ struct rtw89_btc_statistic stat; ++ enum rtw89_tfc_dir dir; ++ u8 rssi_state[BTC_WL_RSSI_THMAX]; ++ u8 mac_addr[ETH_ALEN]; ++ u8 busy; ++ u8 ch; ++ u8 bw; ++ u8 band; ++ u8 role; ++ u8 pid; ++ u8 phy; ++ u8 dtim_period; ++ u8 mode; ++ ++ u8 mac_id; ++ u8 tx_retry; ++ ++ u32 bcn_period; ++ u32 busy_t; ++ u32 tx_time; ++ u32 client_cnt; ++ u32 rx_rate_drop_cnt; ++ ++ u32 active: 1; ++ u32 noa: 1; ++ u32 client_ps: 1; ++ u32 connected: 2; ++}; ++ ++union rtw89_btc_wl_state_map { ++ u32 val; ++ struct rtw89_btc_wl_smap map; ++}; ++ ++struct rtw89_btc_bt_hfp_desc { ++ u32 exist: 1; ++ u32 type: 2; ++ u32 rsvd: 29; ++}; ++ ++struct rtw89_btc_bt_hid_desc { ++ u32 exist: 1; ++ u32 slot_info: 2; ++ u32 pair_cnt: 2; ++ u32 type: 8; ++ u32 rsvd: 19; ++}; ++ ++struct rtw89_btc_bt_a2dp_desc { ++ u8 exist: 1; ++ u8 exist_last: 1; ++ u8 play_latency: 1; ++ u8 type: 3; ++ u8 active: 1; ++ u8 sink: 1; ++ ++ u8 bitpool; ++ u16 vendor_id; ++ u32 device_name; ++ u32 flush_time; ++}; ++ ++struct rtw89_btc_bt_pan_desc { ++ u32 exist: 1; ++ u32 type: 1; ++ u32 active: 1; ++ u32 rsvd: 29; ++}; ++ ++struct rtw89_btc_bt_rfk_info { ++ u32 run: 1; ++ u32 req: 1; ++ u32 timeout: 1; ++ u32 rsvd: 29; ++}; ++ ++union rtw89_btc_bt_rfk_info_map { ++ u32 val; ++ struct rtw89_btc_bt_rfk_info map; ++}; ++ ++struct rtw89_btc_bt_ver_info { ++ u32 fw_coex; /* match with which coex_ver */ ++ u32 fw; ++}; ++ ++struct rtw89_btc_bool_sta_chg { ++ u32 now: 1; ++ u32 last: 1; ++ u32 remain: 1; ++ u32 srvd: 29; ++}; ++ ++struct rtw89_btc_u8_sta_chg { ++ u8 now; ++ u8 last; ++ u8 remain; ++ u8 rsvd; ++}; ++ ++struct rtw89_btc_wl_scan_info { ++ u8 band[RTW89_PHY_MAX]; ++ u8 phy_map; ++ u8 rsvd; ++}; ++ ++struct rtw89_btc_wl_dbcc_info { ++ u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ ++ u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ ++ u8 real_band[RTW89_PHY_MAX]; ++ u8 role[RTW89_PHY_MAX]; /* role in each phy */ ++}; ++ ++struct rtw89_btc_wl_active_role { ++ u8 connected: 1; ++ u8 pid: 3; ++ u8 phy: 1; ++ u8 noa: 1; ++ u8 band: 2; ++ ++ u8 client_ps: 1; ++ u8 bw: 7; ++ ++ u8 role; ++ u8 ch; ++ ++ u16 tx_lvl; ++ u16 rx_lvl; ++ u16 tx_rate; ++ u16 rx_rate; ++}; ++ ++struct rtw89_btc_wl_role_info_bpos { ++ u16 none: 1; ++ u16 station: 1; ++ u16 ap: 1; ++ u16 vap: 1; ++ u16 adhoc: 1; ++ u16 adhoc_master: 1; ++ u16 mesh: 1; ++ u16 moniter: 1; ++ u16 p2p_device: 1; ++ u16 p2p_gc: 1; ++ u16 p2p_go: 1; ++ u16 nan: 1; ++}; ++ ++union rtw89_btc_wl_role_info_map { ++ u16 val; ++ struct rtw89_btc_wl_role_info_bpos role; ++}; ++ ++struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ ++ u8 connect_cnt; ++ u8 link_mode; ++ union rtw89_btc_wl_role_info_map role_map; ++ struct rtw89_btc_wl_active_role active_role[RTW89_MAX_HW_PORT_NUM]; ++}; ++ ++struct rtw89_btc_wl_ver_info { ++ u32 fw_coex; /* match with which coex_ver */ ++ u32 fw; ++ u32 mac; ++ u32 bb; ++ u32 rf; ++}; ++ ++struct rtw89_btc_wl_afh_info { ++ u8 en; ++ u8 ch; ++ u8 bw; ++ u8 rsvd; ++} __packed; ++ ++struct rtw89_btc_wl_rfk_info { ++ u32 state: 2; ++ u32 path_map: 4; ++ u32 phy_map: 2; ++ u32 band: 2; ++ u32 type: 8; ++ u32 rsvd: 14; ++}; ++ ++struct rtw89_btc_bt_smap { ++ u32 connect: 1; ++ u32 ble_connect: 1; ++ u32 acl_busy: 1; ++ u32 sco_busy: 1; ++ u32 mesh_busy: 1; ++ u32 inq_pag: 1; ++}; ++ ++union rtw89_btc_bt_state_map { ++ u32 val; ++ struct rtw89_btc_bt_smap map; ++}; ++ ++#define BTC_BT_RSSI_THMAX 4 ++#define BTC_BT_AFH_GROUP 12 ++ ++struct rtw89_btc_bt_link_info { ++ struct rtw89_btc_u8_sta_chg profile_cnt; ++ struct rtw89_btc_bool_sta_chg multi_link; ++ struct rtw89_btc_bool_sta_chg relink; ++ struct rtw89_btc_bt_hfp_desc hfp_desc; ++ struct rtw89_btc_bt_hid_desc hid_desc; ++ struct rtw89_btc_bt_a2dp_desc a2dp_desc; ++ struct rtw89_btc_bt_pan_desc pan_desc; ++ union rtw89_btc_bt_state_map status; ++ ++ u8 sut_pwr_level[BTC_PROFILE_MAX]; ++ u8 golden_rx_shift[BTC_PROFILE_MAX]; ++ u8 rssi_state[BTC_BT_RSSI_THMAX]; ++ u8 afh_map[BTC_BT_AFH_GROUP]; ++ ++ u32 role_sw: 1; ++ u32 slave_role: 1; ++ u32 afh_update: 1; ++ u32 cqddr: 1; ++ u32 rssi: 8; ++ u32 tx_3m: 1; ++ u32 rsvd: 19; ++}; ++ ++struct rtw89_btc_3rdcx_info { ++ u8 type; /* 0: none, 1:zigbee, 2:LTE */ ++ u8 hw_coex; ++ u16 rsvd; ++}; ++ ++struct rtw89_btc_dm_emap { ++ u32 init: 1; ++ u32 pta_owner: 1; ++ u32 wl_rfk_timeout: 1; ++ u32 bt_rfk_timeout: 1; ++ ++ u32 wl_fw_hang: 1; ++ u32 offload_mismatch: 1; ++ u32 cycle_hang: 1; ++ u32 w1_hang: 1; ++ ++ u32 b1_hang: 1; ++ u32 tdma_no_sync: 1; ++ u32 wl_slot_drift: 1; ++}; ++ ++union rtw89_btc_dm_error_map { ++ u32 val; ++ struct rtw89_btc_dm_emap map; ++}; ++ ++struct rtw89_btc_rf_para { ++ u32 tx_pwr_freerun; ++ u32 rx_gain_freerun; ++ u32 tx_pwr_perpkt; ++ u32 rx_gain_perpkt; ++}; ++ ++struct rtw89_btc_wl_info { ++ struct rtw89_btc_wl_link_info link_info[RTW89_MAX_HW_PORT_NUM]; ++ struct rtw89_btc_wl_rfk_info rfk_info; ++ struct rtw89_btc_wl_ver_info ver_info; ++ struct rtw89_btc_wl_afh_info afh_info; ++ struct rtw89_btc_wl_role_info role_info; ++ struct rtw89_btc_wl_scan_info scan_info; ++ struct rtw89_btc_wl_dbcc_info dbcc_info; ++ struct rtw89_btc_rf_para rf_para; ++ union rtw89_btc_wl_state_map status; ++ ++ u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; ++ u8 rssi_level; ++ ++ u32 scbd; ++}; ++ ++struct rtw89_btc_module { ++ struct rtw89_btc_ant_info ant; ++ u8 rfe_type; ++ u8 cv; ++ ++ u8 bt_solo: 1; ++ u8 bt_pos: 1; ++ u8 switch_type: 1; ++ ++ u8 rsvd; ++}; ++ ++#define RTW89_BTC_DM_MAXSTEP 30 ++#define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) ++ ++struct rtw89_btc_dm_step { ++ u16 step[RTW89_BTC_DM_MAXSTEP]; ++ u8 step_pos; ++ bool step_ov; ++}; ++ ++struct rtw89_btc_init_info { ++ struct rtw89_btc_module module; ++ u8 wl_guard_ch; ++ ++ u8 wl_only: 1; ++ u8 wl_init_ok: 1; ++ u8 dbcc_en: 1; ++ u8 cx_other: 1; ++ u8 bt_only: 1; ++ ++ u16 rsvd; ++}; ++ ++struct rtw89_btc_wl_tx_limit_para { ++ u16 enable; ++ u32 tx_time; /* unit: us */ ++ u16 tx_retry; ++}; ++ ++struct rtw89_btc_bt_scan_info { ++ u16 win; ++ u16 intvl; ++ u32 enable: 1; ++ u32 interlace: 1; ++ u32 rsvd: 30; ++}; ++ ++enum rtw89_btc_bt_scan_type { ++ BTC_SCAN_INQ = 0, ++ BTC_SCAN_PAGE, ++ BTC_SCAN_BLE, ++ BTC_SCAN_INIT, ++ BTC_SCAN_TV, ++ BTC_SCAN_ADV, ++ BTC_SCAN_MAX1, ++}; ++ ++struct rtw89_btc_bt_info { ++ struct rtw89_btc_bt_link_info link_info; ++ struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; ++ struct rtw89_btc_bt_ver_info ver_info; ++ struct rtw89_btc_bool_sta_chg enable; ++ struct rtw89_btc_bool_sta_chg inq_pag; ++ struct rtw89_btc_rf_para rf_para; ++ union rtw89_btc_bt_rfk_info_map rfk_info; ++ ++ u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ ++ ++ u32 scbd; ++ u32 feature; ++ ++ u32 mbx_avl: 1; ++ u32 whql_test: 1; ++ u32 igno_wl: 1; ++ u32 reinit: 1; ++ u32 ble_scan_en: 1; ++ u32 btg_type: 1; ++ u32 inq: 1; ++ u32 pag: 1; ++ u32 run_patch_code: 1; ++ u32 hi_lna_rx: 1; ++ u32 rsvd: 22; ++}; ++ ++struct rtw89_btc_cx { ++ struct rtw89_btc_wl_info wl; ++ struct rtw89_btc_bt_info bt; ++ struct rtw89_btc_3rdcx_info other; ++ u32 state_map; ++ u32 cnt_bt[BTC_BCNT_NUM]; ++ u32 cnt_wl[BTC_WCNT_NUM]; ++}; ++ ++struct rtw89_btc_fbtc_tdma { ++ u8 type; ++ u8 rxflctrl; ++ u8 txpause; ++ u8 wtgle_n; ++ u8 leak_n; ++ u8 ext_ctrl; ++ u8 rsvd0; ++ u8 rsvd1; ++} __packed; ++ ++#define CXMREG_MAX 30 ++#define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ ++#define BTCRPT_VER 1 ++#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ ++ ++enum rtw89_btc_bt_rfk_counter { ++ BTC_BCNT_RFK_REQ = 0, ++ BTC_BCNT_RFK_GO = 1, ++ BTC_BCNT_RFK_REJECT = 2, ++ BTC_BCNT_RFK_FAIL = 3, ++ BTC_BCNT_RFK_TIMEOUT = 4, ++ BTC_BCNT_RFK_MAX ++}; ++ ++struct rtw89_btc_fbtc_rpt_ctrl { ++ u16 fver; ++ u16 rpt_cnt; /* tmr counters */ ++ u32 wl_fw_coex_ver; /* match which driver's coex version */ ++ u32 wl_fw_cx_offload; ++ u32 wl_fw_ver; ++ u32 rpt_enable; ++ u32 rpt_para; /* ms */ ++ u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ ++ u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ ++ u32 mb_recv_cnt; /* fw recv mailbox counter */ ++ u32 mb_a2dp_empty_cnt; /* a2dp empty count */ ++ u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ ++ u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ ++ u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; ++ u32 c2h_cnt; /* fw send c2h counter */ ++ u32 h2c_cnt; /* fw recv h2c counter */ ++} __packed; ++ ++enum rtw89_fbtc_ext_ctrl_type { ++ CXECTL_OFF = 0x0, /* tdma off */ ++ CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ ++ CXECTL_EXT = 0x2, ++ CXECTL_MAX ++}; ++ ++union rtw89_btc_fbtc_rxflct { ++ u8 val; ++ u8 type: 3; ++ u8 tgln_n: 5; ++}; ++ ++enum rtw89_btc_cxst_state { ++ CXST_OFF = 0x0, ++ CXST_B2W = 0x1, ++ CXST_W1 = 0x2, ++ CXST_W2 = 0x3, ++ CXST_W2B = 0x4, ++ CXST_B1 = 0x5, ++ CXST_B2 = 0x6, ++ CXST_B3 = 0x7, ++ CXST_B4 = 0x8, ++ CXST_LK = 0x9, ++ CXST_BLK = 0xa, ++ CXST_E2G = 0xb, ++ CXST_E5G = 0xc, ++ CXST_EBT = 0xd, ++ CXST_ENULL = 0xe, ++ CXST_WLK = 0xf, ++ CXST_W1FDD = 0x10, ++ CXST_B1FDD = 0x11, ++ CXST_MAX = 0x12, ++}; ++ ++enum { ++ CXBCN_ALL = 0x0, ++ CXBCN_ALL_OK, ++ CXBCN_BT_SLOT, ++ CXBCN_BT_OK, ++ CXBCN_MAX ++}; ++ ++enum btc_slot_type { ++ SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ ++ SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ ++ CXSTYPE_NUM, ++}; ++ ++enum { /* TIME */ ++ CXT_BT = 0x0, ++ CXT_WL = 0x1, ++ CXT_MAX ++}; ++ ++enum { /* TIME-A2DP */ ++ CXT_FLCTRL_OFF = 0x0, ++ CXT_FLCTRL_ON = 0x1, ++ CXT_FLCTRL_MAX ++}; ++ ++enum { /* STEP TYPE */ ++ CXSTEP_NONE = 0x0, ++ CXSTEP_EVNT = 0x1, ++ CXSTEP_SLOT = 0x2, ++ CXSTEP_MAX, ++}; ++ ++#define FCXGPIODBG_VER 1 ++#define BTC_DBG_MAX1 32 ++struct rtw89_btc_fbtc_gpio_dbg { ++ u8 fver; ++ u8 rsvd; ++ u16 rsvd2; ++ u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ ++ u32 pre_state; /* the debug signal is 1 or 0 */ ++ u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ ++} __packed; ++ ++#define FCXMREG_VER 1 ++struct rtw89_btc_fbtc_mreg_val { ++ u8 fver; ++ u8 reg_num; ++ __le16 rsvd; ++ __le32 mreg_val[CXMREG_MAX]; ++} __packed; ++ ++#define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ ++ { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ ++ .offset = cpu_to_le32(__offset), } ++ ++struct rtw89_btc_fbtc_mreg { ++ __le16 type; ++ __le16 bytes; ++ __le32 offset; ++} __packed; ++ ++struct rtw89_btc_fbtc_slot { ++ __le16 dur; ++ __le32 cxtbl; ++ __le16 cxtype; ++} __packed; ++ ++#define FCXSLOTS_VER 1 ++struct rtw89_btc_fbtc_slots { ++ u8 fver; ++ u8 tbl_num; ++ __le16 rsvd; ++ __le32 update_map; ++ struct rtw89_btc_fbtc_slot slot[CXST_MAX]; ++} __packed; ++ ++#define FCXSTEP_VER 2 ++struct rtw89_btc_fbtc_step { ++ u8 type; ++ u8 val; ++ __le16 difft; ++} __packed; ++ ++struct rtw89_btc_fbtc_steps { ++ u8 fver; ++ u8 rsvd; ++ __le16 cnt; ++ __le16 pos_old; ++ __le16 pos_new; ++ struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; ++} __packed; ++ ++#define FCXCYSTA_VER 2 ++struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ ++ u8 fver; ++ u8 rsvd; ++ __le16 cycles; /* total cycle number */ ++ __le16 cycles_a2dp[CXT_FLCTRL_MAX]; ++ __le16 a2dpept; /* a2dp empty cnt */ ++ __le16 a2dpeptto; /* a2dp empty timeout cnt*/ ++ __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ ++ __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ ++ __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ ++ __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ ++ __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ ++ __le16 tavg_a2dpept; /* avg a2dp empty time */ ++ __le16 tmax_a2dpept; /* max a2dp empty time */ ++ __le16 tavg_lk; /* avg leak-slot time */ ++ __le16 tmax_lk; /* max leak-slot time */ ++ __le32 slot_cnt[CXST_MAX]; /* slot count */ ++ __le32 bcn_cnt[CXBCN_MAX]; ++ __le32 leakrx_cnt; /* the rximr occur at leak slot */ ++ __le32 collision_cnt; /* counter for event/timer occur at same time */ ++ __le32 skip_cnt; ++ __le32 exception; ++ __le32 except_cnt; ++ __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; ++} __packed; ++ ++#define FCXNULLSTA_VER 1 ++struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ ++ __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ ++ __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ ++} __packed; ++ ++#define FCX_BTVER_VER 1 ++struct rtw89_btc_fbtc_btver { ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ ++ __le32 fw_ver; ++ __le32 feature; ++} __packed; ++ ++#define FCX_BTSCAN_VER 1 ++struct rtw89_btc_fbtc_btscan { ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ u8 scan[6]; ++} __packed; ++ ++#define FCX_BTAFH_VER 1 ++struct rtw89_btc_fbtc_btafh { ++ u8 fver; ++ u8 rsvd; ++ __le16 rsvd2; ++ u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ ++ u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ ++ u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ ++} __packed; ++ ++#define FCX_BTDEVINFO_VER 1 ++struct rtw89_btc_fbtc_btdevinfo { ++ u8 fver; ++ u8 rsvd; ++ __le16 vendor_id; ++ __le32 dev_name; /* only 24 bits valid */ ++ __le32 flush_time; ++} __packed; ++ ++#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) ++struct rtw89_btc_rf_trx_para { ++ u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ ++ u32 wl_rx_gain; /* rx gain table index (TBD.) */ ++ u8 bt_tx_power; /* decrease Tx power (dB) */ ++ u8 bt_rx_gain; /* LNA constrain level */ ++}; ++ ++struct rtw89_btc_dm { ++ struct rtw89_btc_fbtc_slot slot[CXST_MAX]; ++ struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; ++ struct rtw89_btc_fbtc_tdma tdma; ++ struct rtw89_btc_fbtc_tdma tdma_now; ++ struct rtw89_mac_ax_coex_gnt gnt; ++ struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ ++ struct rtw89_btc_rf_trx_para rf_trx_para; ++ struct rtw89_btc_wl_tx_limit_para wl_tx_limit; ++ struct rtw89_btc_dm_step dm_step; ++ union rtw89_btc_dm_error_map error; ++ u32 cnt_dm[BTC_DCNT_NUM]; ++ u32 cnt_notify[BTC_NCNT_NUM]; ++ ++ u32 update_slot_map; ++ u32 set_ant_path; ++ ++ u32 wl_only: 1; ++ u32 wl_fw_cx_offload: 1; ++ u32 freerun: 1; ++ u32 wl_ps_ctrl: 2; ++ u32 wl_mimo_ps: 1; ++ u32 leak_ap: 1; ++ u32 noisy_level: 3; ++ u32 coex_info_map: 8; ++ u32 bt_only: 1; ++ u32 wl_btg_rx: 1; ++ u32 trx_para_level: 8; ++ u32 wl_stb_chg: 1; ++ u32 rsvd: 3; ++ ++ u16 slot_dur[CXST_MAX]; ++ ++ u8 run_reason; ++ u8 run_action; ++}; ++ ++struct rtw89_btc_ctrl { ++ u32 manual: 1; ++ u32 igno_bt: 1; ++ u32 always_freerun: 1; ++ u32 trace_step: 16; ++ u32 rsvd: 12; ++}; ++ ++struct rtw89_btc_dbg { ++ /* cmd "rb" */ ++ bool rb_done; ++ u32 rb_val; ++}; ++ ++#define FCXTDMA_VER 1 ++ ++enum rtw89_btc_btf_fw_event { ++ BTF_EVNT_RPT = 0, ++ BTF_EVNT_BT_INFO = 1, ++ BTF_EVNT_BT_SCBD = 2, ++ BTF_EVNT_BT_REG = 3, ++ BTF_EVNT_CX_RUNINFO = 4, ++ BTF_EVNT_BT_PSD = 5, ++ BTF_EVNT_BUF_OVERFLOW, ++ BTF_EVNT_C2H_LOOPBACK, ++ BTF_EVNT_MAX, ++}; ++ ++enum btf_fw_event_report { ++ BTC_RPT_TYPE_CTRL = 0x0, ++ BTC_RPT_TYPE_TDMA, ++ BTC_RPT_TYPE_SLOT, ++ BTC_RPT_TYPE_CYSTA, ++ BTC_RPT_TYPE_STEP, ++ BTC_RPT_TYPE_NULLSTA, ++ BTC_RPT_TYPE_MREG, ++ BTC_RPT_TYPE_GPIO_DBG, ++ BTC_RPT_TYPE_BT_VER, ++ BTC_RPT_TYPE_BT_SCAN, ++ BTC_RPT_TYPE_BT_AFH, ++ BTC_RPT_TYPE_BT_DEVICE, ++ BTC_RPT_TYPE_TEST, ++ BTC_RPT_TYPE_MAX = 31 ++}; ++ ++enum rtw_btc_btf_reg_type { ++ REG_MAC = 0x0, ++ REG_BB = 0x1, ++ REG_RF = 0x2, ++ REG_BT_RF = 0x3, ++ REG_BT_MODEM = 0x4, ++ REG_BT_BLUEWIZE = 0x5, ++ REG_BT_VENDOR = 0x6, ++ REG_BT_LE = 0x7, ++ REG_MAX_TYPE, ++}; ++ ++struct rtw89_btc_rpt_cmn_info { ++ u32 rx_cnt; ++ u32 rx_len; ++ u32 req_len; /* expected rsp len */ ++ u8 req_fver; /* expected rsp fver */ ++ u8 rsp_fver; /* fver from fw */ ++ u8 valid; ++} __packed; ++ ++struct rtw89_btc_report_ctrl_state { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_tdma { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_slots { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_slots finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_cysta { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_cysta finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_step { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_steps finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_nullsta { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_mreg { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_gpio_dbg { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btver { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btver finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btscan { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btafh { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ ++}; ++ ++struct rtw89_btc_rpt_fbtc_btdev { ++ struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ ++ struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ ++}; ++ ++enum rtw89_btc_btfre_type { ++ BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ ++ BTFRE_UNDEF_TYPE, ++ BTFRE_EXCEPTION, ++ BTFRE_MAX, ++}; ++ ++struct rtw89_btc_btf_fwinfo { ++ u32 cnt_c2h; ++ u32 cnt_h2c; ++ u32 cnt_h2c_fail; ++ u32 event[BTF_EVNT_MAX]; ++ ++ u32 err[BTFRE_MAX]; ++ u32 len_mismch; ++ u32 fver_mismch; ++ u32 rpt_en_map; ++ ++ struct rtw89_btc_report_ctrl_state rpt_ctrl; ++ struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; ++ struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; ++ struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; ++ struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; ++ struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; ++ struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; ++ struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; ++ struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; ++ struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; ++ struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; ++ struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; ++}; ++ ++#define RTW89_BTC_POLICY_MAXLEN 512 ++ ++struct rtw89_btc { ++ struct rtw89_btc_cx cx; ++ struct rtw89_btc_dm dm; ++ struct rtw89_btc_ctrl ctrl; ++ struct rtw89_btc_module mdinfo; ++ struct rtw89_btc_btf_fwinfo fwinfo; ++ struct rtw89_btc_dbg dbg; ++ ++ struct work_struct eapol_notify_work; ++ struct work_struct arp_notify_work; ++ struct work_struct dhcp_notify_work; ++ struct work_struct icmp_notify_work; ++ ++ u32 bt_req_len; ++ ++ u8 policy[RTW89_BTC_POLICY_MAXLEN]; ++ u16 policy_len; ++ u16 policy_type; ++ bool bt_req_en; ++ bool update_policy_force; ++ bool lps; ++}; ++ ++enum rtw89_ra_mode { ++ RTW89_RA_MODE_CCK = BIT(0), ++ RTW89_RA_MODE_OFDM = BIT(1), ++ RTW89_RA_MODE_HT = BIT(2), ++ RTW89_RA_MODE_VHT = BIT(3), ++ RTW89_RA_MODE_HE = BIT(4), ++}; ++ ++enum rtw89_ra_report_mode { ++ RTW89_RA_RPT_MODE_LEGACY, ++ RTW89_RA_RPT_MODE_HT, ++ RTW89_RA_RPT_MODE_VHT, ++ RTW89_RA_RPT_MODE_HE, ++}; ++ ++enum rtw89_dig_noisy_level { ++ RTW89_DIG_NOISY_LEVEL0 = -1, ++ RTW89_DIG_NOISY_LEVEL1 = 0, ++ RTW89_DIG_NOISY_LEVEL2 = 1, ++ RTW89_DIG_NOISY_LEVEL3 = 2, ++ RTW89_DIG_NOISY_LEVEL_MAX = 3, ++}; ++ ++enum rtw89_gi_ltf { ++ RTW89_GILTF_LGI_4XHE32 = 0, ++ RTW89_GILTF_SGI_4XHE08 = 1, ++ RTW89_GILTF_2XHE16 = 2, ++ RTW89_GILTF_2XHE08 = 3, ++ RTW89_GILTF_1XHE16 = 4, ++ RTW89_GILTF_1XHE08 = 5, ++ RTW89_GILTF_MAX ++}; ++ ++enum rtw89_rx_frame_type { ++ RTW89_RX_TYPE_MGNT = 0, ++ RTW89_RX_TYPE_CTRL = 1, ++ RTW89_RX_TYPE_DATA = 2, ++ RTW89_RX_TYPE_RSVD = 3, ++}; ++ ++struct rtw89_ra_info { ++ u8 is_dis_ra:1; ++ /* Bit0 : CCK ++ * Bit1 : OFDM ++ * Bit2 : HT ++ * Bit3 : VHT ++ * Bit4 : HE ++ */ ++ u8 mode_ctrl:5; ++ u8 bw_cap:2; ++ u8 macid; ++ u8 dcm_cap:1; ++ u8 er_cap:1; ++ u8 init_rate_lv:2; ++ u8 upd_all:1; ++ u8 en_sgi:1; ++ u8 ldpc_cap:1; ++ u8 stbc_cap:1; ++ u8 ss_num:3; ++ u8 giltf:3; ++ u8 upd_bw_nss_mask:1; ++ u8 upd_mask:1; ++ u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ ++ /* BFee CSI */ ++ u8 band_num; ++ u8 ra_csi_rate_en:1; ++ u8 fixed_csi_rate_en:1; ++ u8 cr_tbl_sel:1; ++ u8 rsvd2:5; ++ u8 csi_mcs_ss_idx; ++ u8 csi_mode:2; ++ u8 csi_gi_ltf:3; ++ u8 csi_bw:3; ++}; ++ ++#define RTW89_PPDU_MAX_USR 4 ++#define RTW89_PPDU_MAC_INFO_USR_SIZE 4 ++#define RTW89_PPDU_MAC_INFO_SIZE 8 ++#define RTW89_PPDU_MAC_RX_CNT_SIZE 96 ++ ++#define RTW89_MAX_RX_AGG_NUM 64 ++#define RTW89_MAX_TX_AGG_NUM 128 ++ ++struct rtw89_ampdu_params { ++ u16 agg_num; ++ bool amsdu; ++}; ++ ++struct rtw89_ra_report { ++ struct rate_info txrate; ++ u32 bit_rate; ++ u16 hw_rate; ++}; ++ ++DECLARE_EWMA(rssi, 10, 16); ++ ++struct rtw89_sta { ++ u8 mac_id; ++ bool disassoc; ++ struct rtw89_vif *rtwvif; ++ struct rtw89_ra_info ra; ++ struct rtw89_ra_report ra_report; ++ int max_agg_wait; ++ u8 prev_rssi; ++ struct ewma_rssi avg_rssi; ++ struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; ++ struct ieee80211_rx_status rx_status; ++ u16 rx_hw_rate; ++ __le32 htc_template; ++ ++ bool use_cfg_mask; ++ struct cfg80211_bitrate_mask mask; ++ ++ bool cctl_tx_time; ++ u32 ampdu_max_time:4; ++ bool cctl_tx_retry_limit; ++ u32 data_tx_cnt_lmt:6; ++}; ++ ++#define RTW89_MAX_ADDR_CAM_NUM 128 ++#define RTW89_MAX_BSSID_CAM_NUM 20 ++#define RTW89_MAX_SEC_CAM_NUM 128 ++#define RTW89_SEC_CAM_IN_ADDR_CAM 7 ++ ++struct rtw89_addr_cam_entry { ++ u8 addr_cam_idx; ++ u8 offset; ++ u8 len; ++ u8 valid : 1; ++ u8 addr_mask : 6; ++ u8 wapi : 1; ++ u8 mask_sel : 2; ++ u8 bssid_cam_idx: 6; ++ u8 tma[ETH_ALEN]; ++ u8 sma[ETH_ALEN]; ++ ++ u8 sec_ent_mode; ++ DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); ++ u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; ++ u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; ++ struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; ++}; ++ ++struct rtw89_bssid_cam_entry { ++ u8 bssid[ETH_ALEN]; ++ u8 phy_idx; ++ u8 bssid_cam_idx; ++ u8 offset; ++ u8 len; ++ u8 valid : 1; ++ u8 num; ++}; ++ ++struct rtw89_sec_cam_entry { ++ u8 sec_cam_idx; ++ u8 offset; ++ u8 len; ++ u8 type : 4; ++ u8 ext_key : 1; ++ u8 spp_mode : 1; ++ /* 256 bits */ ++ u8 key[32]; ++}; ++ ++struct rtw89_efuse { ++ bool valid; ++ u8 xtal_cap; ++ u8 addr[ETH_ALEN]; ++ u8 rfe_type; ++ char country_code[2]; ++}; ++ ++struct rtw89_phy_rate_pattern { ++ u64 ra_mask; ++ u16 rate; ++ u8 ra_mode; ++ bool enable; ++}; ++ ++struct rtw89_vif { ++ struct list_head list; ++ u8 mac_id; ++ u8 port; ++ u8 mac_addr[ETH_ALEN]; ++ u8 bssid[ETH_ALEN]; ++ u8 phy_idx; ++ u8 mac_idx; ++ u8 net_type; ++ u8 wifi_role; ++ u8 self_role; ++ u8 wmm; ++ u8 bcn_hit_cond; ++ u8 hit_rule; ++ bool trigger; ++ bool lsig_txop; ++ u8 tgt_ind; ++ u8 frm_tgt_ind; ++ bool wowlan_pattern; ++ bool wowlan_uc; ++ bool wowlan_magic; ++ bool is_hesta; ++ bool last_a_ctrl; ++ union { ++ struct { ++ struct ieee80211_sta *ap; ++ } mgd; ++ struct { ++ struct list_head sta_list; ++ } ap; ++ }; ++ struct rtw89_addr_cam_entry addr_cam; ++ struct rtw89_bssid_cam_entry bssid_cam; ++ struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; ++ struct rtw89_traffic_stats stats; ++ struct rtw89_phy_rate_pattern rate_pattern; ++}; ++ ++enum rtw89_lv1_rcvy_step { ++ RTW89_LV1_RCVY_STEP_1, ++ RTW89_LV1_RCVY_STEP_2, ++}; ++ ++struct rtw89_hci_ops { ++ int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); ++ void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); ++ void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); ++ void (*reset)(struct rtw89_dev *rtwdev); ++ int (*start)(struct rtw89_dev *rtwdev); ++ void (*stop)(struct rtw89_dev *rtwdev); ++ void (*recalc_int_mit)(struct rtw89_dev *rtwdev); ++ ++ u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); ++ u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); ++ u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); ++ void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); ++ void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); ++ void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); ++ ++ int (*mac_pre_init)(struct rtw89_dev *rtwdev); ++ int (*mac_post_init)(struct rtw89_dev *rtwdev); ++ int (*deinit)(struct rtw89_dev *rtwdev); ++ ++ u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); ++ int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); ++ void (*dump_err_status)(struct rtw89_dev *rtwdev); ++ int (*napi_poll)(struct napi_struct *napi, int budget); ++}; ++ ++struct rtw89_hci_info { ++ const struct rtw89_hci_ops *ops; ++ enum rtw89_hci_type type; ++ u32 rpwm_addr; ++ u32 cpwm_addr; ++}; ++ ++struct rtw89_chip_ops { ++ void (*bb_reset)(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx); ++ void (*bb_sethw)(struct rtw89_dev *rtwdev); ++ u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask); ++ bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data); ++ void (*set_channel)(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param); ++ void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, ++ struct rtw89_channel_help_params *p); ++ int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); ++ int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); ++ void (*fem_setup)(struct rtw89_dev *rtwdev); ++ void (*rfk_init)(struct rtw89_dev *rtwdev); ++ void (*rfk_channel)(struct rtw89_dev *rtwdev); ++ void (*rfk_band_changed)(struct rtw89_dev *rtwdev); ++ void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); ++ void (*rfk_track)(struct rtw89_dev *rtwdev); ++ void (*power_trim)(struct rtw89_dev *rtwdev); ++ void (*set_txpwr)(struct rtw89_dev *rtwdev); ++ void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev); ++ int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); ++ u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); ++ void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); ++ void (*query_ppdu)(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status); ++ void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); ++ void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, ++ s16 pw_ofst, enum rtw89_mac_idx mac_idx); ++ ++ void (*btc_set_rfe)(struct rtw89_dev *rtwdev); ++ void (*btc_init_cfg)(struct rtw89_dev *rtwdev); ++ void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); ++ void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); ++ s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); ++ void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); ++ void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); ++ void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); ++}; ++ ++enum rtw89_dma_ch { ++ RTW89_DMA_ACH0 = 0, ++ RTW89_DMA_ACH1 = 1, ++ RTW89_DMA_ACH2 = 2, ++ RTW89_DMA_ACH3 = 3, ++ RTW89_DMA_ACH4 = 4, ++ RTW89_DMA_ACH5 = 5, ++ RTW89_DMA_ACH6 = 6, ++ RTW89_DMA_ACH7 = 7, ++ RTW89_DMA_B0MG = 8, ++ RTW89_DMA_B0HI = 9, ++ RTW89_DMA_B1MG = 10, ++ RTW89_DMA_B1HI = 11, ++ RTW89_DMA_H2C = 12, ++ RTW89_DMA_CH_NUM = 13 ++}; ++ ++enum rtw89_qta_mode { ++ RTW89_QTA_SCC, ++ RTW89_QTA_DLFW, ++ ++ /* keep last */ ++ RTW89_QTA_INVALID, ++}; ++ ++struct rtw89_hfc_ch_cfg { ++ u16 min; ++ u16 max; ++#define grp_0 0 ++#define grp_1 1 ++#define grp_num 2 ++ u8 grp; ++}; ++ ++struct rtw89_hfc_ch_info { ++ u16 aval; ++ u16 used; ++}; ++ ++struct rtw89_hfc_pub_cfg { ++ u16 grp0; ++ u16 grp1; ++ u16 pub_max; ++ u16 wp_thrd; ++}; ++ ++struct rtw89_hfc_pub_info { ++ u16 g0_used; ++ u16 g1_used; ++ u16 g0_aval; ++ u16 g1_aval; ++ u16 pub_aval; ++ u16 wp_aval; ++}; ++ ++struct rtw89_hfc_prec_cfg { ++ u16 ch011_prec; ++ u16 h2c_prec; ++ u16 wp_ch07_prec; ++ u16 wp_ch811_prec; ++ u8 ch011_full_cond; ++ u8 h2c_full_cond; ++ u8 wp_ch07_full_cond; ++ u8 wp_ch811_full_cond; ++}; ++ ++struct rtw89_hfc_param { ++ bool en; ++ bool h2c_en; ++ u8 mode; ++ const struct rtw89_hfc_ch_cfg *ch_cfg; ++ struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; ++ struct rtw89_hfc_pub_cfg pub_cfg; ++ struct rtw89_hfc_pub_info pub_info; ++ struct rtw89_hfc_prec_cfg prec_cfg; ++}; ++ ++struct rtw89_hfc_param_ini { ++ const struct rtw89_hfc_ch_cfg *ch_cfg; ++ const struct rtw89_hfc_pub_cfg *pub_cfg; ++ const struct rtw89_hfc_prec_cfg *prec_cfg; ++ u8 mode; ++}; ++ ++struct rtw89_dle_size { ++ u16 pge_size; ++ u16 lnk_pge_num; ++ u16 unlnk_pge_num; ++}; ++ ++struct rtw89_wde_quota { ++ u16 hif; ++ u16 wcpu; ++ u16 pkt_in; ++ u16 cpu_io; ++}; ++ ++struct rtw89_ple_quota { ++ u16 cma0_tx; ++ u16 cma1_tx; ++ u16 c2h; ++ u16 h2c; ++ u16 wcpu; ++ u16 mpdu_proc; ++ u16 cma0_dma; ++ u16 cma1_dma; ++ u16 bb_rpt; ++ u16 wd_rel; ++ u16 cpu_io; ++}; ++ ++struct rtw89_dle_mem { ++ enum rtw89_qta_mode mode; ++ const struct rtw89_dle_size *wde_size; ++ const struct rtw89_dle_size *ple_size; ++ const struct rtw89_wde_quota *wde_min_qt; ++ const struct rtw89_wde_quota *wde_max_qt; ++ const struct rtw89_ple_quota *ple_min_qt; ++ const struct rtw89_ple_quota *ple_max_qt; ++}; ++ ++struct rtw89_reg_def { ++ u32 addr; ++ u32 mask; ++}; ++ ++struct rtw89_reg2_def { ++ u32 addr; ++ u32 data; ++}; ++ ++struct rtw89_reg3_def { ++ u32 addr; ++ u32 mask; ++ u32 data; ++}; ++ ++struct rtw89_reg5_def { ++ u8 flag; /* recognized by parsers */ ++ u8 path; ++ u32 addr; ++ u32 mask; ++ u32 data; ++}; ++ ++struct rtw89_phy_table { ++ const struct rtw89_reg2_def *regs; ++ u32 n_regs; ++ enum rtw89_rf_path rf_path; ++}; ++ ++struct rtw89_txpwr_table { ++ const void *data; ++ u32 size; ++ void (*load)(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl); ++}; ++ ++struct rtw89_chip_info { ++ enum rtw89_core_chip_id chip_id; ++ const struct rtw89_chip_ops *ops; ++ const char *fw_name; ++ u32 fifo_size; ++ u16 max_amsdu_limit; ++ bool dis_2g_40m_ul_ofdma; ++ const struct rtw89_hfc_param_ini *hfc_param_ini; ++ const struct rtw89_dle_mem *dle_mem; ++ u32 rf_base_addr[2]; ++ u8 rf_path_num; ++ u8 tx_nss; ++ u8 rx_nss; ++ u8 acam_num; ++ u8 bcam_num; ++ u8 scam_num; ++ ++ u8 sec_ctrl_efuse_size; ++ u32 physical_efuse_size; ++ u32 logical_efuse_size; ++ u32 limit_efuse_size; ++ u32 phycap_addr; ++ u32 phycap_size; ++ ++ const struct rtw89_pwr_cfg * const *pwr_on_seq; ++ const struct rtw89_pwr_cfg * const *pwr_off_seq; ++ const struct rtw89_phy_table *bb_table; ++ const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; ++ const struct rtw89_phy_table *nctl_table; ++ const struct rtw89_txpwr_table *byr_table; ++ const struct rtw89_phy_dig_gain_table *dig_table; ++ const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++ const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++ const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++ const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++ ++ u8 txpwr_factor_rf; ++ u8 txpwr_factor_mac; ++ ++ u32 para_ver; ++ u32 wlcx_desired; ++ u8 btcx_desired; ++ u8 scbd; ++ u8 mailbox; ++ ++ u8 afh_guard_ch; ++ const u8 *wl_rssi_thres; ++ const u8 *bt_rssi_thres; ++ u8 rssi_tol; ++ ++ u8 mon_reg_num; ++ const struct rtw89_btc_fbtc_mreg *mon_reg; ++ u8 rf_para_ulink_num; ++ const struct rtw89_btc_rf_trx_para *rf_para_ulink; ++ u8 rf_para_dlink_num; ++ const struct rtw89_btc_rf_trx_para *rf_para_dlink; ++ u8 ps_mode_supported; ++}; ++ ++enum rtw89_hcifc_mode { ++ RTW89_HCIFC_POH = 0, ++ RTW89_HCIFC_STF = 1, ++ RTW89_HCIFC_SDIO = 2, ++ ++ /* keep last */ ++ RTW89_HCIFC_MODE_INVALID, ++}; ++ ++struct rtw89_dle_info { ++ enum rtw89_qta_mode qta_mode; ++ u16 wde_pg_size; ++ u16 ple_pg_size; ++ u16 c0_rx_qta; ++ u16 c1_rx_qta; ++}; ++ ++enum rtw89_host_rpr_mode { ++ RTW89_RPR_MODE_POH = 0, ++ RTW89_RPR_MODE_STF ++}; ++ ++struct rtw89_mac_info { ++ struct rtw89_dle_info dle_info; ++ struct rtw89_hfc_param hfc_param; ++ enum rtw89_qta_mode qta_mode; ++ u8 rpwm_seq_num; ++ u8 cpwm_seq_num; ++}; ++ ++enum rtw89_fw_type { ++ RTW89_FW_NORMAL = 1, ++ RTW89_FW_WOWLAN = 3, ++}; ++ ++struct rtw89_fw_suit { ++ const u8 *data; ++ u32 size; ++ u8 major_ver; ++ u8 minor_ver; ++ u8 sub_ver; ++ u8 sub_idex; ++ u16 build_year; ++ u16 build_mon; ++ u16 build_date; ++ u16 build_hour; ++ u16 build_min; ++ u8 cmd_ver; ++}; ++ ++#define RTW89_FW_VER_CODE(major, minor, sub, idx) \ ++ (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) ++#define RTW89_FW_SUIT_VER_CODE(s) \ ++ RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) ++ ++struct rtw89_fw_info { ++ const struct firmware *firmware; ++ struct rtw89_dev *rtwdev; ++ struct completion completion; ++ u8 h2c_seq; ++ u8 rec_seq; ++ struct rtw89_fw_suit normal; ++ struct rtw89_fw_suit wowlan; ++ bool fw_log_enable; ++ bool old_ht_ra_format; ++}; ++ ++struct rtw89_cam_info { ++ DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); ++ DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); ++ DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); ++}; ++ ++enum rtw89_sar_sources { ++ RTW89_SAR_SOURCE_NONE, ++ RTW89_SAR_SOURCE_COMMON, ++ ++ RTW89_SAR_SOURCE_NR, ++}; ++ ++struct rtw89_sar_cfg_common { ++ bool set[RTW89_SUBBAND_NR]; ++ s32 cfg[RTW89_SUBBAND_NR]; ++}; ++ ++struct rtw89_sar_info { ++ /* used to decide how to acces SAR cfg union */ ++ enum rtw89_sar_sources src; ++ ++ /* reserved for different knids of SAR cfg struct. ++ * supposed that a single cfg struct cannot handle various SAR sources. ++ */ ++ union { ++ struct rtw89_sar_cfg_common cfg_common; ++ }; ++}; ++ ++struct rtw89_hal { ++ u32 rx_fltr; ++ u8 cv; ++ u8 current_channel; ++ u8 current_primary_channel; ++ enum rtw89_subband current_subband; ++ u8 current_band_width; ++ u8 current_band_type; ++ /* center channel for different available bandwidth, ++ * val of (bw > current_band_width) is invalid ++ */ ++ u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1]; ++ u32 sw_amsdu_max_size; ++ u32 antenna_tx; ++ u32 antenna_rx; ++ u8 tx_nss; ++ u8 rx_nss; ++}; ++ ++#define RTW89_MAX_MAC_ID_NUM 128 ++ ++enum rtw89_flags { ++ RTW89_FLAG_POWERON, ++ RTW89_FLAG_FW_RDY, ++ RTW89_FLAG_RUNNING, ++ RTW89_FLAG_BFEE_MON, ++ RTW89_FLAG_BFEE_EN, ++ RTW89_FLAG_NAPI_RUNNING, ++ RTW89_FLAG_LEISURE_PS, ++ RTW89_FLAG_LOW_POWER_MODE, ++ RTW89_FLAG_INACTIVE_PS, ++ ++ NUM_OF_RTW89_FLAGS, ++}; ++ ++struct rtw89_pkt_stat { ++ u16 beacon_nr; ++ u32 rx_rate_cnt[RTW89_HW_RATE_NR]; ++}; ++ ++DECLARE_EWMA(thermal, 4, 4); ++ ++struct rtw89_phy_stat { ++ struct ewma_thermal avg_thermal[RF_PATH_MAX]; ++ struct rtw89_pkt_stat cur_pkt_stat; ++ struct rtw89_pkt_stat last_pkt_stat; ++}; ++ ++#define RTW89_DACK_PATH_NR 2 ++#define RTW89_DACK_IDX_NR 2 ++#define RTW89_DACK_MSBK_NR 16 ++struct rtw89_dack_info { ++ bool dack_done; ++ u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; ++ u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; ++ u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; ++ u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; ++ u32 dack_cnt; ++ bool addck_timeout[RTW89_DACK_PATH_NR]; ++ bool dadck_timeout[RTW89_DACK_PATH_NR]; ++ bool msbk_timeout[RTW89_DACK_PATH_NR]; ++}; ++ ++#define RTW89_IQK_CHS_NR 2 ++#define RTW89_IQK_PATH_NR 4 ++struct rtw89_iqk_info { ++ bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ u32 iqk_fail_cnt; ++ bool is_iqk_init; ++ u32 iqk_channel[RTW89_IQK_CHS_NR]; ++ u8 iqk_band[RTW89_IQK_PATH_NR]; ++ u8 iqk_ch[RTW89_IQK_PATH_NR]; ++ u8 iqk_bw[RTW89_IQK_PATH_NR]; ++ u8 kcount; ++ u8 iqk_times; ++ u8 version; ++ u32 nb_txcfir[RTW89_IQK_PATH_NR]; ++ u32 nb_rxcfir[RTW89_IQK_PATH_NR]; ++ u32 bp_txkresult[RTW89_IQK_PATH_NR]; ++ u32 bp_rxkresult[RTW89_IQK_PATH_NR]; ++ u32 bp_iqkenable[RTW89_IQK_PATH_NR]; ++ bool is_wb_txiqk[RTW89_IQK_PATH_NR]; ++ bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; ++ bool is_nbiqk; ++ bool iqk_fft_en; ++ bool iqk_xym_en; ++ bool iqk_sram_en; ++ bool iqk_cfir_en; ++ u8 thermal[RTW89_IQK_PATH_NR]; ++ bool thermal_rek_en; ++ u32 syn1to2; ++ u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; ++ u8 iqk_table_idx[RTW89_IQK_PATH_NR]; ++}; ++ ++#define RTW89_DPK_RF_PATH 2 ++#define RTW89_DPK_AVG_THERMAL_NUM 8 ++#define RTW89_DPK_BKUP_NUM 2 ++struct rtw89_dpk_bkup_para { ++ enum rtw89_band band; ++ enum rtw89_bandwidth bw; ++ u8 ch; ++ bool path_ok; ++ u8 txagc_dpk; ++ u8 ther_dpk; ++ u8 gs; ++ u16 pwsf; ++}; ++ ++struct rtw89_dpk_info { ++ bool is_dpk_enable; ++ bool is_dpk_reload_en; ++ u16 dc_i[RTW89_DPK_RF_PATH]; ++ u16 dc_q[RTW89_DPK_RF_PATH]; ++ u8 corr_val[RTW89_DPK_RF_PATH]; ++ u8 corr_idx[RTW89_DPK_RF_PATH]; ++ u8 cur_idx[RTW89_DPK_RF_PATH]; ++ struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; ++}; ++ ++struct rtw89_fem_info { ++ bool elna_2g; ++ bool elna_5g; ++ bool epa_2g; ++ bool epa_5g; ++}; ++ ++struct rtw89_phy_ch_info { ++ u8 rssi_min; ++ u16 rssi_min_macid; ++ u8 pre_rssi_min; ++ u8 rssi_max; ++ u16 rssi_max_macid; ++ u8 rxsc_160; ++ u8 rxsc_80; ++ u8 rxsc_40; ++ u8 rxsc_20; ++ u8 rxsc_l; ++ u8 is_noisy; ++}; ++ ++struct rtw89_agc_gaincode_set { ++ u8 lna_idx; ++ u8 tia_idx; ++ u8 rxb_idx; ++}; ++ ++#define IGI_RSSI_TH_NUM 5 ++#define FA_TH_NUM 4 ++#define LNA_GAIN_NUM 7 ++#define TIA_GAIN_NUM 2 ++struct rtw89_dig_info { ++ struct rtw89_agc_gaincode_set cur_gaincode; ++ bool force_gaincode_idx_en; ++ struct rtw89_agc_gaincode_set force_gaincode; ++ u8 igi_rssi_th[IGI_RSSI_TH_NUM]; ++ u16 fa_th[FA_TH_NUM]; ++ u8 igi_rssi; ++ u8 igi_fa_rssi; ++ u8 fa_rssi_ofst; ++ u8 dyn_igi_max; ++ u8 dyn_igi_min; ++ bool dyn_pd_th_en; ++ u8 dyn_pd_th_max; ++ u8 pd_low_th_ofst; ++ u8 ib_pbk; ++ s8 ib_pkpwr; ++ s8 lna_gain_a[LNA_GAIN_NUM]; ++ s8 lna_gain_g[LNA_GAIN_NUM]; ++ s8 *lna_gain; ++ s8 tia_gain_a[TIA_GAIN_NUM]; ++ s8 tia_gain_g[TIA_GAIN_NUM]; ++ s8 *tia_gain; ++ bool is_linked_pre; ++ bool bypass_dig; ++}; ++ ++enum rtw89_multi_cfo_mode { ++ RTW89_PKT_BASED_AVG_MODE = 0, ++ RTW89_ENTRY_BASED_AVG_MODE = 1, ++ RTW89_TP_BASED_AVG_MODE = 2, ++}; ++ ++enum rtw89_phy_cfo_status { ++ RTW89_PHY_DCFO_STATE_NORMAL = 0, ++ RTW89_PHY_DCFO_STATE_ENHANCE = 1, ++ RTW89_PHY_DCFO_STATE_MAX ++}; ++ ++struct rtw89_cfo_tracking_info { ++ u16 cfo_timer_ms; ++ bool cfo_trig_by_timer_en; ++ enum rtw89_phy_cfo_status phy_cfo_status; ++ u8 phy_cfo_trk_cnt; ++ bool is_adjust; ++ enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; ++ bool apply_compensation; ++ u8 crystal_cap; ++ u8 crystal_cap_default; ++ u8 def_x_cap; ++ s8 x_cap_ofst; ++ u32 sta_cfo_tolerance; ++ s32 cfo_tail[CFO_TRACK_MAX_USER]; ++ u16 cfo_cnt[CFO_TRACK_MAX_USER]; ++ s32 cfo_avg_pre; ++ s32 cfo_avg[CFO_TRACK_MAX_USER]; ++ s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; ++ u32 packet_count; ++ u32 packet_count_pre; ++ s32 residual_cfo_acc; ++ u8 phy_cfotrk_state; ++ u8 phy_cfotrk_cnt; ++}; ++ ++/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ ++#define TSSI_TRIM_CH_GROUP_NUM 8 ++ ++#define TSSI_CCK_CH_GROUP_NUM 6 ++#define TSSI_MCS_2G_CH_GROUP_NUM 5 ++#define TSSI_MCS_5G_CH_GROUP_NUM 14 ++#define TSSI_MCS_CH_GROUP_NUM \ ++ (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) ++ ++struct rtw89_tssi_info { ++ u8 thermal[RF_PATH_MAX]; ++ s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; ++ s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; ++ s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; ++ s8 extra_ofst[RF_PATH_MAX]; ++ bool tssi_tracking_check[RF_PATH_MAX]; ++ u8 default_txagc_offset[RF_PATH_MAX]; ++ u32 base_thermal[RF_PATH_MAX]; ++}; ++ ++struct rtw89_power_trim_info { ++ bool pg_thermal_trim; ++ bool pg_pa_bias_trim; ++ u8 thermal_trim[RF_PATH_MAX]; ++ u8 pa_bias_trim[RF_PATH_MAX]; ++}; ++ ++struct rtw89_regulatory { ++ char alpha2[3]; ++ u8 txpwr_regd[RTW89_BAND_MAX]; ++}; ++ ++enum rtw89_ifs_clm_application { ++ RTW89_IFS_CLM_INIT = 0, ++ RTW89_IFS_CLM_BACKGROUND = 1, ++ RTW89_IFS_CLM_ACS = 2, ++ RTW89_IFS_CLM_DIG = 3, ++ RTW89_IFS_CLM_TDMA_DIG = 4, ++ RTW89_IFS_CLM_DBG = 5, ++ RTW89_IFS_CLM_DBG_MANUAL = 6 ++}; ++ ++enum rtw89_env_racing_lv { ++ RTW89_RAC_RELEASE = 0, ++ RTW89_RAC_LV_1 = 1, ++ RTW89_RAC_LV_2 = 2, ++ RTW89_RAC_LV_3 = 3, ++ RTW89_RAC_LV_4 = 4, ++ RTW89_RAC_MAX_NUM = 5 ++}; ++ ++struct rtw89_ccx_para_info { ++ enum rtw89_env_racing_lv rac_lv; ++ u16 mntr_time; ++ u8 nhm_manual_th_ofst; ++ u8 nhm_manual_th0; ++ enum rtw89_ifs_clm_application ifs_clm_app; ++ u32 ifs_clm_manual_th_times; ++ u32 ifs_clm_manual_th0; ++ u8 fahm_manual_th_ofst; ++ u8 fahm_manual_th0; ++ u8 fahm_numer_opt; ++ u8 fahm_denom_opt; ++}; ++ ++enum rtw89_ccx_edcca_opt_sc_idx { ++ RTW89_CCX_EDCCA_SEG0_P0 = 0, ++ RTW89_CCX_EDCCA_SEG0_S1 = 1, ++ RTW89_CCX_EDCCA_SEG0_S2 = 2, ++ RTW89_CCX_EDCCA_SEG0_S3 = 3, ++ RTW89_CCX_EDCCA_SEG1_P0 = 4, ++ RTW89_CCX_EDCCA_SEG1_S1 = 5, ++ RTW89_CCX_EDCCA_SEG1_S2 = 6, ++ RTW89_CCX_EDCCA_SEG1_S3 = 7 ++}; ++ ++enum rtw89_ccx_edcca_opt_bw_idx { ++ RTW89_CCX_EDCCA_BW20_0 = 0, ++ RTW89_CCX_EDCCA_BW20_1 = 1, ++ RTW89_CCX_EDCCA_BW20_2 = 2, ++ RTW89_CCX_EDCCA_BW20_3 = 3, ++ RTW89_CCX_EDCCA_BW20_4 = 4, ++ RTW89_CCX_EDCCA_BW20_5 = 5, ++ RTW89_CCX_EDCCA_BW20_6 = 6, ++ RTW89_CCX_EDCCA_BW20_7 = 7 ++}; ++ ++#define RTW89_NHM_TH_NUM 11 ++#define RTW89_FAHM_TH_NUM 11 ++#define RTW89_NHM_RPT_NUM 12 ++#define RTW89_FAHM_RPT_NUM 12 ++#define RTW89_IFS_CLM_NUM 4 ++struct rtw89_env_monitor_info { ++ u32 ccx_trigger_time; ++ u64 start_time; ++ u8 ccx_rpt_stamp; ++ u8 ccx_watchdog_result; ++ bool ccx_ongoing; ++ u8 ccx_rac_lv; ++ bool ccx_manual_ctrl; ++ u8 ccx_pre_rssi; ++ u16 clm_mntr_time; ++ u16 nhm_mntr_time; ++ u16 ifs_clm_mntr_time; ++ enum rtw89_ifs_clm_application ifs_clm_app; ++ u16 fahm_mntr_time; ++ u16 edcca_clm_mntr_time; ++ u16 ccx_period; ++ u8 ccx_unit_idx; ++ enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; ++ u8 nhm_th[RTW89_NHM_TH_NUM]; ++ u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; ++ u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; ++ u8 fahm_numer_opt; ++ u8 fahm_denom_opt; ++ u8 fahm_th[RTW89_FAHM_TH_NUM]; ++ u16 clm_result; ++ u16 nhm_result[RTW89_NHM_RPT_NUM]; ++ u8 nhm_wgt[RTW89_NHM_RPT_NUM]; ++ u16 nhm_tx_cnt; ++ u16 nhm_cca_cnt; ++ u16 nhm_idle_cnt; ++ u16 ifs_clm_tx; ++ u16 ifs_clm_edcca_excl_cca; ++ u16 ifs_clm_ofdmfa; ++ u16 ifs_clm_ofdmcca_excl_fa; ++ u16 ifs_clm_cckfa; ++ u16 ifs_clm_cckcca_excl_fa; ++ u16 ifs_clm_total_ifs; ++ u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; ++ u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; ++ u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; ++ u16 fahm_result[RTW89_FAHM_RPT_NUM]; ++ u16 fahm_denom_result; ++ u16 edcca_clm_result; ++ u8 clm_ratio; ++ u8 nhm_rpt[RTW89_NHM_RPT_NUM]; ++ u8 nhm_tx_ratio; ++ u8 nhm_cca_ratio; ++ u8 nhm_idle_ratio; ++ u8 nhm_ratio; ++ u16 nhm_result_sum; ++ u8 nhm_pwr; ++ u8 ifs_clm_tx_ratio; ++ u8 ifs_clm_edcca_excl_cca_ratio; ++ u8 ifs_clm_cck_fa_ratio; ++ u8 ifs_clm_ofdm_fa_ratio; ++ u8 ifs_clm_cck_cca_excl_fa_ratio; ++ u8 ifs_clm_ofdm_cca_excl_fa_ratio; ++ u16 ifs_clm_cck_fa_permil; ++ u16 ifs_clm_ofdm_fa_permil; ++ u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; ++ u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; ++ u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; ++ u16 fahm_result_sum; ++ u8 fahm_ratio; ++ u8 fahm_denom_ratio; ++ u8 fahm_pwr; ++ u8 edcca_clm_ratio; ++}; ++ ++enum rtw89_ser_rcvy_step { ++ RTW89_SER_DRV_STOP_TX, ++ RTW89_SER_DRV_STOP_RX, ++ RTW89_SER_DRV_STOP_RUN, ++ RTW89_SER_HAL_STOP_DMA, ++ RTW89_NUM_OF_SER_FLAGS ++}; ++ ++struct rtw89_ser { ++ u8 state; ++ u8 alarm_event; ++ ++ struct work_struct ser_hdl_work; ++ struct delayed_work ser_alarm_work; ++ struct state_ent *st_tbl; ++ struct event_ent *ev_tbl; ++ struct list_head msg_q; ++ spinlock_t msg_q_lock; /* lock when read/write ser msg */ ++ DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); ++}; ++ ++enum rtw89_mac_ax_ps_mode { ++ RTW89_MAC_AX_PS_MODE_ACTIVE = 0, ++ RTW89_MAC_AX_PS_MODE_LEGACY = 1, ++ RTW89_MAC_AX_PS_MODE_WMMPS = 2, ++ RTW89_MAC_AX_PS_MODE_MAX = 3, ++}; ++ ++enum rtw89_last_rpwm_mode { ++ RTW89_LAST_RPWM_PS = 0x0, ++ RTW89_LAST_RPWM_ACTIVE = 0x6, ++}; ++ ++struct rtw89_lps_parm { ++ u8 macid; ++ u8 psmode; /* enum rtw89_mac_ax_ps_mode */ ++ u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ ++}; ++ ++struct rtw89_ppdu_sts_info { ++ struct sk_buff_head rx_queue[RTW89_PHY_MAX]; ++ u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; ++}; ++ ++struct rtw89_early_h2c { ++ struct list_head list; ++ u8 *h2c; ++ u16 h2c_len; ++}; ++ ++struct rtw89_dev { ++ struct ieee80211_hw *hw; ++ struct device *dev; ++ ++ bool dbcc_en; ++ const struct rtw89_chip_info *chip; ++ struct rtw89_hal hal; ++ struct rtw89_mac_info mac; ++ struct rtw89_fw_info fw; ++ struct rtw89_hci_info hci; ++ struct rtw89_efuse efuse; ++ struct rtw89_traffic_stats stats; ++ ++ /* ensures exclusive access from mac80211 callbacks */ ++ struct mutex mutex; ++ struct list_head rtwvifs_list; ++ /* used to protect rf read write */ ++ struct mutex rf_mutex; ++ struct workqueue_struct *txq_wq; ++ struct work_struct txq_work; ++ struct delayed_work txq_reinvoke_work; ++ /* used to protect ba_list */ ++ spinlock_t ba_lock; ++ /* txqs to setup ba session */ ++ struct list_head ba_list; ++ struct work_struct ba_work; ++ ++ struct rtw89_cam_info cam_info; ++ ++ struct sk_buff_head c2h_queue; ++ struct work_struct c2h_work; ++ ++ struct list_head early_h2c_list; ++ ++ struct rtw89_ser ser; ++ ++ DECLARE_BITMAP(hw_port, RTW89_MAX_HW_PORT_NUM); ++ DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); ++ DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); ++ ++ struct rtw89_phy_stat phystat; ++ struct rtw89_dack_info dack; ++ struct rtw89_iqk_info iqk; ++ struct rtw89_dpk_info dpk; ++ bool is_tssi_mode[RF_PATH_MAX]; ++ bool is_bt_iqk_timeout; ++ ++ struct rtw89_fem_info fem; ++ struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; ++ struct rtw89_tssi_info tssi; ++ struct rtw89_power_trim_info pwr_trim; ++ ++ struct rtw89_cfo_tracking_info cfo_tracking; ++ struct rtw89_env_monitor_info env_monitor; ++ struct rtw89_dig_info dig; ++ struct rtw89_phy_ch_info ch_info; ++ struct delayed_work track_work; ++ struct delayed_work coex_act1_work; ++ struct delayed_work coex_bt_devinfo_work; ++ struct delayed_work coex_rfk_chk_work; ++ struct delayed_work cfo_track_work; ++ struct rtw89_ppdu_sts_info ppdu_sts; ++ u8 total_sta_assoc; ++ bool scanning; ++ ++ const struct rtw89_regulatory *regd; ++ struct rtw89_sar_info sar; ++ ++ struct rtw89_btc btc; ++ enum rtw89_ps_mode ps_mode; ++ bool lps_enabled; ++ ++ /* napi structure */ ++ struct net_device netdev; ++ struct napi_struct napi; ++ int napi_budget_countdown; ++ ++ /* HCI related data, keep last */ ++ u8 priv[0] __aligned(sizeof(void *)); ++}; ++ ++static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ return rtwdev->hci.ops->tx_write(rtwdev, tx_req); ++} ++ ++static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->hci.ops->reset(rtwdev); ++} ++ ++static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) ++{ ++ return rtwdev->hci.ops->start(rtwdev); ++} ++ ++static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->hci.ops->stop(rtwdev); ++} ++ ++static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) ++{ ++ return rtwdev->hci.ops->deinit(rtwdev); ++} ++ ++static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->hci.ops->recalc_int_mit(rtwdev); ++} ++ ++static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) ++{ ++ return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); ++} ++ ++static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) ++{ ++ return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); ++} ++ ++static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, ++ bool drop) ++{ ++ if (rtwdev->hci.ops->flush_queues) ++ return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); ++} ++ ++static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtwdev->hci.ops->read8(rtwdev, addr); ++} ++ ++static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtwdev->hci.ops->read16(rtwdev, addr); ++} ++ ++static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtwdev->hci.ops->read32(rtwdev, addr); ++} ++ ++static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) ++{ ++ rtwdev->hci.ops->write8(rtwdev, addr, data); ++} ++ ++static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) ++{ ++ rtwdev->hci.ops->write16(rtwdev, addr, data); ++} ++ ++static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) ++{ ++ rtwdev->hci.ops->write32(rtwdev, addr, data); ++} ++ ++static inline void ++rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) ++{ ++ u8 val; ++ ++ val = rtw89_read8(rtwdev, addr); ++ rtw89_write8(rtwdev, addr, val | bit); ++} ++ ++static inline void ++rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) ++{ ++ u16 val; ++ ++ val = rtw89_read16(rtwdev, addr); ++ rtw89_write16(rtwdev, addr, val | bit); ++} ++ ++static inline void ++rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) ++{ ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, addr); ++ rtw89_write32(rtwdev, addr, val | bit); ++} ++ ++static inline void ++rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) ++{ ++ u8 val; ++ ++ val = rtw89_read8(rtwdev, addr); ++ rtw89_write8(rtwdev, addr, val & ~bit); ++} ++ ++static inline void ++rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) ++{ ++ u16 val; ++ ++ val = rtw89_read16(rtwdev, addr); ++ rtw89_write16(rtwdev, addr, val & ~bit); ++} ++ ++static inline void ++rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) ++{ ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, addr); ++ rtw89_write32(rtwdev, addr, val & ~bit); ++} ++ ++static inline u32 ++rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 ret; ++ ++ orig = rtw89_read32(rtwdev, addr); ++ ret = (orig & mask) >> shift; ++ ++ return ret; ++} ++ ++static inline u16 ++rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 ret; ++ ++ orig = rtw89_read16(rtwdev, addr); ++ ret = (orig & mask) >> shift; ++ ++ return ret; ++} ++ ++static inline u8 ++rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 ret; ++ ++ orig = rtw89_read8(rtwdev, addr); ++ ret = (orig & mask) >> shift; ++ ++ return ret; ++} ++ ++static inline void ++rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) ++{ ++ u32 shift = __ffs(mask); ++ u32 orig; ++ u32 set; ++ ++ WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); ++ ++ orig = rtw89_read32(rtwdev, addr); ++ set = (orig & ~mask) | ((data << shift) & mask); ++ rtw89_write32(rtwdev, addr, set); ++} ++ ++static inline void ++rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) ++{ ++ u32 shift; ++ u16 orig, set; ++ ++ mask &= 0xffff; ++ shift = __ffs(mask); ++ ++ orig = rtw89_read16(rtwdev, addr); ++ set = (orig & ~mask) | ((data << shift) & mask); ++ rtw89_write16(rtwdev, addr, set); ++} ++ ++static inline void ++rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) ++{ ++ u32 shift; ++ u8 orig, set; ++ ++ mask &= 0xff; ++ shift = __ffs(mask); ++ ++ orig = rtw89_read8(rtwdev, addr); ++ set = (orig & ~mask) | ((data << shift) & mask); ++ rtw89_write8(rtwdev, addr, set); ++} ++ ++static inline u32 ++rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask) ++{ ++ u32 val; ++ ++ mutex_lock(&rtwdev->rf_mutex); ++ val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); ++ mutex_unlock(&rtwdev->rf_mutex); ++ ++ return val; ++} ++ ++static inline void ++rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data) ++{ ++ mutex_lock(&rtwdev->rf_mutex); ++ rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); ++ mutex_unlock(&rtwdev->rf_mutex); ++} ++ ++static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) ++{ ++ void *p = rtwtxq; ++ ++ return container_of(p, struct ieee80211_txq, drv_priv); ++} ++ ++static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, ++ struct ieee80211_txq *txq) ++{ ++ struct rtw89_txq *rtwtxq; ++ ++ if (!txq) ++ return; ++ ++ rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ INIT_LIST_HEAD(&rtwtxq->list); ++} ++ ++static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) ++{ ++ void *p = rtwvif; ++ ++ return container_of(p, struct ieee80211_vif, drv_priv); ++} ++ ++static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) ++{ ++ void *p = rtwsta; ++ ++ return container_of(p, struct ieee80211_sta, drv_priv); ++} ++ ++static inline ++void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_help_params *p) ++{ ++ rtwdev->chip->ops->set_channel_help(rtwdev, true, p); ++} ++ ++static inline ++void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_help_params *p) ++{ ++ rtwdev->chip->ops->set_channel_help(rtwdev, false, p); ++} ++ ++static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->fem_setup) ++ chip->ops->fem_setup(rtwdev); ++} ++ ++static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->bb_sethw) ++ chip->ops->bb_sethw(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_init) ++ chip->ops->rfk_init(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_channel) ++ chip->ops->rfk_channel(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_band_changed) ++ chip->ops->rfk_band_changed(rtwdev); ++} ++ ++static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_scan) ++ chip->ops->rfk_scan(rtwdev, start); ++} ++ ++static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->rfk_track) ++ chip->ops->rfk_track(rtwdev); ++} ++ ++static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->set_txpwr_ctrl) ++ chip->ops->set_txpwr_ctrl(rtwdev); ++} ++ ++static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 ch = rtwdev->hal.current_channel; ++ ++ if (!ch) ++ return; ++ ++ if (chip->ops->set_txpwr) ++ chip->ops->set_txpwr(rtwdev); ++} ++ ++static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->power_trim) ++ chip->ops->power_trim(rtwdev); ++} ++ ++static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->init_txpwr_unit) ++ chip->ops->init_txpwr_unit(rtwdev, phy_idx); ++} ++ ++static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path rf_path) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (!chip->ops->get_thermal) ++ return 0x10; ++ ++ return chip->ops->get_thermal(rtwdev, rf_path); ++} ++ ++static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->query_ppdu) ++ chip->ops->query_ppdu(rtwdev, phy_ppdu, status); ++} ++ ++static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, ++ bool bt_en) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->bb_ctrl_btc_preagc) ++ chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); ++} ++ ++static inline ++void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) ++ return; ++ ++ if (chip->ops->set_txpwr_ul_tb_offset) ++ chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); ++} ++ ++static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl) ++{ ++ tbl->load(rtwdev, tbl); ++} ++ ++static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) ++{ ++ return rtwdev->regd->txpwr_regd[band]; ++} ++ ++static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ if (chip->ops->ctrl_btg) ++ chip->ops->ctrl_btg(rtwdev, btg); ++} ++ ++static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) ++{ ++ __le16 fc = hdr->frame_control; ++ ++ if (ieee80211_has_tods(fc)) ++ return hdr->addr1; ++ else if (ieee80211_has_fromds(fc)) ++ return hdr->addr2; ++ else ++ return hdr->addr3; ++} ++ ++static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) ++{ ++ if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || ++ (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || ++ (sta->he_cap.he_cap_elem.phy_cap_info[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || ++ (sta->he_cap.he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) ++ return true; ++ return false; ++} ++ ++static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, ++ enum rtw89_fw_type type) ++{ ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ ++ if (type == RTW89_FW_WOWLAN) ++ return &fw_info->wowlan; ++ return &fw_info->normal; ++} ++ ++int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); ++int rtw89_h2c_tx(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, bool fwdl); ++void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); ++void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_tx_desc_info *desc_info, ++ void *txdesc); ++void rtw89_core_rx(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ struct sk_buff *skb); ++void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_desc_info *desc_info, ++ u8 *data, u32 data_offset); ++void rtw89_core_napi_start(struct rtw89_dev *rtwdev); ++void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); ++void rtw89_core_napi_init(struct rtw89_dev *rtwdev); ++void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); ++int rtw89_core_sta_add(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_core_init(struct rtw89_dev *rtwdev); ++void rtw89_core_deinit(struct rtw89_dev *rtwdev); ++int rtw89_core_register(struct rtw89_dev *rtwdev); ++void rtw89_core_unregister(struct rtw89_dev *rtwdev); ++void rtw89_set_channel(struct rtw89_dev *rtwdev); ++u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); ++void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); ++void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); ++void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); ++int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); ++u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate); ++int rtw89_regd_init(struct rtw89_dev *rtwdev, ++ void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); ++void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); ++void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, ++ struct rtw89_traffic_stats *stats); ++int rtw89_core_start(struct rtw89_dev *rtwdev); ++void rtw89_core_stop(struct rtw89_dev *rtwdev); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c +new file mode 100644 +index 000000000000..29eb188c888c +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/debug.c +@@ -0,0 +1,2489 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++ ++#ifdef CONFIG_RTW89_DEBUGMSG ++unsigned int rtw89_debug_mask; ++EXPORT_SYMBOL(rtw89_debug_mask); ++module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); ++MODULE_PARM_DESC(debug_mask, "Debugging mask"); ++#endif ++ ++#ifdef CONFIG_RTW89_DEBUGFS ++struct rtw89_debugfs_priv { ++ struct rtw89_dev *rtwdev; ++ int (*cb_read)(struct seq_file *m, void *v); ++ ssize_t (*cb_write)(struct file *filp, const char __user *buffer, ++ size_t count, loff_t *loff); ++ union { ++ u32 cb_data; ++ struct { ++ u32 addr; ++ u8 len; ++ } read_reg; ++ struct { ++ u32 addr; ++ u32 mask; ++ u8 path; ++ } read_rf; ++ struct { ++ u8 ss_dbg:1; ++ u8 dle_dbg:1; ++ u8 dmac_dbg:1; ++ u8 cmac_dbg:1; ++ u8 dbg_port:1; ++ } dbgpkg_en; ++ struct { ++ u32 start; ++ u32 len; ++ u8 sel; ++ } mac_mem; ++ }; ++}; ++ ++static int rtw89_debugfs_single_show(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ ++ return debugfs_priv->cb_read(m, v); ++} ++ ++static ssize_t rtw89_debugfs_single_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ ++ return debugfs_priv->cb_write(filp, buffer, count, loff); ++} ++ ++static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, ++ const char __user *buffer, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *seqpriv = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; ++ ++ return debugfs_priv->cb_write(filp, buffer, count, loff); ++} ++ ++static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) ++{ ++ return single_open(filp, rtw89_debugfs_single_show, inode->i_private); ++} ++ ++static int rtw89_debugfs_close(struct inode *inode, struct file *filp) ++{ ++ return 0; ++} ++ ++static const struct file_operations file_ops_single_r = { ++ .owner = THIS_MODULE, ++ .open = rtw89_debugfs_single_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct file_operations file_ops_common_rw = { ++ .owner = THIS_MODULE, ++ .open = rtw89_debugfs_single_open, ++ .release = single_release, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = rtw89_debugfs_seq_file_write, ++}; ++ ++static const struct file_operations file_ops_single_w = { ++ .owner = THIS_MODULE, ++ .write = rtw89_debugfs_single_write, ++ .open = simple_open, ++ .release = rtw89_debugfs_close, ++}; ++ ++static ssize_t ++rtw89_debug_priv_read_reg_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, len; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%x %x", &addr, &len); ++ if (num != 2) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ debugfs_priv->read_reg.addr = addr; ++ debugfs_priv->read_reg.len = len; ++ ++ rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ u32 addr, data; ++ u8 len; ++ ++ len = debugfs_priv->read_reg.len; ++ addr = debugfs_priv->read_reg.addr; ++ ++ switch (len) { ++ case 1: ++ data = rtw89_read8(rtwdev, addr); ++ break; ++ case 2: ++ data = rtw89_read16(rtwdev, addr); ++ break; ++ case 4: ++ data = rtw89_read32(rtwdev, addr); ++ break; ++ default: ++ rtw89_info(rtwdev, "invalid read reg len %d\n", len); ++ return -EINVAL; ++ } ++ ++ seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); ++ ++ return 0; ++} ++ ++static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, val, len; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%x %x %x", &addr, &val, &len); ++ if (num != 3) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ switch (len) { ++ case 1: ++ rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); ++ rtw89_write8(rtwdev, addr, (u8)val); ++ break; ++ case 2: ++ rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); ++ rtw89_write16(rtwdev, addr, (u16)val); ++ break; ++ case 4: ++ rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); ++ rtw89_write32(rtwdev, addr, (u32)val); ++ break; ++ default: ++ rtw89_info(rtwdev, "invalid read write len %d\n", len); ++ break; ++ } ++ ++ return count; ++} ++ ++static ssize_t ++rtw89_debug_priv_read_rf_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, mask; ++ u8 path; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); ++ if (num != 3) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ if (path >= rtwdev->chip->rf_path_num) { ++ rtw89_info(rtwdev, "wrong rf path\n"); ++ return -EINVAL; ++ } ++ debugfs_priv->read_rf.addr = addr; ++ debugfs_priv->read_rf.mask = mask; ++ debugfs_priv->read_rf.path = path; ++ ++ rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ u32 addr, data, mask; ++ u8 path; ++ ++ addr = debugfs_priv->read_rf.addr; ++ mask = debugfs_priv->read_rf.mask; ++ path = debugfs_priv->read_rf.path; ++ ++ data = rtw89_read_rf(rtwdev, path, addr, mask); ++ ++ seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); ++ ++ return 0; ++} ++ ++static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 addr, val, mask; ++ u8 path; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); ++ if (num != 4) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ if (path >= rtwdev->chip->rf_path_num) { ++ rtw89_info(rtwdev, "wrong rf path\n"); ++ return -EINVAL; ++ } ++ ++ rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", ++ path, addr, val, mask); ++ rtw89_write_rf(rtwdev, path, addr, mask, val); ++ ++ return count; ++} ++ ++static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u32 addr, offset, data; ++ u8 path; ++ ++ for (path = 0; path < chip->rf_path_num; path++) { ++ seq_printf(m, "RF path %d:\n\n", path); ++ for (addr = 0; addr < 0x100; addr += 4) { ++ seq_printf(m, "0x%08x: ", addr); ++ for (offset = 0; offset < 4; offset++) { ++ data = rtw89_read_rf(rtwdev, path, ++ addr + offset, RFREG_MASK); ++ seq_printf(m, "0x%05x ", data); ++ } ++ seq_puts(m, "\n"); ++ } ++ seq_puts(m, "\n"); ++ } ++ ++ return 0; ++} ++ ++struct txpwr_ent { ++ const char *txt; ++ u8 len; ++}; ++ ++struct txpwr_map { ++ const struct txpwr_ent *ent; ++ u8 size; ++ u32 addr_from; ++ u32 addr_to; ++}; ++ ++#define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ ++ { .len = 2, .txt = _t "\t- " _e0 " " _e1 } ++ ++#define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ ++ { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } ++ ++#define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ ++ { .len = 8, .txt = _t "\t- " \ ++ _e0 " " _e1 " " _e2 " " _e3 " " \ ++ _e4 " " _e5 " " _e6 " " _e7 } ++ ++static const struct txpwr_ent __txpwr_ent_byr[] = { ++ __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), ++ __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), ++ __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), ++ /* 1NSS */ ++ __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), ++ __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), ++ __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), ++ __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), ++ /* 2NSS */ ++ __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), ++ __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), ++ __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), ++ __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), ++}; ++ ++static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == ++ (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); ++ ++static const struct txpwr_map __txpwr_map_byr = { ++ .ent = __txpwr_ent_byr, ++ .size = ARRAY_SIZE(__txpwr_ent_byr), ++ .addr_from = R_AX_PWR_BY_RATE, ++ .addr_to = R_AX_PWR_BY_RATE_MAX, ++}; ++ ++static const struct txpwr_ent __txpwr_ent_lmt[] = { ++ /* 1TX */ ++ __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), ++ /* 2TX */ ++ __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), ++ __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), ++}; ++ ++static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == ++ (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); ++ ++static const struct txpwr_map __txpwr_map_lmt = { ++ .ent = __txpwr_ent_lmt, ++ .size = ARRAY_SIZE(__txpwr_ent_lmt), ++ .addr_from = R_AX_PWR_LMT, ++ .addr_to = R_AX_PWR_LMT_MAX, ++}; ++ ++static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { ++ /* 1TX */ ++ __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", ++ "RU26__4", "RU26__5", "RU26__6", "RU26__7"), ++ __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", ++ "RU52__4", "RU52__5", "RU52__6", "RU52__7"), ++ __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", ++ "RU106_4", "RU106_5", "RU106_6", "RU106_7"), ++ /* 2TX */ ++ __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", ++ "RU26__4", "RU26__5", "RU26__6", "RU26__7"), ++ __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", ++ "RU52__4", "RU52__5", "RU52__6", "RU52__7"), ++ __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", ++ "RU106_4", "RU106_5", "RU106_6", "RU106_7"), ++}; ++ ++static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == ++ (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); ++ ++static const struct txpwr_map __txpwr_map_lmt_ru = { ++ .ent = __txpwr_ent_lmt_ru, ++ .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), ++ .addr_from = R_AX_PWR_RU_LMT, ++ .addr_to = R_AX_PWR_RU_LMT_MAX, ++}; ++ ++static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, ++ const u8 *buf, const u8 cur) ++{ ++ char *fmt; ++ ++ switch (ent->len) { ++ case 2: ++ fmt = "%s\t| %3d, %3d,\tdBm\n"; ++ seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); ++ return 2; ++ case 4: ++ fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; ++ seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], ++ buf[cur + 2], buf[cur + 3]); ++ return 4; ++ case 8: ++ fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; ++ seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], ++ buf[cur + 2], buf[cur + 3], buf[cur + 4], ++ buf[cur + 5], buf[cur + 6], buf[cur + 7]); ++ return 8; ++ default: ++ return 0; ++ } ++} ++ ++static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, ++ const struct txpwr_map *map) ++{ ++ u8 fct = rtwdev->chip->txpwr_factor_mac; ++ u8 *buf, cur, i; ++ u32 val, addr; ++ int ret; ++ ++ buf = vzalloc(map->addr_to - map->addr_from + 4); ++ if (!buf) ++ return -ENOMEM; ++ ++ for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { ++ ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); ++ if (ret) ++ val = MASKDWORD; ++ ++ cur = addr - map->addr_from; ++ for (i = 0; i < 4; i++, val >>= 8) ++ buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; ++ } ++ ++ for (cur = 0, i = 0; i < map->size; i++) ++ cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); ++ ++ vfree(buf); ++ return 0; ++} ++ ++#define case_REGD(_regd) \ ++ case RTW89_ ## _regd: \ ++ seq_puts(m, #_regd "\n"); \ ++ break ++ ++static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) ++{ ++ u8 band = rtwdev->hal.current_band_type; ++ u8 regd = rtw89_regd_get(rtwdev, band); ++ ++ switch (regd) { ++ default: ++ seq_printf(m, "UNKNOWN: %d\n", regd); ++ break; ++ case_REGD(WW); ++ case_REGD(ETSI); ++ case_REGD(FCC); ++ case_REGD(MKK); ++ case_REGD(NA); ++ case_REGD(IC); ++ case_REGD(KCC); ++ case_REGD(NCC); ++ case_REGD(CHILE); ++ case_REGD(ACMA); ++ case_REGD(MEXICO); ++ case_REGD(UKRAINE); ++ case_REGD(CN); ++ } ++} ++ ++#undef case_REGD ++ ++static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ seq_puts(m, "[Regulatory] "); ++ __print_regd(m, rtwdev); ++ ++ seq_puts(m, "[SAR]\n"); ++ rtw89_print_sar(m, rtwdev); ++ ++ seq_puts(m, "\n[TX power byrate]\n"); ++ ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); ++ if (ret) ++ goto err; ++ ++ seq_puts(m, "\n[TX power limit]\n"); ++ ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); ++ if (ret) ++ goto err; ++ ++ seq_puts(m, "\n[TX power limit_ru]\n"); ++ ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); ++ if (ret) ++ goto err; ++ ++err: ++ mutex_unlock(&rtwdev->mutex); ++ return ret; ++} ++ ++static ssize_t ++rtw89_debug_priv_mac_reg_dump_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ int sel; ++ int ret; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ ret = kstrtoint(buf, 0, &sel); ++ if (ret) ++ return ret; ++ ++ if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { ++ rtw89_info(rtwdev, "invalid args: %d\n", sel); ++ return -EINVAL; ++ } ++ ++ debugfs_priv->cb_data = sel; ++ rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); ++ ++ return count; ++} ++ ++#define RTW89_MAC_PAGE_SIZE 0x100 ++ ++static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; ++ u32 start, end; ++ u32 i, j, k, page; ++ u32 val; ++ ++ switch (reg_sel) { ++ case RTW89_DBG_SEL_MAC_00: ++ seq_puts(m, "Debug selected MAC page 0x00\n"); ++ start = 0x000; ++ end = 0x014; ++ break; ++ case RTW89_DBG_SEL_MAC_40: ++ seq_puts(m, "Debug selected MAC page 0x40\n"); ++ start = 0x040; ++ end = 0x07f; ++ break; ++ case RTW89_DBG_SEL_MAC_80: ++ seq_puts(m, "Debug selected MAC page 0x80\n"); ++ start = 0x080; ++ end = 0x09f; ++ break; ++ case RTW89_DBG_SEL_MAC_C0: ++ seq_puts(m, "Debug selected MAC page 0xc0\n"); ++ start = 0x0c0; ++ end = 0x0df; ++ break; ++ case RTW89_DBG_SEL_MAC_E0: ++ seq_puts(m, "Debug selected MAC page 0xe0\n"); ++ start = 0x0e0; ++ end = 0x0ff; ++ break; ++ case RTW89_DBG_SEL_BB: ++ seq_puts(m, "Debug selected BB register\n"); ++ start = 0x100; ++ end = 0x17f; ++ break; ++ case RTW89_DBG_SEL_IQK: ++ seq_puts(m, "Debug selected IQK register\n"); ++ start = 0x180; ++ end = 0x1bf; ++ break; ++ case RTW89_DBG_SEL_RFC: ++ seq_puts(m, "Debug selected RFC register\n"); ++ start = 0x1c0; ++ end = 0x1ff; ++ break; ++ default: ++ seq_puts(m, "Selected invalid register page\n"); ++ return -EINVAL; ++ } ++ ++ for (i = start; i <= end; i++) { ++ page = i << 8; ++ for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { ++ seq_printf(m, "%08xh : ", 0x18600000 + j); ++ for (k = 0; k < 4; k++) { ++ val = rtw89_read32(rtwdev, j + (k << 2)); ++ seq_printf(m, "%08x ", val); ++ } ++ seq_puts(m, "\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static ssize_t ++rtw89_debug_priv_mac_mem_dump_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ u32 sel, start_addr, len; ++ int num; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); ++ if (num != 3) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ debugfs_priv->mac_mem.sel = sel; ++ debugfs_priv->mac_mem.start = start_addr; ++ debugfs_priv->mac_mem.len = len; ++ ++ rtw89_info(rtwdev, "select mem %d start %d len %d\n", ++ sel, start_addr, len); ++ ++ return count; ++} ++ ++static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { ++ [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, ++ [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, ++ [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, ++ [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, ++ [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, ++ [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, ++ [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, ++ [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, ++}; ++ ++static void rtw89_debug_dump_mac_mem(struct seq_file *m, ++ struct rtw89_dev *rtwdev, ++ u8 sel, u32 start_addr, u32 len) ++{ ++ u32 base_addr, start_page, residue; ++ u32 i, j, p, pages; ++ u32 dump_len, remain; ++ u32 val; ++ ++ remain = len; ++ pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; ++ start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; ++ residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; ++ base_addr = mac_mem_base_addr_table[sel]; ++ base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; ++ ++ for (p = 0; p < pages; p++) { ++ dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); ++ rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); ++ for (i = R_AX_INDIR_ACCESS_ENTRY + residue; ++ i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { ++ seq_printf(m, "%08xh:", i); ++ for (j = 0; ++ j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; ++ j++, i += 4) { ++ val = rtw89_read32(rtwdev, i); ++ seq_printf(m, " %08x", val); ++ remain -= 4; ++ } ++ seq_puts(m, "\n"); ++ } ++ base_addr += MAC_MEM_DUMP_PAGE_SIZE; ++ } ++} ++ ++static int ++rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_debug_dump_mac_mem(m, rtwdev, ++ debugfs_priv->mac_mem.sel, ++ debugfs_priv->mac_mem.start, ++ debugfs_priv->mac_mem.len); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ssize_t ++rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ char buf[32]; ++ size_t buf_size; ++ int sel, set; ++ int num; ++ bool enable; ++ ++ buf_size = min(count, sizeof(buf) - 1); ++ if (copy_from_user(buf, user_buf, buf_size)) ++ return -EFAULT; ++ ++ buf[buf_size] = '\0'; ++ num = sscanf(buf, "%d %d", &sel, &set); ++ if (num != 2) { ++ rtw89_info(rtwdev, "invalid format: \n"); ++ return -EINVAL; ++ } ++ ++ enable = set == 0 ? false : true; ++ switch (sel) { ++ case 0: ++ debugfs_priv->dbgpkg_en.ss_dbg = enable; ++ break; ++ case 1: ++ debugfs_priv->dbgpkg_en.dle_dbg = enable; ++ break; ++ case 2: ++ debugfs_priv->dbgpkg_en.dmac_dbg = enable; ++ break; ++ case 3: ++ debugfs_priv->dbgpkg_en.cmac_dbg = enable; ++ break; ++ case 4: ++ debugfs_priv->dbgpkg_en.dbg_port = enable; ++ break; ++ default: ++ rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); ++ return -EINVAL; ++ } ++ ++ rtw89_info(rtwdev, "%s debug port dump %d\n", ++ enable ? "Enable" : "Disable", sel); ++ ++ return count; ++} ++ ++static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ return 0; ++} ++ ++static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++#define DLE_DFI_DUMP(__type, __target, __sel) \ ++({ \ ++ u32 __ctrl; \ ++ u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ ++ u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ ++ u32 __data, __val32; \ ++ int __ret; \ ++ \ ++ __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ ++ DLE_DFI_TYPE_##__target) | \ ++ FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ ++ B_AX_WDE_DFI_ACTIVE; \ ++ rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ ++ __ret = read_poll_timeout(rtw89_read32, __val32, \ ++ !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ ++ 1000, 50000, false, \ ++ rtwdev, __reg_ctrl); \ ++ if (__ret) { \ ++ rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ ++ #__type, #__target, __sel); \ ++ return __ret; \ ++ } \ ++ \ ++ __data = rtw89_read32(rtwdev, __reg_data); \ ++ __data; \ ++}) ++ ++#define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ ++({ \ ++ u32 __freepg, __pubpg; \ ++ u32 __freepg_head, __freepg_tail, __pubpg_num; \ ++ \ ++ __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ ++ __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ ++ __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ ++ __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ ++ __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ ++ seq_printf(__m, "[%s] freepg head: %d\n", \ ++ #__type, __freepg_head); \ ++ seq_printf(__m, "[%s] freepg tail: %d\n", \ ++ #__type, __freepg_tail); \ ++ seq_printf(__m, "[%s] pubpg num : %d\n", \ ++ #__type, __pubpg_num); \ ++}) ++ ++#define case_QUOTA(__m, __type, __id) \ ++ case __type##_QTAID_##__id: \ ++ val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ ++ rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ ++ use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ ++ seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ ++ #__type, #__id, rsv_pgnum); \ ++ seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ ++ #__type, #__id, use_pgnum); \ ++ break ++ u32 quota_id; ++ u32 val32; ++ u16 rsv_pgnum, use_pgnum; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[DLE] : DMAC not enabled\n"); ++ return ret; ++ } ++ ++ DLE_DFI_FREE_PAGE_DUMP(m, WDE); ++ DLE_DFI_FREE_PAGE_DUMP(m, PLE); ++ for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { ++ switch (quota_id) { ++ case_QUOTA(m, WDE, HOST_IF); ++ case_QUOTA(m, WDE, WLAN_CPU); ++ case_QUOTA(m, WDE, DATA_CPU); ++ case_QUOTA(m, WDE, PKTIN); ++ case_QUOTA(m, WDE, CPUIO); ++ } ++ } ++ for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { ++ switch (quota_id) { ++ case_QUOTA(m, PLE, B0_TXPL); ++ case_QUOTA(m, PLE, B1_TXPL); ++ case_QUOTA(m, PLE, C2H); ++ case_QUOTA(m, PLE, H2C); ++ case_QUOTA(m, PLE, WLAN_CPU); ++ case_QUOTA(m, PLE, MPDU); ++ case_QUOTA(m, PLE, CMAC0_RX); ++ case_QUOTA(m, PLE, CMAC1_RX); ++ case_QUOTA(m, PLE, CMAC1_BBRPT); ++ case_QUOTA(m, PLE, WDRLS); ++ case_QUOTA(m, PLE, CPUIO); ++ } ++ } ++ ++ return 0; ++ ++#undef case_QUOTA ++#undef DLE_DFI_DUMP ++#undef DLE_DFI_FREE_PAGE_DUMP ++} ++ ++static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[DMAC] : DMAC not enabled\n"); ++ return ret; ++ } ++ ++ seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); ++ seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); ++ seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); ++ seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); ++ seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); ++ seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); ++ seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); ++ seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); ++ seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); ++ seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); ++ seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); ++ seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); ++ seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); ++ seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); ++ seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); ++ seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); ++ seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); ++ seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); ++ seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); ++ ++ return 0; ++} ++ ++static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); ++ return ret; ++ } ++ ++ seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); ++ seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); ++ seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); ++ seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DLE_CTRL)); ++ seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); ++ seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); ++ seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); ++ seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); ++ if (ret) { ++ seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); ++ return ret; ++ } ++ ++ seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); ++ seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); ++ seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); ++ seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); ++ seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); ++ seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); ++ seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); ++ seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); ++ ++ return 0; ++} ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { ++ .sel_addr = R_AX_PTCL_DBG, ++ .sel_byte = 1, ++ .sel_msk = B_AX_PTCL_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x3F, ++ .rd_addr = R_AX_PTCL_DBG_INFO, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PTCL_DBG_INFO_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { ++ .sel_addr = R_AX_PTCL_DBG_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_PTCL_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x3F, ++ .rd_addr = R_AX_PTCL_DBG_INFO_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PTCL_DBG_INFO_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { ++ .sel_addr = R_AX_SCH_DBG_SEL, ++ .sel_byte = 1, ++ .sel_msk = B_AX_SCH_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x2F, ++ .rd_addr = R_AX_SCH_DBG, ++ .rd_byte = 4, ++ .rd_msk = B_AX_SCHEDULER_DBG_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { ++ .sel_addr = R_AX_SCH_DBG_SEL_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_SCH_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x2F, ++ .rd_addr = R_AX_SCH_DBG_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_SCHEDULER_DBG_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { ++ .sel_addr = R_AX_MACTX_DBG_SEL_CNT, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_MACTX_MASK, ++ .srt = 0x00, ++ .end = 0x19, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { ++ .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_MACTX_MASK, ++ .srt = 0x00, ++ .end = 0x19, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { ++ .sel_addr = R_AX_RX_DEBUG_SELECT, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x58, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { ++ .sel_addr = R_AX_RX_DEBUG_SELECT_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x58, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { ++ .sel_addr = R_AX_RX_STATE_MONITOR, ++ .sel_byte = 1, ++ .sel_msk = B_AX_STATE_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x17, ++ .rd_addr = R_AX_RX_STATE_MONITOR, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RX_STATE_MONITOR_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { ++ .sel_addr = R_AX_RX_STATE_MONITOR_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_STATE_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x17, ++ .rd_addr = R_AX_RX_STATE_MONITOR_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RX_STATE_MONITOR_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { ++ .sel_addr = R_AX_RMAC_PLCP_MON, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PCLP_MON_SEL_MASK, ++ .srt = 0x0, ++ .end = 0xF, ++ .rd_addr = R_AX_RMAC_PLCP_MON, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RMAC_PLCP_MON_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { ++ .sel_addr = R_AX_RMAC_PLCP_MON_C1, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PCLP_MON_SEL_MASK, ++ .srt = 0x0, ++ .end = 0xF, ++ .rd_addr = R_AX_RMAC_PLCP_MON_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_RMAC_PLCP_MON_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { ++ .sel_addr = R_AX_DBGSEL_TRXPTCL, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, ++ .srt = 0x08, ++ .end = 0x10, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { ++ .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, ++ .srt = 0x08, ++ .end = 0x10, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { ++ .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x07, ++ .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_2, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { ++ .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, ++ .sel_byte = 1, ++ .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80000000, ++ .end = 0x80000001, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80010000, ++ .end = 0x80010004, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80020000, ++ .end = 0x80020FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80030000, ++ .end = 0x80030FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80040000, ++ .end = 0x80040FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80050000, ++ .end = 0x80050FFF, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80060000, ++ .end = 0x80060453, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { ++ .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_WDE_DFI_DATA_MASK, ++ .srt = 0x80070000, ++ .end = 0x80070011, ++ .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_WDE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80000000, ++ .end = 0x80000001, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80010000, ++ .end = 0x8001000A, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80020000, ++ .end = 0x80020DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80030000, ++ .end = 0x80030DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80040000, ++ .end = 0x80040DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80050000, ++ .end = 0x80050DBF, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80060000, ++ .end = 0x80060041, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { ++ .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_PLE_DFI_DATA_MASK, ++ .srt = 0x80070000, ++ .end = 0x80070001, ++ .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_PLE_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { ++ .sel_addr = R_AX_DBG_FUN_INTF_CTL, ++ .sel_byte = 4, ++ .sel_msk = B_AX_DFI_DATA_MASK, ++ .srt = 0x80000000, ++ .end = 0x8000017f, ++ .rd_addr = R_AX_DBG_FUN_INTF_DATA, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DFI_DATA_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x03, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x04, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x01, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x05, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x05, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { ++ .sel_addr = R_AX_PCIE_DBG_CTRL, ++ .sel_byte = 2, ++ .sel_msk = B_AX_DBG_SEL_MASK, ++ .srt = 0x00, ++ .end = 0x06, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { ++ .sel_addr = R_AX_DBG_CTRL, ++ .sel_byte = 1, ++ .sel_msk = B_AX_DBG_SEL0, ++ .srt = 0x34, ++ .end = 0x3C, ++ .rd_addr = R_AX_DBG_PORT_SEL, ++ .rd_byte = 4, ++ .rd_msk = B_AX_DEBUG_ST_MASK ++}; ++ ++static const struct rtw89_mac_dbg_port_info * ++rtw89_debug_mac_dbg_port_sel(struct seq_file *m, ++ struct rtw89_dev *rtwdev, u32 sel) ++{ ++ const struct rtw89_mac_dbg_port_info *info; ++ u32 val32; ++ u16 val16; ++ u8 val8; ++ ++ switch (sel) { ++ case RTW89_DBG_PORT_SEL_PTCL_C0: ++ info = &dbg_port_ptcl_c0; ++ val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); ++ val16 |= B_AX_PTCL_DBG_EN; ++ rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); ++ seq_puts(m, "Enable PTCL C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PTCL_C1: ++ info = &dbg_port_ptcl_c1; ++ val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); ++ val16 |= B_AX_PTCL_DBG_EN; ++ rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); ++ seq_puts(m, "Enable PTCL C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_SCH_C0: ++ info = &dbg_port_sch_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); ++ val32 |= B_AX_SCH_DBG_EN; ++ rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); ++ seq_puts(m, "Enable SCH C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_SCH_C1: ++ info = &dbg_port_sch_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); ++ val32 |= B_AX_SCH_DBG_EN; ++ rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); ++ seq_puts(m, "Enable SCH C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TMAC_C0: ++ info = &dbg_port_tmac_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TMAC C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TMAC_C1: ++ info = &dbg_port_tmac_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TMAC C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_C0: ++ info = &dbg_port_rmac_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ ++ val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); ++ val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); ++ seq_puts(m, "Enable RMAC C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_C1: ++ info = &dbg_port_rmac_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); ++ val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ ++ val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); ++ val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, ++ B_AX_DBGSEL_TRXPTCL_MASK); ++ rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); ++ seq_puts(m, "Enable RMAC C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMACST_C0: ++ info = &dbg_port_rmacst_c0; ++ seq_puts(m, "Enable RMAC state C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMACST_C1: ++ info = &dbg_port_rmacst_c1; ++ seq_puts(m, "Enable RMAC state C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: ++ info = &dbg_port_rmac_plcp_c0; ++ seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: ++ info = &dbg_port_rmac_plcp_c1; ++ seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TRXPTCL_C0: ++ info = &dbg_port_trxptcl_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TRXPTCL_C1: ++ info = &dbg_port_trxptcl_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ ++ val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); ++ val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); ++ rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); ++ seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOL_C0: ++ info = &dbg_port_tx_infol_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOH_C0: ++ info = &dbg_port_tx_infoh_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOL_C1: ++ info = &dbg_port_tx_infol_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TX_INFOH_C1: ++ info = &dbg_port_tx_infoh_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: ++ info = &dbg_port_txtf_infol_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx tf infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: ++ info = &dbg_port_txtf_infoh_c0; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1, val32); ++ seq_puts(m, "Enable tx tf infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: ++ info = &dbg_port_txtf_infol_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx tf infol dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: ++ info = &dbg_port_txtf_infoh_c1; ++ val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); ++ val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; ++ rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); ++ seq_puts(m, "Enable tx tf infoh dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: ++ info = &dbg_port_wde_bufmgn_freepg; ++ seq_puts(m, "Enable wde bufmgn freepg dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: ++ info = &dbg_port_wde_bufmgn_quota; ++ seq_puts(m, "Enable wde bufmgn quota dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: ++ info = &dbg_port_wde_bufmgn_pagellt; ++ seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: ++ info = &dbg_port_wde_bufmgn_pktinfo; ++ seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: ++ info = &dbg_port_wde_quemgn_prepkt; ++ seq_puts(m, "Enable wde quemgn prepkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: ++ info = &dbg_port_wde_quemgn_nxtpkt; ++ seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: ++ info = &dbg_port_wde_quemgn_qlnktbl; ++ seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: ++ info = &dbg_port_wde_quemgn_qempty; ++ seq_puts(m, "Enable wde quemgn qempty dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: ++ info = &dbg_port_ple_bufmgn_freepg; ++ seq_puts(m, "Enable ple bufmgn freepg dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: ++ info = &dbg_port_ple_bufmgn_quota; ++ seq_puts(m, "Enable ple bufmgn quota dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: ++ info = &dbg_port_ple_bufmgn_pagellt; ++ seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: ++ info = &dbg_port_ple_bufmgn_pktinfo; ++ seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: ++ info = &dbg_port_ple_quemgn_prepkt; ++ seq_puts(m, "Enable ple quemgn prepkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: ++ info = &dbg_port_ple_quemgn_nxtpkt; ++ seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: ++ info = &dbg_port_ple_quemgn_qlnktbl; ++ seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: ++ info = &dbg_port_ple_quemgn_qempty; ++ seq_puts(m, "Enable ple quemgn qempty dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PKTINFO: ++ info = &dbg_port_pktinfo; ++ seq_puts(m, "Enable pktinfo dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_TXDMA: ++ info = &dbg_port_pcie_txdma; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie txdma dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_RXDMA: ++ info = &dbg_port_pcie_rxdma; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie rxdma dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_CVT: ++ info = &dbg_port_pcie_cvt; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie cvt dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_CXPL: ++ info = &dbg_port_pcie_cxpl; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie cxpl dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_IO: ++ info = &dbg_port_pcie_io; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie io dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_MISC: ++ info = &dbg_port_pcie_misc; ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); ++ val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); ++ val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); ++ seq_puts(m, "Enable pcie misc dump.\n"); ++ break; ++ case RTW89_DBG_PORT_SEL_PCIE_MISC2: ++ info = &dbg_port_pcie_misc2; ++ val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); ++ val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, ++ B_AX_DBG_SEL_MASK); ++ rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); ++ seq_puts(m, "Enable pcie misc2 dump.\n"); ++ break; ++ default: ++ seq_puts(m, "Dbg port select err\n"); ++ return NULL; ++ } ++ ++ return info; ++} ++ ++static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) ++{ ++ if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && ++ sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && ++ sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) ++ return false; ++ if (rtwdev->chip->chip_id == RTL8852B && ++ sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && ++ sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) ++ return false; ++ if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && ++ sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && ++ sel <= RTW89_DBG_PORT_SEL_PKTINFO) ++ return false; ++ if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && ++ sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && ++ sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) ++ return false; ++ if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && ++ sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && ++ sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) ++ return false; ++ ++ return true; ++} ++ ++static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, ++ struct seq_file *m, u32 sel) ++{ ++ const struct rtw89_mac_dbg_port_info *info; ++ u8 val8; ++ u16 val16; ++ u32 val32; ++ u32 i; ++ ++ info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); ++ if (!info) { ++ rtw89_err(rtwdev, "failed to select debug port %d\n", sel); ++ return -EINVAL; ++ } ++ ++#define case_DBG_SEL(__sel) \ ++ case RTW89_DBG_PORT_SEL_##__sel: \ ++ seq_puts(m, "Dump debug port " #__sel ":\n"); \ ++ break ++ ++ switch (sel) { ++ case_DBG_SEL(PTCL_C0); ++ case_DBG_SEL(PTCL_C1); ++ case_DBG_SEL(SCH_C0); ++ case_DBG_SEL(SCH_C1); ++ case_DBG_SEL(TMAC_C0); ++ case_DBG_SEL(TMAC_C1); ++ case_DBG_SEL(RMAC_C0); ++ case_DBG_SEL(RMAC_C1); ++ case_DBG_SEL(RMACST_C0); ++ case_DBG_SEL(RMACST_C1); ++ case_DBG_SEL(TRXPTCL_C0); ++ case_DBG_SEL(TRXPTCL_C1); ++ case_DBG_SEL(TX_INFOL_C0); ++ case_DBG_SEL(TX_INFOH_C0); ++ case_DBG_SEL(TX_INFOL_C1); ++ case_DBG_SEL(TX_INFOH_C1); ++ case_DBG_SEL(TXTF_INFOL_C0); ++ case_DBG_SEL(TXTF_INFOH_C0); ++ case_DBG_SEL(TXTF_INFOL_C1); ++ case_DBG_SEL(TXTF_INFOH_C1); ++ case_DBG_SEL(WDE_BUFMGN_FREEPG); ++ case_DBG_SEL(WDE_BUFMGN_QUOTA); ++ case_DBG_SEL(WDE_BUFMGN_PAGELLT); ++ case_DBG_SEL(WDE_BUFMGN_PKTINFO); ++ case_DBG_SEL(WDE_QUEMGN_PREPKT); ++ case_DBG_SEL(WDE_QUEMGN_NXTPKT); ++ case_DBG_SEL(WDE_QUEMGN_QLNKTBL); ++ case_DBG_SEL(WDE_QUEMGN_QEMPTY); ++ case_DBG_SEL(PLE_BUFMGN_FREEPG); ++ case_DBG_SEL(PLE_BUFMGN_QUOTA); ++ case_DBG_SEL(PLE_BUFMGN_PAGELLT); ++ case_DBG_SEL(PLE_BUFMGN_PKTINFO); ++ case_DBG_SEL(PLE_QUEMGN_PREPKT); ++ case_DBG_SEL(PLE_QUEMGN_NXTPKT); ++ case_DBG_SEL(PLE_QUEMGN_QLNKTBL); ++ case_DBG_SEL(PLE_QUEMGN_QEMPTY); ++ case_DBG_SEL(PKTINFO); ++ case_DBG_SEL(PCIE_TXDMA); ++ case_DBG_SEL(PCIE_RXDMA); ++ case_DBG_SEL(PCIE_CVT); ++ case_DBG_SEL(PCIE_CXPL); ++ case_DBG_SEL(PCIE_IO); ++ case_DBG_SEL(PCIE_MISC); ++ case_DBG_SEL(PCIE_MISC2); ++ } ++ ++#undef case_DBG_SEL ++ ++ seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); ++ seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); ++ ++ for (i = info->srt; i <= info->end; i++) { ++ switch (info->sel_byte) { ++ case 1: ++ default: ++ rtw89_write8_mask(rtwdev, info->sel_addr, ++ info->sel_msk, i); ++ seq_printf(m, "0x%02X: ", i); ++ break; ++ case 2: ++ rtw89_write16_mask(rtwdev, info->sel_addr, ++ info->sel_msk, i); ++ seq_printf(m, "0x%04X: ", i); ++ break; ++ case 4: ++ rtw89_write32_mask(rtwdev, info->sel_addr, ++ info->sel_msk, i); ++ seq_printf(m, "0x%04X: ", i); ++ break; ++ } ++ ++ udelay(10); ++ ++ switch (info->rd_byte) { ++ case 1: ++ default: ++ val8 = rtw89_read8_mask(rtwdev, ++ info->rd_addr, info->rd_msk); ++ seq_printf(m, "0x%02X\n", val8); ++ break; ++ case 2: ++ val16 = rtw89_read16_mask(rtwdev, ++ info->rd_addr, info->rd_msk); ++ seq_printf(m, "0x%04X\n", val16); ++ break; ++ case 4: ++ val32 = rtw89_read32_mask(rtwdev, ++ info->rd_addr, info->rd_msk); ++ seq_printf(m, "0x%08X\n", val32); ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, ++ struct seq_file *m) ++{ ++ u32 sel; ++ int ret = 0; ++ ++ for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; ++ sel < RTW89_DBG_PORT_SEL_LAST; sel++) { ++ if (!is_dbg_port_valid(rtwdev, sel)) ++ continue; ++ ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); ++ if (ret) { ++ rtw89_err(rtwdev, ++ "failed to dump debug port %d\n", sel); ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static int ++rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ ++ if (debugfs_priv->dbgpkg_en.ss_dbg) ++ rtw89_debug_mac_dump_ss_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.dle_dbg) ++ rtw89_debug_mac_dump_dle_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.dmac_dbg) ++ rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.cmac_dbg) ++ rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); ++ if (debugfs_priv->dbgpkg_en.dbg_port) ++ rtw89_debug_mac_dump_dbg_port(rtwdev, m); ++ ++ return 0; ++}; ++ ++static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, ++ const char __user *user_buf, size_t count) ++{ ++ char *buf; ++ u8 *bin; ++ int num; ++ int err = 0; ++ ++ buf = memdup_user(user_buf, count); ++ if (IS_ERR(buf)) ++ return buf; ++ ++ num = count / 2; ++ bin = kmalloc(num, GFP_KERNEL); ++ if (!bin) { ++ err = -EFAULT; ++ goto out; ++ } ++ ++ if (hex2bin(bin, buf, num)) { ++ rtw89_info(rtwdev, "valid format: H1H2H3...\n"); ++ kfree(bin); ++ err = -EINVAL; ++ } ++ ++out: ++ kfree(buf); ++ ++ return err ? ERR_PTR(err) : bin; ++} ++ ++static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ u8 *h2c; ++ u16 h2c_len = count / 2; ++ ++ h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); ++ if (IS_ERR(h2c)) ++ return -EFAULT; ++ ++ rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); ++ ++ kfree(h2c); ++ ++ return count; ++} ++ ++static int ++rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_early_h2c *early_h2c; ++ int seq = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) ++ seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ssize_t ++rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct seq_file *m = (struct seq_file *)filp->private_data; ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_early_h2c *early_h2c; ++ u8 *h2c; ++ u16 h2c_len = count / 2; ++ ++ h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); ++ if (IS_ERR(h2c)) ++ return -EFAULT; ++ ++ if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { ++ kfree(h2c); ++ rtw89_fw_free_all_early_h2c(rtwdev); ++ goto out; ++ } ++ ++ early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); ++ if (!early_h2c) { ++ kfree(h2c); ++ return -EFAULT; ++ } ++ ++ early_h2c->h2c = h2c; ++ early_h2c->h2c_len = h2c_len; ++ ++ mutex_lock(&rtwdev->mutex); ++ list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); ++ mutex_unlock(&rtwdev->mutex); ++ ++out: ++ return count; ++} ++ ++static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ ++ rtw89_btc_dump_info(rtwdev, m); ++ ++ return 0; ++} ++ ++static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_btc *btc = &rtwdev->btc; ++ bool btc_manual; ++ ++ if (kstrtobool_from_user(user_buf, count, &btc_manual)) ++ goto out; ++ ++ btc->ctrl.manual = btc_manual; ++out: ++ return count; ++} ++ ++static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, ++ const char __user *user_buf, ++ size_t count, loff_t *loff) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ bool fw_log_manual; ++ ++ if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) ++ goto out; ++ ++ mutex_lock(&rtwdev->mutex); ++ fw_info->fw_log_enable = fw_log_manual; ++ rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); ++ mutex_unlock(&rtwdev->mutex); ++out: ++ return count; ++} ++ ++static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) ++{ ++ static const char * const he_gi_str[] = { ++ [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", ++ [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", ++ [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", ++ }; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rate_info *rate = &rtwsta->ra_report.txrate; ++ struct ieee80211_rx_status *status = &rtwsta->rx_status; ++ struct seq_file *m = (struct seq_file *)data; ++ u8 rssi; ++ ++ seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); ++ ++ if (rate->flags & RATE_INFO_FLAGS_MCS) ++ seq_printf(m, "HT MCS-%d%s", rate->mcs, ++ rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); ++ else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) ++ seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, ++ rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); ++ else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) ++ seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, ++ rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? ++ he_gi_str[rate->he_gi] : "N/A"); ++ else ++ seq_printf(m, "Legacy %d", rate->legacy); ++ seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); ++ seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, ++ sta->max_rc_amsdu_len); ++ ++ seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); ++ ++ switch (status->encoding) { ++ case RX_ENC_LEGACY: ++ seq_printf(m, "Legacy %d", status->rate_idx + ++ (status->band == NL80211_BAND_5GHZ ? 4 : 0)); ++ break; ++ case RX_ENC_HT: ++ seq_printf(m, "HT MCS-%d%s", status->rate_idx, ++ status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); ++ break; ++ case RX_ENC_VHT: ++ seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, ++ status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); ++ break; ++ case RX_ENC_HE: ++ seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, ++ status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? ++ he_gi_str[rate->he_gi] : "N/A"); ++ break; ++ } ++ seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); ++ ++ rssi = ewma_rssi_read(&rtwsta->avg_rssi); ++ seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", ++ RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); ++} ++ ++static void ++rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, ++ enum rtw89_hw_rate first_rate, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) ++ seq_printf(m, "%s%u", i == 0 ? "" : ", ", ++ pkt_stat->rx_rate_cnt[first_rate + i]); ++} ++ ++static const struct rtw89_rx_rate_cnt_info { ++ enum rtw89_hw_rate first_rate; ++ int len; ++ const char *rate_mode; ++} rtw89_rx_rate_cnt_infos[] = { ++ {RTW89_HW_RATE_CCK1, 4, "Legacy:"}, ++ {RTW89_HW_RATE_OFDM6, 8, "OFDM:"}, ++ {RTW89_HW_RATE_MCS0, 8, "HT 0:"}, ++ {RTW89_HW_RATE_MCS8, 8, "HT 1:"}, ++ {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, "VHT 1SS:"}, ++ {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, "VHT 2SS:"}, ++ {RTW89_HW_RATE_HE_NSS1_MCS0, 12, "HE 1SS:"}, ++ {RTW89_HW_RATE_HE_NSS2_MCS0, 12, "HE 2ss:"}, ++}; ++ ++static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) ++{ ++ struct rtw89_debugfs_priv *debugfs_priv = m->private; ++ struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; ++ const struct rtw89_rx_rate_cnt_info *info; ++ int i; ++ ++ seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", ++ stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, ++ stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); ++ seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr); ++ seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, ++ stats->rx_avg_len); ++ ++ seq_puts(m, "RX count:\n"); ++ for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { ++ info = &rtw89_rx_rate_cnt_infos[i]; ++ seq_printf(m, "%10s [", info->rate_mode); ++ rtw89_debug_append_rx_rate(m, pkt_stat, ++ info->first_rate, info->len); ++ seq_puts(m, "]\n"); ++ } ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); ++ ++ return 0; ++} ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { ++ .cb_read = rtw89_debug_priv_read_reg_get, ++ .cb_write = rtw89_debug_priv_read_reg_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { ++ .cb_write = rtw89_debug_priv_write_reg_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { ++ .cb_read = rtw89_debug_priv_read_rf_get, ++ .cb_write = rtw89_debug_priv_read_rf_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { ++ .cb_write = rtw89_debug_priv_write_rf_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { ++ .cb_read = rtw89_debug_priv_rf_reg_dump_get, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { ++ .cb_read = rtw89_debug_priv_txpwr_table_get, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { ++ .cb_read = rtw89_debug_priv_mac_reg_dump_get, ++ .cb_write = rtw89_debug_priv_mac_reg_dump_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { ++ .cb_read = rtw89_debug_priv_mac_mem_dump_get, ++ .cb_write = rtw89_debug_priv_mac_mem_dump_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { ++ .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, ++ .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { ++ .cb_write = rtw89_debug_priv_send_h2c_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { ++ .cb_read = rtw89_debug_priv_early_h2c_get, ++ .cb_write = rtw89_debug_priv_early_h2c_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { ++ .cb_read = rtw89_debug_priv_btc_info_get, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { ++ .cb_write = rtw89_debug_priv_btc_manual_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { ++ .cb_write = rtw89_debug_fw_log_btc_manual_set, ++}; ++ ++static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { ++ .cb_read = rtw89_debug_priv_phy_info_get, ++}; ++ ++#define rtw89_debugfs_add(name, mode, fopname, parent) \ ++ do { \ ++ rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ ++ if (!debugfs_create_file(#name, mode, \ ++ parent, &rtw89_debug_priv_ ##name, \ ++ &file_ops_ ##fopname)) \ ++ pr_debug("Unable to initialize debugfs:%s\n", #name); \ ++ } while (0) ++ ++#define rtw89_debugfs_add_w(name) \ ++ rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) ++#define rtw89_debugfs_add_rw(name) \ ++ rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) ++#define rtw89_debugfs_add_r(name) \ ++ rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) ++ ++void rtw89_debugfs_init(struct rtw89_dev *rtwdev) ++{ ++ struct dentry *debugfs_topdir; ++ ++ debugfs_topdir = debugfs_create_dir("rtw89", ++ rtwdev->hw->wiphy->debugfsdir); ++ ++ rtw89_debugfs_add_rw(read_reg); ++ rtw89_debugfs_add_w(write_reg); ++ rtw89_debugfs_add_rw(read_rf); ++ rtw89_debugfs_add_w(write_rf); ++ rtw89_debugfs_add_r(rf_reg_dump); ++ rtw89_debugfs_add_r(txpwr_table); ++ rtw89_debugfs_add_rw(mac_reg_dump); ++ rtw89_debugfs_add_rw(mac_mem_dump); ++ rtw89_debugfs_add_rw(mac_dbg_port_dump); ++ rtw89_debugfs_add_w(send_h2c); ++ rtw89_debugfs_add_rw(early_h2c); ++ rtw89_debugfs_add_r(btc_info); ++ rtw89_debugfs_add_w(btc_manual); ++ rtw89_debugfs_add_w(fw_log_manual); ++ rtw89_debugfs_add_r(phy_info); ++} ++#endif ++ ++#ifdef CONFIG_RTW89_DEBUGMSG ++void __rtw89_debug(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *fmt, ...) ++{ ++ struct va_format vaf = { ++ .fmt = fmt, ++ }; ++ ++ va_list args; ++ ++ va_start(args, fmt); ++ vaf.va = &args; ++ ++ if (rtw89_debug_mask & mask) ++ dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); ++ ++ va_end(args); ++} ++EXPORT_SYMBOL(__rtw89_debug); ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/debug.h b/drivers/net/wireless/realtek/rtw89/debug.h +new file mode 100644 +index 000000000000..f14b726c1a9f +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/debug.h +@@ -0,0 +1,77 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_DEBUG_H__ ++#define __RTW89_DEBUG_H__ ++ ++#include "core.h" ++ ++enum rtw89_debug_mask { ++ RTW89_DBG_TXRX = BIT(0), ++ RTW89_DBG_RFK = BIT(1), ++ RTW89_DBG_RFK_TRACK = BIT(2), ++ RTW89_DBG_CFO = BIT(3), ++ RTW89_DBG_TSSI = BIT(4), ++ RTW89_DBG_TXPWR = BIT(5), ++ RTW89_DBG_HCI = BIT(6), ++ RTW89_DBG_RA = BIT(7), ++ RTW89_DBG_REGD = BIT(8), ++ RTW89_DBG_PHY_TRACK = BIT(9), ++ RTW89_DBG_DIG = BIT(10), ++ RTW89_DBG_SER = BIT(11), ++ RTW89_DBG_FW = BIT(12), ++ RTW89_DBG_BTC = BIT(13), ++ RTW89_DBG_BF = BIT(14), ++}; ++ ++enum rtw89_debug_mac_reg_sel { ++ RTW89_DBG_SEL_MAC_00, ++ RTW89_DBG_SEL_MAC_40, ++ RTW89_DBG_SEL_MAC_80, ++ RTW89_DBG_SEL_MAC_C0, ++ RTW89_DBG_SEL_MAC_E0, ++ RTW89_DBG_SEL_BB, ++ RTW89_DBG_SEL_IQK, ++ RTW89_DBG_SEL_RFC, ++}; ++ ++#ifdef CONFIG_RTW89_DEBUGFS ++void rtw89_debugfs_init(struct rtw89_dev *rtwdev); ++#else ++static inline void rtw89_debugfs_init(struct rtw89_dev *rtwdev) {} ++#endif ++ ++#define rtw89_info(rtwdev, a...) dev_info((rtwdev)->dev, ##a) ++#define rtw89_warn(rtwdev, a...) dev_warn((rtwdev)->dev, ##a) ++#define rtw89_err(rtwdev, a...) dev_err((rtwdev)->dev, ##a) ++ ++#ifdef CONFIG_RTW89_DEBUGMSG ++extern unsigned int rtw89_debug_mask; ++#define rtw89_debug(rtwdev, a...) __rtw89_debug(rtwdev, ##a) ++ ++__printf(3, 4) ++void __rtw89_debug(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *fmt, ...); ++static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *prefix_str, ++ const void *buf, size_t len) ++{ ++ if (!(rtw89_debug_mask & mask)) ++ return; ++ ++ print_hex_dump_bytes(prefix_str, DUMP_PREFIX_OFFSET, buf, len); ++} ++#else ++static inline void rtw89_debug(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *fmt, ...) {} ++static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev, ++ enum rtw89_debug_mask mask, ++ const char *prefix_str, ++ const void *buf, size_t len) {} ++#endif ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/efuse.c b/drivers/net/wireless/realtek/rtw89/efuse.c +new file mode 100644 +index 000000000000..c0b80f3da56c +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/efuse.c +@@ -0,0 +1,188 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "efuse.h" ++#include "reg.h" ++ ++enum rtw89_efuse_bank { ++ RTW89_EFUSE_BANK_WIFI, ++ RTW89_EFUSE_BANK_BT, ++}; ++ ++static int rtw89_switch_efuse_bank(struct rtw89_dev *rtwdev, ++ enum rtw89_efuse_bank bank) ++{ ++ u8 val; ++ ++ val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1, ++ B_AX_EF_CELL_SEL_MASK); ++ if (bank == val) ++ return 0; ++ ++ rtw89_write32_mask(rtwdev, R_AX_EFUSE_CTRL_1, B_AX_EF_CELL_SEL_MASK, ++ bank); ++ ++ val = rtw89_read32_mask(rtwdev, R_AX_EFUSE_CTRL_1, ++ B_AX_EF_CELL_SEL_MASK); ++ if (bank == val) ++ return 0; ++ ++ return -EBUSY; ++} ++ ++static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map, ++ u32 dump_addr, u32 dump_size) ++{ ++ u32 efuse_ctl; ++ u32 addr; ++ int ret; ++ ++ rtw89_switch_efuse_bank(rtwdev, RTW89_EFUSE_BANK_WIFI); ++ ++ for (addr = dump_addr; addr < dump_addr + dump_size; addr++) { ++ efuse_ctl = u32_encode_bits(addr, B_AX_EF_ADDR_MASK); ++ rtw89_write32(rtwdev, R_AX_EFUSE_CTRL, efuse_ctl & ~B_AX_EF_RDY); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, efuse_ctl, ++ efuse_ctl & B_AX_EF_RDY, 1, 1000000, ++ true, rtwdev, R_AX_EFUSE_CTRL); ++ if (ret) ++ return -EBUSY; ++ ++ *map++ = (u8)(efuse_ctl & 0xff); ++ } ++ ++ return 0; ++} ++ ++#define invalid_efuse_header(hdr1, hdr2) \ ++ ((hdr1) == 0xff || (hdr2) == 0xff) ++#define invalid_efuse_content(word_en, i) \ ++ (((word_en) & BIT(i)) != 0x0) ++#define get_efuse_blk_idx(hdr1, hdr2) \ ++ ((((hdr2) & 0xf0) >> 4) | (((hdr1) & 0x0f) << 4)) ++#define block_idx_to_logical_idx(blk_idx, i) \ ++ (((blk_idx) << 3) + ((i) << 1)) ++static int rtw89_dump_logical_efuse_map(struct rtw89_dev *rtwdev, u8 *phy_map, ++ u8 *log_map) ++{ ++ u32 physical_size = rtwdev->chip->physical_efuse_size; ++ u32 logical_size = rtwdev->chip->logical_efuse_size; ++ u8 sec_ctrl_size = rtwdev->chip->sec_ctrl_efuse_size; ++ u32 phy_idx = sec_ctrl_size; ++ u32 log_idx; ++ u8 hdr1, hdr2; ++ u8 blk_idx; ++ u8 word_en; ++ int i; ++ ++ while (phy_idx < physical_size - sec_ctrl_size) { ++ hdr1 = phy_map[phy_idx]; ++ hdr2 = phy_map[phy_idx + 1]; ++ if (invalid_efuse_header(hdr1, hdr2)) ++ break; ++ ++ blk_idx = get_efuse_blk_idx(hdr1, hdr2); ++ word_en = hdr2 & 0xf; ++ phy_idx += 2; ++ ++ for (i = 0; i < 4; i++) { ++ if (invalid_efuse_content(word_en, i)) ++ continue; ++ ++ log_idx = block_idx_to_logical_idx(blk_idx, i); ++ if (phy_idx + 1 > physical_size - sec_ctrl_size - 1 || ++ log_idx + 1 > logical_size) ++ return -EINVAL; ++ ++ log_map[log_idx] = phy_map[phy_idx]; ++ log_map[log_idx + 1] = phy_map[phy_idx + 1]; ++ phy_idx += 2; ++ } ++ } ++ return 0; ++} ++ ++int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev) ++{ ++ u32 phy_size = rtwdev->chip->physical_efuse_size; ++ u32 log_size = rtwdev->chip->logical_efuse_size; ++ u8 *phy_map = NULL; ++ u8 *log_map = NULL; ++ int ret; ++ ++ if (rtw89_read16(rtwdev, R_AX_SYS_WL_EFUSE_CTRL) & B_AX_AUTOLOAD_SUS) ++ rtwdev->efuse.valid = true; ++ else ++ rtw89_warn(rtwdev, "failed to check efuse autoload\n"); ++ ++ phy_map = kmalloc(phy_size, GFP_KERNEL); ++ log_map = kmalloc(log_size, GFP_KERNEL); ++ ++ if (!phy_map || !log_map) { ++ ret = -ENOMEM; ++ goto out_free; ++ } ++ ++ ret = rtw89_dump_physical_efuse_map(rtwdev, phy_map, 0, phy_size); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to dump efuse physical map\n"); ++ goto out_free; ++ } ++ ++ memset(log_map, 0xff, log_size); ++ ret = rtw89_dump_logical_efuse_map(rtwdev, phy_map, log_map); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to dump efuse logical map\n"); ++ goto out_free; ++ } ++ ++ rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "log_map: ", log_map, log_size); ++ ++ ret = rtwdev->chip->ops->read_efuse(rtwdev, log_map); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to read efuse map\n"); ++ goto out_free; ++ } ++ ++out_free: ++ kfree(log_map); ++ kfree(phy_map); ++ ++ return ret; ++} ++ ++int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev) ++{ ++ u32 phycap_addr = rtwdev->chip->phycap_addr; ++ u32 phycap_size = rtwdev->chip->phycap_size; ++ u8 *phycap_map = NULL; ++ int ret = 0; ++ ++ if (!phycap_size) ++ return 0; ++ ++ phycap_map = kmalloc(phycap_size, GFP_KERNEL); ++ if (!phycap_map) ++ return -ENOMEM; ++ ++ ret = rtw89_dump_physical_efuse_map(rtwdev, phycap_map, ++ phycap_addr, phycap_size); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to dump phycap map\n"); ++ goto out_free; ++ } ++ ++ ret = rtwdev->chip->ops->read_phycap(rtwdev, phycap_map); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to read phycap map\n"); ++ goto out_free; ++ } ++ ++out_free: ++ kfree(phycap_map); ++ ++ return ret; ++} +diff --git a/drivers/net/wireless/realtek/rtw89/efuse.h b/drivers/net/wireless/realtek/rtw89/efuse.h +new file mode 100644 +index 000000000000..622ff95e7476 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/efuse.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_EFUSE_H__ ++#define __RTW89_EFUSE_H__ ++ ++#include "core.h" ++ ++int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev); ++int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c +new file mode 100644 +index 000000000000..212aaf577d3c +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/fw.c +@@ -0,0 +1,1641 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "phy.h" ++#include "reg.h" ++ ++static struct sk_buff *rtw89_fw_h2c_alloc_skb(u32 len, bool header) ++{ ++ struct sk_buff *skb; ++ u32 header_len = 0; ++ ++ if (header) ++ header_len = H2C_HEADER_LEN; ++ ++ skb = dev_alloc_skb(len + header_len + 24); ++ if (!skb) ++ return NULL; ++ skb_reserve(skb, header_len + 24); ++ memset(skb->data, 0, len); ++ ++ return skb; ++} ++ ++struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len) ++{ ++ return rtw89_fw_h2c_alloc_skb(len, true); ++} ++ ++struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len) ++{ ++ return rtw89_fw_h2c_alloc_skb(len, false); ++} ++ ++static u8 _fw_get_rdy(struct rtw89_dev *rtwdev) ++{ ++ u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); ++ ++ return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); ++} ++ ++#define FWDL_WAIT_CNT 400000 ++int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev) ++{ ++ u8 val; ++ int ret; ++ ++ ret = read_poll_timeout_atomic(_fw_get_rdy, val, ++ val == RTW89_FWDL_WCPU_FW_INIT_RDY, ++ 1, FWDL_WAIT_CNT, false, rtwdev); ++ if (ret) { ++ switch (val) { ++ case RTW89_FWDL_CHECKSUM_FAIL: ++ rtw89_err(rtwdev, "fw checksum fail\n"); ++ return -EINVAL; ++ ++ case RTW89_FWDL_SECURITY_FAIL: ++ rtw89_err(rtwdev, "fw security fail\n"); ++ return -EINVAL; ++ ++ case RTW89_FWDL_CV_NOT_MATCH: ++ rtw89_err(rtwdev, "fw cv not match\n"); ++ return -EINVAL; ++ ++ default: ++ return -EBUSY; ++ } ++ } ++ ++ set_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); ++ ++ return 0; ++} ++ ++static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len, ++ struct rtw89_fw_bin_info *info) ++{ ++ struct rtw89_fw_hdr_section_info *section_info; ++ const u8 *fw_end = fw + len; ++ const u8 *bin; ++ u32 i; ++ ++ if (!info) ++ return -EINVAL; ++ ++ info->section_num = GET_FW_HDR_SEC_NUM(fw); ++ info->hdr_len = RTW89_FW_HDR_SIZE + ++ info->section_num * RTW89_FW_SECTION_HDR_SIZE; ++ SET_FW_HDR_PART_SIZE(fw, FWDL_SECTION_PER_PKT_LEN); ++ ++ bin = fw + info->hdr_len; ++ ++ /* jump to section header */ ++ fw += RTW89_FW_HDR_SIZE; ++ section_info = info->section_info; ++ for (i = 0; i < info->section_num; i++) { ++ section_info->len = GET_FWSECTION_HDR_SEC_SIZE(fw); ++ if (GET_FWSECTION_HDR_CHECKSUM(fw)) ++ section_info->len += FWDL_SECTION_CHKSUM_LEN; ++ section_info->redl = GET_FWSECTION_HDR_REDL(fw); ++ section_info->dladdr = ++ GET_FWSECTION_HDR_DL_ADDR(fw) & 0x1fffffff; ++ section_info->addr = bin; ++ bin += section_info->len; ++ fw += RTW89_FW_SECTION_HDR_SIZE; ++ section_info++; ++ } ++ ++ if (fw_end != bin) { ++ rtw89_err(rtwdev, "[ERR]fw bin size\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static ++int rtw89_mfw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type, ++ struct rtw89_fw_suit *fw_suit) ++{ ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ const u8 *mfw = fw_info->firmware->data; ++ u32 mfw_len = fw_info->firmware->size; ++ const struct rtw89_mfw_hdr *mfw_hdr = (const struct rtw89_mfw_hdr *)mfw; ++ const struct rtw89_mfw_info *mfw_info; ++ int i; ++ ++ if (mfw_hdr->sig != RTW89_MFW_SIG) { ++ rtw89_debug(rtwdev, RTW89_DBG_FW, "use legacy firmware\n"); ++ /* legacy firmware support normal type only */ ++ if (type != RTW89_FW_NORMAL) ++ return -EINVAL; ++ fw_suit->data = mfw; ++ fw_suit->size = mfw_len; ++ return 0; ++ } ++ ++ for (i = 0; i < mfw_hdr->fw_nr; i++) { ++ mfw_info = &mfw_hdr->info[i]; ++ if (mfw_info->cv != rtwdev->hal.cv || ++ mfw_info->type != type || ++ mfw_info->mp) ++ continue; ++ ++ fw_suit->data = mfw + le32_to_cpu(mfw_info->shift); ++ fw_suit->size = le32_to_cpu(mfw_info->size); ++ return 0; ++ } ++ ++ rtw89_err(rtwdev, "no suitable firmware found\n"); ++ return -ENOENT; ++} ++ ++static void rtw89_fw_update_ver(struct rtw89_dev *rtwdev, ++ enum rtw89_fw_type type, ++ struct rtw89_fw_suit *fw_suit) ++{ ++ const u8 *hdr = fw_suit->data; ++ ++ fw_suit->major_ver = GET_FW_HDR_MAJOR_VERSION(hdr); ++ fw_suit->minor_ver = GET_FW_HDR_MINOR_VERSION(hdr); ++ fw_suit->sub_ver = GET_FW_HDR_SUBVERSION(hdr); ++ fw_suit->sub_idex = GET_FW_HDR_SUBINDEX(hdr); ++ fw_suit->build_year = GET_FW_HDR_YEAR(hdr); ++ fw_suit->build_mon = GET_FW_HDR_MONTH(hdr); ++ fw_suit->build_date = GET_FW_HDR_DATE(hdr); ++ fw_suit->build_hour = GET_FW_HDR_HOUR(hdr); ++ fw_suit->build_min = GET_FW_HDR_MIN(hdr); ++ fw_suit->cmd_ver = GET_FW_HDR_CMD_VERSERION(hdr); ++ ++ rtw89_info(rtwdev, ++ "Firmware version %u.%u.%u.%u, cmd version %u, type %u\n", ++ fw_suit->major_ver, fw_suit->minor_ver, fw_suit->sub_ver, ++ fw_suit->sub_idex, fw_suit->cmd_ver, type); ++} ++ ++static ++int __rtw89_fw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type) ++{ ++ struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type); ++ int ret; ++ ++ ret = rtw89_mfw_recognize(rtwdev, type, fw_suit); ++ if (ret) ++ return ret; ++ ++ rtw89_fw_update_ver(rtwdev, type, fw_suit); ++ ++ return 0; ++} ++ ++static void rtw89_fw_recognize_features(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, RTW89_FW_NORMAL); ++ ++ if (chip->chip_id == RTL8852A && ++ RTW89_FW_SUIT_VER_CODE(fw_suit) <= RTW89_FW_VER_CODE(0, 13, 29, 0)) ++ rtwdev->fw.old_ht_ra_format = true; ++} ++ ++int rtw89_fw_recognize(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = __rtw89_fw_recognize(rtwdev, RTW89_FW_NORMAL); ++ if (ret) ++ return ret; ++ ++ /* It still works if wowlan firmware isn't existing. */ ++ __rtw89_fw_recognize(rtwdev, RTW89_FW_WOWLAN); ++ ++ rtw89_fw_recognize_features(rtwdev); ++ ++ return 0; ++} ++ ++void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u8 type, u8 cat, u8 class, u8 func, ++ bool rack, bool dack, u32 len) ++{ ++ struct fwcmd_hdr *hdr; ++ ++ hdr = (struct fwcmd_hdr *)skb_push(skb, 8); ++ ++ if (!(rtwdev->fw.h2c_seq % 4)) ++ rack = true; ++ hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) | ++ FIELD_PREP(H2C_HDR_CAT, cat) | ++ FIELD_PREP(H2C_HDR_CLASS, class) | ++ FIELD_PREP(H2C_HDR_FUNC, func) | ++ FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq)); ++ ++ hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN, ++ len + H2C_HEADER_LEN) | ++ (rack ? H2C_HDR_REC_ACK : 0) | ++ (dack ? H2C_HDR_DONE_ACK : 0)); ++ ++ rtwdev->fw.h2c_seq++; ++} ++ ++static void rtw89_h2c_pkt_set_hdr_fwdl(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb, ++ u8 type, u8 cat, u8 class, u8 func, ++ u32 len) ++{ ++ struct fwcmd_hdr *hdr; ++ ++ hdr = (struct fwcmd_hdr *)skb_push(skb, 8); ++ ++ hdr->hdr0 = cpu_to_le32(FIELD_PREP(H2C_HDR_DEL_TYPE, type) | ++ FIELD_PREP(H2C_HDR_CAT, cat) | ++ FIELD_PREP(H2C_HDR_CLASS, class) | ++ FIELD_PREP(H2C_HDR_FUNC, func) | ++ FIELD_PREP(H2C_HDR_H2C_SEQ, rtwdev->fw.h2c_seq)); ++ ++ hdr->hdr1 = cpu_to_le32(FIELD_PREP(H2C_HDR_TOTAL_LEN, ++ len + H2C_HEADER_LEN)); ++} ++ ++static int __rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len) ++{ ++ struct sk_buff *skb; ++ u32 ret = 0; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw hdr dl\n"); ++ return -ENOMEM; ++ } ++ ++ skb_put_data(skb, fw, len); ++ rtw89_h2c_pkt_set_hdr_fwdl(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FWDL, ++ H2C_FUNC_MAC_FWHDR_DL, len); ++ ++ ret = rtw89_h2c_tx(rtwdev, skb, false); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ ret = -1; ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return ret; ++} ++ ++static int rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len) ++{ ++ u8 val; ++ int ret; ++ ++ ret = __rtw89_fw_download_hdr(rtwdev, fw, len); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]FW header download\n"); ++ return ret; ++ } ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, val, val & B_AX_FWDL_PATH_RDY, ++ 1, FWDL_WAIT_CNT, false, ++ rtwdev, R_AX_WCPU_FW_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]FWDL path ready\n"); ++ return ret; ++ } ++ ++ rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); ++ rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); ++ ++ return 0; ++} ++ ++static int __rtw89_fw_download_main(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_hdr_section_info *info) ++{ ++ struct sk_buff *skb; ++ const u8 *section = info->addr; ++ u32 residue_len = info->len; ++ u32 pkt_len; ++ int ret; ++ ++ while (residue_len) { ++ if (residue_len >= FWDL_SECTION_PER_PKT_LEN) ++ pkt_len = FWDL_SECTION_PER_PKT_LEN; ++ else ++ pkt_len = residue_len; ++ ++ skb = rtw89_fw_h2c_alloc_skb_no_hdr(pkt_len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, section, pkt_len); ++ ++ ret = rtw89_h2c_tx(rtwdev, skb, true); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ ret = -1; ++ goto fail; ++ } ++ ++ section += pkt_len; ++ residue_len -= pkt_len; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return ret; ++} ++ ++static int rtw89_fw_download_main(struct rtw89_dev *rtwdev, const u8 *fw, ++ struct rtw89_fw_bin_info *info) ++{ ++ struct rtw89_fw_hdr_section_info *section_info = info->section_info; ++ u8 section_num = info->section_num; ++ int ret; ++ ++ while (section_num--) { ++ ret = __rtw89_fw_download_main(rtwdev, section_info); ++ if (ret) ++ return ret; ++ section_info++; ++ } ++ ++ mdelay(5); ++ ++ ret = rtw89_fw_check_rdy(rtwdev); ++ if (ret) { ++ rtw89_warn(rtwdev, "download firmware fail\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rtw89_fw_prog_cnt_dump(struct rtw89_dev *rtwdev) ++{ ++ u32 val32; ++ u16 index; ++ ++ rtw89_write32(rtwdev, R_AX_DBG_CTRL, ++ FIELD_PREP(B_AX_DBG_SEL0, FW_PROG_CNTR_DBG_SEL) | ++ FIELD_PREP(B_AX_DBG_SEL1, FW_PROG_CNTR_DBG_SEL)); ++ rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_SEL_0XC0_MASK, MAC_DBG_SEL); ++ ++ for (index = 0; index < 15; index++) { ++ val32 = rtw89_read32(rtwdev, R_AX_DBG_PORT_SEL); ++ rtw89_err(rtwdev, "[ERR]fw PC = 0x%x\n", val32); ++ fsleep(10); ++ } ++} ++ ++static void rtw89_fw_dl_fail_dump(struct rtw89_dev *rtwdev) ++{ ++ u32 val32; ++ u16 val16; ++ ++ val32 = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); ++ rtw89_err(rtwdev, "[ERR]fwdl 0x1E0 = 0x%x\n", val32); ++ ++ val16 = rtw89_read16(rtwdev, R_AX_BOOT_DBG + 2); ++ rtw89_err(rtwdev, "[ERR]fwdl 0x83F2 = 0x%x\n", val16); ++ ++ rtw89_fw_prog_cnt_dump(rtwdev); ++} ++ ++int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type) ++{ ++ struct rtw89_fw_info *fw_info = &rtwdev->fw; ++ struct rtw89_fw_suit *fw_suit = rtw89_fw_suit_get(rtwdev, type); ++ struct rtw89_fw_bin_info info; ++ const u8 *fw = fw_suit->data; ++ u32 len = fw_suit->size; ++ u8 val; ++ int ret; ++ ++ if (!fw || !len) { ++ rtw89_err(rtwdev, "fw type %d isn't recognized\n", type); ++ return -ENOENT; ++ } ++ ++ ret = rtw89_fw_hdr_parser(rtwdev, fw, len, &info); ++ if (ret) { ++ rtw89_err(rtwdev, "parse fw header fail\n"); ++ goto fwdl_err; ++ } ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, val, val & B_AX_H2C_PATH_RDY, ++ 1, FWDL_WAIT_CNT, false, ++ rtwdev, R_AX_WCPU_FW_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]H2C path ready\n"); ++ goto fwdl_err; ++ } ++ ++ ret = rtw89_fw_download_hdr(rtwdev, fw, info.hdr_len); ++ if (ret) { ++ ret = -EBUSY; ++ goto fwdl_err; ++ } ++ ++ ret = rtw89_fw_download_main(rtwdev, fw, &info); ++ if (ret) { ++ ret = -EBUSY; ++ goto fwdl_err; ++ } ++ ++ fw_info->h2c_seq = 0; ++ fw_info->rec_seq = 0; ++ rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX; ++ rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX; ++ ++ return ret; ++ ++fwdl_err: ++ rtw89_fw_dl_fail_dump(rtwdev); ++ return ret; ++} ++ ++int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_fw_info *fw = &rtwdev->fw; ++ ++ wait_for_completion(&fw->completion); ++ if (!fw->firmware) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void rtw89_load_firmware_cb(const struct firmware *firmware, void *context) ++{ ++ struct rtw89_fw_info *fw = context; ++ struct rtw89_dev *rtwdev = fw->rtwdev; ++ ++ if (!firmware || !firmware->data) { ++ rtw89_err(rtwdev, "failed to request firmware\n"); ++ complete_all(&fw->completion); ++ return; ++ } ++ ++ fw->firmware = firmware; ++ complete_all(&fw->completion); ++} ++ ++int rtw89_load_firmware(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_fw_info *fw = &rtwdev->fw; ++ const char *fw_name = rtwdev->chip->fw_name; ++ int ret; ++ ++ fw->rtwdev = rtwdev; ++ init_completion(&fw->completion); ++ ++ ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, ++ GFP_KERNEL, fw, rtw89_load_firmware_cb); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to async firmware request\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++void rtw89_unload_firmware(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_fw_info *fw = &rtwdev->fw; ++ ++ rtw89_wait_firmware_completion(rtwdev); ++ ++ if (fw->firmware) ++ release_firmware(fw->firmware); ++} ++ ++#define H2C_CAM_LEN 60 ++int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CAM_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CAM_LEN); ++ rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, skb->data); ++ rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif, skb->data); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_ADDR_CAM_UPDATE, ++ H2C_FUNC_MAC_ADDR_CAM_UPD, 0, 1, ++ H2C_CAM_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_BA_CAM_LEN 4 ++int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, ++ struct ieee80211_ampdu_params *params) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_BA_CAM_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c ba cam\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_BA_CAM_LEN); ++ SET_BA_CAM_MACID(skb->data, macid); ++ if (!valid) ++ goto end; ++ SET_BA_CAM_VALID(skb->data, valid); ++ SET_BA_CAM_TID(skb->data, params->tid); ++ if (params->buf_size > 64) ++ SET_BA_CAM_BMAP_SIZE(skb->data, 4); ++ else ++ SET_BA_CAM_BMAP_SIZE(skb->data, 0); ++ /* If init req is set, hw will set the ssn */ ++ SET_BA_CAM_INIT_REQ(skb->data, 0); ++ SET_BA_CAM_SSN(skb->data, params->ssn); ++ ++end: ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_BA_CAM, ++ H2C_FUNC_MAC_BA_CAM, 0, 1, ++ H2C_BA_CAM_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LOG_CFG_LEN 12 ++int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable) ++{ ++ struct sk_buff *skb; ++ u32 comp = enable ? BIT(RTW89_FW_LOG_COMP_INIT) | BIT(RTW89_FW_LOG_COMP_TASK) | ++ BIT(RTW89_FW_LOG_COMP_PS) | BIT(RTW89_FW_LOG_COMP_ERROR) : 0; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LOG_CFG_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw log cfg\n"); ++ return -ENOMEM; ++ } ++ ++ skb_put(skb, H2C_LOG_CFG_LEN); ++ SET_LOG_CFG_LEVEL(skb->data, RTW89_FW_LOG_LEVEL_SER); ++ SET_LOG_CFG_PATH(skb->data, BIT(RTW89_FW_LOG_LEVEL_C2H)); ++ SET_LOG_CFG_COMP(skb->data, comp); ++ SET_LOG_CFG_COMP_EXT(skb->data, 0); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_FW_INFO, ++ H2C_FUNC_LOG_CFG, 0, 0, ++ H2C_LOG_CFG_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_GENERAL_PKT_LEN 6 ++#define H2C_GENERAL_PKT_ID_UND 0xff ++int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_GENERAL_PKT_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_GENERAL_PKT_LEN); ++ SET_GENERAL_PKT_MACID(skb->data, macid); ++ SET_GENERAL_PKT_PROBRSP_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_PSPOLL_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_NULL_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_QOS_NULL_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ SET_GENERAL_PKT_CTS2SELF_ID(skb->data, H2C_GENERAL_PKT_ID_UND); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_FW_INFO, ++ H2C_FUNC_MAC_GENERAL_PKT, 0, 1, ++ H2C_GENERAL_PKT_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LPS_PARM_LEN 8 ++int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, ++ struct rtw89_lps_parm *lps_param) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LPS_PARM_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LPS_PARM_LEN); ++ ++ SET_LPS_PARM_MACID(skb->data, lps_param->macid); ++ SET_LPS_PARM_PSMODE(skb->data, lps_param->psmode); ++ SET_LPS_PARM_LASTRPWM(skb->data, lps_param->lastrpwm); ++ SET_LPS_PARM_RLBM(skb->data, 1); ++ SET_LPS_PARM_SMARTPS(skb->data, 1); ++ SET_LPS_PARM_AWAKEINTERVAL(skb->data, 1); ++ SET_LPS_PARM_VOUAPSD(skb->data, 0); ++ SET_LPS_PARM_VIUAPSD(skb->data, 0); ++ SET_LPS_PARM_BEUAPSD(skb->data, 0); ++ SET_LPS_PARM_BKUAPSD(skb->data, 0); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, ++ H2C_CL_MAC_PS, ++ H2C_FUNC_MAC_LPS_PARM, 0, 1, ++ H2C_LPS_PARM_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_CMC_TBL_LEN 68 ++int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct sk_buff *skb; ++ u8 ntx_path = hal->antenna_tx ? hal->antenna_tx : RF_B; ++ u8 map_b = hal->antenna_tx == RF_AB ? 1 : 0; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CMC_TBL_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CMC_TBL_LEN); ++ SET_CTRL_INFO_MACID(skb->data, macid); ++ SET_CTRL_INFO_OPERATION(skb->data, 1); ++ SET_CMC_TBL_TXPWR_MODE(skb->data, 0); ++ SET_CMC_TBL_NTX_PATH_EN(skb->data, ntx_path); ++ SET_CMC_TBL_PATH_MAP_A(skb->data, 0); ++ SET_CMC_TBL_PATH_MAP_B(skb->data, map_b); ++ SET_CMC_TBL_PATH_MAP_C(skb->data, 0); ++ SET_CMC_TBL_PATH_MAP_D(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_A(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_B(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_C(skb->data, 0); ++ SET_CMC_TBL_ANTSEL_D(skb->data, 0); ++ SET_CMC_TBL_DOPPLER_CTRL(skb->data, 0); ++ SET_CMC_TBL_TXPWR_TOLERENCE(skb->data, 0); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG, ++ H2C_FUNC_MAC_CCTLINFO_UD, 0, 1, ++ H2C_CMC_TBL_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++static void __get_sta_he_pkt_padding(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, u8 *pads) ++{ ++ bool ppe_th; ++ u8 ppe16, ppe8; ++ u8 nss = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1; ++ u8 ppe_thres_hdr = sta->he_cap.ppe_thres[0]; ++ u8 ru_bitmap; ++ u8 n, idx, sh; ++ u16 ppe; ++ int i; ++ ++ if (!sta->he_cap.has_he) ++ return; ++ ++ ppe_th = FIELD_GET(IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT, ++ sta->he_cap.he_cap_elem.phy_cap_info[6]); ++ if (!ppe_th) { ++ u8 pad; ++ ++ pad = FIELD_GET(IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_MASK, ++ sta->he_cap.he_cap_elem.phy_cap_info[9]); ++ ++ for (i = 0; i < RTW89_PPE_BW_NUM; i++) ++ pads[i] = pad; ++ } ++ ++ ru_bitmap = FIELD_GET(IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK, ppe_thres_hdr); ++ n = hweight8(ru_bitmap); ++ n = 7 + (n * IEEE80211_PPE_THRES_INFO_PPET_SIZE * 2) * nss; ++ ++ for (i = 0; i < RTW89_PPE_BW_NUM; i++) { ++ if (!(ru_bitmap & BIT(i))) { ++ pads[i] = 1; ++ continue; ++ } ++ ++ idx = n >> 3; ++ sh = n & 7; ++ n += IEEE80211_PPE_THRES_INFO_PPET_SIZE * 2; ++ ++ ppe = le16_to_cpu(*((__le16 *)&sta->he_cap.ppe_thres[idx])); ++ ppe16 = (ppe >> sh) & IEEE80211_PPE_THRES_NSS_MASK; ++ sh += IEEE80211_PPE_THRES_INFO_PPET_SIZE; ++ ppe8 = (ppe >> sh) & IEEE80211_PPE_THRES_NSS_MASK; ++ ++ if (ppe16 != 7 && ppe8 == 7) ++ pads[i] = 2; ++ else if (ppe8 != 7) ++ pads[i] = 1; ++ else ++ pads[i] = 0; ++ } ++} ++ ++int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct sk_buff *skb; ++ u8 pads[RTW89_PPE_BW_NUM]; ++ ++ memset(pads, 0, sizeof(pads)); ++ __get_sta_he_pkt_padding(rtwdev, sta, pads); ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CMC_TBL_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CMC_TBL_LEN); ++ SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id); ++ SET_CTRL_INFO_OPERATION(skb->data, 1); ++ SET_CMC_TBL_DISRTSFB(skb->data, 1); ++ SET_CMC_TBL_DISDATAFB(skb->data, 1); ++ if (hal->current_band_type == RTW89_BAND_2G) ++ SET_CMC_TBL_RTS_RTY_LOWEST_RATE(skb->data, RTW89_HW_RATE_CCK1); ++ else ++ SET_CMC_TBL_RTS_RTY_LOWEST_RATE(skb->data, RTW89_HW_RATE_OFDM6); ++ SET_CMC_TBL_RTS_TXCNT_LMT_SEL(skb->data, 0); ++ SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 0); ++ if (vif->type == NL80211_IFTYPE_STATION) ++ SET_CMC_TBL_ULDL(skb->data, 1); ++ else ++ SET_CMC_TBL_ULDL(skb->data, 0); ++ SET_CMC_TBL_MULTI_PORT_ID(skb->data, rtwvif->port); ++ SET_CMC_TBL_NOMINAL_PKT_PADDING(skb->data, pads[RTW89_CHANNEL_WIDTH_20]); ++ SET_CMC_TBL_NOMINAL_PKT_PADDING40(skb->data, pads[RTW89_CHANNEL_WIDTH_40]); ++ SET_CMC_TBL_NOMINAL_PKT_PADDING80(skb->data, pads[RTW89_CHANNEL_WIDTH_80]); ++ SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(skb->data, sta->he_cap.has_he); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG, ++ H2C_FUNC_MAC_CCTLINFO_UD, 0, 1, ++ H2C_CMC_TBL_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_CMC_TBL_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for fw dl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_CMC_TBL_LEN); ++ SET_CTRL_INFO_MACID(skb->data, rtwsta->mac_id); ++ SET_CTRL_INFO_OPERATION(skb->data, 1); ++ if (rtwsta->cctl_tx_time) { ++ SET_CMC_TBL_AMPDU_TIME_SEL(skb->data, 1); ++ SET_CMC_TBL_AMPDU_MAX_TIME(skb->data, rtwsta->ampdu_max_time); ++ } ++ if (rtwsta->cctl_tx_retry_limit) { ++ SET_CMC_TBL_DATA_TXCNT_LMT_SEL(skb->data, 1); ++ SET_CMC_TBL_DATA_TX_CNT_LMT(skb->data, rtwsta->data_tx_cnt_lmt); ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FR_EXCHG, ++ H2C_FUNC_MAC_CCTLINFO_UD, 0, 1, ++ H2C_CMC_TBL_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_VIF_MAINTAIN_LEN 4 ++int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, ++ enum rtw89_upd_mode upd_mode) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_VIF_MAINTAIN_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_VIF_MAINTAIN_LEN); ++ SET_FWROLE_MAINTAIN_MACID(skb->data, rtwvif->mac_id); ++ SET_FWROLE_MAINTAIN_SELF_ROLE(skb->data, rtwvif->self_role); ++ SET_FWROLE_MAINTAIN_UPD_MODE(skb->data, upd_mode); ++ SET_FWROLE_MAINTAIN_WIFI_ROLE(skb->data, rtwvif->wifi_role); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_MEDIA_RPT, ++ H2C_FUNC_MAC_FWROLE_MAINTAIN, 0, 1, ++ H2C_VIF_MAINTAIN_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_JOIN_INFO_LEN 4 ++int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 dis_conn) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_JOIN_INFO_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_JOIN_INFO_LEN); ++ SET_JOININFO_MACID(skb->data, rtwvif->mac_id); ++ SET_JOININFO_OP(skb->data, dis_conn); ++ SET_JOININFO_BAND(skb->data, rtwvif->mac_idx); ++ SET_JOININFO_WMM(skb->data, rtwvif->wmm); ++ SET_JOININFO_TGR(skb->data, rtwvif->trigger); ++ SET_JOININFO_ISHESTA(skb->data, 0); ++ SET_JOININFO_DLBW(skb->data, 0); ++ SET_JOININFO_TF_MAC_PAD(skb->data, 0); ++ SET_JOININFO_DL_T_PE(skb->data, 0); ++ SET_JOININFO_PORT_ID(skb->data, rtwvif->port); ++ SET_JOININFO_NET_TYPE(skb->data, rtwvif->net_type); ++ SET_JOININFO_WIFI_ROLE(skb->data, rtwvif->wifi_role); ++ SET_JOININFO_SELF_ROLE(skb->data, rtwvif->self_role); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_MEDIA_RPT, ++ H2C_FUNC_MAC_JOININFO, 0, 1, ++ H2C_JOIN_INFO_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, ++ bool pause) ++{ ++ struct rtw89_fw_macid_pause_grp h2c = {{0}}; ++ u8 len = sizeof(struct rtw89_fw_macid_pause_grp); ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_JOIN_INFO_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ h2c.mask_grp[grp] = cpu_to_le32(BIT(sh)); ++ if (pause) ++ h2c.pause_grp[grp] = cpu_to_le32(BIT(sh)); ++ skb_put_data(skb, &h2c, len); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD, ++ H2C_FUNC_MAC_MACID_PAUSE, 1, 0, ++ len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_EDCA_LEN 12 ++int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 ac, u32 val) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_EDCA_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c edca\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_EDCA_LEN); ++ RTW89_SET_EDCA_SEL(skb->data, 0); ++ RTW89_SET_EDCA_BAND(skb->data, rtwvif->mac_idx); ++ RTW89_SET_EDCA_WMM(skb->data, 0); ++ RTW89_SET_EDCA_AC(skb->data, ac); ++ RTW89_SET_EDCA_PARAM(skb->data, val); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD, ++ H2C_FUNC_USR_EDCA, 0, 1, ++ H2C_EDCA_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_OFLD_CFG_LEN 8 ++int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev) ++{ ++ static const u8 cfg[] = {0x09, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00}; ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_OFLD_CFG_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c ofld\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, cfg, H2C_OFLD_CFG_LEN); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_MAC, H2C_CL_MAC_FW_OFLD, ++ H2C_FUNC_OFLD_CFG, 0, 1, ++ H2C_OFLD_CFG_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_RA_LEN 16 ++int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi) ++{ ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_RA_LEN); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c join\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_RA_LEN); ++ cmd = skb->data; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra cmd msk: %llx ", ra->ra_mask); ++ ++ RTW89_SET_FWCMD_RA_MODE(cmd, ra->mode_ctrl); ++ RTW89_SET_FWCMD_RA_BW_CAP(cmd, ra->bw_cap); ++ RTW89_SET_FWCMD_RA_MACID(cmd, ra->macid); ++ RTW89_SET_FWCMD_RA_DCM(cmd, ra->dcm_cap); ++ RTW89_SET_FWCMD_RA_ER(cmd, ra->er_cap); ++ RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, ra->init_rate_lv); ++ RTW89_SET_FWCMD_RA_UPD_ALL(cmd, ra->upd_all); ++ RTW89_SET_FWCMD_RA_SGI(cmd, ra->en_sgi); ++ RTW89_SET_FWCMD_RA_LDPC(cmd, ra->ldpc_cap); ++ RTW89_SET_FWCMD_RA_STBC(cmd, ra->stbc_cap); ++ RTW89_SET_FWCMD_RA_SS_NUM(cmd, ra->ss_num); ++ RTW89_SET_FWCMD_RA_GILTF(cmd, ra->giltf); ++ RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, ra->upd_bw_nss_mask); ++ RTW89_SET_FWCMD_RA_UPD_MASK(cmd, ra->upd_mask); ++ RTW89_SET_FWCMD_RA_MASK_0(cmd, FIELD_GET(MASKBYTE0, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_1(cmd, FIELD_GET(MASKBYTE1, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_2(cmd, FIELD_GET(MASKBYTE2, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_3(cmd, FIELD_GET(MASKBYTE3, ra->ra_mask)); ++ RTW89_SET_FWCMD_RA_MASK_4(cmd, FIELD_GET(MASKBYTE4, ra->ra_mask)); ++ ++ if (csi) { ++ RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, 1); ++ RTW89_SET_FWCMD_RA_BAND_NUM(cmd, ra->band_num); ++ RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, ra->cr_tbl_sel); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, ra->fixed_csi_rate_en); ++ RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, ra->ra_csi_rate_en); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, ra->csi_mcs_ss_idx); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, ra->csi_mode); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, ra->csi_gi_ltf); ++ RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, ra->csi_bw); ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA, ++ H2C_FUNC_OUTSRC_RA_MACIDCFG, 0, 0, ++ H2C_RA_LEN); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVHDR 2 ++#define H2C_LEN_CXDRVINFO_INIT (12 + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_init_info *init_info = &dm->init_info; ++ struct rtw89_btc_module *module = &init_info->module; ++ struct rtw89_btc_ant_info *ant = &module->ant; ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_INIT); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_init\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_INIT); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_INIT); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_INIT - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, ant->type); ++ RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, ant->num); ++ RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, ant->isolation); ++ RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, ant->single_pos); ++ RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, ant->diversity); ++ ++ RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, module->rfe_type); ++ RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, module->cv); ++ RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, module->bt_solo); ++ RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, module->bt_pos); ++ RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, module->switch_type); ++ ++ RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, init_info->wl_guard_ch); ++ RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, init_info->wl_only); ++ RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, init_info->wl_init_ok); ++ RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, init_info->dbcc_en); ++ RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, init_info->cx_other); ++ RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, init_info->bt_only); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_INIT); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVINFO_ROLE (4 + 12 * RTW89_MAX_HW_PORT_NUM + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_role_info *role_info = &wl->role_info; ++ struct rtw89_btc_wl_role_info_bpos *bpos = &role_info->role_map.role; ++ struct rtw89_btc_wl_active_role *active = role_info->active_role; ++ struct sk_buff *skb; ++ u8 *cmd; ++ int i; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_ROLE); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_role\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_ROLE); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_ROLE); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_ROLE - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, role_info->connect_cnt); ++ RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, role_info->link_mode); ++ ++ RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, bpos->none); ++ RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, bpos->station); ++ RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, bpos->ap); ++ RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, bpos->vap); ++ RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, bpos->adhoc); ++ RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, bpos->adhoc_master); ++ RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, bpos->mesh); ++ RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, bpos->moniter); ++ RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, bpos->p2p_device); ++ RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, bpos->p2p_gc); ++ RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, bpos->p2p_go); ++ RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, bpos->nan); ++ ++ for (i = 0; i < RTW89_MAX_HW_PORT_NUM; i++, active++) { ++ RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, active->connected, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, active->pid, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, active->phy, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, active->noa, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, active->band, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, active->client_ps, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, active->bw, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, active->role, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, active->ch, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, active->tx_lvl, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, active->rx_lvl, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, active->tx_rate, i); ++ RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, active->rx_rate, i); ++ } ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_ROLE); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVINFO_CTRL (4 + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_ctrl *ctrl = &btc->ctrl; ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_CTRL); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_CTRL); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_CTRL); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_CTRL - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, ctrl->manual); ++ RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, ctrl->igno_bt); ++ RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, ctrl->always_freerun); ++ RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, ctrl->trace_step); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_CTRL); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++#define H2C_LEN_CXDRVINFO_RFK (4 + H2C_LEN_CXDRVHDR) ++int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_wl_info *wl = &btc->cx.wl; ++ struct rtw89_btc_wl_rfk_info *rfk_info = &wl->rfk_info; ++ struct sk_buff *skb; ++ u8 *cmd; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(H2C_LEN_CXDRVINFO_RFK); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c cxdrv_ctrl\n"); ++ return -ENOMEM; ++ } ++ skb_put(skb, H2C_LEN_CXDRVINFO_RFK); ++ cmd = skb->data; ++ ++ RTW89_SET_FWCMD_CXHDR_TYPE(cmd, CXDRVINFO_RFK); ++ RTW89_SET_FWCMD_CXHDR_LEN(cmd, H2C_LEN_CXDRVINFO_RFK - H2C_LEN_CXDRVHDR); ++ ++ RTW89_SET_FWCMD_CXRFK_STATE(cmd, rfk_info->state); ++ RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, rfk_info->path_map); ++ RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, rfk_info->phy_map); ++ RTW89_SET_FWCMD_CXRFK_BAND(cmd, rfk_info->band); ++ RTW89_SET_FWCMD_CXRFK_TYPE(cmd, rfk_info->type); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, BTFC_SET, ++ SET_DRV_INFO, 0, 0, ++ H2C_LEN_CXDRVINFO_RFK); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_h2c_rf_reg_info *info, ++ u16 len, u8 page) ++{ ++ struct sk_buff *skb; ++ u8 class = info->rf_path == RF_PATH_A ? ++ H2C_CL_OUTSRC_RF_REG_A : H2C_CL_OUTSRC_RF_REG_B; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c rf reg\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, info->rtw89_phy_config_rf_h2c[page], len); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, class, page, 0, 0, ++ len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, ++ u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, ++ bool rack, bool dack) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_with_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for raw with hdr\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, buf, len); ++ ++ rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, ++ H2C_CAT_OUTSRC, h2c_class, h2c_func, rack, dack, ++ len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len) ++{ ++ struct sk_buff *skb; ++ ++ skb = rtw89_fw_h2c_alloc_skb_no_hdr(len); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to alloc skb for h2c raw\n"); ++ return -ENOMEM; ++ } ++ skb_put_data(skb, buf, len); ++ ++ if (rtw89_h2c_tx(rtwdev, skb, false)) { ++ rtw89_err(rtwdev, "failed to send h2c\n"); ++ goto fail; ++ } ++ ++ return 0; ++fail: ++ dev_kfree_skb_any(skb); ++ ++ return -EBUSY; ++} ++ ++void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_early_h2c *early_h2c; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) { ++ rtw89_fw_h2c_raw(rtwdev, early_h2c->h2c, early_h2c->h2c_len); ++ } ++} ++ ++void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_early_h2c *early_h2c, *tmp; ++ ++ mutex_lock(&rtwdev->mutex); ++ list_for_each_entry_safe(early_h2c, tmp, &rtwdev->early_h2c_list, list) { ++ list_del(&early_h2c->list); ++ kfree(early_h2c->h2c); ++ kfree(early_h2c); ++ } ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h) ++{ ++ skb_queue_tail(&rtwdev->c2h_queue, c2h); ++ ieee80211_queue_work(rtwdev->hw, &rtwdev->c2h_work); ++} ++ ++static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ u8 category = RTW89_GET_C2H_CATEGORY(skb->data); ++ u8 class = RTW89_GET_C2H_CLASS(skb->data); ++ u8 func = RTW89_GET_C2H_FUNC(skb->data); ++ u16 len = RTW89_GET_C2H_LEN(skb->data); ++ bool dump = true; ++ ++ if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) ++ return; ++ ++ switch (category) { ++ case RTW89_C2H_CAT_TEST: ++ break; ++ case RTW89_C2H_CAT_MAC: ++ rtw89_mac_c2h_handle(rtwdev, skb, len, class, func); ++ if (class == RTW89_MAC_C2H_CLASS_INFO && ++ func == RTW89_MAC_C2H_FUNC_C2H_LOG) ++ dump = false; ++ break; ++ case RTW89_C2H_CAT_OUTSRC: ++ if (class >= RTW89_PHY_C2H_CLASS_BTC_MIN && ++ class <= RTW89_PHY_C2H_CLASS_BTC_MAX) ++ rtw89_btc_c2h_handle(rtwdev, skb, len, class, func); ++ else ++ rtw89_phy_c2h_handle(rtwdev, skb, len, class, func); ++ break; ++ } ++ ++ if (dump) ++ rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "C2H: ", skb->data, skb->len); ++} ++ ++void rtw89_fw_c2h_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ c2h_work); ++ struct sk_buff *skb, *tmp; ++ ++ skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { ++ skb_unlink(skb, &rtwdev->c2h_queue); ++ mutex_lock(&rtwdev->mutex); ++ rtw89_fw_c2h_cmd_handle(rtwdev, skb); ++ mutex_unlock(&rtwdev->mutex); ++ dev_kfree_skb_any(skb); ++ } ++} ++ ++static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_h2c_info *info) ++{ ++ static const u32 h2c_reg[RTW89_H2CREG_MAX] = { ++ R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, ++ R_AX_H2CREG_DATA2, R_AX_H2CREG_DATA3 ++ }; ++ u8 i, val, len; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read8, val, val == 0, 1000, 5000, false, ++ rtwdev, R_AX_H2CREG_CTRL); ++ if (ret) { ++ rtw89_warn(rtwdev, "FW does not process h2c registers\n"); ++ return ret; ++ } ++ ++ len = DIV_ROUND_UP(info->content_len + RTW89_H2CREG_HDR_LEN, ++ sizeof(info->h2creg[0])); ++ ++ RTW89_SET_H2CREG_HDR_FUNC(&info->h2creg[0], info->id); ++ RTW89_SET_H2CREG_HDR_LEN(&info->h2creg[0], len); ++ for (i = 0; i < RTW89_H2CREG_MAX; i++) ++ rtw89_write32(rtwdev, h2c_reg[i], info->h2creg[i]); ++ ++ rtw89_write8(rtwdev, R_AX_H2CREG_CTRL, B_AX_H2CREG_TRIGGER); ++ ++ return 0; ++} ++ ++static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_c2h_info *info) ++{ ++ static const u32 c2h_reg[RTW89_C2HREG_MAX] = { ++ R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, ++ R_AX_C2HREG_DATA2, R_AX_C2HREG_DATA3 ++ }; ++ u32 ret; ++ u8 i, val; ++ ++ info->id = RTW89_FWCMD_C2HREG_FUNC_NULL; ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, val, val, 1, ++ RTW89_C2H_TIMEOUT, false, rtwdev, ++ R_AX_C2HREG_CTRL); ++ if (ret) { ++ rtw89_warn(rtwdev, "c2h reg timeout\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < RTW89_C2HREG_MAX; i++) ++ info->c2hreg[i] = rtw89_read32(rtwdev, c2h_reg[i]); ++ ++ rtw89_write8(rtwdev, R_AX_C2HREG_CTRL, 0); ++ ++ info->id = RTW89_GET_C2H_HDR_FUNC(*info->c2hreg); ++ info->content_len = (RTW89_GET_C2H_HDR_LEN(*info->c2hreg) << 2) - ++ RTW89_C2HREG_HDR_LEN; ++ ++ return 0; ++} ++ ++int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_h2c_info *h2c_info, ++ struct rtw89_mac_c2h_info *c2h_info) ++{ ++ u32 ret; ++ ++ if (h2c_info && h2c_info->id != RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE) ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (!h2c_info && !c2h_info) ++ return -EINVAL; ++ ++ if (!h2c_info) ++ goto recv_c2h; ++ ++ ret = rtw89_fw_write_h2c_reg(rtwdev, h2c_info); ++ if (ret) ++ return ret; ++ ++recv_c2h: ++ if (!c2h_info) ++ return 0; ++ ++ ret = rtw89_fw_read_c2h_reg(rtwdev, c2h_info); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev) ++{ ++ if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { ++ rtw89_err(rtwdev, "[ERR]pwr is off\n"); ++ return; ++ } ++ ++ rtw89_info(rtwdev, "FW status = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM0)); ++ rtw89_info(rtwdev, "FW BADADDR = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM1)); ++ rtw89_info(rtwdev, "FW EPC/RA = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM2)); ++ rtw89_info(rtwdev, "FW MISC = 0x%x\n", rtw89_read32(rtwdev, R_AX_UDM3)); ++ rtw89_info(rtwdev, "R_AX_HALT_C2H = 0x%x\n", ++ rtw89_read32(rtwdev, R_AX_HALT_C2H)); ++ rtw89_info(rtwdev, "R_AX_SER_DBG_INFO = 0x%x\n", ++ rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); ++ ++ rtw89_fw_prog_cnt_dump(rtwdev); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +new file mode 100644 +index 000000000000..7ee0d9323310 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -0,0 +1,1378 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_FW_H__ ++#define __RTW89_FW_H__ ++ ++#include "core.h" ++ ++enum rtw89_fw_dl_status { ++ RTW89_FWDL_INITIAL_STATE = 0, ++ RTW89_FWDL_FWDL_ONGOING = 1, ++ RTW89_FWDL_CHECKSUM_FAIL = 2, ++ RTW89_FWDL_SECURITY_FAIL = 3, ++ RTW89_FWDL_CV_NOT_MATCH = 4, ++ RTW89_FWDL_RSVD0 = 5, ++ RTW89_FWDL_WCPU_FWDL_RDY = 6, ++ RTW89_FWDL_WCPU_FW_INIT_RDY = 7 ++}; ++ ++#define RTW89_GET_C2H_HDR_FUNC(info) \ ++ u32_get_bits(info, GENMASK(6, 0)) ++#define RTW89_GET_C2H_HDR_LEN(info) \ ++ u32_get_bits(info, GENMASK(11, 8)) ++ ++#define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ ++ u32p_replace_bits(info, val, GENMASK(6, 0)) ++#define RTW89_SET_H2CREG_HDR_LEN(info, val) \ ++ u32p_replace_bits(info, val, GENMASK(11, 8)) ++ ++#define RTW89_H2CREG_MAX 4 ++#define RTW89_C2HREG_MAX 4 ++#define RTW89_C2HREG_HDR_LEN 2 ++#define RTW89_H2CREG_HDR_LEN 2 ++#define RTW89_C2H_TIMEOUT 1000000 ++struct rtw89_mac_c2h_info { ++ u8 id; ++ u8 content_len; ++ u32 c2hreg[RTW89_C2HREG_MAX]; ++}; ++ ++struct rtw89_mac_h2c_info { ++ u8 id; ++ u8 content_len; ++ u32 h2creg[RTW89_H2CREG_MAX]; ++}; ++ ++enum rtw89_mac_h2c_type { ++ RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, ++ RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, ++ RTW89_FWCMD_H2CREG_FUNC_FWERR, ++ RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, ++ RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, ++ RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN ++}; ++ ++enum rtw89_mac_c2h_type { ++ RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, ++ RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, ++ RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, ++ RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, ++ RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, ++ RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF ++}; ++ ++struct rtw89_c2h_phy_cap { ++ u32 func:7; ++ u32 ack:1; ++ u32 len:4; ++ u32 seq:4; ++ u32 rx_nss:8; ++ u32 bw:8; ++ ++ u32 tx_nss:8; ++ u32 prot:8; ++ u32 nic:8; ++ u32 wl_func:8; ++ ++ u32 hw_type:8; ++} __packed; ++ ++enum rtw89_fw_c2h_category { ++ RTW89_C2H_CAT_TEST, ++ RTW89_C2H_CAT_MAC, ++ RTW89_C2H_CAT_OUTSRC, ++}; ++ ++enum rtw89_fw_log_level { ++ RTW89_FW_LOG_LEVEL_OFF, ++ RTW89_FW_LOG_LEVEL_CRT, ++ RTW89_FW_LOG_LEVEL_SER, ++ RTW89_FW_LOG_LEVEL_WARN, ++ RTW89_FW_LOG_LEVEL_LOUD, ++ RTW89_FW_LOG_LEVEL_TR, ++}; ++ ++enum rtw89_fw_log_path { ++ RTW89_FW_LOG_LEVEL_UART, ++ RTW89_FW_LOG_LEVEL_C2H, ++ RTW89_FW_LOG_LEVEL_SNI, ++}; ++ ++enum rtw89_fw_log_comp { ++ RTW89_FW_LOG_COMP_VER, ++ RTW89_FW_LOG_COMP_INIT, ++ RTW89_FW_LOG_COMP_TASK, ++ RTW89_FW_LOG_COMP_CNS, ++ RTW89_FW_LOG_COMP_H2C, ++ RTW89_FW_LOG_COMP_C2H, ++ RTW89_FW_LOG_COMP_TX, ++ RTW89_FW_LOG_COMP_RX, ++ RTW89_FW_LOG_COMP_IPSEC, ++ RTW89_FW_LOG_COMP_TIMER, ++ RTW89_FW_LOG_COMP_DBGPKT, ++ RTW89_FW_LOG_COMP_PS, ++ RTW89_FW_LOG_COMP_ERROR, ++ RTW89_FW_LOG_COMP_WOWLAN, ++ RTW89_FW_LOG_COMP_SECURE_BOOT, ++ RTW89_FW_LOG_COMP_BTC, ++ RTW89_FW_LOG_COMP_BB, ++ RTW89_FW_LOG_COMP_TWT, ++ RTW89_FW_LOG_COMP_RF, ++ RTW89_FW_LOG_COMP_MCC = 20, ++}; ++ ++#define FWDL_SECTION_MAX_NUM 10 ++#define FWDL_SECTION_CHKSUM_LEN 8 ++#define FWDL_SECTION_PER_PKT_LEN 2020 ++ ++struct rtw89_fw_hdr_section_info { ++ u8 redl; ++ const u8 *addr; ++ u32 len; ++ u32 dladdr; ++}; ++ ++struct rtw89_fw_bin_info { ++ u8 section_num; ++ u32 hdr_len; ++ struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; ++}; ++ ++struct rtw89_fw_macid_pause_grp { ++ __le32 pause_grp[4]; ++ __le32 mask_grp[4]; ++} __packed; ++ ++struct rtw89_h2creg_sch_tx_en { ++ u8 func:7; ++ u8 ack:1; ++ u8 total_len:4; ++ u8 seq_num:4; ++ u16 tx_en:16; ++ u16 mask:16; ++ u8 band:1; ++ u16 rsvd:15; ++} __packed; ++ ++#define RTW89_SET_FWCMD_RA_IS_DIS(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)) ++#define RTW89_SET_FWCMD_RA_MODE(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)) ++#define RTW89_SET_FWCMD_RA_BW_CAP(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)) ++#define RTW89_SET_FWCMD_RA_MACID(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) ++#define RTW89_SET_FWCMD_RA_DCM(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)) ++#define RTW89_SET_FWCMD_RA_ER(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)) ++#define RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)) ++#define RTW89_SET_FWCMD_RA_UPD_ALL(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)) ++#define RTW89_SET_FWCMD_RA_SGI(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)) ++#define RTW89_SET_FWCMD_RA_LDPC(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)) ++#define RTW89_SET_FWCMD_RA_STBC(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)) ++#define RTW89_SET_FWCMD_RA_SS_NUM(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)) ++#define RTW89_SET_FWCMD_RA_GILTF(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)) ++#define RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)) ++#define RTW89_SET_FWCMD_RA_UPD_MASK(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)) ++#define RTW89_SET_FWCMD_RA_MASK_0(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_RA_MASK_1(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)) ++#define RTW89_SET_FWCMD_RA_MASK_2(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)) ++#define RTW89_SET_FWCMD_RA_MASK_3(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)) ++#define RTW89_SET_FWCMD_RA_MASK_4(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)) ++#define RTW89_SET_FWCMD_RA_BAND_NUM(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)) ++#define RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)) ++#define RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)) ++ ++#define RTW89_SET_FWCMD_SEC_IDX(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_SEC_OFFSET(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) ++#define RTW89_SET_FWCMD_SEC_LEN(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)) ++#define RTW89_SET_FWCMD_SEC_TYPE(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)) ++#define RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)) ++#define RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)) ++#define RTW89_SET_FWCMD_SEC_KEY0(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)) ++#define RTW89_SET_FWCMD_SEC_KEY1(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)) ++#define RTW89_SET_FWCMD_SEC_KEY2(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)) ++#define RTW89_SET_FWCMD_SEC_KEY3(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)) ++ ++#define RTW89_SET_EDCA_SEL(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)) ++#define RTW89_SET_EDCA_BAND(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)) ++#define RTW89_SET_EDCA_WMM(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)) ++#define RTW89_SET_EDCA_AC(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)) ++#define RTW89_SET_EDCA_PARAM(cmd, val) \ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)) ++#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) ++#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) ++#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) ++#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) ++ ++#define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 0)) ++#define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(28)) ++#define GET_FWSECTION_HDR_REDL(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(29)) ++#define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr)), GENMASK(31, 0)) ++ ++#define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(7, 0)) ++#define GET_FW_HDR_MINOR_VERSION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(15, 8)) ++#define GET_FW_HDR_SUBVERSION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 16)) ++#define GET_FW_HDR_SUBINDEX(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(31, 24)) ++#define GET_FW_HDR_MONTH(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(7, 0)) ++#define GET_FW_HDR_DATE(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(15, 8)) ++#define GET_FW_HDR_HOUR(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(23, 16)) ++#define GET_FW_HDR_MIN(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(31, 24)) ++#define GET_FW_HDR_YEAR(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 5), GENMASK(31, 0)) ++#define GET_FW_HDR_SEC_NUM(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 6), GENMASK(15, 8)) ++#define GET_FW_HDR_CMD_VERSERION(fwhdr) \ ++ le32_get_bits(*((__le32 *)(fwhdr) + 7), GENMASK(31, 24)) ++#define SET_FW_HDR_PART_SIZE(fwhdr, val) \ ++ le32p_replace_bits((__le32 *)(fwhdr) + 7, val, GENMASK(15, 0)) ++ ++#define SET_CTRL_INFO_MACID(table, val) \ ++ le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)) ++#define SET_CTRL_INFO_OPERATION(table, val) \ ++ le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)) ++#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) ++#define SET_CMC_TBL_DATARATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, \ ++ GENMASK(8, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) ++#define SET_CMC_TBL_FORCE_TXOP(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, \ ++ BIT(9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) ++#define SET_CMC_TBL_DATA_BW(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, \ ++ GENMASK(11, 10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) ++#define SET_CMC_TBL_DATA_GI_LTF(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, \ ++ GENMASK(14, 12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) ++#define SET_CMC_TBL_DARF_TC_INDEX(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, \ ++ BIT(15)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) ++#define SET_CMC_TBL_ARFR_CTRL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, \ ++ GENMASK(19, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_ACQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, \ ++ BIT(20)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_MGQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, \ ++ BIT(21)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_ULQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, \ ++ BIT(22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) ++#define SET_CMC_TBL_TWTQ_RPT_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, \ ++ BIT(23)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DISRTSFB BIT(0) ++#define SET_CMC_TBL_DISRTSFB(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, \ ++ BIT(25)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DISDATAFB BIT(0) ++#define SET_CMC_TBL_DISDATAFB(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, \ ++ BIT(26)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TRYRATE BIT(0) ++#define SET_CMC_TBL_TRYRATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) ++#define SET_CMC_TBL_AMPDU_DENSITY(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) ++#define SET_CMC_TBL_DATA_RTY_LOWEST_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, \ ++ GENMASK(8, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) ++#define SET_CMC_TBL_AMPDU_TIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, \ ++ BIT(9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) ++#define SET_CMC_TBL_AMPDU_LEN_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, \ ++ BIT(10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) ++#define SET_CMC_TBL_RTS_TXCNT_LMT_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, \ ++ BIT(11)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) ++#define SET_CMC_TBL_RTS_TXCNT_LMT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, \ ++ GENMASK(15, 12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) ++#define SET_CMC_TBL_RTSRATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, \ ++ GENMASK(24, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_VCS_STBC BIT(0) ++#define SET_CMC_TBL_VCS_STBC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) ++#define SET_CMC_TBL_RTS_RTY_LOWEST_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) ++#define SET_CMC_TBL_DATA_TX_CNT_LMT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, \ ++ GENMASK(5, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) ++#define SET_CMC_TBL_DATA_TXCNT_LMT_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, \ ++ BIT(6)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) ++#define SET_CMC_TBL_MAX_AGG_NUM_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, \ ++ BIT(7)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_EN BIT(0) ++#define SET_CMC_TBL_RTS_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, \ ++ BIT(8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) ++#define SET_CMC_TBL_CTS2SELF_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, \ ++ BIT(9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) ++#define SET_CMC_TBL_CCA_RTS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, \ ++ GENMASK(11, 10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) ++#define SET_CMC_TBL_HW_RTS_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) ++#define SET_CMC_TBL_RTS_DROP_DATA_MODE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, \ ++ GENMASK(14, 13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) ++#define SET_CMC_TBL_AMPDU_MAX_LEN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, \ ++ GENMASK(26, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) ++#define SET_CMC_TBL_UL_MU_DIS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) ++#define SET_CMC_TBL_AMPDU_MAX_TIME(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) ++#define SET_CMC_TBL_MAX_AGG_NUM(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, \ ++ GENMASK(7, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) ++#define SET_CMC_TBL_BA_BMAP(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, \ ++ GENMASK(9, 8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_VO_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, \ ++ GENMASK(18, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_VI_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, \ ++ GENMASK(21, 19)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_BE_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, \ ++ GENMASK(24, 22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) ++#define SET_CMC_TBL_BK_LFTIME_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, \ ++ GENMASK(27, 25)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) ++#define SET_CMC_TBL_SECTYPE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) ++#define SET_CMC_TBL_MULTI_PORT_ID(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, \ ++ GENMASK(2, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BMC BIT(0) ++#define SET_CMC_TBL_BMC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, \ ++ BIT(3)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) ++#define SET_CMC_TBL_MBSSID(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, \ ++ GENMASK(7, 4)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) ++#define SET_CMC_TBL_NAVUSEHDR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, \ ++ BIT(8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) ++#define SET_CMC_TBL_TXPWR_MODE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, \ ++ GENMASK(11, 9)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_DCM BIT(0) ++#define SET_CMC_TBL_DATA_DCM(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_ER BIT(0) ++#define SET_CMC_TBL_DATA_ER(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, \ ++ BIT(13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) ++#define SET_CMC_TBL_DATA_LDPC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, \ ++ BIT(14)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_STBC BIT(0) ++#define SET_CMC_TBL_DATA_STBC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, \ ++ BIT(15)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) ++#define SET_CMC_TBL_A_CTRL_BQR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, \ ++ BIT(16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) ++#define SET_CMC_TBL_A_CTRL_UPH(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, \ ++ BIT(17)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) ++#define SET_CMC_TBL_A_CTRL_BSR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, \ ++ BIT(18)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) ++#define SET_CMC_TBL_A_CTRL_CAS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, \ ++ BIT(19)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) ++#define SET_CMC_TBL_DATA_BW_ER(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, \ ++ BIT(20)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) ++#define SET_CMC_TBL_LSIG_TXOP_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, \ ++ BIT(21)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) ++#define SET_CMC_TBL_CTRL_CNT_VLD(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, \ ++ BIT(27)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) ++#define SET_CMC_TBL_CTRL_CNT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); \ ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, \ ++ GENMASK(31, 28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) ++#define SET_CMC_TBL_RESP_REF_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, \ ++ GENMASK(8, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) ++#define SET_CMC_TBL_ALL_ACK_SUPPORT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) ++#define SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, \ ++ BIT(13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) ++#define SET_CMC_TBL_NTX_PATH_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, \ ++ GENMASK(19, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_A(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, \ ++ GENMASK(21, 20)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_B(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, \ ++ GENMASK(23, 22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_C(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, \ ++ GENMASK(25, 24)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) ++#define SET_CMC_TBL_PATH_MAP_D(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, \ ++ GENMASK(27, 26)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) ++#define SET_CMC_TBL_ANTSEL_A(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, \ ++ BIT(28)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) ++#define SET_CMC_TBL_ANTSEL_B(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, \ ++ BIT(29)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) ++#define SET_CMC_TBL_ANTSEL_C(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, \ ++ BIT(30)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) ++#define SET_CMC_TBL_ANTSEL_D(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); \ ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, \ ++ BIT(31)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) ++#define SET_CMC_TBL_ADDR_CAM_INDEX(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, \ ++ GENMASK(7, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) ++#define SET_CMC_TBL_PAID(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, \ ++ GENMASK(16, 8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_ULDL BIT(0) ++#define SET_CMC_TBL_ULDL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, \ ++ BIT(17)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) ++#define SET_CMC_TBL_DOPPLER_CTRL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, \ ++ GENMASK(19, 18)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) ++#define SET_CMC_TBL_NOMINAL_PKT_PADDING(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ ++ GENMASK(21, 20)); \ ++} while (0) ++#define SET_CMC_TBL_NOMINAL_PKT_PADDING40(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ ++ GENMASK(23, 22)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) ++#define SET_CMC_TBL_TXPWR_TOLERENCE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, \ ++ GENMASK(27, 24)); \ ++} while (0) ++#define SET_CMC_TBL_NOMINAL_PKT_PADDING80(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); \ ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ ++ GENMASK(31, 30)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NC GENMASK(2, 0) ++#define SET_CMC_TBL_NC(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, \ ++ GENMASK(2, 0)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NR GENMASK(2, 0) ++#define SET_CMC_TBL_NR(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, \ ++ GENMASK(5, 3)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_NG GENMASK(1, 0) ++#define SET_CMC_TBL_NG(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, \ ++ GENMASK(7, 6)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CB GENMASK(1, 0) ++#define SET_CMC_TBL_CB(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, \ ++ GENMASK(9, 8)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CS GENMASK(1, 0) ++#define SET_CMC_TBL_CS(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, \ ++ GENMASK(11, 10)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) ++#define SET_CMC_TBL_CSI_TXBF_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, \ ++ BIT(12)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) ++#define SET_CMC_TBL_CSI_STBC_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, \ ++ BIT(13)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) ++#define SET_CMC_TBL_CSI_LDPC_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, \ ++ BIT(14)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) ++#define SET_CMC_TBL_CSI_PARA_EN(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, \ ++ BIT(15)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) ++#define SET_CMC_TBL_CSI_FIX_RATE(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, \ ++ GENMASK(24, 16)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) ++#define SET_CMC_TBL_CSI_GI_LTF(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, \ ++ GENMASK(27, 25)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0) ++#define SET_CMC_TBL_CSI_GID_SEL(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, \ ++ BIT(29)); \ ++} while (0) ++#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) ++#define SET_CMC_TBL_CSI_BW(table, val) \ ++do { \ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); \ ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, \ ++ GENMASK(31, 30)); \ ++} while (0) ++ ++#define SET_FWROLE_MAINTAIN_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_FWROLE_MAINTAIN_SELF_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)) ++#define SET_FWROLE_MAINTAIN_UPD_MODE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)) ++#define SET_FWROLE_MAINTAIN_WIFI_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)) ++ ++#define SET_JOININFO_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_JOININFO_OP(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(8)) ++#define SET_JOININFO_BAND(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(9)) ++#define SET_JOININFO_WMM(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)) ++#define SET_JOININFO_TGR(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(12)) ++#define SET_JOININFO_ISHESTA(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(13)) ++#define SET_JOININFO_DLBW(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)) ++#define SET_JOININFO_TF_MAC_PAD(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)) ++#define SET_JOININFO_DL_T_PE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)) ++#define SET_JOININFO_PORT_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)) ++#define SET_JOININFO_NET_TYPE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)) ++#define SET_JOININFO_WIFI_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)) ++#define SET_JOININFO_SELF_ROLE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)) ++ ++#define SET_GENERAL_PKT_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_GENERAL_PKT_PROBRSP_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_GENERAL_PKT_PSPOLL_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)) ++#define SET_GENERAL_PKT_NULL_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) ++#define SET_GENERAL_PKT_QOS_NULL_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)) ++#define SET_GENERAL_PKT_CTS2SELF_ID(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) ++ ++#define SET_LOG_CFG_LEVEL(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_LOG_CFG_PATH(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_LOG_CFG_COMP(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)) ++#define SET_LOG_CFG_COMP_EXT(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)) ++ ++#define SET_BA_CAM_VALID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(0)) ++#define SET_BA_CAM_INIT_REQ(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(1)) ++#define SET_BA_CAM_ENTRY_IDX(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)) ++#define SET_BA_CAM_TID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)) ++#define SET_BA_CAM_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_BA_CAM_BMAP_SIZE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) ++#define SET_BA_CAM_SSN(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)) ++ ++#define SET_LPS_PARM_MACID(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) ++#define SET_LPS_PARM_PSMODE(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) ++#define SET_LPS_PARM_RLBM(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) ++#define SET_LPS_PARM_SMARTPS(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)) ++#define SET_LPS_PARM_AWAKEINTERVAL(h2c, val) \ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) ++#define SET_LPS_PARM_VOUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)) ++#define SET_LPS_PARM_VIUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)) ++#define SET_LPS_PARM_BEUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)) ++#define SET_LPS_PARM_BKUAPSD(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)) ++#define SET_LPS_PARM_LASTRPWM(h2c, val) \ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) ++ ++enum rtw89_btc_btf_h2c_class { ++ BTFC_SET = 0x10, ++ BTFC_GET = 0x11, ++ BTFC_FW_EVENT = 0x12, ++}; ++ ++enum rtw89_btc_btf_set { ++ SET_REPORT_EN = 0x0, ++ SET_SLOT_TABLE, ++ SET_MREG_TABLE, ++ SET_CX_POLICY, ++ SET_GPIO_DBG, ++ SET_DRV_INFO, ++ SET_DRV_EVENT, ++ SET_BT_WREG_ADDR, ++ SET_BT_WREG_VAL, ++ SET_BT_RREG_ADDR, ++ SET_BT_WL_CH_INFO, ++ SET_BT_INFO_REPORT, ++ SET_BT_IGNORE_WLAN_ACT, ++ SET_BT_TX_PWR, ++ SET_BT_LNA_CONSTRAIN, ++ SET_BT_GOLDEN_RX_RANGE, ++ SET_BT_PSD_REPORT, ++ SET_H2C_TEST, ++ SET_MAX1, ++}; ++ ++enum rtw89_btc_cxdrvinfo { ++ CXDRVINFO_INIT = 0, ++ CXDRVINFO_ROLE, ++ CXDRVINFO_DBCC, ++ CXDRVINFO_SMAP, ++ CXDRVINFO_RFK, ++ CXDRVINFO_RUN, ++ CXDRVINFO_CTRL, ++ CXDRVINFO_SCAN, ++ CXDRVINFO_MAX, ++}; ++ ++#define RTW89_SET_FWCMD_CXHDR_TYPE(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXHDR_LEN(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)) ++ ++#define RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)) ++#define RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)) ++#define RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)) ++#define RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)) ++#define RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)) ++#define RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)) ++#define RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)) ++#define RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)) ++ ++#define RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, val) \ ++ u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)) ++#define RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, val) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, val, n) \ ++ u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, val, n) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, val, n) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, val, n) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0)) ++#define RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, val, n) \ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0)) ++ ++#define RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)) ++#define RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)) ++#define RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)) ++#define RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)) ++ ++#define RTW89_SET_FWCMD_CXRFK_STATE(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)) ++#define RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)) ++#define RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)) ++#define RTW89_SET_FWCMD_CXRFK_BAND(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)) ++#define RTW89_SET_FWCMD_CXRFK_TYPE(cmd, val) \ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)) ++ ++#define RTW89_C2H_HEADER_LEN 8 ++ ++#define RTW89_GET_C2H_CATEGORY(c2h) \ ++ le32_get_bits(*((__le32 *)c2h), GENMASK(1, 0)) ++#define RTW89_GET_C2H_CLASS(c2h) \ ++ le32_get_bits(*((__le32 *)c2h), GENMASK(7, 2)) ++#define RTW89_GET_C2H_FUNC(c2h) \ ++ le32_get_bits(*((__le32 *)c2h), GENMASK(15, 8)) ++#define RTW89_GET_C2H_LEN(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 1), GENMASK(13, 0)) ++ ++#define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) ++#define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) ++ ++#define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++#define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(31, 24)) ++ ++#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) ++#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) ++#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) ++#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++ ++#define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 0)) ++#define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++#define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(6, 0)) ++#define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(9, 8)) ++#define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(12, 10)) ++#define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ ++ le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(14, 13)) ++ ++/* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS ++ * HT-new: [6:5]: NA, [4:0]: MCS ++ */ ++#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) ++#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) ++#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) ++#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ ++ FIELD_PREP(GENMASK(2, 0), mcs)) ++ ++#define RTW89_FW_HDR_SIZE 32 ++#define RTW89_FW_SECTION_HDR_SIZE 16 ++ ++#define RTW89_MFW_SIG 0xFF ++ ++struct rtw89_mfw_info { ++ u8 cv; ++ u8 type; /* enum rtw89_fw_type */ ++ u8 mp; ++ u8 rsvd; ++ __le32 shift; ++ __le32 size; ++ u8 rsvd2[4]; ++} __packed; ++ ++struct rtw89_mfw_hdr { ++ u8 sig; /* RTW89_MFW_SIG */ ++ u8 fw_nr; ++ u8 rsvd[14]; ++ struct rtw89_mfw_info info[]; ++} __packed; ++ ++struct fwcmd_hdr { ++ __le32 hdr0; ++ __le32 hdr1; ++}; ++ ++#define RTW89_H2C_RF_PAGE_SIZE 500 ++#define RTW89_H2C_RF_PAGE_NUM 3 ++struct rtw89_fw_h2c_rf_reg_info { ++ enum rtw89_rf_path rf_path; ++ __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; ++ u16 curr_idx; ++}; ++ ++#define H2C_SEC_CAM_LEN 24 ++ ++#define H2C_HEADER_LEN 8 ++#define H2C_HDR_CAT GENMASK(1, 0) ++#define H2C_HDR_CLASS GENMASK(7, 2) ++#define H2C_HDR_FUNC GENMASK(15, 8) ++#define H2C_HDR_DEL_TYPE GENMASK(19, 16) ++#define H2C_HDR_H2C_SEQ GENMASK(31, 24) ++#define H2C_HDR_TOTAL_LEN GENMASK(13, 0) ++#define H2C_HDR_REC_ACK BIT(14) ++#define H2C_HDR_DONE_ACK BIT(15) ++ ++#define FWCMD_TYPE_H2C 0 ++ ++#define H2C_CAT_MAC 0x1 ++ ++/* CLASS 0 - FW INFO */ ++#define H2C_CL_FW_INFO 0x0 ++#define H2C_FUNC_LOG_CFG 0x0 ++#define H2C_FUNC_MAC_GENERAL_PKT 0x1 ++ ++/* CLASS 2 - PS */ ++#define H2C_CL_MAC_PS 0x2 ++#define H2C_FUNC_MAC_LPS_PARM 0x0 ++ ++/* CLASS 3 - FW download */ ++#define H2C_CL_MAC_FWDL 0x3 ++#define H2C_FUNC_MAC_FWHDR_DL 0x0 ++ ++/* CLASS 5 - Frame Exchange */ ++#define H2C_CL_MAC_FR_EXCHG 0x5 ++#define H2C_FUNC_MAC_CCTLINFO_UD 0x2 ++ ++/* CLASS 6 - Address CAM */ ++#define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 ++#define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 ++ ++/* CLASS 8 - Media Status Report */ ++#define H2C_CL_MAC_MEDIA_RPT 0x8 ++#define H2C_FUNC_MAC_JOININFO 0x0 ++#define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 ++ ++/* CLASS 9 - FW offload */ ++#define H2C_CL_MAC_FW_OFLD 0x9 ++#define H2C_FUNC_MAC_MACID_PAUSE 0x8 ++#define H2C_FUNC_USR_EDCA 0xF ++#define H2C_FUNC_OFLD_CFG 0x14 ++ ++/* CLASS 10 - Security CAM */ ++#define H2C_CL_MAC_SEC_CAM 0xa ++#define H2C_FUNC_MAC_SEC_UPD 0x1 ++ ++/* CLASS 12 - BA CAM */ ++#define H2C_CL_BA_CAM 0xc ++#define H2C_FUNC_MAC_BA_CAM 0x0 ++ ++#define H2C_CAT_OUTSRC 0x2 ++ ++#define H2C_CL_OUTSRC_RA 0x1 ++#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 ++ ++#define H2C_CL_OUTSRC_RF_REG_A 0x8 ++#define H2C_CL_OUTSRC_RF_REG_B 0x9 ++ ++int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); ++int rtw89_fw_recognize(struct rtw89_dev *rtwdev); ++int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); ++int rtw89_load_firmware(struct rtw89_dev *rtwdev); ++void rtw89_unload_firmware(struct rtw89_dev *rtwdev); ++int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); ++void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u8 type, u8 cat, u8 class, u8 func, ++ bool rack, bool dack, u32 len); ++int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid); ++int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta); ++int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); ++void rtw89_fw_c2h_work(struct work_struct *work); ++int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, ++ enum rtw89_upd_mode upd_mode); ++int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 dis_conn); ++int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, ++ bool pause); ++int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u8 ac, u32 val); ++int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); ++int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_h2c_rf_reg_info *info, ++ u16 len, u8 page); ++int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, ++ u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, ++ bool rack, bool dack); ++int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); ++void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); ++void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); ++int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); ++int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, ++ struct ieee80211_ampdu_params *params); ++int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, ++ struct rtw89_lps_parm *lps_param); ++struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len); ++struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len); ++int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_h2c_info *h2c_info, ++ struct rtw89_mac_c2h_info *c2h_info); ++int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); ++void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +new file mode 100644 +index 000000000000..0171a5a7b1de +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -0,0 +1,3838 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++#include "util.h" ++ ++int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, ++ enum rtw89_mac_hwmod_sel sel) ++{ ++ u32 val, r_val; ++ ++ if (sel == RTW89_DMAC_SEL) { ++ r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); ++ val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); ++ } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { ++ r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); ++ val = B_AX_CMAC_EN; ++ } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { ++ r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); ++ val = B_AX_CMAC1_FEN; ++ } else { ++ return -EINVAL; ++ } ++ if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || ++ (val & r_val) != val) ++ return -EFAULT; ++ ++ return 0; ++} ++ ++int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) ++{ ++ u8 lte_ctrl; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, ++ 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); ++ if (ret) ++ rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); ++ ++ rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); ++ rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); ++ ++ return ret; ++} ++ ++int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) ++{ ++ u8 lte_ctrl; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, ++ 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); ++ if (ret) ++ rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); ++ ++ rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); ++ *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); ++ ++ return ret; ++} ++ ++static ++int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) ++{ ++ u32 ctrl_reg, data_reg, ctrl_data; ++ u32 val; ++ int ret; ++ ++ switch (ctrl->type) { ++ case DLE_CTRL_TYPE_WDE: ++ ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; ++ data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; ++ ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | ++ FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | ++ B_AX_WDE_DFI_ACTIVE; ++ break; ++ case DLE_CTRL_TYPE_PLE: ++ ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; ++ data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; ++ ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | ++ FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | ++ B_AX_PLE_DFI_ACTIVE; ++ break; ++ default: ++ rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); ++ return -EINVAL; ++ } ++ ++ rtw89_write32(rtwdev, ctrl_reg, ctrl_data); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), ++ 1, 1000, false, rtwdev, ctrl_reg); ++ if (ret) { ++ rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", ++ ctrl_reg, ctrl_data); ++ return ret; ++ } ++ ++ ctrl->out_data = rtw89_read32(rtwdev, data_reg); ++ return 0; ++} ++ ++static int dle_dfi_quota(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_dle_dfi_quota *quota) ++{ ++ struct rtw89_mac_dle_dfi_ctrl ctrl; ++ int ret; ++ ++ ctrl.type = quota->dle_type; ++ ctrl.target = DLE_DFI_TYPE_QUOTA; ++ ctrl.addr = quota->qtaid; ++ ret = dle_dfi_ctrl(rtwdev, &ctrl); ++ if (ret) { ++ rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); ++ return ret; ++ } ++ ++ quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); ++ quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); ++ return 0; ++} ++ ++static int dle_dfi_qempty(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_dle_dfi_qempty *qempty) ++{ ++ struct rtw89_mac_dle_dfi_ctrl ctrl; ++ u32 ret; ++ ++ ctrl.type = qempty->dle_type; ++ ctrl.target = DLE_DFI_TYPE_QEMPTY; ++ ctrl.addr = qempty->grpsel; ++ ret = dle_dfi_ctrl(rtwdev, &ctrl); ++ if (ret) { ++ rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); ++ return ret; ++ } ++ ++ qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); ++ return 0; ++} ++ ++static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) ++{ ++ rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); ++} ++ ++static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_mac_dle_dfi_qempty qempty; ++ struct rtw89_mac_dle_dfi_quota quota; ++ struct rtw89_mac_dle_dfi_ctrl ctrl; ++ u32 val, not_empty, i; ++ int ret; ++ ++ qempty.dle_type = DLE_CTRL_TYPE_PLE; ++ qempty.grpsel = 0; ++ ret = dle_dfi_qempty(rtwdev, &qempty); ++ if (ret) ++ rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); ++ else ++ rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); ++ ++ for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { ++ if (!(not_empty & BIT(0))) ++ continue; ++ ctrl.type = DLE_CTRL_TYPE_PLE; ++ ctrl.target = DLE_DFI_TYPE_QLNKTBL; ++ ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | ++ FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); ++ ret = dle_dfi_ctrl(rtwdev, &ctrl); ++ if (ret) ++ rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); ++ else ++ rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, ++ FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, ++ ctrl.out_data)); ++ } ++ ++ quota.dle_type = DLE_CTRL_TYPE_PLE; ++ quota.qtaid = 6; ++ ret = dle_dfi_quota(rtwdev, "a); ++ if (ret) ++ rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); ++ else ++ rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", ++ quota.rsv_pgnum, quota.use_pgnum); ++ ++ val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); ++ rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", ++ FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); ++ rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", ++ FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); ++ ++ dump_err_status_dispatcher(rtwdev); ++} ++ ++static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, ++ enum mac_ax_err_info err) ++{ ++ u32 dbg, event; ++ ++ dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); ++ event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); ++ ++ switch (event) { ++ case MAC_AX_L0_TO_L1_RX_QTA_LOST: ++ rtw89_info(rtwdev, "quota lost!\n"); ++ rtw89_mac_dump_qta_lost(rtwdev); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, ++ enum mac_ax_err_info err) ++{ ++ u32 dmac_err, cmac_err; ++ ++ if (err != MAC_AX_ERR_L1_ERR_DMAC && ++ err != MAC_AX_ERR_L0_PROMOTE_TO_L1) ++ return; ++ ++ rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); ++ rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); ++ ++ cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); ++ rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); ++ dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); ++ rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); ++ ++ if (dmac_err) { ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); ++ } ++ ++ if (dmac_err & B_AX_WDRLS_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_WSEC_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); ++ rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); ++ } ++ ++ if (dmac_err & B_AX_MPDU_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); ++ dump_err_status_dispatcher(rtwdev); ++ } ++ ++ if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); ++ rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); ++ } ++ ++ if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); ++ rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); ++ rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); ++ rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); ++ rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); ++ rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); ++ dump_err_status_dispatcher(rtwdev); ++ } ++ ++ if (dmac_err & B_AX_PKTIN_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); ++ } ++ ++ if (dmac_err & B_AX_DISPATCH_ERR_FLAG) ++ dump_err_status_dispatcher(rtwdev); ++ ++ if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { ++ rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); ++ } ++ ++ if (dmac_err & BIT(11)) { ++ rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); ++ rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", ++ rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); ++ rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); ++ } ++ ++ if (cmac_err & B_AX_DMA_TOP_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DLE_CTRL)); ++ } ++ ++ if (cmac_err & B_AX_PHYINTF_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); ++ } ++ ++ if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); ++ rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_WMAC_RX_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); ++ rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); ++ } ++ ++ if (cmac_err & B_AX_WMAC_TX_ERR_IND) { ++ rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", ++ rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); ++ rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); ++ } ++ ++ rtwdev->hci.ops->dump_err_status(rtwdev); ++ ++ if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) ++ rtw89_mac_dump_l0_to_l1(rtwdev, err); ++ ++ rtw89_info(rtwdev, "<---\n"); ++} ++ ++u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) ++{ ++ u32 err; ++ int ret; ++ ++ ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, ++ false, rtwdev, R_AX_HALT_C2H_CTRL); ++ if (ret) { ++ rtw89_warn(rtwdev, "Polling FW err status fail\n"); ++ return ret; ++ } ++ ++ err = rtw89_read32(rtwdev, R_AX_HALT_C2H); ++ rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); ++ ++ rtw89_fw_st_dbg_dump(rtwdev); ++ rtw89_mac_dump_err_status(rtwdev, err); ++ ++ return err; ++} ++EXPORT_SYMBOL(rtw89_mac_get_err_status); ++ ++int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) ++{ ++ u32 halt; ++ int ret = 0; ++ ++ if (err > MAC_AX_SET_ERR_MAX) { ++ rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); ++ return -EINVAL; ++ } ++ ++ ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, ++ 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); ++ return -EFAULT; ++ } ++ ++ rtw89_write32(rtwdev, R_AX_HALT_H2C, err); ++ rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); ++ ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_mac_set_err_status); ++ ++const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie = { ++ 2, 40, 0, 0, 1, 0, 0, 0 ++}; ++ ++static int hfc_reset_param(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_param_ini param_ini = {NULL}; ++ u8 qta_mode = rtwdev->mac.dle_info.qta_mode; ++ ++ switch (rtwdev->hci.type) { ++ case RTW89_HCI_TYPE_PCIE: ++ param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; ++ param->en = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (param_ini.pub_cfg) ++ param->pub_cfg = *param_ini.pub_cfg; ++ ++ if (param_ini.prec_cfg) { ++ param->prec_cfg = *param_ini.prec_cfg; ++ rtwdev->hal.sw_amsdu_max_size = ++ param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; ++ } ++ ++ if (param_ini.ch_cfg) ++ param->ch_cfg = param_ini.ch_cfg; ++ ++ memset(¶m->ch_info, 0, sizeof(param->ch_info)); ++ memset(¶m->pub_info, 0, sizeof(param->pub_info)); ++ param->mode = param_ini.mode; ++ ++ return 0; ++} ++ ++static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; ++ const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; ++ const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; ++ ++ if (ch >= RTW89_DMA_CH_NUM) ++ return -EINVAL; ++ ++ if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || ++ ch_cfg[ch].max > pub_cfg->pub_max) ++ return -EINVAL; ++ if (ch_cfg[ch].grp >= grp_num) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; ++ struct rtw89_hfc_pub_info *info = ¶m->pub_info; ++ ++ if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { ++ if (rtwdev->chip->chip_id == RTL8852A) ++ return 0; ++ else ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; ++ ++ if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) ++ return 0; ++ ++ return 0; ++} ++ ++static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; ++ int ret = 0; ++ u32 val = 0; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ ret = hfc_ch_cfg_chk(rtwdev, ch); ++ if (ret) ++ return ret; ++ ++ if (ch > RTW89_DMA_B1HI) ++ return -EINVAL; ++ ++ val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | ++ u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | ++ (cfg[ch].grp ? B_AX_GRP : 0); ++ rtw89_write32(rtwdev, R_AX_ACH0_PAGE_CTRL + ch * 4, val); ++ ++ return 0; ++} ++ ++static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_ch_info *info = param->ch_info; ++ const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; ++ u32 val; ++ u32 ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (ch > RTW89_DMA_H2C) ++ return -EINVAL; ++ ++ val = rtw89_read32(rtwdev, R_AX_ACH0_PAGE_INFO + ch * 4); ++ info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); ++ if (ch < RTW89_DMA_H2C) ++ info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); ++ else ++ info[ch].used = cfg[ch].min - info[ch].aval; ++ ++ return 0; ++} ++ ++static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; ++ u32 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ ret = hfc_pub_cfg_chk(rtwdev); ++ if (ret) ++ return ret; ++ ++ val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | ++ u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); ++ rtw89_write32(rtwdev, R_AX_PUB_PAGE_CTRL1, val); ++ ++ val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); ++ rtw89_write32(rtwdev, R_AX_WP_PAGE_CTRL2, val); ++ ++ return 0; ++} ++ ++static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; ++ struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; ++ struct rtw89_hfc_pub_info *info = ¶m->pub_info; ++ u32 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO1); ++ info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); ++ info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO3); ++ info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); ++ info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); ++ info->pub_aval = ++ u32_get_bits(rtw89_read32(rtwdev, R_AX_PUB_PAGE_INFO2), ++ B_AX_PUB_AVAL_PG_MASK); ++ info->wp_aval = ++ u32_get_bits(rtw89_read32(rtwdev, R_AX_WP_PAGE_INFO1), ++ B_AX_WP_AVAL_PG_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL); ++ param->en = val & B_AX_HCI_FC_EN ? 1 : 0; ++ param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; ++ param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); ++ prec_cfg->ch011_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); ++ prec_cfg->h2c_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); ++ prec_cfg->wp_ch07_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); ++ prec_cfg->wp_ch811_full_cond = ++ u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_CH_PAGE_CTRL); ++ prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); ++ prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_CTRL2); ++ pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_WP_PAGE_CTRL1); ++ prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); ++ prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_WP_PAGE_CTRL2); ++ pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); ++ ++ val = rtw89_read32(rtwdev, R_AX_PUB_PAGE_CTRL1); ++ pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); ++ pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); ++ ++ ret = hfc_pub_info_chk(rtwdev); ++ if (param->en && ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; ++ u32 val; ++ ++ val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); ++ rtw89_write32(rtwdev, R_AX_CH_PAGE_CTRL, val); ++ ++ rtw89_write32_mask(rtwdev, R_AX_HCI_FC_CTRL, ++ B_AX_HCI_FC_CH12_FULL_COND_MASK, ++ prec_cfg->h2c_full_cond); ++} ++ ++static void hfc_mix_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; ++ const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; ++ u32 val; ++ ++ val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | ++ u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); ++ rtw89_write32(rtwdev, R_AX_CH_PAGE_CTRL, val); ++ ++ val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); ++ rtw89_write32(rtwdev, R_AX_PUB_PAGE_CTRL2, val); ++ ++ val = u32_encode_bits(prec_cfg->wp_ch07_prec, ++ B_AX_PREC_PAGE_WP_CH07_MASK) | ++ u32_encode_bits(prec_cfg->wp_ch811_prec, ++ B_AX_PREC_PAGE_WP_CH811_MASK); ++ rtw89_write32(rtwdev, R_AX_WP_PAGE_CTRL1, val); ++ ++ val = u32_replace_bits(rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL), ++ param->mode, B_AX_HCI_FC_MODE_MASK); ++ val = u32_replace_bits(val, prec_cfg->ch011_full_cond, ++ B_AX_HCI_FC_WD_FULL_COND_MASK); ++ val = u32_replace_bits(val, prec_cfg->h2c_full_cond, ++ B_AX_HCI_FC_CH12_FULL_COND_MASK); ++ val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, ++ B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); ++ val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, ++ B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); ++ rtw89_write32(rtwdev, R_AX_HCI_FC_CTRL, val); ++} ++ ++static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) ++{ ++ struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, R_AX_HCI_FC_CTRL); ++ param->en = en; ++ param->h2c_en = h2c_en; ++ val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); ++ val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : ++ (val & ~B_AX_HCI_FC_CH12_EN); ++ rtw89_write32(rtwdev, R_AX_HCI_FC_CTRL, val); ++} ++ ++static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) ++{ ++ u8 ch; ++ u32 ret = 0; ++ ++ if (reset) ++ ret = hfc_reset_param(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ hfc_func_en(rtwdev, false, false); ++ ++ if (!en && h2c_en) { ++ hfc_h2c_cfg(rtwdev); ++ hfc_func_en(rtwdev, en, h2c_en); ++ return ret; ++ } ++ ++ for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { ++ ret = hfc_ch_ctrl(rtwdev, ch); ++ if (ret) ++ return ret; ++ } ++ ++ ret = hfc_pub_ctrl(rtwdev); ++ if (ret) ++ return ret; ++ ++ hfc_mix_cfg(rtwdev); ++ if (en || h2c_en) { ++ hfc_func_en(rtwdev, en, h2c_en); ++ udelay(10); ++ } ++ for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { ++ ret = hfc_upd_ch_info(rtwdev, ch); ++ if (ret) ++ return ret; ++ } ++ ret = hfc_upd_mix_info(rtwdev); ++ ++ return ret; ++} ++ ++#define PWR_POLL_CNT 2000 ++static int pwr_cmd_poll(struct rtw89_dev *rtwdev, ++ const struct rtw89_pwr_cfg *cfg) ++{ ++ u8 val = 0; ++ int ret; ++ u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? ++ cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; ++ ++ ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), ++ 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); ++ ++ if (!ret) ++ return 0; ++ ++ rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); ++ rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); ++ rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); ++ ++ return -EBUSY; ++} ++ ++static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, ++ u8 intf_msk, const struct rtw89_pwr_cfg *cfg) ++{ ++ const struct rtw89_pwr_cfg *cur_cfg; ++ u32 addr; ++ u8 val; ++ ++ for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { ++ if (!(cur_cfg->intf_msk & intf_msk) || ++ !(cur_cfg->cv_msk & cv_msk)) ++ continue; ++ ++ switch (cur_cfg->cmd) { ++ case PWR_CMD_WRITE: ++ addr = cur_cfg->addr; ++ ++ if (cur_cfg->base == PWR_BASE_SDIO) ++ addr |= SDIO_LOCAL_BASE_ADDR; ++ ++ val = rtw89_read8(rtwdev, addr); ++ val &= ~(cur_cfg->msk); ++ val |= (cur_cfg->val & cur_cfg->msk); ++ ++ rtw89_write8(rtwdev, addr, val); ++ break; ++ case PWR_CMD_POLL: ++ if (pwr_cmd_poll(rtwdev, cur_cfg)) ++ return -EBUSY; ++ break; ++ case PWR_CMD_DELAY: ++ if (cur_cfg->val == PWR_DELAY_US) ++ udelay(cur_cfg->addr); ++ else ++ fsleep(cur_cfg->addr * 1000); ++ break; ++ default: ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, ++ const struct rtw89_pwr_cfg * const *cfg_seq) ++{ ++ int ret; ++ ++ for (; *cfg_seq; cfg_seq++) { ++ ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), ++ PWR_INTF_MSK_PCIE, *cfg_seq); ++ if (ret) ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static enum rtw89_rpwm_req_pwr_state ++rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) ++{ ++ enum rtw89_rpwm_req_pwr_state state; ++ ++ switch (rtwdev->ps_mode) { ++ case RTW89_PS_MODE_RFOFF: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; ++ break; ++ case RTW89_PS_MODE_CLK_GATED: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; ++ break; ++ case RTW89_PS_MODE_PWR_GATED: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; ++ break; ++ default: ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; ++ break; ++ } ++ return state; ++} ++ ++static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, ++ enum rtw89_rpwm_req_pwr_state req_pwr_state) ++{ ++ u16 request; ++ ++ request = rtw89_read16(rtwdev, R_AX_RPWM); ++ request ^= request | PS_RPWM_TOGGLE; ++ ++ rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & ++ RPWM_SEQ_NUM_MAX; ++ request |= FIELD_PREP(PS_RPWM_SEQ_NUM, rtwdev->mac.rpwm_seq_num); ++ ++ request |= req_pwr_state; ++ ++ if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) ++ request |= PS_RPWM_ACK; ++ ++ rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); ++} ++ ++static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, ++ enum rtw89_rpwm_req_pwr_state req_pwr_state) ++{ ++ bool request_deep_mode; ++ bool in_deep_mode; ++ u8 rpwm_req_num; ++ u8 cpwm_rsp_seq; ++ u8 cpwm_seq; ++ u8 cpwm_status; ++ ++ if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) ++ request_deep_mode = true; ++ else ++ request_deep_mode = false; ++ ++ if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) ++ in_deep_mode = true; ++ else ++ in_deep_mode = false; ++ ++ if (request_deep_mode != in_deep_mode) ++ return -EPERM; ++ ++ if (request_deep_mode) ++ return 0; ++ ++ rpwm_req_num = rtwdev->mac.rpwm_seq_num; ++ cpwm_rsp_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, ++ PS_CPWM_RSP_SEQ_NUM); ++ ++ if (rpwm_req_num != cpwm_rsp_seq) ++ return -EPERM; ++ ++ rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & ++ CPWM_SEQ_NUM_MAX; ++ ++ cpwm_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_SEQ_NUM); ++ if (cpwm_seq != rtwdev->mac.cpwm_seq_num) ++ return -EPERM; ++ ++ cpwm_status = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_STATE); ++ if (cpwm_status != req_pwr_state) ++ return -EPERM; ++ ++ return 0; ++} ++ ++void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) ++{ ++ enum rtw89_rpwm_req_pwr_state state; ++ int ret; ++ ++ if (enter) ++ state = rtw89_mac_get_req_pwr_state(rtwdev); ++ else ++ state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; ++ ++ rtw89_mac_send_rpwm(rtwdev, state); ++ ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, ++ 1000, 15000, false, rtwdev, state); ++ if (ret) ++ rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", ++ enter ? "entering" : "leaving"); ++} ++ ++static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) ++{ ++#define PWR_ACT 1 ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_pwr_cfg * const *cfg_seq; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ int ret; ++ u8 val; ++ ++ if (on) ++ cfg_seq = chip->pwr_on_seq; ++ else ++ cfg_seq = chip->pwr_off_seq; ++ ++ if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) ++ __rtw89_leave_ps_mode(rtwdev); ++ ++ val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); ++ if (on && val == PWR_ACT) { ++ rtw89_err(rtwdev, "MAC has already powered on\n"); ++ return -EBUSY; ++ } ++ ++ ret = rtw89_mac_pwr_seq(rtwdev, cfg_seq); ++ if (ret) ++ return ret; ++ ++ if (on) { ++ set_bit(RTW89_FLAG_POWERON, rtwdev->flags); ++ rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); ++ } else { ++ clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); ++ clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); ++ rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); ++ hal->current_channel = 0; ++ } ++ ++ return 0; ++#undef PWR_ACT ++} ++ ++void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) ++{ ++ rtw89_mac_power_switch(rtwdev, false); ++} ++ ++static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) ++{ ++ u32 func_en = 0; ++ u32 ck_en = 0; ++ u32 c1pc_en = 0; ++ u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; ++ u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; ++ ++ func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | ++ B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | ++ B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN; ++ ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | ++ B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | ++ B_AX_RMAC_CKEN; ++ c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P1_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P2_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P3_PC_EN | ++ B_AX_R_SYM_WLCMAC1_P4_PC_EN; ++ ++ if (en) { ++ if (mac_idx == RTW89_MAC_1) { ++ rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); ++ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_R_SYM_ISO_CMAC12PP); ++ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_CMAC1_FEN); ++ } ++ rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); ++ rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); ++ } else { ++ rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); ++ rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); ++ if (mac_idx == RTW89_MAC_1) { ++ rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_CMAC1_FEN); ++ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_R_SYM_ISO_CMAC12PP); ++ rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); ++ } ++ } ++ ++ return 0; ++} ++ ++static int dmac_func_en(struct rtw89_dev *rtwdev) ++{ ++ u32 val32; ++ u32 ret = 0; ++ ++ val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN | ++ B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | ++ B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | B_AX_STA_SCH_EN | ++ B_AX_TXPKT_CTRL_EN | B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN); ++ rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); ++ ++ val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | ++ B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | ++ B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | ++ B_AX_WD_RLS_CLK_EN); ++ rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); ++ ++ return ret; ++} ++ ++static int chip_func_en(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, B_AX_OCP_L1_MASK); ++ ++ return 0; ++} ++ ++static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = dmac_func_en(rtwdev); ++ if (ret) ++ return ret; ++ ++ ret = cmac_func_en(rtwdev, 0, true); ++ if (ret) ++ return ret; ++ ++ ret = chip_func_en(rtwdev); ++ if (ret) ++ return ret; ++ ++ return ret; ++} ++ ++/* PCIE 64 */ ++const struct rtw89_dle_size wde_size0 = { ++ RTW89_WDE_PG_64, 4095, 1, ++}; ++ ++/* DLFW */ ++const struct rtw89_dle_size wde_size4 = { ++ RTW89_WDE_PG_64, 0, 4096, ++}; ++ ++/* PCIE */ ++const struct rtw89_dle_size ple_size0 = { ++ RTW89_PLE_PG_128, 1520, 16, ++}; ++ ++/* DLFW */ ++const struct rtw89_dle_size ple_size4 = { ++ RTW89_PLE_PG_128, 64, 1472, ++}; ++ ++/* PCIE 64 */ ++const struct rtw89_wde_quota wde_qt0 = { ++ 3792, 196, 0, 107, ++}; ++ ++/* DLFW */ ++const struct rtw89_wde_quota wde_qt4 = { ++ 0, 0, 0, 0, ++}; ++ ++/* PCIE SCC */ ++const struct rtw89_ple_quota ple_qt4 = { ++ 264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8, ++}; ++ ++/* PCIE SCC */ ++const struct rtw89_ple_quota ple_qt5 = { ++ 264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120, ++}; ++ ++/* DLFW */ ++const struct rtw89_ple_quota ple_qt13 = { ++ 0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0 ++}; ++ ++static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, ++ enum rtw89_qta_mode mode) ++{ ++ struct rtw89_mac_info *mac = &rtwdev->mac; ++ const struct rtw89_dle_mem *cfg; ++ ++ cfg = &rtwdev->chip->dle_mem[mode]; ++ if (!cfg) ++ return NULL; ++ ++ if (cfg->mode != mode) { ++ rtw89_warn(rtwdev, "qta mode unmatch!\n"); ++ return NULL; ++ } ++ ++ mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; ++ mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; ++ mac->dle_info.qta_mode = mode; ++ mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; ++ mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; ++ ++ return cfg; ++} ++ ++static inline u32 dle_used_size(const struct rtw89_dle_size *wde, ++ const struct rtw89_dle_size *ple) ++{ ++ return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + ++ ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); ++} ++ ++static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) ++{ ++ if (enable) ++ rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, ++ B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); ++ else ++ rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, ++ B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); ++} ++ ++static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) ++{ ++ if (enable) ++ rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, ++ B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); ++ else ++ rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, ++ B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); ++} ++ ++static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) ++{ ++ const struct rtw89_dle_size *size_cfg; ++ u32 val; ++ u8 bound = 0; ++ ++ val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); ++ size_cfg = cfg->wde_size; ++ ++ switch (size_cfg->pge_size) { ++ default: ++ case RTW89_WDE_PG_64: ++ val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, ++ B_AX_WDE_PAGE_SEL_MASK); ++ break; ++ case RTW89_WDE_PG_128: ++ val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, ++ B_AX_WDE_PAGE_SEL_MASK); ++ break; ++ case RTW89_WDE_PG_256: ++ rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); ++ return -EINVAL; ++ } ++ ++ val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); ++ val = u32_replace_bits(val, size_cfg->lnk_pge_num, ++ B_AX_WDE_FREE_PAGE_NUM_MASK); ++ rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); ++ ++ val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); ++ bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) ++ * size_cfg->pge_size / DLE_BOUND_UNIT; ++ size_cfg = cfg->ple_size; ++ ++ switch (size_cfg->pge_size) { ++ default: ++ case RTW89_PLE_PG_64: ++ rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); ++ return -EINVAL; ++ case RTW89_PLE_PG_128: ++ val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, ++ B_AX_PLE_PAGE_SEL_MASK); ++ break; ++ case RTW89_PLE_PG_256: ++ val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, ++ B_AX_PLE_PAGE_SEL_MASK); ++ break; ++ } ++ ++ val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); ++ val = u32_replace_bits(val, size_cfg->lnk_pge_num, ++ B_AX_PLE_FREE_PAGE_NUM_MASK); ++ rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); ++ ++ return 0; ++} ++ ++#define INVALID_QT_WCPU U16_MAX ++#define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ ++ do { \ ++ val = ((_min_x) & \ ++ B_AX_ ## _module ## _MIN_SIZE_MASK) | \ ++ (((_max_x) << 16) & \ ++ B_AX_ ## _module ## _MAX_SIZE_MASK); \ ++ rtw89_write32(rtwdev, \ ++ R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ ++ val); \ ++ } while (0) ++#define SET_QUOTA(_x, _module, _idx) \ ++ SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) ++ ++static void wde_quota_cfg(struct rtw89_dev *rtwdev, ++ const struct rtw89_wde_quota *min_cfg, ++ const struct rtw89_wde_quota *max_cfg, ++ u16 ext_wde_min_qt_wcpu) ++{ ++ u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? ++ ext_wde_min_qt_wcpu : min_cfg->wcpu; ++ u32 val; ++ ++ SET_QUOTA(hif, WDE, 0); ++ SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); ++ SET_QUOTA(pkt_in, WDE, 3); ++ SET_QUOTA(cpu_io, WDE, 4); ++} ++ ++static void ple_quota_cfg(struct rtw89_dev *rtwdev, ++ const struct rtw89_ple_quota *min_cfg, ++ const struct rtw89_ple_quota *max_cfg) ++{ ++ u32 val; ++ ++ SET_QUOTA(cma0_tx, PLE, 0); ++ SET_QUOTA(cma1_tx, PLE, 1); ++ SET_QUOTA(c2h, PLE, 2); ++ SET_QUOTA(h2c, PLE, 3); ++ SET_QUOTA(wcpu, PLE, 4); ++ SET_QUOTA(mpdu_proc, PLE, 5); ++ SET_QUOTA(cma0_dma, PLE, 6); ++ SET_QUOTA(cma1_dma, PLE, 7); ++ SET_QUOTA(bb_rpt, PLE, 8); ++ SET_QUOTA(wd_rel, PLE, 9); ++ SET_QUOTA(cpu_io, PLE, 10); ++} ++ ++#undef SET_QUOTA ++ ++static void dle_quota_cfg(struct rtw89_dev *rtwdev, ++ const struct rtw89_dle_mem *cfg, ++ u16 ext_wde_min_qt_wcpu) ++{ ++ wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); ++ ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); ++} ++ ++static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, ++ enum rtw89_qta_mode ext_mode) ++{ ++ const struct rtw89_dle_mem *cfg, *ext_cfg; ++ u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; ++ int ret = 0; ++ u32 ini; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ cfg = get_dle_mem_cfg(rtwdev, mode); ++ if (!cfg) { ++ rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ if (mode == RTW89_QTA_DLFW) { ++ ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); ++ if (!ext_cfg) { ++ rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", ++ ext_mode); ++ ret = -EINVAL; ++ goto error; ++ } ++ ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; ++ } ++ ++ if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { ++ rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ dle_func_en(rtwdev, false); ++ dle_clk_en(rtwdev, true); ++ ++ ret = dle_mix_cfg(rtwdev, cfg); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); ++ goto error; ++ } ++ dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); ++ ++ dle_func_en(rtwdev, true); ++ ++ ret = read_poll_timeout(rtw89_read32, ini, ++ (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, ++ 2000, false, rtwdev, R_AX_WDE_INI_STATUS); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); ++ return ret; ++ } ++ ++ ret = read_poll_timeout(rtw89_read32, ini, ++ (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, ++ 2000, false, rtwdev, R_AX_PLE_INI_STATUS); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); ++ return ret; ++ } ++ ++ return 0; ++error: ++ dle_func_en(rtwdev, false); ++ rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", ++ rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); ++ rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", ++ rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); ++ ++ return ret; ++} ++ ++static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) ++{ ++ u32 msk32; ++ u32 val32; ++ ++ msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | ++ B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | ++ B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | ++ B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | ++ B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | ++ B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | ++ B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | ++ B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | ++ B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | ++ B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | ++ B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | ++ B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | ++ B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; ++ val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); ++ ++ if ((val32 & msk32) == msk32) ++ return true; ++ ++ return false; ++} ++ ++static int sta_sch_init(struct rtw89_dev *rtwdev) ++{ ++ u32 p_val; ++ u8 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ val = rtw89_read8(rtwdev, R_AX_SS_CTRL); ++ val |= B_AX_SS_EN; ++ rtw89_write8(rtwdev, R_AX_SS_CTRL, val); ++ ++ ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, ++ 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); ++ return ret; ++ } ++ ++ rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); ++ ++ return 0; ++} ++ ++static int mpdu_proc_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); ++ rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); ++ rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, ++ B_AX_APPEND_FCS | B_AX_A_ICV_ERR); ++ rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); ++ ++ return 0; ++} ++ ++static int sec_eng_init(struct rtw89_dev *rtwdev) ++{ ++ u32 val = 0; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) ++ return ret; ++ ++ val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); ++ /* init clock */ ++ val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); ++ /* init TX encryption */ ++ val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); ++ val |= (B_AX_MC_DEC | B_AX_BC_DEC); ++ val &= ~B_AX_TX_PARTIAL_MODE; ++ rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); ++ ++ /* init MIC ICV append */ ++ val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); ++ val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); ++ ++ /* option init */ ++ rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); ++ ++ return 0; ++} ++ ++static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret; ++ ++ ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); ++ return ret; ++ } ++ ++ ret = hfc_init(rtwdev, true, true, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); ++ return ret; ++ } ++ ++ ret = sta_sch_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); ++ return ret; ++ } ++ ++ ret = mpdu_proc_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); ++ return ret; ++ } ++ ++ ret = sec_eng_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ u16 p_val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); ++ ++ val = rtw89_read32(rtwdev, reg); ++ val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | ++ B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), ++ 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 ret; ++ u32 reg; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); ++ ++ return 0; ++} ++ ++static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, ++ enum rtw89_machdr_frame_type type, ++ enum rtw89_mac_fwd_target fwd_target, ++ u8 mac_idx) ++{ ++ u32 reg; ++ u32 val; ++ ++ switch (fwd_target) { ++ case RTW89_FWD_DONT_CARE: ++ val = RX_FLTR_FRAME_DROP; ++ break; ++ case RTW89_FWD_TO_HOST: ++ val = RX_FLTR_FRAME_TO_HOST; ++ break; ++ case RTW89_FWD_TO_WLAN_CPU: ++ val = RX_FLTR_FRAME_TO_WLCPU; ++ break; ++ default: ++ rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); ++ return -EINVAL; ++ } ++ ++ switch (type) { ++ case RTW89_MGNT: ++ reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); ++ break; ++ case RTW89_CTRL: ++ reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); ++ break; ++ case RTW89_DATA: ++ reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); ++ break; ++ default: ++ rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); ++ return -EINVAL; ++ } ++ rtw89_write32(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret, i; ++ u32 mac_ftlr, plcp_ftlr; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { ++ ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, ++ mac_idx); ++ if (ret) ++ return ret; ++ } ++ mac_ftlr = rtwdev->hal.rx_fltr; ++ plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | ++ B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | ++ B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | ++ B_AX_HE_SIGB_CRC_CHK; ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), ++ mac_ftlr); ++ rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), ++ plcp_ftlr); ++ ++ return 0; ++} ++ ++static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg, val32; ++ u32 b_rsp_chk_nav, b_rsp_chk_cca; ++ ++ b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | ++ B_AX_RSP_CHK_BASIC_NAV; ++ b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | ++ B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | ++ B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; ++ ++ switch (rtwdev->chip->chip_id) { ++ case RTL8852A: ++ case RTL8852B: ++ reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; ++ rtw89_write32(rtwdev, reg, val32); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; ++ rtw89_write32(rtwdev, reg, val32); ++ break; ++ default: ++ reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; ++ rtw89_write32(rtwdev, reg, val32); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); ++ val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; ++ rtw89_write32(rtwdev, reg, val32); ++ break; ++ } ++} ++ ++static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | ++ B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | ++ B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | ++ B_AX_CTN_CHK_INTRA_NAV | ++ B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | ++ B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | ++ B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | ++ B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); ++ val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | ++ B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | ++ B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | ++ B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); ++ ++ rtw89_write32(rtwdev, reg, val); ++ ++ _patch_dis_resp_chk(rtwdev, mac_idx); ++ ++ return 0; ++} ++ ++static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); ++ rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); ++ ++ return 0; ++} ++ ++static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); ++ rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); ++ ++ return 0; ++} ++ ++static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg, val, sifs; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; ++ val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); ++ ++ switch (rtwdev->chip->chip_id) { ++ case RTL8852A: ++ sifs = WMAC_SPEC_SIFS_OFDM_52A; ++ break; ++ case RTL8852B: ++ sifs = WMAC_SPEC_SIFS_OFDM_52B; ++ break; ++ default: ++ sifs = WMAC_SPEC_SIFS_OFDM_52C; ++ break; ++ } ++ val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; ++ val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); ++ ++ return 0; ++} ++ ++static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++#define TRXCFG_RMAC_CCA_TO 32 ++#define TRXCFG_RMAC_DATA_TO 15 ++#define RX_MAX_LEN_UNIT 512 ++#define PLD_RLS_MAX_PG 127 ++ int ret; ++ u32 reg, rx_max_len, rx_qta; ++ u16 val; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); ++ rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); ++ val = rtw89_read16(rtwdev, reg); ++ val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, ++ B_AX_RX_DLK_DATA_TIME_MASK); ++ val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, ++ B_AX_RX_DLK_CCA_TIME_MASK); ++ rtw89_write16(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); ++ rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); ++ if (mac_idx == RTW89_MAC_0) ++ rx_qta = rtwdev->mac.dle_info.c0_rx_qta; ++ else ++ rx_qta = rtwdev->mac.dle_info.c1_rx_qta; ++ rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; ++ rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / ++ RX_MAX_LEN_UNIT; ++ rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? ++ B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; ++ rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); ++ ++ if (rtwdev->chip->chip_id == RTL8852A && ++ rtwdev->hal.cv == CHIP_CBV) { ++ rtw89_write16_mask(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), ++ B_AX_RX_DLK_CCA_TIME_MASK, 0); ++ rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), ++ BIT(12)); ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); ++ rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); ++ ++ return ret; ++} ++ ++static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); ++ val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); ++ val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); ++ rtw89_write32(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) ++{ ++ const struct rtw89_dle_mem *cfg; ++ ++ cfg = get_dle_mem_cfg(rtwdev, mode); ++ if (!cfg) { ++ rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); ++ return false; ++ } ++ ++ return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); ++} ++ ++static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 val, reg; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { ++ reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, ++ B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); ++ val |= B_AX_HW_CTS2SELF_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); ++ val &= ~B_AX_PTCL_TX_ARB_TO_MODE; ++ rtw89_write32(rtwdev, reg, val); ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); ++ val |= B_AX_HW_CTS2SELF_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret; ++ ++ ret = scheduler_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = addr_cam_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, ++ ret); ++ return ret; ++ } ++ ++ ret = rx_fltr_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, ++ ret); ++ return ret; ++ } ++ ++ ret = cca_ctrl_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, ++ ret); ++ return ret; ++ } ++ ++ ret = spatial_reuse_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", ++ mac_idx, ret); ++ return ret; ++ } ++ ++ ret = tmac_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = trxptcl_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = rmac_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = cmac_com_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ ret = ptcl_init(rtwdev, mac_idx); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, ++ struct rtw89_mac_c2h_info *c2h_info) ++{ ++ struct rtw89_mac_h2c_info h2c_info = {0}; ++ u32 ret; ++ ++ h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; ++ h2c_info.content_len = 0; ++ ++ ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); ++ if (ret) ++ return ret; ++ ++ if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_mac_c2h_info c2h_info = {0}; ++ struct rtw89_c2h_phy_cap *cap = ++ (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; ++ u32 ret; ++ ++ ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); ++ if (ret) ++ return ret; ++ ++ hal->tx_nss = cap->tx_nss ? ++ min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; ++ hal->rx_nss = cap->rx_nss ? ++ min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", ++ hal->tx_nss, cap->tx_nss, chip->tx_nss, ++ hal->rx_nss, cap->rx_nss, chip->rx_nss); ++ ++ return 0; ++} ++ ++static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, ++ u16 tx_en_u16, u16 mask_u16) ++{ ++ u32 ret; ++ struct rtw89_mac_c2h_info c2h_info = {0}; ++ struct rtw89_mac_h2c_info h2c_info = {0}; ++ struct rtw89_h2creg_sch_tx_en *h2creg = ++ (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; ++ ++ h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; ++ h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; ++ h2creg->tx_en = tx_en_u16; ++ h2creg->mask = mask_u16; ++ h2creg->band = band; ++ ++ ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); ++ if (ret) ++ return ret; ++ ++ if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, ++ u16 tx_en, u16 tx_en_mask) ++{ ++ u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); ++ u16 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) ++ return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, ++ tx_en, tx_en_mask); ++ ++ val = rtw89_read16(rtwdev, reg); ++ val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); ++ rtw89_write16(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, ++ u16 *tx_en, enum rtw89_sch_tx_sel sel) ++{ ++ int ret; ++ ++ *tx_en = rtw89_read16(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); ++ ++ switch (sel) { ++ case RTW89_SCH_TX_SEL_ALL: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 0xffff); ++ if (ret) ++ return ret; ++ break; ++ case RTW89_SCH_TX_SEL_HIQ: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, ++ 0, B_AX_CTN_TXEN_HGQ); ++ if (ret) ++ return ret; ++ break; ++ case RTW89_SCH_TX_SEL_MG0: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, ++ 0, B_AX_CTN_TXEN_MGQ); ++ if (ret) ++ return ret; ++ break; ++ case RTW89_SCH_TX_SEL_MACID: ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 0xffff); ++ if (ret) ++ return ret; ++ break; ++ default: ++ return 0; ++ } ++ ++ return 0; ++} ++ ++int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en) ++{ ++ int ret; ++ ++ ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, 0xffff); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, ++ bool wd) ++{ ++ u32 val, reg; ++ int ret; ++ ++ reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; ++ val = buf_len; ++ val |= B_AX_WD_BUF_REQ_EXEC; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; ++ ++ ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, ++ 1, 2000, false, rtwdev, reg); ++ if (ret) ++ return 0xffff; ++ ++ return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); ++} ++ ++static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, ++ struct rtw89_cpuio_ctrl *ctrl_para, ++ bool wd) ++{ ++ u32 val, cmd_type, reg; ++ int ret; ++ ++ cmd_type = ctrl_para->cmd_type; ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; ++ val = 0; ++ val = u32_replace_bits(val, ctrl_para->start_pktid, ++ B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); ++ val = u32_replace_bits(val, ctrl_para->end_pktid, ++ B_AX_WD_CPUQ_OP_END_PKTID_MASK); ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; ++ val = 0; ++ val = u32_replace_bits(val, ctrl_para->src_pid, ++ B_AX_CPUQ_OP_SRC_PID_MASK); ++ val = u32_replace_bits(val, ctrl_para->src_qid, ++ B_AX_CPUQ_OP_SRC_QID_MASK); ++ val = u32_replace_bits(val, ctrl_para->dst_pid, ++ B_AX_CPUQ_OP_DST_PID_MASK); ++ val = u32_replace_bits(val, ctrl_para->dst_qid, ++ B_AX_CPUQ_OP_DST_QID_MASK); ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; ++ val = 0; ++ val = u32_replace_bits(val, cmd_type, ++ B_AX_CPUQ_OP_CMD_TYPE_MASK); ++ val = u32_replace_bits(val, ctrl_para->macid, ++ B_AX_CPUQ_OP_MACID_MASK); ++ val = u32_replace_bits(val, ctrl_para->pkt_num, ++ B_AX_CPUQ_OP_PKTNUM_MASK); ++ val |= B_AX_WD_CPUQ_OP_EXEC; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; ++ ++ ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, ++ 1, 2000, false, rtwdev, reg); ++ if (ret) ++ return ret; ++ ++ if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || ++ cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) ++ ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); ++ ++ return 0; ++} ++ ++static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) ++{ ++ const struct rtw89_dle_mem *cfg; ++ struct rtw89_cpuio_ctrl ctrl_para = {0}; ++ u16 pkt_id; ++ int ret; ++ ++ cfg = get_dle_mem_cfg(rtwdev, mode); ++ if (!cfg) { ++ rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); ++ return -EINVAL; ++ } ++ ++ if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { ++ rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); ++ return -EINVAL; ++ } ++ ++ dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); ++ ++ pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); ++ if (pkt_id == 0xffff) { ++ rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); ++ return -ENOMEM; ++ } ++ ++ ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; ++ ctrl_para.start_pktid = pkt_id; ++ ctrl_para.end_pktid = pkt_id; ++ ctrl_para.pkt_num = 0; ++ ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; ++ ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; ++ ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); ++ return -EFAULT; ++ } ++ ++ pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); ++ if (pkt_id == 0xffff) { ++ rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); ++ return -ENOMEM; ++ } ++ ++ ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; ++ ctrl_para.start_pktid = pkt_id; ++ ctrl_para.end_pktid = pkt_id; ++ ctrl_para.pkt_num = 0; ++ ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; ++ ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; ++ ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ int ret; ++ u32 reg; ++ u8 val; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); ++ ++ ret = read_poll_timeout(rtw89_read8, val, ++ (val & B_AX_PTCL_TX_ON_STAT) == 0, ++ SW_CVR_DUR_US, ++ SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, ++ false, rtwdev, reg); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int band1_enable(struct rtw89_dev *rtwdev) ++{ ++ int ret, i; ++ u32 sleep_bak[4] = {0}; ++ u32 pause_bak[4] = {0}; ++ u16 tx_en; ++ ++ ret = rtw89_mac_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); ++ pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); ++ rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); ++ rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); ++ } ++ ++ ret = band_idle_ck_b(rtwdev, 0); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); ++ return ret; ++ } ++ ++ ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); ++ return ret; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); ++ rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); ++ } ++ ++ ret = rtw89_mac_resume_sch_tx(rtwdev, 0, tx_en); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); ++ return ret; ++ } ++ ++ ret = cmac_func_en(rtwdev, 1, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); ++ return ret; ++ } ++ ++ ret = cmac_init(rtwdev, 1); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); ++ return ret; ++ } ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, ++ B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); ++ ++ return 0; ++} ++ ++static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, ++ enum rtw89_mac_hwmod_sel sel) ++{ ++ u32 reg, val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); ++ if (ret) { ++ rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", ++ sel, mac_idx); ++ return ret; ++ } ++ ++ if (sel == RTW89_DMAC_SEL) { ++ rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, ++ B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | ++ B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | ++ B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1, ++ B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | ++ B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, ++ B_AX_HDT_PKT_FAIL_DBG_INT_EN | ++ B_AX_HDT_OFFSET_UNMATCH_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, ++ B_AX_CPU_SHIFT_EN_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, ++ B_AX_PLE_GETNPG_STRPG_ERR_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, ++ B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN); ++ rtw89_write32_set(rtwdev, R_AX_HD0IMR, B_AX_WDT_PTFM_INT_EN); ++ rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, ++ B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN); ++ } else if (sel == RTW89_CMAC_SEL) { ++ reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); ++ rtw89_write32_clr(rtwdev, reg, ++ B_AX_SORT_NON_IDLE_ERR_INT_EN); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_DLE_CTRL, mac_idx); ++ rtw89_write32_clr(rtwdev, reg, ++ B_AX_NO_RESERVE_PAGE_ERR_IMR | ++ B_AX_RXDATA_FSM_HANG_ERROR_IMR); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); ++ val = B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | ++ B_AX_TX_RECORD_PKTID_ERR_INT_EN | ++ B_AX_FSM_TIMEOUT_ERR_INT_EN; ++ rtw89_write32(rtwdev, reg, val); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_PHYINFO_ERR_IMR, mac_idx); ++ rtw89_write32_set(rtwdev, reg, ++ B_AX_PHY_TXON_TIMEOUT_INT_EN | ++ B_AX_CCK_CCA_TIMEOUT_INT_EN | ++ B_AX_OFDM_CCA_TIMEOUT_INT_EN | ++ B_AX_DATA_ON_TIMEOUT_INT_EN | ++ B_AX_STS_ON_TIMEOUT_INT_EN | ++ B_AX_CSI_ON_TIMEOUT_INT_EN); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_RMAC_ERR_ISR, mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val |= (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN | ++ B_AX_RMAC_RX_TIMEOUT_INT_EN | ++ B_AX_RMAC_CSI_TIMEOUT_INT_EN); ++ val &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | ++ B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | ++ B_AX_RMAC_CCA_TIMEOUT_INT_EN | ++ B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN); ++ rtw89_write32(rtwdev, reg, val); ++ } else { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret = 0; ++ ++ if (enable) { ++ ret = band1_enable(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); ++ return ret; ++ } ++ ++ ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); ++ return ret; ++ } ++ } else { ++ rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int set_host_rpr(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { ++ rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, ++ B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); ++ rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, ++ B_AX_RLSRPT0_FLTR_MAP_MASK); ++ } else { ++ rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, ++ B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); ++ rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, ++ B_AX_RLSRPT0_FLTR_MAP_MASK); ++ } ++ ++ rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); ++ rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); ++ ++ return 0; ++} ++ ++static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) ++{ ++ enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; ++ int ret; ++ ++ ret = dmac_init(rtwdev, 0); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); ++ return ret; ++ } ++ ++ ret = cmac_init(rtwdev, 0); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); ++ return ret; ++ } ++ ++ if (is_qta_dbcc(rtwdev, qta_mode)) { ++ ret = rtw89_mac_dbcc_enable(rtwdev, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); ++ return ret; ++ } ++ } ++ ++ ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); ++ return ret; ++ } ++ ++ ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); ++ return ret; ++ } ++ ++ ret = set_host_rpr(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) ++{ ++ clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); ++ ++ rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); ++ rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); ++} ++ ++static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, ++ bool dlfw) ++{ ++ u32 val; ++ int ret; ++ ++ if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) ++ return -EFAULT; ++ ++ rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); ++ rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); ++ ++ val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); ++ val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); ++ val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, ++ B_AX_WCPU_FWDL_STS_MASK); ++ ++ if (dlfw) ++ val |= B_AX_WCPU_FWDL_EN; ++ ++ rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); ++ rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, ++ boot_reason); ++ rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); ++ ++ if (!dlfw) { ++ mdelay(5); ++ ++ ret = rtw89_fw_check_rdy(rtwdev); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_mac_fw_dl_pre_init(struct rtw89_dev *rtwdev) ++{ ++ u32 val; ++ int ret; ++ ++ val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | ++ B_AX_PKT_BUF_EN; ++ rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); ++ ++ val = B_AX_DISPATCHER_CLK_EN; ++ rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); ++ ++ ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); ++ return ret; ++ } ++ ++ ret = hfc_init(rtwdev, true, false, true); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write32_set(rtwdev, R_AX_HCI_FUNC_EN, ++ B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); ++} ++ ++void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, ++ B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); ++ rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, ++ B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | ++ B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); ++ rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); ++} ++ ++void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, ++ B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); ++ rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, ++ B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | ++ B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); ++ rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); ++} ++ ++int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_power_switch(rtwdev, true); ++ if (ret) { ++ rtw89_mac_power_switch(rtwdev, false); ++ ret = rtw89_mac_power_switch(rtwdev, true); ++ if (ret) ++ return ret; ++ } ++ ++ rtw89_mac_hci_func_en(rtwdev); ++ ++ if (rtwdev->hci.ops->mac_pre_init) { ++ ret = rtwdev->hci.ops->mac_pre_init(rtwdev); ++ if (ret) ++ return ret; ++ } ++ ++ ret = rtw89_mac_fw_dl_pre_init(rtwdev); ++ if (ret) ++ return ret; ++ ++ rtw89_mac_disable_cpu(rtwdev); ++ ret = rtw89_mac_enable_cpu(rtwdev, 0, true); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++int rtw89_mac_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_mac_partial_init(rtwdev); ++ if (ret) ++ goto fail; ++ ++ rtw89_mac_enable_bb_rf(rtwdev); ++ if (ret) ++ goto fail; ++ ++ ret = rtw89_mac_sys_init(rtwdev); ++ if (ret) ++ goto fail; ++ ++ ret = rtw89_mac_trx_init(rtwdev); ++ if (ret) ++ goto fail; ++ ++ if (rtwdev->hci.ops->mac_post_init) { ++ ret = rtwdev->hci.ops->mac_post_init(rtwdev); ++ if (ret) ++ goto fail; ++ } ++ ++ rtw89_fw_send_all_early_h2c(rtwdev); ++ rtw89_fw_h2c_set_ofld_cfg(rtwdev); ++ ++ return ret; ++fail: ++ rtw89_mac_power_switch(rtwdev, false); ++ ++ return ret; ++} ++ ++static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ u8 i; ++ ++ for (i = 0; i < 4; i++) { ++ rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, ++ DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); ++ } ++} ++ ++static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, ++ CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); ++ rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); ++} ++ ++static int rtw89_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) ++{ ++ u8 sh = FIELD_GET(GENMASK(4, 0), macid); ++ u8 grp = macid >> 5; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); ++ ++ return 0; ++} ++ ++static const struct rtw89_port_reg rtw_port_base = { ++ .port_cfg = R_AX_PORT_CFG_P0, ++ .tbtt_prohib = R_AX_TBTT_PROHIB_P0, ++ .bcn_area = R_AX_BCN_AREA_P0, ++ .bcn_early = R_AX_BCNERLYINT_CFG_P0, ++ .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, ++ .tbtt_agg = R_AX_TBTT_AGG_P0, ++ .bcn_space = R_AX_BCN_SPACE_CFG_P0, ++ .bcn_forcetx = R_AX_BCN_FORCETX_P0, ++ .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, ++ .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, ++ .dtim_ctrl = R_AX_DTIM_CTRL_P0, ++ .tbtt_shift = R_AX_TBTT_SHIFT_P0, ++ .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, ++ .tsftr_l = R_AX_TSFTR_LOW_P0, ++ .tsftr_h = R_AX_TSFTR_HIGH_P0 ++}; ++ ++#define BCN_INTERVAL 100 ++#define BCN_ERLY_DEF 160 ++#define BCN_SETUP_DEF 2 ++#define BCN_HOLD_DEF 200 ++#define BCN_MASK_DEF 0 ++#define TBTT_ERLY_DEF 5 ++#define BCN_SET_UNIT 32 ++#define BCN_ERLY_SET_DLY (10 * 2) ++ ++static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) ++ return; ++ ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); ++ rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); ++ rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); ++ ++ msleep(vif->bss_conf.beacon_int + 1); ++ ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | ++ B_AX_BRK_SETUP); ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); ++ rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); ++} ++ ++static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); ++} ++ ++static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); ++} ++ ++static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, ++ rtwvif->net_type); ++} ++ ++static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; ++ u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); ++} ++ ++static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || ++ rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; ++ u32 bit = B_AX_RX_BSSID_FIT_EN; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); ++} ++ ++static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || ++ rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); ++} ++ ++static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || ++ rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; ++ ++ if (en) ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); ++ else ++ rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); ++} ++ ++static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, ++ bcn_int); ++} ++ ++static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, ++ B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); ++} ++ ++static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, ++ B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); ++} ++ ++static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, ++ B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); ++} ++ ++static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, ++ B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); ++} ++ ++static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ static const u32 masks[RTW89_PORT_NUM] = { ++ B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, ++ B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, ++ B_AX_BSS_COLOB_AX_PORT_4_MASK, ++ }; ++ u8 port = rtwvif->port; ++ u32 reg_base; ++ u32 reg; ++ u8 bss_color; ++ ++ bss_color = vif->bss_conf.he_bss_color.color; ++ reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; ++ reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); ++ rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); ++} ++ ++static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ u8 port = rtwvif->port; ++ u32 reg; ++ ++ if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) ++ return; ++ ++ if (port == 0) { ++ reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); ++ rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); ++ } ++} ++ ++static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ u8 port = rtwvif->port; ++ u32 reg; ++ u32 val; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); ++ val = rtw89_read32(rtwdev, reg); ++ val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); ++ if (port == 0) ++ val &= ~BIT(0); ++ rtw89_write32(rtwdev, reg, val); ++} ++ ++static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); ++} ++ ++static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ const struct rtw89_port_reg *p = &rtw_port_base; ++ ++ rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, ++ BCN_ERLY_DEF); ++} ++ ++int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ ret = rtw89_mac_port_update(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); ++ rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); ++ ++ ret = rtw89_set_macid_pause(rtwdev, rtwvif->mac_id, false); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_h2c_vif_maintain(rtwdev, rtwvif, RTW89_VIF_CREATE); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_cam_init(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif->mac_id); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ ret = rtw89_fw_h2c_vif_maintain(rtwdev, rtwvif, RTW89_VIF_REMOVE); ++ if (ret) ++ return ret; ++ ++ rtw89_cam_deinit(rtwdev, rtwvif); ++ ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ u8 port = rtwvif->port; ++ ++ if (port >= RTW89_PORT_NUM) ++ return -EINVAL; ++ ++ rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); ++ rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); ++ rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); ++ rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); ++ fsleep(BCN_ERLY_SET_DLY); ++ rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); ++ ++ return 0; ++} ++ ++int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, ++ RTW89_MAX_MAC_ID_NUM); ++ if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) ++ return -ENOSPC; ++ ++ ret = rtw89_mac_vif_init(rtwdev, rtwvif); ++ if (ret) ++ goto release_mac_id; ++ ++ return 0; ++ ++release_mac_id: ++ rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); ++ ++ return ret; ++} ++ ++int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ int ret; ++ ++ ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); ++ rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); ++ ++ return ret; ++} ++ ++static void ++rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++} ++ ++static void ++rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", ++ RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), ++ RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), ++ RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), ++ RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); ++} ++ ++static void ++rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", ++ RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), ++ RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); ++} ++ ++static void ++rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), ++ RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); ++} ++ ++static ++void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = { ++ [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, ++ [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, ++ [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = NULL, ++ [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, ++ [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, ++}; ++ ++static ++void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = { ++ [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, ++ [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, ++ [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, ++}; ++ ++void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func) ++{ ++ void (*handler)(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = NULL; ++ ++ switch (class) { ++ case RTW89_MAC_C2H_CLASS_INFO: ++ if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) ++ handler = rtw89_mac_c2h_info_handler[func]; ++ break; ++ case RTW89_MAC_C2H_CLASS_OFLD: ++ if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) ++ handler = rtw89_mac_c2h_ofld_handler[func]; ++ break; ++ case RTW89_MAC_C2H_CLASS_FWDBG: ++ return; ++ default: ++ rtw89_info(rtwdev, "c2h class %d not support\n", class); ++ return; ++ } ++ if (!handler) { ++ rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, ++ func); ++ return; ++ } ++ handler(rtwdev, skb, len); ++} ++ ++bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 *cr) ++{ ++ const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; ++ enum rtw89_qta_mode mode = dle_mem->mode; ++ u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); ++ ++ if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { ++ rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", ++ addr); ++ goto error; ++ } ++ ++ if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) ++ if (mode == RTW89_QTA_SCC) { ++ rtw89_err(rtwdev, ++ "[TXPWR] addr=0x%x but hw not enable\n", ++ addr); ++ goto error; ++ } ++ ++ *cr = addr; ++ return true; ++ ++error: ++ rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", ++ addr, phy_idx); ++ ++ return false; ++} ++ ++int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) ++{ ++ u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); ++ int ret = 0; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (!enable) { ++ rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); ++ return ret; ++ } ++ ++ rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | ++ B_AX_APP_MAC_INFO_RPT | ++ B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | ++ B_AX_PPDU_STAT_RPT_CRC32); ++ rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, ++ RTW89_PRPT_DEST_HOST); ++ ++ return ret; ++} ++ ++void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++#define MAC_AX_TIME_TH_SH 5 ++#define MAC_AX_LEN_TH_SH 4 ++#define MAC_AX_TIME_TH_MAX 255 ++#define MAC_AX_LEN_TH_MAX 255 ++#define MAC_AX_TIME_TH_DEF 88 ++#define MAC_AX_LEN_TH_DEF 4080 ++ struct ieee80211_hw *hw = rtwdev->hw; ++ u32 rts_threshold = hw->wiphy->rts_threshold; ++ u32 time_th, len_th; ++ u32 reg; ++ ++ if (rts_threshold == (u32)-1) { ++ time_th = MAC_AX_TIME_TH_DEF; ++ len_th = MAC_AX_LEN_TH_DEF; ++ } else { ++ time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; ++ len_th = rts_threshold; ++ } ++ ++ time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); ++ len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); ++ rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); ++ rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); ++} ++ ++void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) ++{ ++ bool empty; ++ int ret; ++ ++ if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) ++ return; ++ ++ ret = read_poll_timeout(dle_is_txq_empty, empty, empty, ++ 10000, 200000, false, rtwdev); ++ if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) ++ rtw89_info(rtwdev, "timed out to flush queues\n"); ++} ++ ++int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) ++{ ++ u8 val; ++ u16 val16; ++ u32 val32; ++ int ret; ++ ++ rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); ++ rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); ++ rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); ++ rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); ++ rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); ++ rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); ++ ++ val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); ++ val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; ++ rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); ++ ++ ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); ++ if (ret) { ++ rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); ++ return ret; ++ } ++ val32 = val32 & B_AX_WL_RX_CTRL; ++ ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); ++ if (ret) { ++ rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); ++ return ret; ++ } ++ ++ switch (coex->pta_mode) { ++ case RTW89_MAC_AX_COEX_RTK_MODE: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); ++ val &= ~B_AX_BTMODE_MASK; ++ val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); ++ ++ val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); ++ rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); ++ ++ val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); ++ val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; ++ val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); ++ rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); ++ break; ++ case RTW89_MAC_AX_COEX_CSR_MODE: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); ++ val &= ~B_AX_BTMODE_MASK; ++ val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); ++ ++ val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); ++ val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; ++ val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); ++ val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; ++ val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); ++ val16 &= ~B_AX_BT_STAT_DELAY_MASK; ++ val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); ++ val16 |= B_AX_ENHANCED_BT; ++ rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); ++ ++ rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (coex->direction) { ++ case RTW89_MAC_AX_COEX_INNER: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); ++ val = (val & ~BIT(2)) | BIT(1); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); ++ break; ++ case RTW89_MAC_AX_COEX_OUTPUT: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); ++ val = val | BIT(1) | BIT(0); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); ++ break; ++ case RTW89_MAC_AX_COEX_INPUT: ++ val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); ++ val = val & ~(BIT(2) | BIT(1)); ++ rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, ++ const struct rtw89_mac_ax_coex_gnt *gnt_cfg) ++{ ++ u32 val, ret; ++ ++ ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); ++ if (ret) { ++ rtw89_err(rtwdev, "Read LTE fail!\n"); ++ return ret; ++ } ++ val = (gnt_cfg->band[0].gnt_bt ? ++ B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL : 0) | ++ (gnt_cfg->band[0].gnt_bt_sw_en ? ++ B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL : 0) | ++ (gnt_cfg->band[0].gnt_wl ? ++ B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL : 0) | ++ (gnt_cfg->band[0].gnt_wl_sw_en ? ++ B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL : 0) | ++ (gnt_cfg->band[1].gnt_bt ? ++ B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL : 0) | ++ (gnt_cfg->band[1].gnt_bt_sw_en ? ++ B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL : 0) | ++ (gnt_cfg->band[1].gnt_wl ? ++ B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL : 0) | ++ (gnt_cfg->band[1].gnt_wl_sw_en ? ++ B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL : 0); ++ ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); ++ if (ret) { ++ rtw89_err(rtwdev, "Write LTE fail!\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) ++{ ++ u32 reg; ++ u8 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); ++ val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | ++ (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | ++ (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | ++ (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | ++ (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0); ++ rtw89_write8(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) ++{ ++ u32 fw_sb; ++ ++ fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); ++ fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); ++ fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; ++ if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) ++ fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; ++ else ++ fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; ++ val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); ++ val = B_AX_TOGGLE | ++ FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | ++ FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); ++ rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); ++ fsleep(1000); /* avoid BT FW loss information */ ++} ++ ++u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) ++{ ++ return rtw89_read32(rtwdev, R_AX_SCOREBOARD); ++} ++ ++int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) ++{ ++ u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); ++ ++ val = wl ? val | BIT(2) : val & ~BIT(2); ++ rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); ++ ++ return 0; ++} ++ ++bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) ++{ ++ u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); ++ ++ return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); ++} ++ ++static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) ++{ ++ u32 reg; ++ u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | ++ B_AX_BFMEE_HE_NDPA_EN; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); ++ reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); ++ if (en) { ++ set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); ++ rtw89_write32_set(rtwdev, reg, mask); ++ } else { ++ clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); ++ rtw89_write32_clr(rtwdev, reg, mask); ++ } ++} ++ ++static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) ++{ ++ u32 reg; ++ u32 val32; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ /* AP mode set tx gid to 63 */ ++ /* STA mode set tx gid to 0(default) */ ++ reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); ++ rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); ++ val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); ++ val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); ++ rtw89_write32(rtwdev, reg, val32); ++ rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | ++ B_AX_BFMEE_USE_NSTS | ++ B_AX_BFMEE_CSI_GID_SEL | ++ B_AX_BFMEE_CSI_FORCE_RETE_EN); ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); ++ rtw89_write32(rtwdev, reg, ++ u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | ++ u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | ++ u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); ++ ++ return 0; ++} ++ ++static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ u8 mac_idx = rtwvif->mac_idx; ++ u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; ++ u8 port_sel = rtwvif->port; ++ u8 sound_dim = 3, t; ++ u8 *phy_cap = sta->he_cap.he_cap_elem.phy_cap_info; ++ u32 reg; ++ u16 val; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || ++ (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { ++ ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); ++ stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); ++ t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, ++ phy_cap[5]); ++ sound_dim = min(sound_dim, t); ++ } ++ if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || ++ (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { ++ ldpc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); ++ stbc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); ++ t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, ++ sta->vht_cap.cap); ++ sound_dim = min(sound_dim, t); ++ } ++ nc = min(nc, sound_dim); ++ nr = min(nr, sound_dim); ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); ++ ++ val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | ++ FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); ++ ++ if (port_sel == 0) ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ else ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); ++ ++ rtw89_write16(rtwdev, reg, val); ++ ++ return 0; ++} ++ ++static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); ++ u32 reg; ++ u8 mac_idx = rtwvif->mac_idx; ++ int ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ if (sta->he_cap.has_he) { ++ rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | ++ BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | ++ BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); ++ } ++ if (sta->vht_cap.vht_supported) { ++ rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | ++ BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | ++ BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); ++ } ++ if (sta->ht_cap.ht_supported) { ++ rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | ++ BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | ++ BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); ++ } ++ reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); ++ rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); ++ rtw89_write32(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), ++ rrsc); ++ ++ return 0; ++} ++ ++void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ if (rtw89_sta_has_beamformer_cap(sta)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BF, ++ "initialize bfee for new association\n"); ++ rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); ++ rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); ++ rtw89_mac_csi_rrsc(rtwdev, vif, sta); ++ } ++} ++ ++void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); ++} ++ ++void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf) ++{ ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ u8 mac_idx = rtwvif->mac_idx; ++ __le32 *p; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); ++ ++ p = (__le32 *)conf->mu_group.membership; ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), ++ le32_to_cpu(p[0])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), ++ le32_to_cpu(p[1])); ++ ++ p = (__le32 *)conf->mu_group.position; ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), ++ le32_to_cpu(p[0])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), ++ le32_to_cpu(p[1])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), ++ le32_to_cpu(p[2])); ++ rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), ++ le32_to_cpu(p[3])); ++} ++ ++struct rtw89_mac_bf_monitor_iter_data { ++ struct rtw89_dev *rtwdev; ++ struct ieee80211_sta *down_sta; ++ int count; ++}; ++ ++static ++void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_mac_bf_monitor_iter_data *iter_data = ++ (struct rtw89_mac_bf_monitor_iter_data *)data; ++ struct ieee80211_sta *down_sta = iter_data->down_sta; ++ int *count = &iter_data->count; ++ ++ if (down_sta == sta) ++ return; ++ ++ if (rtw89_sta_has_beamformer_cap(sta)) ++ (*count)++; ++} ++ ++void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, bool disconnect) ++{ ++ struct rtw89_mac_bf_monitor_iter_data data; ++ ++ data.rtwdev = rtwdev; ++ data.down_sta = disconnect ? sta : NULL; ++ data.count = 0; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_mac_bf_monitor_calc_iter, ++ &data); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); ++ if (data.count) ++ set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); ++ else ++ clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); ++} ++ ++void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ struct rtw89_vif *rtwvif; ++ bool en = stats->tx_tfc_lv > stats->rx_tfc_lv ? false : true; ++ bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); ++ ++ if (en == old) ++ return; ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); ++} ++ ++static int ++__rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ u32 tx_time) ++{ ++#define MAC_AX_DFLT_TX_TIME 5280 ++ u8 mac_idx = rtwsta->rtwvif->mac_idx; ++ u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; ++ u32 reg; ++ int ret = 0; ++ ++ if (rtwsta->cctl_tx_time) { ++ rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; ++ ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); ++ } else { ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); ++ return ret; ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, ++ max_tx_time >> 5); ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ bool resume, u32 tx_time) ++{ ++ int ret = 0; ++ ++ if (!resume) { ++ rtwsta->cctl_tx_time = true; ++ ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); ++ } else { ++ ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); ++ rtwsta->cctl_tx_time = false; ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ u32 *tx_time) ++{ ++ u8 mac_idx = rtwsta->rtwvif->mac_idx; ++ u32 reg; ++ int ret = 0; ++ ++ if (rtwsta->cctl_tx_time) { ++ *tx_time = (rtwsta->ampdu_max_time + 1) << 9; ++ } else { ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); ++ return ret; ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); ++ *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, ++ bool resume, u8 tx_retry) ++{ ++ int ret = 0; ++ ++ rtwsta->data_tx_cnt_lmt = tx_retry; ++ ++ if (!resume) { ++ rtwsta->cctl_tx_retry_limit = true; ++ ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); ++ } else { ++ ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); ++ rtwsta->cctl_tx_retry_limit = false; ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, u8 *tx_retry) ++{ ++ u8 mac_idx = rtwsta->rtwvif->mac_idx; ++ u32 reg; ++ int ret = 0; ++ ++ if (rtwsta->cctl_tx_retry_limit) { ++ *tx_retry = rtwsta->data_tx_cnt_lmt; ++ } else { ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) { ++ rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); ++ return ret; ++ } ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); ++ *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); ++ } ++ ++ return ret; ++} ++ ++int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en) ++{ ++ u8 mac_idx = rtwvif->mac_idx; ++ u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; ++ u32 reg; ++ u32 ret; ++ ++ ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); ++ if (ret) ++ return ret; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); ++ if (en) ++ rtw89_write16_set(rtwdev, reg, set); ++ else ++ rtw89_write16_clr(rtwdev, reg, set); ++ ++ return 0; ++} +diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h +new file mode 100644 +index 000000000000..6f3db8a2a9c2 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/mac.h +@@ -0,0 +1,860 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_MAC_H__ ++#define __RTW89_MAC_H__ ++ ++#include "core.h" ++ ++#define MAC_MEM_DUMP_PAGE_SIZE 0x40000 ++#define ADDR_CAM_ENT_SIZE 0x40 ++#define BSSID_CAM_ENT_SIZE 0x08 ++#define HFC_PAGE_UNIT 64 ++ ++enum rtw89_mac_hwmod_sel { ++ RTW89_DMAC_SEL = 0, ++ RTW89_CMAC_SEL = 1, ++ ++ RTW89_MAC_INVALID, ++}; ++ ++enum rtw89_mac_fwd_target { ++ RTW89_FWD_DONT_CARE = 0, ++ RTW89_FWD_TO_HOST = 1, ++ RTW89_FWD_TO_WLAN_CPU = 2 ++}; ++ ++enum rtw89_mac_wd_dma_intvl { ++ RTW89_MAC_WD_DMA_INTVL_0S, ++ RTW89_MAC_WD_DMA_INTVL_256NS, ++ RTW89_MAC_WD_DMA_INTVL_512NS, ++ RTW89_MAC_WD_DMA_INTVL_768NS, ++ RTW89_MAC_WD_DMA_INTVL_1US, ++ RTW89_MAC_WD_DMA_INTVL_1_5US, ++ RTW89_MAC_WD_DMA_INTVL_2US, ++ RTW89_MAC_WD_DMA_INTVL_4US, ++ RTW89_MAC_WD_DMA_INTVL_8US, ++ RTW89_MAC_WD_DMA_INTVL_16US, ++ RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE ++}; ++ ++enum rtw89_mac_multi_tag_num { ++ RTW89_MAC_TAG_NUM_1, ++ RTW89_MAC_TAG_NUM_2, ++ RTW89_MAC_TAG_NUM_3, ++ RTW89_MAC_TAG_NUM_4, ++ RTW89_MAC_TAG_NUM_5, ++ RTW89_MAC_TAG_NUM_6, ++ RTW89_MAC_TAG_NUM_7, ++ RTW89_MAC_TAG_NUM_8, ++ RTW89_MAC_TAG_NUM_DEF = 0xFE ++}; ++ ++enum rtw89_mac_lbc_tmr { ++ RTW89_MAC_LBC_TMR_8US = 0, ++ RTW89_MAC_LBC_TMR_16US, ++ RTW89_MAC_LBC_TMR_32US, ++ RTW89_MAC_LBC_TMR_64US, ++ RTW89_MAC_LBC_TMR_128US, ++ RTW89_MAC_LBC_TMR_256US, ++ RTW89_MAC_LBC_TMR_512US, ++ RTW89_MAC_LBC_TMR_1MS, ++ RTW89_MAC_LBC_TMR_2MS, ++ RTW89_MAC_LBC_TMR_4MS, ++ RTW89_MAC_LBC_TMR_8MS, ++ RTW89_MAC_LBC_TMR_DEF = 0xFE ++}; ++ ++enum rtw89_mac_cpuio_op_cmd_type { ++ CPUIO_OP_CMD_GET_1ST_PID = 0, ++ CPUIO_OP_CMD_GET_NEXT_PID = 1, ++ CPUIO_OP_CMD_ENQ_TO_TAIL = 4, ++ CPUIO_OP_CMD_ENQ_TO_HEAD = 5, ++ CPUIO_OP_CMD_DEQ = 8, ++ CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, ++ CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 ++}; ++ ++enum rtw89_mac_wde_dle_port_id { ++ WDE_DLE_PORT_ID_DISPATCH = 0, ++ WDE_DLE_PORT_ID_PKTIN = 1, ++ WDE_DLE_PORT_ID_CMAC0 = 3, ++ WDE_DLE_PORT_ID_CMAC1 = 4, ++ WDE_DLE_PORT_ID_CPU_IO = 6, ++ WDE_DLE_PORT_ID_WDRLS = 7, ++ WDE_DLE_PORT_ID_END = 8 ++}; ++ ++enum rtw89_mac_wde_dle_queid_wdrls { ++ WDE_DLE_QUEID_TXOK = 0, ++ WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, ++ WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, ++ WDE_DLE_QUEID_DROP_MACID_DROP = 3, ++ WDE_DLE_QUEID_NO_REPORT = 4 ++}; ++ ++enum rtw89_mac_ple_dle_port_id { ++ PLE_DLE_PORT_ID_DISPATCH = 0, ++ PLE_DLE_PORT_ID_MPDU = 1, ++ PLE_DLE_PORT_ID_SEC = 2, ++ PLE_DLE_PORT_ID_CMAC0 = 3, ++ PLE_DLE_PORT_ID_CMAC1 = 4, ++ PLE_DLE_PORT_ID_WDRLS = 5, ++ PLE_DLE_PORT_ID_CPU_IO = 6, ++ PLE_DLE_PORT_ID_PLRLS = 7, ++ PLE_DLE_PORT_ID_END = 8 ++}; ++ ++enum rtw89_mac_ple_dle_queid_plrls { ++ PLE_DLE_QUEID_NO_REPORT = 0x0 ++}; ++ ++enum rtw89_machdr_frame_type { ++ RTW89_MGNT = 0, ++ RTW89_CTRL = 1, ++ RTW89_DATA = 2, ++}; ++ ++enum rtw89_mac_dle_dfi_type { ++ DLE_DFI_TYPE_FREEPG = 0, ++ DLE_DFI_TYPE_QUOTA = 1, ++ DLE_DFI_TYPE_PAGELLT = 2, ++ DLE_DFI_TYPE_PKTINFO = 3, ++ DLE_DFI_TYPE_PREPKTLLT = 4, ++ DLE_DFI_TYPE_NXTPKTLLT = 5, ++ DLE_DFI_TYPE_QLNKTBL = 6, ++ DLE_DFI_TYPE_QEMPTY = 7, ++}; ++ ++enum rtw89_mac_dle_wde_quota_id { ++ WDE_QTAID_HOST_IF = 0, ++ WDE_QTAID_WLAN_CPU = 1, ++ WDE_QTAID_DATA_CPU = 2, ++ WDE_QTAID_PKTIN = 3, ++ WDE_QTAID_CPUIO = 4, ++}; ++ ++enum rtw89_mac_dle_ple_quota_id { ++ PLE_QTAID_B0_TXPL = 0, ++ PLE_QTAID_B1_TXPL = 1, ++ PLE_QTAID_C2H = 2, ++ PLE_QTAID_H2C = 3, ++ PLE_QTAID_WLAN_CPU = 4, ++ PLE_QTAID_MPDU = 5, ++ PLE_QTAID_CMAC0_RX = 6, ++ PLE_QTAID_CMAC1_RX = 7, ++ PLE_QTAID_CMAC1_BBRPT = 8, ++ PLE_QTAID_WDRLS = 9, ++ PLE_QTAID_CPUIO = 10, ++}; ++ ++enum rtw89_mac_dle_ctrl_type { ++ DLE_CTRL_TYPE_WDE = 0, ++ DLE_CTRL_TYPE_PLE = 1, ++ DLE_CTRL_TYPE_NUM = 2, ++}; ++ ++enum rtw89_mac_ax_l0_to_l1_event { ++ MAC_AX_L0_TO_L1_CHIF_IDLE = 0, ++ MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, ++ MAC_AX_L0_TO_L1_RLS_PKID = 2, ++ MAC_AX_L0_TO_L1_PTCL_IDLE = 3, ++ MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, ++ MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, ++ MAC_AX_L0_TO_L1_PCIE_STUCK = 6, ++ MAC_AX_L0_TO_L1_EVENT_MAX = 15, ++}; ++ ++enum rtw89_mac_dbg_port_sel { ++ /* CMAC 0 related */ ++ RTW89_DBG_PORT_SEL_PTCL_C0 = 0, ++ RTW89_DBG_PORT_SEL_SCH_C0, ++ RTW89_DBG_PORT_SEL_TMAC_C0, ++ RTW89_DBG_PORT_SEL_RMAC_C0, ++ RTW89_DBG_PORT_SEL_RMACST_C0, ++ RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, ++ RTW89_DBG_PORT_SEL_TRXPTCL_C0, ++ RTW89_DBG_PORT_SEL_TX_INFOL_C0, ++ RTW89_DBG_PORT_SEL_TX_INFOH_C0, ++ RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, ++ RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, ++ /* CMAC 1 related */ ++ RTW89_DBG_PORT_SEL_PTCL_C1, ++ RTW89_DBG_PORT_SEL_SCH_C1, ++ RTW89_DBG_PORT_SEL_TMAC_C1, ++ RTW89_DBG_PORT_SEL_RMAC_C1, ++ RTW89_DBG_PORT_SEL_RMACST_C1, ++ RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, ++ RTW89_DBG_PORT_SEL_TRXPTCL_C1, ++ RTW89_DBG_PORT_SEL_TX_INFOL_C1, ++ RTW89_DBG_PORT_SEL_TX_INFOH_C1, ++ RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, ++ RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, ++ /* DLE related */ ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, ++ RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, ++ RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, ++ RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, ++ RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, ++ RTW89_DBG_PORT_SEL_PKTINFO, ++ /* PCIE related */ ++ RTW89_DBG_PORT_SEL_PCIE_TXDMA, ++ RTW89_DBG_PORT_SEL_PCIE_RXDMA, ++ RTW89_DBG_PORT_SEL_PCIE_CVT, ++ RTW89_DBG_PORT_SEL_PCIE_CXPL, ++ RTW89_DBG_PORT_SEL_PCIE_IO, ++ RTW89_DBG_PORT_SEL_PCIE_MISC, ++ RTW89_DBG_PORT_SEL_PCIE_MISC2, ++ ++ /* keep last */ ++ RTW89_DBG_PORT_SEL_LAST, ++ RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, ++ RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, ++}; ++ ++/* SRAM mem dump */ ++#define R_AX_INDIR_ACCESS_ENTRY 0x40000 ++ ++#define STA_SCHED_BASE_ADDR 0x18808000 ++#define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 ++#define SECURITY_CAM_BASE_ADDR 0x18814000 ++#define WOW_CAM_BASE_ADDR 0x18815000 ++#define CMAC_TBL_BASE_ADDR 0x18840000 ++#define ADDR_CAM_BASE_ADDR 0x18850000 ++#define BSSID_CAM_BASE_ADDR 0x18853000 ++#define BA_CAM_BASE_ADDR 0x18854000 ++#define BCN_IE_CAM0_BASE_ADDR 0x18855000 ++#define SHARED_BUF_BASE_ADDR 0x18700000 ++#define DMAC_TBL_BASE_ADDR 0x18800000 ++#define SHCUT_MACHDR_BASE_ADDR 0x18800800 ++#define BCN_IE_CAM1_BASE_ADDR 0x188A0000 ++ ++#define CCTL_INFO_SIZE 32 ++ ++enum rtw89_mac_mem_sel { ++ RTW89_MAC_MEM_SHARED_BUF, ++ RTW89_MAC_MEM_DMAC_TBL, ++ RTW89_MAC_MEM_SHCUT_MACHDR, ++ RTW89_MAC_MEM_STA_SCHED, ++ RTW89_MAC_MEM_RXPLD_FLTR_CAM, ++ RTW89_MAC_MEM_SECURITY_CAM, ++ RTW89_MAC_MEM_WOW_CAM, ++ RTW89_MAC_MEM_CMAC_TBL, ++ RTW89_MAC_MEM_ADDR_CAM, ++ RTW89_MAC_MEM_BA_CAM, ++ RTW89_MAC_MEM_BCN_IE_CAM0, ++ RTW89_MAC_MEM_BCN_IE_CAM1, ++ ++ /* keep last */ ++ RTW89_MAC_MEM_LAST, ++ RTW89_MAC_MEM_MAX = RTW89_MAC_MEM_LAST, ++ RTW89_MAC_MEM_INVALID = RTW89_MAC_MEM_LAST, ++}; ++ ++enum rtw89_rpwm_req_pwr_state { ++ RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, ++ RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, ++}; ++ ++struct rtw89_pwr_cfg { ++ u16 addr; ++ u8 cv_msk; ++ u8 intf_msk; ++ u8 base:4; ++ u8 cmd:4; ++ u8 msk; ++ u8 val; ++}; ++ ++enum rtw89_mac_c2h_ofld_func { ++ RTW89_MAC_C2H_FUNC_EFUSE_DUMP, ++ RTW89_MAC_C2H_FUNC_READ_RSP, ++ RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, ++ RTW89_MAC_C2H_FUNC_BCN_RESEND, ++ RTW89_MAC_C2H_FUNC_MACID_PAUSE, ++ RTW89_MAC_C2H_FUNC_OFLD_MAX, ++}; ++ ++enum rtw89_mac_c2h_info_func { ++ RTW89_MAC_C2H_FUNC_REC_ACK, ++ RTW89_MAC_C2H_FUNC_DONE_ACK, ++ RTW89_MAC_C2H_FUNC_C2H_LOG, ++ RTW89_MAC_C2H_FUNC_INFO_MAX, ++}; ++ ++enum rtw89_mac_c2h_class { ++ RTW89_MAC_C2H_CLASS_INFO, ++ RTW89_MAC_C2H_CLASS_OFLD, ++ RTW89_MAC_C2H_CLASS_TWT, ++ RTW89_MAC_C2H_CLASS_WOW, ++ RTW89_MAC_C2H_CLASS_MCC, ++ RTW89_MAC_C2H_CLASS_FWDBG, ++ RTW89_MAC_C2H_CLASS_MAX, ++}; ++ ++struct rtw89_mac_ax_coex { ++#define RTW89_MAC_AX_COEX_RTK_MODE 0 ++#define RTW89_MAC_AX_COEX_CSR_MODE 1 ++ u8 pta_mode; ++#define RTW89_MAC_AX_COEX_INNER 0 ++#define RTW89_MAC_AX_COEX_OUTPUT 1 ++#define RTW89_MAC_AX_COEX_INPUT 2 ++ u8 direction; ++}; ++ ++struct rtw89_mac_ax_plt { ++#define RTW89_MAC_AX_PLT_LTE_RX BIT(0) ++#define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) ++#define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) ++#define RTW89_MAC_AX_PLT_GNT_WL BIT(3) ++ u8 band; ++ u8 tx; ++ u8 rx; ++}; ++ ++enum rtw89_mac_bf_rrsc_rate { ++ RTW89_MAC_BF_RRSC_6M = 0, ++ RTW89_MAC_BF_RRSC_9M = 1, ++ RTW89_MAC_BF_RRSC_12M, ++ RTW89_MAC_BF_RRSC_18M, ++ RTW89_MAC_BF_RRSC_24M, ++ RTW89_MAC_BF_RRSC_36M, ++ RTW89_MAC_BF_RRSC_48M, ++ RTW89_MAC_BF_RRSC_54M, ++ RTW89_MAC_BF_RRSC_HT_MSC0, ++ RTW89_MAC_BF_RRSC_HT_MSC1, ++ RTW89_MAC_BF_RRSC_HT_MSC2, ++ RTW89_MAC_BF_RRSC_HT_MSC3, ++ RTW89_MAC_BF_RRSC_HT_MSC4, ++ RTW89_MAC_BF_RRSC_HT_MSC5, ++ RTW89_MAC_BF_RRSC_HT_MSC6, ++ RTW89_MAC_BF_RRSC_HT_MSC7, ++ RTW89_MAC_BF_RRSC_VHT_MSC0, ++ RTW89_MAC_BF_RRSC_VHT_MSC1, ++ RTW89_MAC_BF_RRSC_VHT_MSC2, ++ RTW89_MAC_BF_RRSC_VHT_MSC3, ++ RTW89_MAC_BF_RRSC_VHT_MSC4, ++ RTW89_MAC_BF_RRSC_VHT_MSC5, ++ RTW89_MAC_BF_RRSC_VHT_MSC6, ++ RTW89_MAC_BF_RRSC_VHT_MSC7, ++ RTW89_MAC_BF_RRSC_HE_MSC0, ++ RTW89_MAC_BF_RRSC_HE_MSC1, ++ RTW89_MAC_BF_RRSC_HE_MSC2, ++ RTW89_MAC_BF_RRSC_HE_MSC3, ++ RTW89_MAC_BF_RRSC_HE_MSC4, ++ RTW89_MAC_BF_RRSC_HE_MSC5, ++ RTW89_MAC_BF_RRSC_HE_MSC6, ++ RTW89_MAC_BF_RRSC_HE_MSC7 = 31, ++ RTW89_MAC_BF_RRSC_MAX = 32 ++}; ++ ++#define RTW89_R32_EA 0xEAEAEAEA ++#define RTW89_R32_DEAD 0xDEADBEEF ++#define MAC_REG_POOL_COUNT 10 ++#define ACCESS_CMAC(_addr) \ ++ ({typeof(_addr) __addr = (_addr); \ ++ __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) ++ ++#define PTCL_IDLE_POLL_CNT 10000 ++#define SW_CVR_DUR_US 8 ++#define SW_CVR_CNT 8 ++ ++#define DLE_BOUND_UNIT (8 * 1024) ++#define DLE_WAIT_CNT 2000 ++#define TRXCFG_WAIT_CNT 2000 ++ ++#define RTW89_WDE_PG_64 64 ++#define RTW89_WDE_PG_128 128 ++#define RTW89_WDE_PG_256 256 ++ ++#define S_AX_WDE_PAGE_SEL_64 0 ++#define S_AX_WDE_PAGE_SEL_128 1 ++#define S_AX_WDE_PAGE_SEL_256 2 ++ ++#define RTW89_PLE_PG_64 64 ++#define RTW89_PLE_PG_128 128 ++#define RTW89_PLE_PG_256 256 ++ ++#define S_AX_PLE_PAGE_SEL_64 0 ++#define S_AX_PLE_PAGE_SEL_128 1 ++#define S_AX_PLE_PAGE_SEL_256 2 ++ ++#define SDIO_LOCAL_BASE_ADDR 0x80000000 ++ ++#define PWR_CMD_WRITE 0 ++#define PWR_CMD_POLL 1 ++#define PWR_CMD_DELAY 2 ++#define PWR_CMD_END 3 ++ ++#define PWR_INTF_MSK_SDIO BIT(0) ++#define PWR_INTF_MSK_USB BIT(1) ++#define PWR_INTF_MSK_PCIE BIT(2) ++#define PWR_INTF_MSK_ALL 0x7 ++ ++#define PWR_BASE_MAC 0 ++#define PWR_BASE_USB 1 ++#define PWR_BASE_PCIE 2 ++#define PWR_BASE_SDIO 3 ++ ++#define PWR_CV_MSK_A BIT(0) ++#define PWR_CV_MSK_B BIT(1) ++#define PWR_CV_MSK_C BIT(2) ++#define PWR_CV_MSK_D BIT(3) ++#define PWR_CV_MSK_E BIT(4) ++#define PWR_CV_MSK_F BIT(5) ++#define PWR_CV_MSK_G BIT(6) ++#define PWR_CV_MSK_TEST BIT(7) ++#define PWR_CV_MSK_ALL 0xFF ++ ++#define PWR_DELAY_US 0 ++#define PWR_DELAY_MS 1 ++ ++/* STA scheduler */ ++#define SS_MACID_SH 8 ++#define SS_TX_LEN_MSK 0x1FFFFF ++#define SS_CTRL1_R_TX_LEN 5 ++#define SS_CTRL1_R_NEXT_LINK 20 ++#define SS_LINK_SIZE 256 ++ ++/* MAC debug port */ ++#define TMAC_DBG_SEL_C0 0xA5 ++#define RMAC_DBG_SEL_C0 0xA6 ++#define TRXPTCL_DBG_SEL_C0 0xA7 ++#define TMAC_DBG_SEL_C1 0xB5 ++#define RMAC_DBG_SEL_C1 0xB6 ++#define TRXPTCL_DBG_SEL_C1 0xB7 ++#define FW_PROG_CNTR_DBG_SEL 0xF2 ++#define PCIE_TXDMA_DBG_SEL 0x30 ++#define PCIE_RXDMA_DBG_SEL 0x31 ++#define PCIE_CVT_DBG_SEL 0x32 ++#define PCIE_CXPL_DBG_SEL 0x33 ++#define PCIE_IO_DBG_SEL 0x37 ++#define PCIE_MISC_DBG_SEL 0x38 ++#define PCIE_MISC2_DBG_SEL 0x00 ++#define MAC_DBG_SEL 1 ++#define RMAC_CMAC_DBG_SEL 1 ++ ++/* TRXPTCL dbg port sel */ ++#define TRXPTRL_DBG_SEL_TMAC 0 ++#define TRXPTRL_DBG_SEL_RMAC 1 ++ ++struct rtw89_cpuio_ctrl { ++ u16 pkt_num; ++ u16 start_pktid; ++ u16 end_pktid; ++ u8 cmd_type; ++ u8 macid; ++ u8 src_pid; ++ u8 src_qid; ++ u8 dst_pid; ++ u8 dst_qid; ++ u16 pktid; ++}; ++ ++struct rtw89_mac_dbg_port_info { ++ u32 sel_addr; ++ u8 sel_byte; ++ u32 sel_msk; ++ u32 srt; ++ u32 end; ++ u32 rd_addr; ++ u8 rd_byte; ++ u32 rd_msk; ++}; ++ ++#define QLNKTBL_ADDR_INFO_SEL BIT(0) ++#define QLNKTBL_ADDR_INFO_SEL_0 0 ++#define QLNKTBL_ADDR_INFO_SEL_1 1 ++#define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) ++#define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) ++ ++struct rtw89_mac_dle_dfi_ctrl { ++ enum rtw89_mac_dle_ctrl_type type; ++ u32 target; ++ u32 addr; ++ u32 out_data; ++}; ++ ++struct rtw89_mac_dle_dfi_quota { ++ enum rtw89_mac_dle_ctrl_type dle_type; ++ u32 qtaid; ++ u16 rsv_pgnum; ++ u16 use_pgnum; ++}; ++ ++struct rtw89_mac_dle_dfi_qempty { ++ enum rtw89_mac_dle_ctrl_type dle_type; ++ u32 grpsel; ++ u32 qempty; ++}; ++ ++/* Define DBG and recovery enum */ ++enum mac_ax_err_info { ++ /* Get error info */ ++ ++ /* L0 */ ++ MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, ++ MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, ++ MAC_AX_ERR_L0_RESET_DONE = 0x0003, ++ MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, ++ ++ /* L1 */ ++ MAC_AX_ERR_L1_ERR_DMAC = 0x1000, ++ MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, ++ MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, ++ MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, ++ MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, ++ ++ /* L2 */ ++ /* address hole (master) */ ++ MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, ++ MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, ++ MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, ++ MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, ++ MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, ++ MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, ++ MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, ++ MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, ++ ++ /* AHB bridge timeout (master) */ ++ MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, ++ MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, ++ MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, ++ MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, ++ MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, ++ MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, ++ MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, ++ MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, ++ ++ /* APB_SA bridge timeout (master + slave) */ ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, ++ MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, ++ ++ /* APB_BBRF bridge timeout (master) */ ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, ++ MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, ++ MAC_AX_ERR_L2_RESET_DONE = 0x2400, ++ MAC_AX_ERR_CPU_EXCEPTION = 0x3000, ++ MAC_AX_GET_ERR_MAX, ++ MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, ++ ++ /* set error info */ ++ MAC_AX_ERR_L1_DISABLE_EN = 0x0001, ++ MAC_AX_ERR_L1_RCVY_EN = 0x0002, ++ MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, ++ MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, ++ MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, ++ MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, ++ MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, ++ MAC_AX_ERR_L0_RCVY_EN = 0x0013, ++ MAC_AX_SET_ERR_MAX, ++}; ++ ++extern const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie; ++extern const struct rtw89_dle_size wde_size0; ++extern const struct rtw89_dle_size wde_size4; ++extern const struct rtw89_dle_size ple_size0; ++extern const struct rtw89_dle_size ple_size4; ++extern const struct rtw89_wde_quota wde_qt0; ++extern const struct rtw89_wde_quota wde_qt4; ++extern const struct rtw89_ple_quota ple_qt4; ++extern const struct rtw89_ple_quota ple_qt5; ++extern const struct rtw89_ple_quota ple_qt13; ++ ++static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) ++{ ++ return band == 0 ? reg_base : (reg_base + 0x2000); ++} ++ ++static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) ++{ ++ return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); ++} ++ ++static inline u32 ++rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 mask) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ return rtw89_read32_mask(rtwdev, reg, mask); ++} ++ ++static inline void ++rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, ++ u32 data) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32(rtwdev, reg, data); ++} ++ ++static inline void ++rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 mask, u32 data) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32_mask(rtwdev, reg, mask, data); ++} ++ ++static inline void ++rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 mask, u16 data) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write16_mask(rtwdev, reg, mask, data); ++} ++ ++static inline void ++rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 bit) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32_clr(rtwdev, reg, bit); ++} ++ ++static inline void ++rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u16 bit) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write16_clr(rtwdev, reg, bit); ++} ++ ++static inline void ++rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ u32 base, u32 bit) ++{ ++ u32 reg; ++ ++ reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); ++ rtw89_write32_set(rtwdev, reg, bit); ++} ++ ++void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); ++int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); ++int rtw89_mac_init(struct rtw89_dev *rtwdev); ++int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, ++ enum rtw89_mac_hwmod_sel sel); ++int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); ++int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); ++int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); ++int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); ++void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); ++u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); ++int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); ++void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func); ++int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); ++int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, ++ u16 *tx_en, enum rtw89_sch_tx_sel sel); ++int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en); ++int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); ++void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); ++void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); ++int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); ++int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, ++ const struct rtw89_mac_ax_coex_gnt *gnt_cfg); ++int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); ++void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); ++u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); ++bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); ++int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); ++bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 *cr); ++void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); ++void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta); ++void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf); ++void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, bool disconnect); ++void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); ++int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); ++int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); ++int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, bool en); ++ ++static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) ++{ ++ if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) ++ return; ++ ++ _rtw89_mac_bf_monitor_track(rtwdev); ++} ++ ++static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 *val) ++{ ++ u32 cr; ++ ++ if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) ++ return -EINVAL; ++ ++ *val = rtw89_read32(rtwdev, cr); ++ return 0; ++} ++ ++static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 val) ++{ ++ u32 cr; ++ ++ if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) ++ return -EINVAL; ++ ++ rtw89_write32(rtwdev, cr, val); ++ return 0; ++} ++ ++static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, ++ u32 reg_base, u32 mask, u32 val) ++{ ++ u32 cr; ++ ++ if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) ++ return -EINVAL; ++ ++ rtw89_write32_mask(rtwdev, cr, mask, val); ++ return 0; ++} ++ ++int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ bool resume, u32 tx_time); ++int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, ++ u32 *tx_time); ++int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, ++ bool resume, u8 tx_retry); ++int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_sta *rtwsta, u8 *tx_retry); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c +new file mode 100644 +index 000000000000..16dc6fb7dbb0 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -0,0 +1,676 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "coex.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "phy.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++#include "ser.h" ++ ++static void rtw89_ops_tx(struct ieee80211_hw *hw, ++ struct ieee80211_tx_control *control, ++ struct sk_buff *skb) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ struct ieee80211_vif *vif = info->control.vif; ++ struct ieee80211_sta *sta = control->sta; ++ int ret, qsel; ++ ++ ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to transmit skb: %d\n", ret); ++ ieee80211_free_txskb(hw, skb); ++ } ++ rtw89_core_tx_kick_off(rtwdev, qsel); ++} ++ ++static void rtw89_ops_wake_tx_queue(struct ieee80211_hw *hw, ++ struct ieee80211_txq *txq) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ ieee80211_schedule_txq(hw, txq); ++ queue_work(rtwdev->txq_wq, &rtwdev->txq_work); ++} ++ ++static int rtw89_ops_start(struct ieee80211_hw *hw) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ int ret; ++ ++ mutex_lock(&rtwdev->mutex); ++ ret = rtw89_core_start(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static void rtw89_ops_stop(struct ieee80211_hw *hw) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_core_stop(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static int rtw89_ops_config(struct ieee80211_hw *hw, u32 changed) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ if ((changed & IEEE80211_CONF_CHANGE_IDLE) && ++ !(hw->conf.flags & IEEE80211_CONF_IDLE)) ++ rtw89_leave_ips(rtwdev); ++ ++ if (changed & IEEE80211_CONF_CHANGE_PS) { ++ if (hw->conf.flags & IEEE80211_CONF_PS) { ++ rtwdev->lps_enabled = true; ++ } else { ++ rtw89_leave_lps(rtwdev); ++ rtwdev->lps_enabled = false; ++ } ++ } ++ ++ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) ++ rtw89_set_channel(rtwdev); ++ ++ if ((changed & IEEE80211_CONF_CHANGE_IDLE) && ++ (hw->conf.flags & IEEE80211_CONF_IDLE)) ++ rtw89_enter_ips(rtwdev); ++ ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static int rtw89_ops_add_interface(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ list_add_tail(&rtwvif->list, &rtwdev->rtwvifs_list); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ rtw89_traffic_stats_init(rtwdev, &rtwvif->stats); ++ rtw89_vif_type_mapping(vif, false); ++ rtwvif->port = rtw89_core_acquire_bit_map(rtwdev->hw_port, ++ RTW89_MAX_HW_PORT_NUM); ++ if (rtwvif->port == RTW89_MAX_HW_PORT_NUM) { ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ rtwvif->bcn_hit_cond = 0; ++ rtwvif->mac_idx = RTW89_MAC_0; ++ rtwvif->phy_idx = RTW89_PHY_0; ++ rtwvif->hit_rule = 0; ++ ether_addr_copy(rtwvif->mac_addr, vif->addr); ++ ++ ret = rtw89_mac_add_vif(rtwdev, rtwvif); ++ if (ret) { ++ rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port); ++ goto out; ++ } ++ ++ rtw89_core_txq_init(rtwdev, vif->txq); ++ ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, NULL, BTC_ROLE_START); ++out: ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static void rtw89_ops_remove_interface(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_btc_ntfy_role_info(rtwdev, rtwvif, NULL, BTC_ROLE_STOP); ++ rtw89_mac_remove_vif(rtwdev, rtwvif); ++ rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port); ++ list_del_init(&rtwvif->list); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_ops_configure_filter(struct ieee80211_hw *hw, ++ unsigned int changed_flags, ++ unsigned int *new_flags, ++ u64 multicast) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ *new_flags &= FIF_ALLMULTI | FIF_OTHER_BSS | FIF_FCSFAIL | ++ FIF_BCN_PRBRESP_PROMISC; ++ ++ if (changed_flags & FIF_ALLMULTI) { ++ if (*new_flags & FIF_ALLMULTI) ++ rtwdev->hal.rx_fltr &= ~B_AX_A_MC; ++ else ++ rtwdev->hal.rx_fltr |= B_AX_A_MC; ++ } ++ if (changed_flags & FIF_FCSFAIL) { ++ if (*new_flags & FIF_FCSFAIL) ++ rtwdev->hal.rx_fltr |= B_AX_A_CRC32_ERR; ++ else ++ rtwdev->hal.rx_fltr &= ~B_AX_A_CRC32_ERR; ++ } ++ if (changed_flags & FIF_OTHER_BSS) { ++ if (*new_flags & FIF_OTHER_BSS) ++ rtwdev->hal.rx_fltr &= ~B_AX_A_A1_MATCH; ++ else ++ rtwdev->hal.rx_fltr |= B_AX_A_A1_MATCH; ++ } ++ if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { ++ if (*new_flags & FIF_BCN_PRBRESP_PROMISC) { ++ rtwdev->hal.rx_fltr &= ~B_AX_A_BCN_CHK_EN; ++ rtwdev->hal.rx_fltr &= ~B_AX_A_BC; ++ rtwdev->hal.rx_fltr &= ~B_AX_A_A1_MATCH; ++ } else { ++ rtwdev->hal.rx_fltr |= B_AX_A_BCN_CHK_EN; ++ rtwdev->hal.rx_fltr |= B_AX_A_BC; ++ rtwdev->hal.rx_fltr |= B_AX_A_A1_MATCH; ++ } ++ } ++ ++ rtw89_write32_mask(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0), ++ B_AX_RX_FLTR_CFG_MASK, ++ rtwdev->hal.rx_fltr); ++ if (!rtwdev->dbcc_en) ++ goto out; ++ rtw89_write32_mask(rtwdev, ++ rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_1), ++ B_AX_RX_FLTR_CFG_MASK, ++ rtwdev->hal.rx_fltr); ++ ++out: ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static const u8 ac_to_fw_idx[IEEE80211_NUM_ACS] = { ++ [IEEE80211_AC_VO] = 3, ++ [IEEE80211_AC_VI] = 2, ++ [IEEE80211_AC_BE] = 0, ++ [IEEE80211_AC_BK] = 1, ++}; ++ ++static u8 rtw89_aifsn_to_aifs(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u8 aifsn) ++{ ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); ++ u8 slot_time; ++ u8 sifs; ++ ++ slot_time = vif->bss_conf.use_short_slot ? 9 : 20; ++ sifs = rtwdev->hal.current_band_type == RTW89_BAND_5G ? 16 : 10; ++ ++ return aifsn * slot_time + sifs; ++} ++ ++static void ____rtw89_conf_tx_edca(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u16 ac) ++{ ++ struct ieee80211_tx_queue_params *params = &rtwvif->tx_params[ac]; ++ u32 val; ++ u8 ecw_max, ecw_min; ++ u8 aifs; ++ ++ /* 2^ecw - 1 = cw; ecw = log2(cw + 1) */ ++ ecw_max = ilog2(params->cw_max + 1); ++ ecw_min = ilog2(params->cw_min + 1); ++ aifs = rtw89_aifsn_to_aifs(rtwdev, rtwvif, params->aifs); ++ val = FIELD_PREP(FW_EDCA_PARAM_TXOPLMT_MSK, params->txop) | ++ FIELD_PREP(FW_EDCA_PARAM_CWMAX_MSK, ecw_max) | ++ FIELD_PREP(FW_EDCA_PARAM_CWMIN_MSK, ecw_min) | ++ FIELD_PREP(FW_EDCA_PARAM_AIFS_MSK, aifs); ++ rtw89_fw_h2c_set_edca(rtwdev, rtwvif, ac_to_fw_idx[ac], val); ++} ++ ++static const u32 ac_to_mu_edca_param[IEEE80211_NUM_ACS] = { ++ [IEEE80211_AC_VO] = R_AX_MUEDCA_VO_PARAM_0, ++ [IEEE80211_AC_VI] = R_AX_MUEDCA_VI_PARAM_0, ++ [IEEE80211_AC_BE] = R_AX_MUEDCA_BE_PARAM_0, ++ [IEEE80211_AC_BK] = R_AX_MUEDCA_BK_PARAM_0, ++}; ++ ++static void ____rtw89_conf_tx_mu_edca(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u16 ac) ++{ ++ struct ieee80211_tx_queue_params *params = &rtwvif->tx_params[ac]; ++ struct ieee80211_he_mu_edca_param_ac_rec *mu_edca; ++ u8 aifs, aifsn; ++ u16 timer_32us; ++ u32 reg; ++ u32 val; ++ ++ if (!params->mu_edca) ++ return; ++ ++ mu_edca = ¶ms->mu_edca_param_rec; ++ aifsn = FIELD_GET(GENMASK(3, 0), mu_edca->aifsn); ++ aifs = aifsn ? rtw89_aifsn_to_aifs(rtwdev, rtwvif, aifsn) : 0; ++ timer_32us = mu_edca->mu_edca_timer << 8; ++ ++ val = FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK, timer_32us) | ++ FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_CW_MASK, mu_edca->ecw_min_max) | ++ FIELD_PREP(B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK, aifs); ++ reg = rtw89_mac_reg_by_idx(ac_to_mu_edca_param[ac], rtwvif->mac_idx); ++ rtw89_write32(rtwdev, reg, val); ++ ++ rtw89_mac_set_hw_muedca_ctrl(rtwdev, rtwvif, true); ++} ++ ++static void __rtw89_conf_tx(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif, u16 ac) ++{ ++ ____rtw89_conf_tx_edca(rtwdev, rtwvif, ac); ++ ____rtw89_conf_tx_mu_edca(rtwdev, rtwvif, ac); ++} ++ ++static void rtw89_conf_tx(struct rtw89_dev *rtwdev, ++ struct rtw89_vif *rtwvif) ++{ ++ u16 ac; ++ ++ for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) ++ __rtw89_conf_tx(rtwdev, rtwvif, ac); ++} ++ ++static void rtw89_station_mode_sta_assoc(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf) ++{ ++ struct ieee80211_sta *sta; ++ ++ if (vif->type != NL80211_IFTYPE_STATION) ++ return; ++ ++ sta = ieee80211_find_sta(vif, conf->bssid); ++ if (!sta) { ++ rtw89_err(rtwdev, "can't find sta to set sta_assoc state\n"); ++ return; ++ } ++ rtw89_core_sta_assoc(rtwdev, vif, sta); ++} ++ ++static void rtw89_ops_bss_info_changed(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *conf, ++ u32 changed) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ if (changed & BSS_CHANGED_ASSOC) { ++ if (conf->assoc) { ++ rtw89_station_mode_sta_assoc(rtwdev, vif, conf); ++ rtw89_phy_set_bss_color(rtwdev, vif); ++ rtw89_chip_cfg_txpwr_ul_tb_offset(rtwdev, vif); ++ rtw89_mac_port_update(rtwdev, rtwvif); ++ } ++ } ++ ++ if (changed & BSS_CHANGED_BSSID) { ++ ether_addr_copy(rtwvif->bssid, conf->bssid); ++ rtw89_cam_bssid_changed(rtwdev, rtwvif); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ } ++ ++ if (changed & BSS_CHANGED_ERP_SLOT) ++ rtw89_conf_tx(rtwdev, rtwvif); ++ ++ if (changed & BSS_CHANGED_HE_BSS_COLOR) ++ rtw89_phy_set_bss_color(rtwdev, vif); ++ ++ if (changed & BSS_CHANGED_MU_GROUPS) ++ rtw89_mac_bf_set_gid_table(rtwdev, vif, conf); ++ ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static int rtw89_ops_conf_tx(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, u16 ac, ++ const struct ieee80211_tx_queue_params *params) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ rtwvif->tx_params[ac] = *params; ++ __rtw89_conf_tx(rtwdev, rtwvif, ac); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static int __rtw89_ops_sta_state(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ enum ieee80211_sta_state old_state, ++ enum ieee80211_sta_state new_state) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ if (old_state == IEEE80211_STA_NOTEXIST && ++ new_state == IEEE80211_STA_NONE) ++ return rtw89_core_sta_add(rtwdev, vif, sta); ++ ++ if (old_state == IEEE80211_STA_AUTH && ++ new_state == IEEE80211_STA_ASSOC) { ++ if (vif->type == NL80211_IFTYPE_STATION) ++ return 0; /* defer to bss_info_changed to have vif info */ ++ return rtw89_core_sta_assoc(rtwdev, vif, sta); ++ } ++ ++ if (old_state == IEEE80211_STA_ASSOC && ++ new_state == IEEE80211_STA_AUTH) ++ return rtw89_core_sta_disassoc(rtwdev, vif, sta); ++ ++ if (old_state == IEEE80211_STA_AUTH && ++ new_state == IEEE80211_STA_NONE) ++ return rtw89_core_sta_disconnect(rtwdev, vif, sta); ++ ++ if (old_state == IEEE80211_STA_NONE && ++ new_state == IEEE80211_STA_NOTEXIST) ++ return rtw89_core_sta_remove(rtwdev, vif, sta); ++ ++ return 0; ++} ++ ++static int rtw89_ops_sta_state(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ enum ieee80211_sta_state old_state, ++ enum ieee80211_sta_state new_state) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ int ret; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ret = __rtw89_ops_sta_state(hw, vif, sta, old_state, new_state); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static int rtw89_ops_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ switch (cmd) { ++ case SET_KEY: ++ rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_EAPOL_END); ++ ret = rtw89_cam_sec_key_add(rtwdev, vif, sta, key); ++ if (ret && ret != -EOPNOTSUPP) { ++ rtw89_err(rtwdev, "failed to add key to sec cam\n"); ++ goto out; ++ } ++ break; ++ case DISABLE_KEY: ++ rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, ++ false); ++ rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, false); ++ ret = rtw89_cam_sec_key_del(rtwdev, vif, sta, key, true); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to remove key from sec cam\n"); ++ goto out; ++ } ++ break; ++ } ++ ++out: ++ mutex_unlock(&rtwdev->mutex); ++ ++ return ret; ++} ++ ++static int rtw89_ops_ampdu_action(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_ampdu_params *params) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct ieee80211_sta *sta = params->sta; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ u16 tid = params->tid; ++ struct ieee80211_txq *txq = sta->txq[tid]; ++ struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; ++ ++ switch (params->action) { ++ case IEEE80211_AMPDU_TX_START: ++ return IEEE80211_AMPDU_TX_START_IMMEDIATE; ++ case IEEE80211_AMPDU_TX_STOP_CONT: ++ case IEEE80211_AMPDU_TX_STOP_FLUSH: ++ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: ++ mutex_lock(&rtwdev->mutex); ++ clear_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags); ++ rtw89_fw_h2c_ba_cam(rtwdev, false, rtwsta->mac_id, params); ++ mutex_unlock(&rtwdev->mutex); ++ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); ++ break; ++ case IEEE80211_AMPDU_TX_OPERATIONAL: ++ mutex_lock(&rtwdev->mutex); ++ set_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags); ++ rtwsta->ampdu_params[tid].agg_num = params->buf_size; ++ rtwsta->ampdu_params[tid].amsdu = params->amsdu; ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_fw_h2c_ba_cam(rtwdev, true, rtwsta->mac_id, params); ++ mutex_unlock(&rtwdev->mutex); ++ break; ++ case IEEE80211_AMPDU_RX_START: ++ case IEEE80211_AMPDU_RX_STOP: ++ break; ++ default: ++ WARN_ON(1); ++ return -ENOTSUPP; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ if (test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) ++ rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static void rtw89_ops_sta_statistics(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta, ++ struct station_info *sinfo) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ ++ sinfo->txrate = rtwsta->ra_report.txrate; ++ sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); ++} ++ ++static void rtw89_ops_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ u32 queues, bool drop) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_lps(rtwdev); ++ rtw89_hci_flush_queues(rtwdev, queues, drop); ++ rtw89_mac_flush_txq(rtwdev, queues, drop); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++struct rtw89_iter_bitrate_mask_data { ++ struct rtw89_dev *rtwdev; ++ struct ieee80211_vif *vif; ++ const struct cfg80211_bitrate_mask *mask; ++}; ++ ++static void rtw89_ra_mask_info_update_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_iter_bitrate_mask_data *br_data = data; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); ++ ++ if (vif != br_data->vif) ++ return; ++ ++ rtwsta->use_cfg_mask = true; ++ rtwsta->mask = *br_data->mask; ++ rtw89_phy_ra_updata_sta(br_data->rtwdev, sta); ++} ++ ++static void rtw89_ra_mask_info_update(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ struct rtw89_iter_bitrate_mask_data br_data = { .rtwdev = rtwdev, ++ .vif = vif, ++ .mask = mask}; ++ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_ra_mask_info_update_iter, ++ &br_data); ++} ++ ++static int rtw89_ops_set_bitrate_mask(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_phy_rate_pattern_vif(rtwdev, vif, mask); ++ rtw89_ra_mask_info_update(rtwdev, vif, mask); ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ++int rtw89_ops_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ if (rx_ant != hw->wiphy->available_antennas_rx) ++ return -EINVAL; ++ ++ mutex_lock(&rtwdev->mutex); ++ hal->antenna_tx = tx_ant; ++ hal->antenna_rx = rx_ant; ++ mutex_unlock(&rtwdev->mutex); ++ ++ return 0; ++} ++ ++static ++int rtw89_ops_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ *tx_ant = hal->antenna_tx; ++ *rx_ant = hal->antenna_rx; ++ ++ return 0; ++} ++ ++static void rtw89_ops_sw_scan_start(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ const u8 *mac_addr) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtwdev->scanning = true; ++ rtw89_leave_lps(rtwdev); ++ rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, hal->current_band_type); ++ rtw89_chip_rfk_scan(rtwdev, true); ++ rtw89_hci_recalc_int_mit(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_ops_sw_scan_complete(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_chip_rfk_scan(rtwdev, false); ++ rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); ++ rtwdev->scanning = false; ++ rtwdev->dig.bypass_dig = true; ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_ops_reconfig_complete(struct ieee80211_hw *hw, ++ enum ieee80211_reconfig_type reconfig_type) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ if (reconfig_type == IEEE80211_RECONFIG_TYPE_RESTART) ++ rtw89_ser_recfg_done(rtwdev); ++} ++ ++const struct ieee80211_ops rtw89_ops = { ++ .tx = rtw89_ops_tx, ++ .wake_tx_queue = rtw89_ops_wake_tx_queue, ++ .start = rtw89_ops_start, ++ .stop = rtw89_ops_stop, ++ .config = rtw89_ops_config, ++ .add_interface = rtw89_ops_add_interface, ++ .remove_interface = rtw89_ops_remove_interface, ++ .configure_filter = rtw89_ops_configure_filter, ++ .bss_info_changed = rtw89_ops_bss_info_changed, ++ .conf_tx = rtw89_ops_conf_tx, ++ .sta_state = rtw89_ops_sta_state, ++ .set_key = rtw89_ops_set_key, ++ .ampdu_action = rtw89_ops_ampdu_action, ++ .set_rts_threshold = rtw89_ops_set_rts_threshold, ++ .sta_statistics = rtw89_ops_sta_statistics, ++ .flush = rtw89_ops_flush, ++ .set_bitrate_mask = rtw89_ops_set_bitrate_mask, ++ .set_antenna = rtw89_ops_set_antenna, ++ .get_antenna = rtw89_ops_get_antenna, ++ .sw_scan_start = rtw89_ops_sw_scan_start, ++ .sw_scan_complete = rtw89_ops_sw_scan_complete, ++ .reconfig_complete = rtw89_ops_reconfig_complete, ++ .set_sar_specs = rtw89_ops_set_sar_specs, ++}; ++EXPORT_SYMBOL(rtw89_ops); +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +new file mode 100644 +index 000000000000..e9731012bca9 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -0,0 +1,3060 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2020 Realtek Corporation ++ */ ++ ++#include ++ ++#include "mac.h" ++#include "pci.h" ++#include "reg.h" ++#include "ser.h" ++ ++static bool rtw89_pci_disable_clkreq; ++static bool rtw89_pci_disable_aspm_l1; ++static bool rtw89_pci_disable_l1ss; ++module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644); ++module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644); ++module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644); ++MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support"); ++MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support"); ++MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support"); ++ ++static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev) ++{ ++ u32 val; ++ int ret; ++ ++ rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, ++ rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM), ++ 1, RTW89_PCI_POLL_BDRAM_RST_CNT, false, ++ rtwdev, R_AX_PCIE_INIT_CFG1); ++ ++ if (ret) ++ return -EBUSY; ++ ++ return 0; ++} ++ ++static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_dma_ring *bd_ring, ++ u32 cur_idx, bool tx) ++{ ++ u32 cnt, cur_rp, wp, rp, len; ++ ++ rp = bd_ring->rp; ++ wp = bd_ring->wp; ++ len = bd_ring->len; ++ ++ cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); ++ if (tx) ++ cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); ++ else ++ cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); ++ ++ bd_ring->rp = cur_rp; ++ ++ return cnt; ++} ++ ++static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 addr_idx = bd_ring->addr_idx; ++ u32 cnt, idx; ++ ++ idx = rtw89_read32(rtwdev, addr_idx); ++ cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true); ++ ++ return cnt; ++} ++ ++static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, ++ u32 cnt, bool release_all) ++{ ++ struct rtw89_pci_tx_data *tx_data; ++ struct sk_buff *skb; ++ u32 qlen; ++ ++ while (cnt--) { ++ skb = skb_dequeue(&rtwpci->h2c_queue); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to pre-release fwcmd\n"); ++ return; ++ } ++ skb_queue_tail(&rtwpci->h2c_release_queue, skb); ++ } ++ ++ qlen = skb_queue_len(&rtwpci->h2c_release_queue); ++ if (!release_all) ++ qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0; ++ ++ while (qlen--) { ++ skb = skb_dequeue(&rtwpci->h2c_release_queue); ++ if (!skb) { ++ rtw89_err(rtwdev, "failed to release fwcmd\n"); ++ return; ++ } ++ tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, ++ DMA_TO_DEVICE); ++ dev_kfree_skb_any(skb); ++ } ++} ++ ++static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; ++ u32 cnt; ++ ++ cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); ++ if (!cnt) ++ return; ++ rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false); ++} ++ ++static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u32 addr_idx = bd_ring->addr_idx; ++ u32 cnt, idx; ++ ++ idx = rtw89_read32(rtwdev, addr_idx); ++ cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false); ++ ++ return cnt; ++} ++ ++static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ dma_addr_t dma; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ dma = rx_info->dma; ++ dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++} ++ ++static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ dma_addr_t dma; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ dma = rx_info->dma; ++ dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++} ++ ++static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev, ++ struct sk_buff *skb) ++{ ++ struct rtw89_pci_rxbd_info *rxbd_info; ++ struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ ++ rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data; ++ rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS); ++ rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS); ++ rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE); ++ rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG); ++ ++ return 0; ++} ++ ++static bool ++rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls, ++ struct sk_buff *new, ++ const struct sk_buff *skb, u32 offset, ++ const struct rtw89_pci_rx_info *rx_info, ++ const struct rtw89_rx_desc_info *desc_info) ++{ ++ u32 copy_len = rx_info->len - offset; ++ ++ if (unlikely(skb_tailroom(new) < copy_len)) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n", ++ rx_info->len, desc_info->pkt_size, offset, fs, ls); ++ rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ", ++ skb->data, rx_info->len); ++ /* length of a single segment skb is desc_info->pkt_size */ ++ if (fs && ls) { ++ copy_len = desc_info->pkt_size; ++ } else { ++ rtw89_info(rtwdev, "drop rx data due to invalid length\n"); ++ return false; ++ } ++ } ++ ++ skb_put_data(new, skb->data + offset, copy_len); ++ ++ return true; ++} ++ ++static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ struct rtw89_pci_rx_info *rx_info; ++ struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc; ++ struct sk_buff *new = rx_ring->diliver_skb; ++ struct sk_buff *skb; ++ u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); ++ u32 offset; ++ u32 cnt = 1; ++ bool fs, ls; ++ int ret; ++ ++ skb = rx_ring->buf[bd_ring->wp]; ++ rtw89_pci_sync_skb_for_cpu(rtwdev, skb); ++ ++ ret = rtw89_pci_rxbd_info_update(rtwdev, skb); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", ++ bd_ring->wp, ret); ++ goto err_sync_device; ++ } ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ fs = rx_info->fs; ++ ls = rx_info->ls; ++ ++ if (fs) { ++ if (new) { ++ rtw89_err(rtwdev, "skb should not be ready before first segment start\n"); ++ goto err_sync_device; ++ } ++ if (desc_info->ready) { ++ rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n"); ++ goto err_sync_device; ++ } ++ ++ rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size); ++ ++ new = dev_alloc_skb(desc_info->pkt_size); ++ if (!new) ++ goto err_sync_device; ++ ++ rx_ring->diliver_skb = new; ++ ++ /* first segment has RX desc */ ++ offset = desc_info->offset; ++ offset += desc_info->long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : ++ sizeof(struct rtw89_rxdesc_short); ++ } else { ++ offset = sizeof(struct rtw89_pci_rxbd_info); ++ if (!new) { ++ rtw89_warn(rtwdev, "no last skb\n"); ++ goto err_sync_device; ++ } ++ } ++ if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info)) ++ goto err_sync_device; ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ rtw89_pci_rxbd_increase(rx_ring, 1); ++ ++ if (!desc_info->ready) { ++ rtw89_warn(rtwdev, "no rx desc information\n"); ++ goto err_free_resource; ++ } ++ if (ls) { ++ rtw89_core_rx(rtwdev, desc_info, new); ++ rx_ring->diliver_skb = NULL; ++ desc_info->ready = false; ++ } ++ ++ return cnt; ++ ++err_sync_device: ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ rtw89_pci_rxbd_increase(rx_ring, 1); ++err_free_resource: ++ if (new) ++ dev_kfree_skb_any(new); ++ rx_ring->diliver_skb = NULL; ++ desc_info->ready = false; ++ ++ return cnt; ++} ++ ++static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u32 rx_cnt; ++ ++ while (cnt && rtwdev->napi_budget_countdown > 0) { ++ rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring); ++ if (!rx_cnt) { ++ rtw89_err(rtwdev, "failed to deliver RXBD skb\n"); ++ ++ /* skip the rest RXBD bufs */ ++ rtw89_pci_rxbd_increase(rx_ring, cnt); ++ break; ++ } ++ ++ cnt -= rx_cnt; ++ } ++ ++ rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp); ++} ++ ++static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, int budget) ++{ ++ struct rtw89_pci_rx_ring *rx_ring; ++ int countdown = rtwdev->napi_budget_countdown; ++ u32 cnt; ++ ++ rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; ++ ++ cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); ++ if (!cnt) ++ return 0; ++ ++ cnt = min_t(u32, budget, cnt); ++ ++ rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt); ++ ++ /* In case of flushing pending SKBs, the countdown may exceed. */ ++ if (rtwdev->napi_budget_countdown <= 0) ++ return budget; ++ ++ return budget - countdown; ++} ++ ++static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct sk_buff *skb, u8 tx_status) ++{ ++ struct ieee80211_tx_info *info; ++ ++ info = IEEE80211_SKB_CB(skb); ++ ieee80211_tx_info_clear_status(info); ++ ++ if (info->flags & IEEE80211_TX_CTL_NO_ACK) ++ info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; ++ if (tx_status == RTW89_TX_DONE) { ++ info->flags |= IEEE80211_TX_STAT_ACK; ++ tx_ring->tx_acked++; ++ } else { ++ if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) ++ rtw89_debug(rtwdev, RTW89_DBG_FW, ++ "failed to TX of status %x\n", tx_status); ++ switch (tx_status) { ++ case RTW89_TX_RETRY_LIMIT: ++ tx_ring->tx_retry_lmt++; ++ break; ++ case RTW89_TX_LIFE_TIME: ++ tx_ring->tx_life_time++; ++ break; ++ case RTW89_TX_MACID_DROP: ++ tx_ring->tx_mac_id_drop++; ++ break; ++ default: ++ rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status); ++ break; ++ } ++ } ++ ++ ieee80211_tx_status_ni(rtwdev->hw, skb); ++} ++ ++static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd *txwd; ++ u32 cnt; ++ ++ cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); ++ while (cnt--) { ++ txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); ++ if (!txwd) { ++ rtw89_warn(rtwdev, "No busy txwd pages available\n"); ++ break; ++ } ++ ++ list_del_init(&txwd->list); ++ } ++} ++ ++static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ int i; ++ ++ for (i = 0; i < wd_ring->page_num; i++) { ++ txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); ++ if (!txwd) ++ break; ++ ++ list_del_init(&txwd->list); ++ } ++} ++ ++static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_wd *txwd, u16 seq, ++ u8 tx_status) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_data *tx_data; ++ struct sk_buff *skb, *tmp; ++ u8 txch = tx_ring->txch; ++ ++ if (!list_empty(&txwd->list)) { ++ rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n", ++ txch, seq); ++ return; ++ } ++ ++ /* currently, support for only one frame */ ++ if (skb_queue_len(&txwd->queue) != 1) { ++ rtw89_warn(rtwdev, "empty pending queue %d page %d\n", ++ txch, seq); ++ return; ++ } ++ ++ skb_queue_walk_safe(&txwd->queue, skb, tmp) { ++ skb_unlink(skb, &txwd->queue); ++ ++ tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, ++ DMA_TO_DEVICE); ++ ++ rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status); ++ } ++ ++ rtw89_pci_enqueue_txwd(tx_ring, txwd); ++} ++ ++static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rpp_fmt *rpp) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ struct rtw89_pci_tx_wd_ring *wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ u16 seq; ++ u8 qsel, tx_status, txch; ++ ++ seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); ++ qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); ++ tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); ++ txch = rtw89_core_get_ch_dma(rtwdev, qsel); ++ ++ if (txch == RTW89_TXCH_CH12) { ++ rtw89_warn(rtwdev, "should no fwcmd release report\n"); ++ return; ++ } ++ ++ tx_ring = &rtwpci->tx_rings[txch]; ++ rtw89_pci_reclaim_txbd(rtwdev, tx_ring); ++ wd_ring = &tx_ring->wd_ring; ++ txwd = &wd_ring->pages[seq]; ++ ++ rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status); ++} ++ ++static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ int i; ++ ++ for (i = 0; i < wd_ring->page_num; i++) { ++ txwd = &wd_ring->pages[i]; ++ ++ if (!list_empty(&txwd->list)) ++ continue; ++ ++ rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP); ++ } ++} ++ ++static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 max_cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ struct rtw89_pci_rx_info *rx_info; ++ struct rtw89_pci_rpp_fmt *rpp; ++ struct rtw89_rx_desc_info desc_info = {}; ++ struct sk_buff *skb; ++ u32 cnt = 0; ++ u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt); ++ u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); ++ u32 offset; ++ int ret; ++ ++ skb = rx_ring->buf[bd_ring->wp]; ++ rtw89_pci_sync_skb_for_cpu(rtwdev, skb); ++ ++ ret = rtw89_pci_rxbd_info_update(rtwdev, skb); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", ++ bd_ring->wp, ret); ++ goto err_sync_device; ++ } ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ if (!rx_info->fs || !rx_info->ls) { ++ rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n"); ++ return cnt; ++ } ++ ++ rtw89_core_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size); ++ ++ /* first segment has RX desc */ ++ offset = desc_info.offset; ++ offset += desc_info.long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : ++ sizeof(struct rtw89_rxdesc_short); ++ for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { ++ rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset); ++ rtw89_pci_release_rpp(rtwdev, rpp); ++ } ++ ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ rtw89_pci_rxbd_increase(rx_ring, 1); ++ cnt++; ++ ++ return cnt; ++ ++err_sync_device: ++ rtw89_pci_sync_skb_for_device(rtwdev, skb); ++ return 0; ++} ++ ++static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u32 release_cnt; ++ ++ while (cnt) { ++ release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt); ++ if (!release_cnt) { ++ rtw89_err(rtwdev, "failed to release TX skbs\n"); ++ ++ /* skip the rest RXBD bufs */ ++ rtw89_pci_rxbd_increase(rx_ring, cnt); ++ break; ++ } ++ ++ cnt -= release_cnt; ++ } ++ ++ rtw89_write16(rtwdev, bd_ring->addr_idx, bd_ring->wp); ++} ++ ++static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, int budget) ++{ ++ struct rtw89_pci_rx_ring *rx_ring; ++ u32 cnt; ++ int work_done; ++ ++ rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ ++ cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); ++ if (cnt == 0) ++ goto out_unlock; ++ ++ rtw89_pci_release_tx(rtwdev, rx_ring, cnt); ++ ++out_unlock: ++ spin_unlock_bh(&rtwpci->trx_lock); ++ ++ /* always release all RPQ */ ++ work_done = min_t(int, cnt, budget); ++ rtwdev->napi_budget_countdown -= work_done; ++ ++ return work_done; ++} ++ ++static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ struct rtw89_pci_rx_ring *rx_ring; ++ struct rtw89_pci_dma_ring *bd_ring; ++ u32 reg_idx; ++ u16 hw_idx, hw_idx_next, host_idx; ++ int i; ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ bd_ring = &rx_ring->bd_ring; ++ ++ reg_idx = rtw89_read32(rtwdev, bd_ring->addr_idx); ++ hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx); ++ host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx); ++ hw_idx_next = (hw_idx + 1) % bd_ring->len; ++ ++ if (hw_idx_next == host_idx) ++ rtw89_warn(rtwdev, "%d RXD unavailable\n", i); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXRX, ++ "%d RXD unavailable, idx=0x%08x, len=%d\n", ++ i, reg_idx, bd_ring->len); ++ } ++} ++ ++static void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci, ++ struct rtw89_pci_isrs *isrs) ++{ ++ isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs; ++ isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0]; ++ isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1]; ++ ++ rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); ++ rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]); ++ rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]); ++} ++ ++static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00) ++{ ++ /* write 1 clear */ ++ rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00); ++} ++ ++static void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]); ++} ++ ++static void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ rtw89_write32(rtwdev, R_AX_HIMR0, 0); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0); ++ rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0); ++} ++ ++static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) ++{ ++ struct rtw89_dev *rtwdev = dev; ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_isrs isrs; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ rtw89_pci_recognize_intrs(rtwdev, rtwpci, &isrs); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ if (unlikely(isrs.isrs[0] & B_AX_RDU_INT)) ++ rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); ++ ++ if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN)) ++ rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); ++ ++ if (likely(rtwpci->running)) { ++ local_bh_disable(); ++ napi_schedule(&rtwdev->napi); ++ local_bh_enable(); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) ++{ ++ struct rtw89_dev *rtwdev = dev; ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long flags; ++ irqreturn_t irqret = IRQ_WAKE_THREAD; ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ ++ /* If interrupt event is on the road, it is still trigger interrupt ++ * even we have done pci_stop() to turn off IMR. ++ */ ++ if (unlikely(!rtwpci->running)) { ++ irqret = IRQ_HANDLED; ++ goto exit; ++ } ++ ++ rtw89_pci_disable_intr(rtwdev, rtwpci); ++exit: ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ return irqret; ++} ++ ++#define case_TXCHADDRS(txch) \ ++ case RTW89_TXCH_##txch: \ ++ *addr_num = R_AX_##txch##_TXBD_NUM; \ ++ *addr_idx = R_AX_##txch##_TXBD_IDX; \ ++ *addr_bdram = R_AX_##txch##_BDRAM_CTRL; \ ++ *addr_desa_l = R_AX_##txch##_TXBD_DESA_L; \ ++ *addr_desa_h = R_AX_##txch##_TXBD_DESA_H; \ ++ break ++ ++static int rtw89_pci_get_txch_addrs(enum rtw89_tx_channel txch, ++ u32 *addr_num, ++ u32 *addr_idx, ++ u32 *addr_bdram, ++ u32 *addr_desa_l, ++ u32 *addr_desa_h) ++{ ++ switch (txch) { ++ case_TXCHADDRS(ACH0); ++ case_TXCHADDRS(ACH1); ++ case_TXCHADDRS(ACH2); ++ case_TXCHADDRS(ACH3); ++ case_TXCHADDRS(ACH4); ++ case_TXCHADDRS(ACH5); ++ case_TXCHADDRS(ACH6); ++ case_TXCHADDRS(ACH7); ++ case_TXCHADDRS(CH8); ++ case_TXCHADDRS(CH9); ++ case_TXCHADDRS(CH10); ++ case_TXCHADDRS(CH11); ++ case_TXCHADDRS(CH12); ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#undef case_TXCHADDRS ++ ++#define case_RXCHADDRS(rxch) \ ++ case RTW89_RXCH_##rxch: \ ++ *addr_num = R_AX_##rxch##_RXBD_NUM; \ ++ *addr_idx = R_AX_##rxch##_RXBD_IDX; \ ++ *addr_desa_l = R_AX_##rxch##_RXBD_DESA_L; \ ++ *addr_desa_h = R_AX_##rxch##_RXBD_DESA_H; \ ++ break ++ ++static int rtw89_pci_get_rxch_addrs(enum rtw89_rx_channel rxch, ++ u32 *addr_num, ++ u32 *addr_idx, ++ u32 *addr_desa_l, ++ u32 *addr_desa_h) ++{ ++ switch (rxch) { ++ case_RXCHADDRS(RXQ); ++ case_RXCHADDRS(RPQ); ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#undef case_RXCHADDRS ++ ++static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring; ++ ++ /* reserved 1 desc check ring is full or not */ ++ if (bd_ring->rp > bd_ring->wp) ++ return bd_ring->rp - bd_ring->wp - 1; ++ ++ return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1; ++} ++ ++static ++u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; ++ u32 cnt; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci); ++ cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ++ spin_unlock_bh(&rtwpci->trx_lock); ++ ++ return cnt; ++} ++ ++static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, ++ u8 txch) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ u32 bd_cnt, wd_cnt, min_cnt = 0; ++ struct rtw89_pci_rx_ring *rx_ring; ++ u32 cnt; ++ ++ rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ++ wd_cnt = wd_ring->curr_num; ++ ++ if (wd_cnt == 0 || bd_cnt == 0) { ++ cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); ++ if (!cnt) ++ goto out_unlock; ++ rtw89_pci_release_tx(rtwdev, rx_ring, cnt); ++ } ++ ++ bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); ++ wd_cnt = wd_ring->curr_num; ++ min_cnt = min(bd_cnt, wd_cnt); ++ if (min_cnt == 0) ++ rtw89_warn(rtwdev, "still no tx resource after reclaim\n"); ++ ++out_unlock: ++ spin_unlock_bh(&rtwpci->trx_lock); ++ ++ return min_cnt; ++} ++ ++static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, ++ u8 txch) ++{ ++ if (txch == RTW89_TXCH_CH12) ++ return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev); ++ ++ return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch); ++} ++ ++static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 host_idx, addr; ++ ++ addr = bd_ring->addr_idx; ++ host_idx = bd_ring->wp; ++ rtw89_write16(rtwdev, addr, host_idx); ++} ++ ++static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, ++ int n_txbd) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 host_idx, len; ++ ++ len = bd_ring->len; ++ host_idx = bd_ring->wp + n_txbd; ++ host_idx = host_idx < len ? host_idx : host_idx - len; ++ ++ bd_ring->wp = host_idx; ++} ++ ++static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ __rtw89_pci_tx_kick_off(rtwdev, tx_ring); ++ spin_unlock_bh(&rtwpci->trx_lock); ++} ++ ++static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ u32 cur_idx, cur_rp; ++ u8 i; ++ ++ /* Because the time taked by the I/O is a bit dynamic, it's hard to ++ * define a reasonable fixed total timeout to use read_poll_timeout* ++ * helper. Instead, we can ensure a reasonable polling times, so we ++ * just use for loop with udelay here. ++ */ ++ for (i = 0; i < 60; i++) { ++ cur_idx = rtw89_read32(rtwdev, bd_ring->addr_idx); ++ cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); ++ if (cur_rp == bd_ring->wp) ++ return; ++ ++ udelay(1); ++ } ++ ++ if (!drop) ++ rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch); ++} ++ ++static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs, ++ bool drop) ++{ ++ u8 i; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ /* It may be unnecessary to flush FWCMD queue. */ ++ if (i == RTW89_TXCH_CH12) ++ continue; ++ ++ if (txchs & BIT(i)) ++ __pci_flush_txch(rtwdev, i, drop); ++ } ++} ++ ++static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues, ++ bool drop) ++{ ++ __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop); ++} ++ ++static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_wd *txwd, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct rtw89_txwd_body *txwd_body; ++ struct rtw89_txwd_info *txwd_info; ++ struct rtw89_pci_tx_wp_info *txwp_info; ++ struct rtw89_pci_tx_addr_info_32 *txaddr_info; ++ struct pci_dev *pdev = rtwpci->pdev; ++ struct sk_buff *skb = tx_req->skb; ++ struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ bool en_wd_info = desc_info->en_wd_info; ++ u32 txwd_len; ++ u32 txwp_len; ++ u32 txaddr_info_len; ++ dma_addr_t dma; ++ int ret; ++ ++ rtw89_core_fill_txdesc(rtwdev, desc_info, txwd->vaddr); ++ ++ dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(&pdev->dev, dma)) { ++ rtw89_err(rtwdev, "failed to map skb dma data\n"); ++ ret = -EBUSY; ++ goto err; ++ } ++ ++ tx_data->dma = dma; ++ ++ txaddr_info_len = sizeof(*txaddr_info); ++ txwp_len = sizeof(*txwp_info); ++ txwd_len = sizeof(*txwd_body); ++ txwd_len += en_wd_info ? sizeof(*txwd_info) : 0; ++ ++ txwp_info = txwd->vaddr + txwd_len; ++ txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID); ++ txwp_info->seq1 = 0; ++ txwp_info->seq2 = 0; ++ txwp_info->seq3 = 0; ++ ++ tx_ring->tx_cnt++; ++ txaddr_info = txwd->vaddr + txwd_len + txwp_len; ++ txaddr_info->length = cpu_to_le16(skb->len); ++ txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | ++ RTW89_PCI_ADDR_NUM(1)); ++ txaddr_info->dma = cpu_to_le32(dma); ++ ++ txwd->len = txwd_len + txwp_len + txaddr_info_len; ++ ++ skb_queue_tail(&txwd->queue, skb); ++ ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_bd_32 *txbd, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ struct rtw89_txwd_body *txwd_body; ++ struct pci_dev *pdev = rtwpci->pdev; ++ struct sk_buff *skb = tx_req->skb; ++ struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); ++ dma_addr_t dma; ++ ++ txwd_body = (struct rtw89_txwd_body *)skb_push(skb, sizeof(*txwd_body)); ++ memset(txwd_body, 0, sizeof(*txwd_body)); ++ rtw89_core_fill_txdesc(rtwdev, desc_info, txwd_body); ++ ++ dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(&pdev->dev, dma)) { ++ rtw89_err(rtwdev, "failed to map fwcmd dma data\n"); ++ return -EBUSY; ++ } ++ ++ tx_data->dma = dma; ++ txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); ++ txbd->length = cpu_to_le16(skb->len); ++ txbd->dma = cpu_to_le32(tx_data->dma); ++ skb_queue_tail(&rtwpci->h2c_queue, skb); ++ ++ rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); ++ ++ return 0; ++} ++ ++static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_bd_32 *txbd, ++ struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_pci_tx_wd *txwd; ++ int ret; ++ ++ /* FWCMD queue doesn't have wd pages. Instead, it submits the CMD ++ * buffer with WD BODY only. So here we don't need to check the free ++ * pages of the wd ring. ++ */ ++ if (tx_ring->txch == RTW89_TXCH_CH12) ++ return rtw89_pci_fwcmd_submit(rtwdev, tx_ring, txbd, tx_req); ++ ++ txwd = rtw89_pci_dequeue_txwd(tx_ring); ++ if (!txwd) { ++ rtw89_err(rtwdev, "no available TXWD\n"); ++ ret = -ENOSPC; ++ goto err; ++ } ++ ++ ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq); ++ goto err_enqueue_wd; ++ } ++ ++ list_add_tail(&txwd->list, &tx_ring->busy_pages); ++ ++ txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); ++ txbd->length = cpu_to_le16(txwd->len); ++ txbd->dma = cpu_to_le32(txwd->paddr); ++ ++ rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); ++ ++ return 0; ++ ++err_enqueue_wd: ++ rtw89_pci_enqueue_txwd(tx_ring, txwd); ++err: ++ return ret; ++} ++ ++static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req, ++ u8 txch) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ struct rtw89_pci_tx_bd_32 *txbd; ++ u32 n_avail_txbd; ++ int ret = 0; ++ ++ /* check the tx type and dma channel for fw cmd queue */ ++ if ((txch == RTW89_TXCH_CH12 || ++ tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) && ++ (txch != RTW89_TXCH_CH12 || ++ tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) { ++ rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n"); ++ return -EINVAL; ++ } ++ ++ tx_ring = &rtwpci->tx_rings[txch]; ++ spin_lock_bh(&rtwpci->trx_lock); ++ ++ n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); ++ if (n_avail_txbd == 0) { ++ rtw89_err(rtwdev, "no available TXBD\n"); ++ ret = -ENOSPC; ++ goto err_unlock; ++ } ++ ++ txbd = rtw89_pci_get_next_txbd(tx_ring); ++ ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to submit TXBD\n"); ++ goto err_unlock; ++ } ++ ++ spin_unlock_bh(&rtwpci->trx_lock); ++ return 0; ++ ++err_unlock: ++ spin_unlock_bh(&rtwpci->trx_lock); ++ return ret; ++} ++ ++static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) ++{ ++ struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; ++ int ret; ++ ++ ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct rtw89_pci_bd_ram bd_ram_table[RTW89_TXCH_NUM] = { ++ [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH4] = {.start_idx = 20, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH5] = {.start_idx = 25, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH6] = {.start_idx = 30, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_ACH7] = {.start_idx = 35, .max_num = 5, .min_num = 2}, ++ [RTW89_TXCH_CH8] = {.start_idx = 40, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH9] = {.start_idx = 45, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH10] = {.start_idx = 50, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH11] = {.start_idx = 55, .max_num = 5, .min_num = 1}, ++ [RTW89_TXCH_CH12] = {.start_idx = 60, .max_num = 4, .min_num = 1}, ++}; ++ ++static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ struct rtw89_pci_rx_ring *rx_ring; ++ struct rtw89_pci_dma_ring *bd_ring; ++ const struct rtw89_pci_bd_ram *bd_ram; ++ u32 addr_num; ++ u32 addr_bdram; ++ u32 addr_desa_l; ++ u32 val32; ++ int i; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ bd_ring = &tx_ring->bd_ring; ++ bd_ram = &bd_ram_table[i]; ++ addr_num = bd_ring->addr_num; ++ addr_bdram = bd_ring->addr_bdram; ++ addr_desa_l = bd_ring->addr_desa_l; ++ bd_ring->wp = 0; ++ bd_ring->rp = 0; ++ ++ val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | ++ FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | ++ FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num); ++ ++ rtw89_write16(rtwdev, addr_num, bd_ring->len); ++ rtw89_write32(rtwdev, addr_bdram, val32); ++ rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); ++ } ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ bd_ring = &rx_ring->bd_ring; ++ addr_num = bd_ring->addr_num; ++ addr_desa_l = bd_ring->addr_desa_l; ++ bd_ring->wp = 0; ++ bd_ring->rp = 0; ++ rx_ring->diliver_skb = NULL; ++ rx_ring->diliver_desc.ready = false; ++ ++ rtw89_write16(rtwdev, addr_num, bd_ring->len); ++ rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); ++ } ++} ++ ++static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ rtw89_pci_release_busy_txwd(rtwdev, tx_ring); ++ rtw89_pci_release_pending_txwd_skb(rtwdev, tx_ring); ++} ++ ++static void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ int txch; ++ ++ rtw89_pci_reset_trx_rings(rtwdev); ++ ++ spin_lock_bh(&rtwpci->trx_lock); ++ for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { ++ if (txch == RTW89_TXCH_CH12) { ++ rtw89_pci_release_fwcmd(rtwdev, rtwpci, ++ skb_queue_len(&rtwpci->h2c_queue), true); ++ continue; ++ } ++ rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]); ++ } ++ spin_unlock_bh(&rtwpci->trx_lock); ++} ++ ++static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long flags; ++ ++ rtw89_core_napi_start(rtwdev); ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ rtwpci->running = true; ++ rtw89_pci_enable_intr(rtwdev, rtwpci); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ return 0; ++} ++ ++static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct pci_dev *pdev = rtwpci->pdev; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ rtwpci->running = false; ++ rtw89_pci_disable_intr(rtwdev, rtwpci); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ ++ synchronize_irq(pdev->irq); ++ rtw89_core_napi_stop(rtwdev); ++} ++ ++static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data); ++ ++static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ u32 val = readl(rtwpci->mmap + addr); ++ int count; ++ ++ for (count = 0; ; count++) { ++ if (val != RTW89_R32_DEAD) ++ return val; ++ if (count >= MAC_REG_POOL_COUNT) { ++ rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val); ++ return RTW89_R32_DEAD; ++ } ++ rtw89_pci_ops_write32(rtwdev, R_AX_CK_EN, B_AX_CMAC_ALLCKEN); ++ val = readl(rtwpci->mmap + addr); ++ } ++ ++ return val; ++} ++ ++static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ u32 addr32, val32, shift; ++ ++ if (!ACCESS_CMAC(addr)) ++ return readb(rtwpci->mmap + addr); ++ ++ addr32 = addr & ~0x3; ++ shift = (addr & 0x3) * 8; ++ val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); ++ return val32 >> shift; ++} ++ ++static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ u32 addr32, val32, shift; ++ ++ if (!ACCESS_CMAC(addr)) ++ return readw(rtwpci->mmap + addr); ++ ++ addr32 = addr & ~0x3; ++ shift = (addr & 0x3) * 8; ++ val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); ++ return val32 >> shift; ++} ++ ++static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ if (!ACCESS_CMAC(addr)) ++ return readl(rtwpci->mmap + addr); ++ ++ return rtw89_pci_ops_read32_cmac(rtwdev, addr); ++} ++ ++static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ writeb(data, rtwpci->mmap + addr); ++} ++ ++static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ writew(data, rtwpci->mmap + addr); ++} ++ ++static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ writel(data, rtwpci->mmap + addr); ++} ++ ++static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable) ++{ ++ if (enable) { ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_TXHCI_EN | B_AX_RXHCI_EN); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, ++ B_AX_STOP_PCIEIO); ++ } else { ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, ++ B_AX_STOP_PCIEIO); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_TXHCI_EN | B_AX_RXHCI_EN); ++ } ++} ++ ++static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit) ++{ ++ u16 val; ++ ++ rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F); ++ ++ val = rtw89_read16(rtwdev, R_AX_MDIO_CFG); ++ switch (speed) { ++ case PCIE_PHY_GEN1: ++ if (addr < 0x20) ++ val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK); ++ else ++ val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK); ++ break; ++ case PCIE_PHY_GEN2: ++ if (addr < 0x20) ++ val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK); ++ else ++ val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK); ++ break; ++ default: ++ rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); ++ return -EINVAL; ++ }; ++ rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); ++ rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); ++ ++ return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000, ++ false, rtwdev, R_AX_MDIO_CFG); ++} ++ ++static int ++rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val) ++{ ++ int ret; ++ ++ ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret); ++ return ret; ++ } ++ *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA); ++ ++ return 0; ++} ++ ++static int ++rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed) ++{ ++ int ret; ++ ++ rtw89_write16(rtwdev, R_AX_MDIO_WDATA, data); ++ ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) ++{ ++ int ret; ++ u16 val; ++ ++ ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) ++{ ++ int ret; ++ u16 val; ++ ++ ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int rtw89_dbi_write8(struct rtw89_dev *rtwdev, u16 addr, u8 data) ++{ ++ u16 write_addr; ++ u16 remainder = addr & ~(B_AX_DBI_ADDR_MSK | B_AX_DBI_WREN_MSK); ++ u8 flag; ++ int ret; ++ ++ write_addr = addr & B_AX_DBI_ADDR_MSK; ++ write_addr |= u16_encode_bits(BIT(remainder), B_AX_DBI_WREN_MSK); ++ rtw89_write8(rtwdev, R_AX_DBI_WDATA + remainder, data); ++ rtw89_write16(rtwdev, R_AX_DBI_FLAG, write_addr); ++ rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_WFLAG >> 16); ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10, ++ 10 * RTW89_PCI_WR_RETRY_CNT, false, ++ rtwdev, R_AX_DBI_FLAG + 2); ++ if (ret) ++ WARN(flag, "failed to write to DBI register, addr=0x%04x\n", ++ addr); ++ ++ return ret; ++} ++ ++static int rtw89_dbi_read8(struct rtw89_dev *rtwdev, u16 addr, u8 *value) ++{ ++ u16 read_addr = addr & B_AX_DBI_ADDR_MSK; ++ u8 flag; ++ int ret; ++ ++ rtw89_write16(rtwdev, R_AX_DBI_FLAG, read_addr); ++ rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_RFLAG >> 16); ++ ++ ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10, ++ 10 * RTW89_PCI_WR_RETRY_CNT, false, ++ rtwdev, R_AX_DBI_FLAG + 2); ++ ++ if (!ret) { ++ read_addr = R_AX_DBI_RDATA + (addr & 3); ++ *value = rtw89_read8(rtwdev, read_addr); ++ } else { ++ WARN(1, "failed to read DBI register, addr=0x%04x\n", addr); ++ ret = -EIO; ++ } ++ ++ return ret; ++} ++ ++static int rtw89_dbi_write8_set(struct rtw89_dev *rtwdev, u16 addr, u8 bit) ++{ ++ u8 value; ++ int ret; ++ ++ ret = rtw89_dbi_read8(rtwdev, addr, &value); ++ if (ret) ++ return ret; ++ ++ value |= bit; ++ ret = rtw89_dbi_write8(rtwdev, addr, value); ++ ++ return ret; ++} ++ ++static int rtw89_dbi_write8_clr(struct rtw89_dev *rtwdev, u16 addr, u8 bit) ++{ ++ u8 value; ++ int ret; ++ ++ ret = rtw89_dbi_read8(rtwdev, addr, &value); ++ if (ret) ++ return ret; ++ ++ value &= ~bit; ++ ret = rtw89_dbi_write8(rtwdev, addr, value); ++ ++ return ret; ++} ++ ++static int ++__get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) ++{ ++ u16 val, tar; ++ int ret; ++ ++ /* Enable counter */ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, ++ phy_rate); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN, ++ phy_rate); ++ if (ret) ++ return ret; ++ ++ fsleep(300); ++ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, ++ phy_rate); ++ if (ret) ++ return ret; ++ ++ tar = tar & 0x0FFF; ++ if (tar == 0 || tar == 0x0FFF) { ++ rtw89_err(rtwdev, "[ERR]Get target failed.\n"); ++ return -EINVAL; ++ } ++ ++ *target = tar; ++ ++ return 0; ++} ++ ++static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) ++{ ++ enum rtw89_pcie_phy phy_rate; ++ u16 val16, mgn_set, div_set, tar; ++ u8 val8, bdr_ori; ++ bool l1_flag = false; ++ int ret = 0; ++ ++ if ((rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) || ++ rtwdev->chip->chip_id == RTL8852C) ++ return 0; ++ ++ ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_PHY_RATE, &val8); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_r8_pcie %X\n", RTW89_PCIE_PHY_RATE); ++ return ret; ++ } ++ ++ if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x1) { ++ phy_rate = PCIE_PHY_GEN1; ++ } else if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x2) { ++ phy_rate = PCIE_PHY_GEN2; ++ } else { ++ rtw89_err(rtwdev, "[ERR]PCIe PHY rate %#x not support\n", val8); ++ return -EOPNOTSUPP; ++ } ++ /* Disable L1BD */ ++ ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_r8_pcie %X\n", RTW89_PCIE_L1_CTRL); ++ return ret; ++ } ++ ++ if (bdr_ori & RTW89_PCIE_BIT_L1) { ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_L1_CTRL, ++ bdr_ori & ~RTW89_PCIE_BIT_L1); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_w8_pcie %X\n", RTW89_PCIE_L1_CTRL); ++ return ret; ++ } ++ l1_flag = true; ++ } ++ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ if (val16 & B_AX_CALIB_EN) { ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, ++ val16 & ~B_AX_CALIB_EN, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ } ++ ++ if (!autook_en) ++ goto end; ++ /* Set div */ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ /* Obtain div and margin */ ++ ret = __get_target(rtwdev, &tar, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret); ++ goto end; ++ } ++ ++ mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar; ++ ++ if (mgn_set >= 128) { ++ div_set = 0x0003; ++ mgn_set = 0x000F; ++ } else if (mgn_set >= 64) { ++ div_set = 0x0003; ++ mgn_set >>= 3; ++ } else if (mgn_set >= 32) { ++ div_set = 0x0002; ++ mgn_set >>= 2; ++ } else if (mgn_set >= 16) { ++ div_set = 0x0001; ++ mgn_set >>= 1; ++ } else if (mgn_set == 0) { ++ rtw89_err(rtwdev, "[ERR]cal mgn is 0,tar = %d\n", tar); ++ goto end; ++ } else { ++ div_set = 0x0000; ++ } ++ ++ ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ val16 |= u16_encode_bits(div_set, B_AX_DIV); ++ ++ ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ ret = __get_target(rtwdev, &tar, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret); ++ goto end; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_HCI, "[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", ++ tar, div_set, mgn_set); ++ ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1, ++ (tar & 0x0FFF) | (mgn_set << 12), phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_SET_PPR_V1); ++ goto end; ++ } ++ ++ /* Enable function */ ++ ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); ++ goto end; ++ } ++ ++ /* CLK delay = 0 */ ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_CLK_CTRL, PCIE_CLKDLY_HW_0); ++ ++end: ++ /* Set L1BD to ori */ ++ if (l1_flag) { ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_L1_CTRL, bdr_ori); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR]dbi_w8_pcie %X\n", RTW89_PCIE_L1_CTRL); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++ ++static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ if (rtwdev->chip->chip_id != RTL8852A) ++ return 0; ++ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, ++ PCIE_PHY_GEN1); ++ if (ret) ++ return ret; ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, ++ PCIE_PHY_GEN2); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev) ++{ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); ++} ++ ++static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN); ++} ++ ++static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return 0; ++ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, ++ PCIE_PHY_GEN1); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, ++ PCIE_PHY_GEN2); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id != RTL8852A) ++ return; ++ ++ rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN); ++} ++ ++static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id != RTL8852A) ++ return; ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); ++ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_WLSUS_AFT_PDN); ++} ++ ++static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_EXP_CTRL, ++ B_AX_SIC_EN_FORCE_CLKREQ); ++} ++ ++static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, ++ B_AX_ASFF_FULL_NO_STK | B_AX_EN_STUCK_DBG); ++ ++ if (rtwdev->chip->chip_id == RTL8852A) ++ rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, ++ B_AX_EN_CHKDSC_NO_RX_STUCK); ++} ++ ++static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev) ++{ ++ u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX | ++ B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX | ++ B_AX_CLR_CH12_IDX; ++ ++ if (rtwdev->chip->chip_id == RTL8852A) ++ val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX | ++ B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX; ++ /* clear DMA indexes */ ++ rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); ++ if (rtwdev->chip->chip_id == RTL8852A) ++ rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR2, ++ B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX); ++ rtw89_write32_set(rtwdev, R_AX_RXBD_RWPTR_CLR, ++ B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); ++} ++ ++static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852A) { ++ /* ltr sw trigger */ ++ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); ++ } ++ rtw89_pci_ctrl_dma_all(rtwdev, false); ++ rtw89_pci_clr_idx_all(rtwdev); ++ ++ return 0; ++} ++ ++static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev) ++{ ++ u32 dma_busy; ++ u32 check; ++ u32 lbc; ++ int ret; ++ ++ rtw89_pci_rxdma_prefth(rtwdev); ++ rtw89_pci_l1off_pwroff(rtwdev); ++ rtw89_pci_deglitch_setting(rtwdev); ++ ret = rtw89_pci_l2_rxen_lat(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret); ++ return ret; ++ } ++ ++ rtw89_pci_aphy_pwrcut(rtwdev); ++ rtw89_pci_hci_ldo(rtwdev); ++ ++ ret = rtw89_pci_auto_refclk_cal(rtwdev, false); ++ if (ret) { ++ rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret); ++ return ret; ++ } ++ ++ rtw89_pci_set_sic(rtwdev); ++ rtw89_pci_set_dbg(rtwdev); ++ ++ if (rtwdev->chip->chip_id == RTL8852A) ++ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_AUXCLK_GATE); ++ ++ lbc = rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG); ++ lbc = u32_replace_bits(lbc, RTW89_MAC_LBC_TMR_128US, B_AX_LBC_TIMER); ++ lbc |= B_AX_LBC_FLAG | B_AX_LBC_EN; ++ rtw89_write32(rtwdev, R_AX_LBC_WATCHDOG, lbc); ++ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_PCIE_TXRST_KEEP_REG | B_AX_PCIE_RXRST_KEEP_REG); ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_STOP_WPDMA); ++ ++ /* stop DMA activities */ ++ rtw89_pci_ctrl_dma_all(rtwdev, false); ++ ++ /* check PCI at idle state */ ++ check = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; ++ ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, ++ 100, 3000, false, rtwdev, R_AX_PCIE_DMA_BUSY1); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to poll io busy\n"); ++ return ret; ++ } ++ ++ rtw89_pci_clr_idx_all(rtwdev); ++ ++ /* configure TX/RX op modes */ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE | ++ B_AX_RX_TRUNC_MODE); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RXBD_MODE); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, 7); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, 3); ++ /* multi-tag mode */ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_LATENCY_CONTROL); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_EXP_CTRL, B_AX_MAX_TAG_NUM, ++ RTW89_MAC_TAG_NUM_8); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, ++ RTW89_MAC_WD_DMA_INTVL_256NS); ++ rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, ++ RTW89_MAC_WD_DMA_INTVL_256NS); ++ ++ /* fill TRX BD indexes */ ++ rtw89_pci_ops_reset(rtwdev); ++ ++ ret = rtw89_pci_rst_bdram_pcie(rtwdev); ++ if (ret) { ++ rtw89_warn(rtwdev, "reset bdram busy\n"); ++ return ret; ++ } ++ ++ /* enable FW CMD queue to download firmware */ ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_ALL); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_STOP_CH12); ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL); ++ ++ /* start DMA activities */ ++ rtw89_pci_ctrl_dma_all(rtwdev, true); ++ ++ return 0; ++} ++ ++static int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev) ++{ ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY); ++ if (rtw89_pci_ltr_is_err_reg_val(val)) ++ return -EINVAL; ++ ++ rtw89_write32_clr(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN); ++ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_EN); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, ++ PCI_LTR_SPC_500US); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, ++ PCI_LTR_IDLE_TIMER_800US); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); ++ rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); ++ rtw89_write32(rtwdev, R_AX_LTR_IDLE_LATENCY, 0x88e088e0); ++ rtw89_write32(rtwdev, R_AX_LTR_ACTIVE_LATENCY, 0x880b880b); ++ ++ return 0; ++} ++ ++static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev) ++{ ++ int ret; ++ ++ ret = rtw89_pci_ltr_set(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "pci ltr set fail\n"); ++ return ret; ++ } ++ if (rtwdev->chip->chip_id == RTL8852A) { ++ /* ltr sw trigger */ ++ rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); ++ } ++ /* ADDR info 8-byte mode */ ++ rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, ++ B_AX_HOST_ADDR_INFO_8B_SEL); ++ rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); ++ ++ /* enable DMA for all queues */ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_ALL); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL); ++ ++ /* Release PCI IO */ ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, ++ B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO); ++ ++ return 0; ++} ++ ++static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ int ret; ++ ++ ret = pci_enable_device(pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to enable pci device\n"); ++ return ret; ++ } ++ ++ pci_set_master(pdev); ++ pci_set_drvdata(pdev, rtwdev->hw); ++ ++ rtwpci->pdev = pdev; ++ ++ return 0; ++} ++ ++static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ pci_clear_master(pdev); ++ pci_disable_device(pdev); ++} ++ ++static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long resource_len; ++ u8 bar_id = 2; ++ int ret; ++ ++ ret = pci_request_regions(pdev, KBUILD_MODNAME); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to request pci regions\n"); ++ goto err; ++ } ++ ++ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to set dma mask to 32-bit\n"); ++ goto err_release_regions; ++ } ++ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to set consistent dma mask to 32-bit\n"); ++ goto err_release_regions; ++ } ++ ++ resource_len = pci_resource_len(pdev, bar_id); ++ rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len); ++ if (!rtwpci->mmap) { ++ rtw89_err(rtwdev, "failed to map pci io\n"); ++ ret = -EIO; ++ goto err_release_regions; ++ } ++ ++ return 0; ++ ++err_release_regions: ++ pci_release_regions(pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ if (rtwpci->mmap) { ++ pci_iounmap(pdev, rtwpci->mmap); ++ pci_release_regions(pdev); ++ } ++} ++ ++static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ u8 *head = wd_ring->head; ++ dma_addr_t dma = wd_ring->dma; ++ u32 page_size = wd_ring->page_size; ++ u32 page_num = wd_ring->page_num; ++ u32 ring_sz = page_size * page_num; ++ ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ wd_ring->head = NULL; ++} ++ ++static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring) ++{ ++ int ring_sz; ++ u8 *head; ++ dma_addr_t dma; ++ ++ head = tx_ring->bd_ring.head; ++ dma = tx_ring->bd_ring.dma; ++ ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len; ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ ++ tx_ring->bd_ring.head = NULL; ++} ++ ++static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ int i; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); ++ rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); ++ } ++} ++ ++static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_rx_ring *rx_ring) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ struct sk_buff *skb; ++ dma_addr_t dma; ++ u32 buf_sz; ++ u8 *head; ++ int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len; ++ int i; ++ ++ buf_sz = rx_ring->buf_sz; ++ for (i = 0; i < rx_ring->bd_ring.len; i++) { ++ skb = rx_ring->buf[i]; ++ if (!skb) ++ continue; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ dma = rx_info->dma; ++ dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); ++ dev_kfree_skb(skb); ++ rx_ring->buf[i] = NULL; ++ } ++ ++ head = rx_ring->bd_ring.head; ++ dma = rx_ring->bd_ring.dma; ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ ++ rx_ring->bd_ring.head = NULL; ++} ++ ++static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_rx_ring *rx_ring; ++ int i; ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); ++ } ++} ++ ++static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ rtw89_pci_free_rx_rings(rtwdev, pdev); ++ rtw89_pci_free_tx_rings(rtwdev, pdev); ++} ++ ++static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ struct sk_buff *skb, int buf_sz, u32 idx) ++{ ++ struct rtw89_pci_rx_info *rx_info; ++ struct rtw89_pci_rx_bd_32 *rx_bd; ++ dma_addr_t dma; ++ ++ if (!skb) ++ return -EINVAL; ++ ++ dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); ++ if (dma_mapping_error(&pdev->dev, dma)) ++ return -EBUSY; ++ ++ rx_info = RTW89_PCI_RX_SKB_CB(skb); ++ rx_bd = RTW89_PCI_RX_BD(rx_ring, idx); ++ ++ memset(rx_bd, 0, sizeof(*rx_bd)); ++ rx_bd->buf_size = cpu_to_le16(buf_sz); ++ rx_bd->dma = cpu_to_le32(dma); ++ rx_info->dma = dma; ++ ++ return 0; ++} ++ ++static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ enum rtw89_tx_channel txch) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ dma_addr_t dma; ++ dma_addr_t cur_paddr; ++ u8 *head; ++ u8 *cur_vaddr; ++ u32 page_size = RTW89_PCI_TXWD_PAGE_SIZE; ++ u32 page_num = RTW89_PCI_TXWD_NUM_MAX; ++ u32 ring_sz = page_size * page_num; ++ u32 page_offset; ++ int i; ++ ++ /* FWCMD queue doesn't use txwd as pages */ ++ if (txch == RTW89_TXCH_CH12) ++ return 0; ++ ++ head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); ++ if (!head) ++ return -ENOMEM; ++ ++ INIT_LIST_HEAD(&wd_ring->free_pages); ++ wd_ring->head = head; ++ wd_ring->dma = dma; ++ wd_ring->page_size = page_size; ++ wd_ring->page_num = page_num; ++ ++ page_offset = 0; ++ for (i = 0; i < page_num; i++) { ++ txwd = &wd_ring->pages[i]; ++ cur_paddr = dma + page_offset; ++ cur_vaddr = head + page_offset; ++ ++ skb_queue_head_init(&txwd->queue); ++ INIT_LIST_HEAD(&txwd->list); ++ txwd->paddr = cur_paddr; ++ txwd->vaddr = cur_vaddr; ++ txwd->len = page_size; ++ txwd->seq = i; ++ rtw89_pci_enqueue_txwd(tx_ring, txwd); ++ ++ page_offset += page_size; ++ } ++ ++ return 0; ++} ++ ++static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_tx_ring *tx_ring, ++ u32 desc_size, u32 len, ++ enum rtw89_tx_channel txch) ++{ ++ int ring_sz = desc_size * len; ++ u8 *head; ++ dma_addr_t dma; ++ u32 addr_num; ++ u32 addr_idx; ++ u32 addr_bdram; ++ u32 addr_desa_l; ++ u32 addr_desa_h; ++ int ret; ++ ++ ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc txwd ring of txch %d\n", txch); ++ goto err; ++ } ++ ++ ret = rtw89_pci_get_txch_addrs(txch, &addr_num, &addr_idx, &addr_bdram, ++ &addr_desa_l, &addr_desa_h); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get address of txch %d", txch); ++ goto err_free_wd_ring; ++ } ++ ++ head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); ++ if (!head) { ++ ret = -ENOMEM; ++ goto err_free_wd_ring; ++ } ++ ++ INIT_LIST_HEAD(&tx_ring->busy_pages); ++ tx_ring->bd_ring.head = head; ++ tx_ring->bd_ring.dma = dma; ++ tx_ring->bd_ring.len = len; ++ tx_ring->bd_ring.desc_size = desc_size; ++ tx_ring->bd_ring.addr_num = addr_num; ++ tx_ring->bd_ring.addr_idx = addr_idx; ++ tx_ring->bd_ring.addr_bdram = addr_bdram; ++ tx_ring->bd_ring.addr_desa_l = addr_desa_l; ++ tx_ring->bd_ring.addr_desa_h = addr_desa_h; ++ tx_ring->bd_ring.wp = 0; ++ tx_ring->bd_ring.rp = 0; ++ tx_ring->txch = txch; ++ ++ return 0; ++ ++err_free_wd_ring: ++ rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); ++err: ++ return ret; ++} ++ ++static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_tx_ring *tx_ring; ++ u32 desc_size; ++ u32 len; ++ u32 i, tx_allocated; ++ int ret; ++ ++ for (i = 0; i < RTW89_TXCH_NUM; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ desc_size = sizeof(struct rtw89_pci_tx_bd_32); ++ len = RTW89_PCI_TXBD_NUM_MAX; ++ ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, ++ desc_size, len, i); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); ++ goto err_free; ++ } ++ } ++ ++ return 0; ++ ++err_free: ++ tx_allocated = i; ++ for (i = 0; i < tx_allocated; i++) { ++ tx_ring = &rtwpci->tx_rings[i]; ++ rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); ++ } ++ ++ return ret; ++} ++ ++static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev, ++ struct rtw89_pci_rx_ring *rx_ring, ++ u32 desc_size, u32 len, u32 rxch) ++{ ++ struct sk_buff *skb; ++ u8 *head; ++ dma_addr_t dma; ++ u32 addr_num; ++ u32 addr_idx; ++ u32 addr_desa_l; ++ u32 addr_desa_h; ++ int ring_sz = desc_size * len; ++ int buf_sz = RTW89_PCI_RX_BUF_SIZE; ++ int i, allocated; ++ int ret; ++ ++ ret = rtw89_pci_get_rxch_addrs(rxch, &addr_num, &addr_idx, ++ &addr_desa_l, &addr_desa_h); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); ++ return ret; ++ } ++ ++ head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); ++ if (!head) { ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ rx_ring->bd_ring.head = head; ++ rx_ring->bd_ring.dma = dma; ++ rx_ring->bd_ring.len = len; ++ rx_ring->bd_ring.desc_size = desc_size; ++ rx_ring->bd_ring.addr_num = addr_num; ++ rx_ring->bd_ring.addr_idx = addr_idx; ++ rx_ring->bd_ring.addr_desa_l = addr_desa_l; ++ rx_ring->bd_ring.addr_desa_h = addr_desa_h; ++ rx_ring->bd_ring.wp = 0; ++ rx_ring->bd_ring.rp = 0; ++ rx_ring->buf_sz = buf_sz; ++ rx_ring->diliver_skb = NULL; ++ rx_ring->diliver_desc.ready = false; ++ ++ for (i = 0; i < len; i++) { ++ skb = dev_alloc_skb(buf_sz); ++ if (!skb) { ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ ++ memset(skb->data, 0, buf_sz); ++ rx_ring->buf[i] = skb; ++ ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb, ++ buf_sz, i); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to init rx buf %d\n", i); ++ dev_kfree_skb_any(skb); ++ rx_ring->buf[i] = NULL; ++ goto err_free; ++ } ++ } ++ ++ return 0; ++ ++err_free: ++ allocated = i; ++ for (i = 0; i < allocated; i++) { ++ skb = rx_ring->buf[i]; ++ if (!skb) ++ continue; ++ dma = *((dma_addr_t *)skb->cb); ++ dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); ++ dev_kfree_skb(skb); ++ rx_ring->buf[i] = NULL; ++ } ++ ++ head = rx_ring->bd_ring.head; ++ dma = rx_ring->bd_ring.dma; ++ dma_free_coherent(&pdev->dev, ring_sz, head, dma); ++ ++ rx_ring->bd_ring.head = NULL; ++err: ++ return ret; ++} ++ ++static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct rtw89_pci_rx_ring *rx_ring; ++ u32 desc_size; ++ u32 len; ++ int i, rx_allocated; ++ int ret; ++ ++ for (i = 0; i < RTW89_RXCH_NUM; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ desc_size = sizeof(struct rtw89_pci_rx_bd_32); ++ len = RTW89_PCI_RXBD_NUM_MAX; ++ ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, ++ desc_size, len, i); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); ++ goto err_free; ++ } ++ } ++ ++ return 0; ++ ++err_free: ++ rx_allocated = i; ++ for (i = 0; i < rx_allocated; i++) { ++ rx_ring = &rtwpci->rx_rings[i]; ++ rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); ++ } ++ ++ return ret; ++} ++ ++static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ int ret; ++ ++ ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc dma tx rings\n"); ++ goto err; ++ } ++ ++ ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc dma rx rings\n"); ++ goto err_free_tx_rings; ++ } ++ ++ return 0; ++ ++err_free_tx_rings: ++ rtw89_pci_free_tx_rings(rtwdev, pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev, ++ struct rtw89_pci *rtwpci) ++{ ++ skb_queue_head_init(&rtwpci->h2c_queue); ++ skb_queue_head_init(&rtwpci->h2c_release_queue); ++} ++ ++static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ int ret; ++ ++ ret = rtw89_pci_setup_mapping(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to setup pci mapping\n"); ++ goto err; ++ } ++ ++ ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to alloc pci trx rings\n"); ++ goto err_pci_unmap; ++ } ++ ++ rtw89_pci_h2c_init(rtwdev, rtwpci); ++ ++ spin_lock_init(&rtwpci->irq_lock); ++ spin_lock_init(&rtwpci->trx_lock); ++ ++ return 0; ++ ++err_pci_unmap: ++ rtw89_pci_clear_mapping(rtwdev, pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ rtw89_pci_free_trx_rings(rtwdev, pdev); ++ rtw89_pci_clear_mapping(rtwdev, pdev); ++ rtw89_pci_release_fwcmd(rtwdev, rtwpci, ++ skb_queue_len(&rtwpci->h2c_queue), true); ++} ++ ++static void rtw89_pci_default_intr_mask(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ ++ rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0; ++ rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | ++ B_AX_RXDMA_INT_EN | ++ B_AX_RXP1DMA_INT_EN | ++ B_AX_RPQDMA_INT_EN | ++ B_AX_RXDMA_STUCK_INT_EN | ++ B_AX_RDU_INT_EN | ++ B_AX_RPQBD_FULL_INT_EN | ++ B_AX_HS0ISR_IND_INT_EN; ++ ++ rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN; ++} ++ ++static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ unsigned long flags = 0; ++ int ret; ++ ++ flags |= PCI_IRQ_LEGACY | PCI_IRQ_MSI; ++ ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); ++ if (ret < 0) { ++ rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret); ++ goto err; ++ } ++ ++ ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, ++ rtw89_pci_interrupt_handler, ++ rtw89_pci_interrupt_threadfn, ++ IRQF_SHARED, KBUILD_MODNAME, rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to request threaded irq\n"); ++ goto err_free_vector; ++ } ++ ++ rtw89_pci_default_intr_mask(rtwdev); ++ ++ return 0; ++ ++err_free_vector: ++ pci_free_irq_vectors(pdev); ++err: ++ return ret; ++} ++ ++static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev, ++ struct pci_dev *pdev) ++{ ++ devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); ++ pci_free_irq_vectors(pdev); ++} ++ ++static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret; ++ ++ if (rtw89_pci_disable_clkreq) ++ return; ++ ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_CLK_CTRL, ++ PCIE_CLKDLY_HW_30US); ++ if (ret) ++ rtw89_err(rtwdev, "failed to set CLKREQ Delay\n"); ++ ++ if (enable) ++ ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_CLK); ++ else ++ ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_CLK); ++ if (ret) ++ rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d", ++ enable ? "set" : "unset", ret); ++} ++ ++static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) ++{ ++ u8 value = 0; ++ int ret; ++ ++ if (rtw89_pci_disable_aspm_l1) ++ return; ++ ++ ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_ASPM_CTRL, &value); ++ if (ret) ++ rtw89_err(rtwdev, "failed to read ASPM Delay\n"); ++ ++ value &= ~(RTW89_L1DLY_MASK | RTW89_L0DLY_MASK); ++ value |= FIELD_PREP(RTW89_L1DLY_MASK, PCIE_L1DLY_16US) | ++ FIELD_PREP(RTW89_L0DLY_MASK, PCIE_L0SDLY_4US); ++ ++ ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_ASPM_CTRL, value); ++ if (ret) ++ rtw89_err(rtwdev, "failed to read ASPM Delay\n"); ++ ++ if (enable) ++ ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_L1); ++ else ++ ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_L1_CTRL, ++ RTW89_PCIE_BIT_L1); ++ if (ret) ++ rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d", ++ enable ? "set" : "unset", ret); ++} ++ ++static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; ++ enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; ++ u32 val = 0; ++ ++ if (!rtwdev->scanning && ++ (tx_tfc_lv >= RTW89_TFC_HIGH || rx_tfc_lv >= RTW89_TFC_HIGH)) ++ val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL | ++ FIELD_PREP(B_AX_RXCOUNTER_MATCH_MASK, RTW89_PCI_RXBD_NUM_MAX / 2) | ++ FIELD_PREP(B_AX_RXTIMER_UNIT_MASK, AX_RXTIMER_UNIT_64US) | ++ FIELD_PREP(B_AX_RXTIMER_MATCH_MASK, 2048 / 64); ++ ++ rtw89_write32(rtwdev, R_AX_INT_MIT_RX, val); ++} ++ ++static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct pci_dev *pdev = rtwpci->pdev; ++ u16 link_ctrl; ++ int ret; ++ ++ /* Though there is standard PCIE configuration space to set the ++ * link control register, but by Realtek's design, driver should ++ * check if host supports CLKREQ/ASPM to enable the HW module. ++ * ++ * These functions are implemented by two HW modules associated, ++ * one is responsible to access PCIE configuration space to ++ * follow the host settings, and another is in charge of doing ++ * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes ++ * the host does not support it, and due to some reasons or wrong ++ * settings (ex. CLKREQ# not Bi-Direction), it could lead to device ++ * loss if HW misbehaves on the link. ++ * ++ * Hence it's designed that driver should first check the PCIE ++ * configuration space is sync'ed and enabled, then driver can turn ++ * on the other module that is actually working on the mechanism. ++ */ ++ ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); ++ return; ++ } ++ ++ if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) ++ rtw89_pci_clkreq_set(rtwdev, true); ++ ++ if (link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) ++ rtw89_pci_aspm_set(rtwdev, true); ++} ++ ++static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) ++{ ++ int ret; ++ ++ if (enable) ++ ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_TIMER_CTRL, ++ RTW89_PCIE_BIT_L1SUB); ++ else ++ ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_TIMER_CTRL, ++ RTW89_PCIE_BIT_L1SUB); ++ if (ret) ++ rtw89_err(rtwdev, "failed to %s L1SS, ret=%d", ++ enable ? "set" : "unset", ret); ++} ++ ++static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ struct pci_dev *pdev = rtwpci->pdev; ++ u32 l1ss_cap_ptr, l1ss_ctrl; ++ ++ if (rtw89_pci_disable_l1ss) ++ return; ++ ++ l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); ++ if (!l1ss_cap_ptr) ++ return; ++ ++ pci_read_config_dword(pdev, l1ss_cap_ptr + PCI_L1SS_CTL1, &l1ss_ctrl); ++ ++ if (l1ss_ctrl & PCI_L1SS_CTL1_L1SS_MASK) ++ rtw89_pci_l1ss_set(rtwdev, true); ++} ++ ++static void rtw89_pci_ctrl_dma_all_pcie(struct rtw89_dev *rtwdev, u8 en) ++{ ++ u32 val32; ++ ++ if (en == MAC_AX_FUNC_EN) { ++ val32 = B_AX_STOP_PCIEIO; ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_DMA_STOP1, val32); ++ ++ val32 = B_AX_TXHCI_EN | B_AX_RXHCI_EN; ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ++ } else { ++ val32 = B_AX_STOP_PCIEIO; ++ rtw89_write32_set(rtwdev, R_AX_PCIE_DMA_STOP1, val32); ++ ++ val32 = B_AX_TXHCI_EN | B_AX_RXHCI_EN; ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ++ } ++} ++ ++static int rtw89_pci_poll_io_idle(struct rtw89_dev *rtwdev) ++{ ++ int ret = 0; ++ u32 sts; ++ u32 busy = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0, ++ 10, 1000, false, rtwdev, ++ R_AX_PCIE_DMA_BUSY1); ++ if (ret) { ++ rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", ++ rtw89_read32(rtwdev, R_AX_PCIE_DMA_BUSY1)); ++ return -EINVAL; ++ } ++ return ret; ++} ++ ++static int rtw89_pci_lv1rst_stop_dma(struct rtw89_dev *rtwdev) ++{ ++ u32 val, dma_rst = 0; ++ int ret; ++ ++ rtw89_pci_ctrl_dma_all_pcie(rtwdev, MAC_AX_FUNC_DIS); ++ ret = rtw89_pci_poll_io_idle(rtwdev); ++ if (ret) { ++ val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); ++ rtw89_debug(rtwdev, RTW89_DBG_HCI, ++ "[PCIe] poll_io_idle fail, before 0x%08x: 0x%08x\n", ++ R_AX_DBG_ERR_FLAG, val); ++ if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0) ++ dma_rst |= B_AX_HCI_TXDMA_EN; ++ if (val & B_AX_RX_STUCK) ++ dma_rst |= B_AX_HCI_RXDMA_EN; ++ val = rtw89_read32(rtwdev, R_AX_HCI_FUNC_EN); ++ rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val & ~dma_rst); ++ rtw89_write32(rtwdev, R_AX_HCI_FUNC_EN, val | dma_rst); ++ ret = rtw89_pci_poll_io_idle(rtwdev); ++ val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); ++ rtw89_debug(rtwdev, RTW89_DBG_HCI, ++ "[PCIe] poll_io_idle fail, after 0x%08x: 0x%08x\n", ++ R_AX_DBG_ERR_FLAG, val); ++ } ++ ++ return ret; ++} ++ ++static void rtw89_pci_ctrl_hci_dma_en(struct rtw89_dev *rtwdev, u8 en) ++{ ++ u32 val32; ++ ++ if (en == MAC_AX_FUNC_EN) { ++ val32 = B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; ++ rtw89_write32_set(rtwdev, R_AX_HCI_FUNC_EN, val32); ++ } else { ++ val32 = B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN; ++ rtw89_write32_clr(rtwdev, R_AX_HCI_FUNC_EN, val32); ++ } ++} ++ ++static int rtw89_pci_rst_bdram(struct rtw89_dev *rtwdev) ++{ ++ int ret = 0; ++ u32 val32, sts; ++ ++ val32 = B_AX_RST_BDRAM; ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); ++ ++ ret = read_poll_timeout_atomic(rtw89_read32, sts, ++ (sts & B_AX_RST_BDRAM) == 0x0, 1, 100, ++ true, rtwdev, R_AX_PCIE_INIT_CFG1); ++ return ret; ++} ++ ++static int rtw89_pci_lv1rst_start_dma(struct rtw89_dev *rtwdev) ++{ ++ u32 ret; ++ ++ rtw89_pci_ctrl_hci_dma_en(rtwdev, MAC_AX_FUNC_DIS); ++ rtw89_pci_ctrl_hci_dma_en(rtwdev, MAC_AX_FUNC_EN); ++ rtw89_pci_clr_idx_all(rtwdev); ++ ++ ret = rtw89_pci_rst_bdram(rtwdev); ++ if (ret) ++ return ret; ++ ++ rtw89_pci_ctrl_dma_all_pcie(rtwdev, MAC_AX_FUNC_EN); ++ return ret; ++} ++ ++static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, ++ enum rtw89_lv1_rcvy_step step) ++{ ++ int ret; ++ ++ switch (step) { ++ case RTW89_LV1_RCVY_STEP_1: ++ ret = rtw89_pci_lv1rst_stop_dma(rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n"); ++ ++ break; ++ ++ case RTW89_LV1_RCVY_STEP_2: ++ ret = rtw89_pci_lv1rst_start_dma(rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n"); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev) ++{ ++ rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX =0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); ++ rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG)); ++ rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", ++ rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG)); ++} ++ ++static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); ++ struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; ++ unsigned long flags; ++ int work_done; ++ ++ rtwdev->napi_budget_countdown = budget; ++ ++ rtw89_pci_clear_isr0(rtwdev, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT); ++ work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); ++ if (work_done == budget) ++ return budget; ++ ++ rtw89_pci_clear_isr0(rtwdev, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT); ++ work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); ++ if (work_done < budget && napi_complete_done(napi, work_done)) { ++ spin_lock_irqsave(&rtwpci->irq_lock, flags); ++ if (likely(rtwpci->running)) ++ rtw89_pci_enable_intr(rtwdev, rtwpci); ++ spin_unlock_irqrestore(&rtwpci->irq_lock, flags); ++ } ++ ++ return work_done; ++} ++ ++static int __maybe_unused rtw89_pci_suspend(struct device *dev) ++{ ++ struct ieee80211_hw *hw = dev_get_drvdata(dev); ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); ++ rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); ++ rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); ++ ++ return 0; ++} ++ ++static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev) ++{ ++ if (rtwdev->chip->chip_id == RTL8852C) ++ return; ++ ++ /* Hardware need write the reg twice to ensure the setting work */ ++ rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_RST_MSTATE, ++ RTW89_PCIE_BIT_CFG_RST_MSTATE); ++ rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_RST_MSTATE, ++ RTW89_PCIE_BIT_CFG_RST_MSTATE); ++} ++ ++static int __maybe_unused rtw89_pci_resume(struct device *dev) ++{ ++ struct ieee80211_hw *hw = dev_get_drvdata(dev); ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, ++ B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); ++ rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); ++ rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); ++ rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, ++ B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); ++ rtw89_pci_l2_hci_ldo(rtwdev); ++ rtw89_pci_link_cfg(rtwdev); ++ rtw89_pci_l1ss_cfg(rtwdev); ++ ++ return 0; ++} ++ ++SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume); ++EXPORT_SYMBOL(rtw89_pm_ops); ++ ++static const struct rtw89_hci_ops rtw89_pci_ops = { ++ .tx_write = rtw89_pci_ops_tx_write, ++ .tx_kick_off = rtw89_pci_ops_tx_kick_off, ++ .flush_queues = rtw89_pci_ops_flush_queues, ++ .reset = rtw89_pci_ops_reset, ++ .start = rtw89_pci_ops_start, ++ .stop = rtw89_pci_ops_stop, ++ .recalc_int_mit = rtw89_pci_recalc_int_mit, ++ ++ .read8 = rtw89_pci_ops_read8, ++ .read16 = rtw89_pci_ops_read16, ++ .read32 = rtw89_pci_ops_read32, ++ .write8 = rtw89_pci_ops_write8, ++ .write16 = rtw89_pci_ops_write16, ++ .write32 = rtw89_pci_ops_write32, ++ ++ .mac_pre_init = rtw89_pci_ops_mac_pre_init, ++ .mac_post_init = rtw89_pci_ops_mac_post_init, ++ .deinit = rtw89_pci_ops_deinit, ++ ++ .check_and_reclaim_tx_resource = rtw89_pci_check_and_reclaim_tx_resource, ++ .mac_lv1_rcvy = rtw89_pci_ops_mac_lv1_recovery, ++ .dump_err_status = rtw89_pci_ops_dump_err_status, ++ .napi_poll = rtw89_pci_napi_poll, ++}; ++ ++static int rtw89_pci_probe(struct pci_dev *pdev, ++ const struct pci_device_id *id) ++{ ++ struct ieee80211_hw *hw; ++ struct rtw89_dev *rtwdev; ++ int driver_data_size; ++ int ret; ++ ++ driver_data_size = sizeof(struct rtw89_dev) + sizeof(struct rtw89_pci); ++ hw = ieee80211_alloc_hw(driver_data_size, &rtw89_ops); ++ if (!hw) { ++ dev_err(&pdev->dev, "failed to allocate hw\n"); ++ return -ENOMEM; ++ } ++ ++ rtwdev = hw->priv; ++ rtwdev->hw = hw; ++ rtwdev->dev = &pdev->dev; ++ rtwdev->hci.ops = &rtw89_pci_ops; ++ rtwdev->hci.type = RTW89_HCI_TYPE_PCIE; ++ rtwdev->hci.rpwm_addr = R_AX_PCIE_HRPWM; ++ rtwdev->hci.cpwm_addr = R_AX_CPWM; ++ ++ SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); ++ ++ switch (id->driver_data) { ++ case RTL8852A: ++ rtwdev->chip = &rtw8852a_chip_info; ++ break; ++ default: ++ return -ENOENT; ++ } ++ ++ ret = rtw89_core_init(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to initialise core\n"); ++ goto err_release_hw; ++ } ++ ++ ret = rtw89_pci_claim_device(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to claim pci device\n"); ++ goto err_core_deinit; ++ } ++ ++ ret = rtw89_pci_setup_resource(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to setup pci resource\n"); ++ goto err_declaim_pci; ++ } ++ ++ ret = rtw89_chip_info_setup(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to setup chip information\n"); ++ goto err_clear_resource; ++ } ++ ++ rtw89_pci_link_cfg(rtwdev); ++ rtw89_pci_l1ss_cfg(rtwdev); ++ ++ ret = rtw89_core_register(rtwdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to register core\n"); ++ goto err_clear_resource; ++ } ++ ++ rtw89_core_napi_init(rtwdev); ++ ++ ret = rtw89_pci_request_irq(rtwdev, pdev); ++ if (ret) { ++ rtw89_err(rtwdev, "failed to request pci irq\n"); ++ goto err_unregister; ++ } ++ ++ return 0; ++ ++err_unregister: ++ rtw89_core_napi_deinit(rtwdev); ++ rtw89_core_unregister(rtwdev); ++err_clear_resource: ++ rtw89_pci_clear_resource(rtwdev, pdev); ++err_declaim_pci: ++ rtw89_pci_declaim_device(rtwdev, pdev); ++err_core_deinit: ++ rtw89_core_deinit(rtwdev); ++err_release_hw: ++ ieee80211_free_hw(hw); ++ ++ return ret; ++} ++ ++static void rtw89_pci_remove(struct pci_dev *pdev) ++{ ++ struct ieee80211_hw *hw = pci_get_drvdata(pdev); ++ struct rtw89_dev *rtwdev; ++ ++ rtwdev = hw->priv; ++ ++ rtw89_pci_free_irq(rtwdev, pdev); ++ rtw89_core_napi_deinit(rtwdev); ++ rtw89_core_unregister(rtwdev); ++ rtw89_pci_clear_resource(rtwdev, pdev); ++ rtw89_pci_declaim_device(rtwdev, pdev); ++ rtw89_core_deinit(rtwdev); ++ ieee80211_free_hw(hw); ++} ++ ++static const struct pci_device_id rtw89_pci_id_table[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8852), .driver_data = RTL8852A }, ++ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xa85a), .driver_data = RTL8852A }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(pci, rtw89_pci_id_table); ++ ++static struct pci_driver rtw89_pci_driver = { ++ .name = "rtw89_pci", ++ .id_table = rtw89_pci_id_table, ++ .probe = rtw89_pci_probe, ++ .remove = rtw89_pci_remove, ++ .driver.pm = &rtw89_pm_ops, ++}; ++module_pci_driver(rtw89_pci_driver); ++ ++MODULE_AUTHOR("Realtek Corporation"); ++MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); ++MODULE_LICENSE("Dual BSD/GPL"); +diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h +new file mode 100644 +index 000000000000..34333c441aea +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/pci.h +@@ -0,0 +1,635 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_PCI_H__ ++#define __RTW89_PCI_H__ ++ ++#include "txrx.h" ++ ++#define MDIO_PG0_G1 0 ++#define MDIO_PG1_G1 1 ++#define MDIO_PG0_G2 2 ++#define MDIO_PG1_G2 3 ++#define RAC_ANA10 0x10 ++#define RAC_ANA19 0x19 ++#define RAC_ANA1F 0x1F ++#define RAC_ANA24 0x24 ++#define B_AX_DEGLITCH GENMASK(11, 8) ++#define RAC_ANA26 0x26 ++#define B_AX_RXEN GENMASK(15, 14) ++#define RAC_CTRL_PPR_V1 0x30 ++#define B_AX_CLK_CALIB_EN BIT(12) ++#define B_AX_CALIB_EN BIT(13) ++#define B_AX_DIV GENMASK(15, 14) ++#define RAC_SET_PPR_V1 0x31 ++ ++#define R_AX_DBI_FLAG 0x1090 ++#define B_AX_DBI_RFLAG BIT(17) ++#define B_AX_DBI_WFLAG BIT(16) ++#define B_AX_DBI_WREN_MSK GENMASK(15, 12) ++#define B_AX_DBI_ADDR_MSK GENMASK(11, 2) ++#define R_AX_DBI_WDATA 0x1094 ++#define R_AX_DBI_RDATA 0x1098 ++ ++#define R_AX_MDIO_WDATA 0x10A4 ++#define R_AX_MDIO_RDATA 0x10A6 ++ ++#define RTW89_PCI_WR_RETRY_CNT 20 ++ ++/* Interrupts */ ++#define R_AX_HIMR0 0x01A0 ++#define B_AX_HALT_C2H_INT_EN BIT(21) ++#define R_AX_HISR0 0x01A4 ++ ++#define R_AX_MDIO_CFG 0x10A0 ++#define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12) ++#define B_AX_MDIO_RFLAG BIT(9) ++#define B_AX_MDIO_WFLAG BIT(8) ++#define B_AX_MDIO_ADDR_MASK GENMASK(4, 0) ++ ++#define R_AX_PCIE_HIMR00 0x10B0 ++#define B_AX_HC00ISR_IND_INT_EN BIT(27) ++#define B_AX_HD1ISR_IND_INT_EN BIT(26) ++#define B_AX_HD0ISR_IND_INT_EN BIT(25) ++#define B_AX_HS0ISR_IND_INT_EN BIT(24) ++#define B_AX_RETRAIN_INT_EN BIT(21) ++#define B_AX_RPQBD_FULL_INT_EN BIT(20) ++#define B_AX_RDU_INT_EN BIT(19) ++#define B_AX_RXDMA_STUCK_INT_EN BIT(18) ++#define B_AX_TXDMA_STUCK_INT_EN BIT(17) ++#define B_AX_PCIE_HOTRST_INT_EN BIT(16) ++#define B_AX_PCIE_FLR_INT_EN BIT(15) ++#define B_AX_PCIE_PERST_INT_EN BIT(14) ++#define B_AX_TXDMA_CH12_INT_EN BIT(13) ++#define B_AX_TXDMA_CH9_INT_EN BIT(12) ++#define B_AX_TXDMA_CH8_INT_EN BIT(11) ++#define B_AX_TXDMA_ACH7_INT_EN BIT(10) ++#define B_AX_TXDMA_ACH6_INT_EN BIT(9) ++#define B_AX_TXDMA_ACH5_INT_EN BIT(8) ++#define B_AX_TXDMA_ACH4_INT_EN BIT(7) ++#define B_AX_TXDMA_ACH3_INT_EN BIT(6) ++#define B_AX_TXDMA_ACH2_INT_EN BIT(5) ++#define B_AX_TXDMA_ACH1_INT_EN BIT(4) ++#define B_AX_TXDMA_ACH0_INT_EN BIT(3) ++#define B_AX_RPQDMA_INT_EN BIT(2) ++#define B_AX_RXP1DMA_INT_EN BIT(1) ++#define B_AX_RXDMA_INT_EN BIT(0) ++ ++#define R_AX_PCIE_HISR00 0x10B4 ++#define B_AX_HC00ISR_IND_INT BIT(27) ++#define B_AX_HD1ISR_IND_INT BIT(26) ++#define B_AX_HD0ISR_IND_INT BIT(25) ++#define B_AX_HS0ISR_IND_INT BIT(24) ++#define B_AX_RETRAIN_INT BIT(21) ++#define B_AX_RPQBD_FULL_INT BIT(20) ++#define B_AX_RDU_INT BIT(19) ++#define B_AX_RXDMA_STUCK_INT BIT(18) ++#define B_AX_TXDMA_STUCK_INT BIT(17) ++#define B_AX_PCIE_HOTRST_INT BIT(16) ++#define B_AX_PCIE_FLR_INT BIT(15) ++#define B_AX_PCIE_PERST_INT BIT(14) ++#define B_AX_TXDMA_CH12_INT BIT(13) ++#define B_AX_TXDMA_CH9_INT BIT(12) ++#define B_AX_TXDMA_CH8_INT BIT(11) ++#define B_AX_TXDMA_ACH7_INT BIT(10) ++#define B_AX_TXDMA_ACH6_INT BIT(9) ++#define B_AX_TXDMA_ACH5_INT BIT(8) ++#define B_AX_TXDMA_ACH4_INT BIT(7) ++#define B_AX_TXDMA_ACH3_INT BIT(6) ++#define B_AX_TXDMA_ACH2_INT BIT(5) ++#define B_AX_TXDMA_ACH1_INT BIT(4) ++#define B_AX_TXDMA_ACH0_INT BIT(3) ++#define B_AX_RPQDMA_INT BIT(2) ++#define B_AX_RXP1DMA_INT BIT(1) ++#define B_AX_RXDMA_INT BIT(0) ++ ++#define R_AX_PCIE_HIMR10 0x13B0 ++#define B_AX_HC10ISR_IND_INT_EN BIT(28) ++#define B_AX_TXDMA_CH11_INT_EN BIT(12) ++#define B_AX_TXDMA_CH10_INT_EN BIT(11) ++ ++#define R_AX_PCIE_HISR10 0x13B4 ++#define B_AX_HC10ISR_IND_INT BIT(28) ++#define B_AX_TXDMA_CH11_INT BIT(12) ++#define B_AX_TXDMA_CH10_INT BIT(11) ++ ++/* TX/RX */ ++#define R_AX_RXQ_RXBD_IDX 0x1050 ++#define R_AX_RPQ_RXBD_IDX 0x1054 ++#define R_AX_ACH0_TXBD_IDX 0x1058 ++#define R_AX_ACH1_TXBD_IDX 0x105C ++#define R_AX_ACH2_TXBD_IDX 0x1060 ++#define R_AX_ACH3_TXBD_IDX 0x1064 ++#define R_AX_ACH4_TXBD_IDX 0x1068 ++#define R_AX_ACH5_TXBD_IDX 0x106C ++#define R_AX_ACH6_TXBD_IDX 0x1070 ++#define R_AX_ACH7_TXBD_IDX 0x1074 ++#define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */ ++#define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */ ++#define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */ ++#define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */ ++#define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */ ++#define TXBD_HW_IDX_MASK GENMASK(27, 16) ++#define TXBD_HOST_IDX_MASK GENMASK(11, 0) ++ ++#define R_AX_ACH0_TXBD_DESA_L 0x1110 ++#define R_AX_ACH0_TXBD_DESA_H 0x1114 ++#define R_AX_ACH1_TXBD_DESA_L 0x1118 ++#define R_AX_ACH1_TXBD_DESA_H 0x111C ++#define R_AX_ACH2_TXBD_DESA_L 0x1120 ++#define R_AX_ACH2_TXBD_DESA_H 0x1124 ++#define R_AX_ACH3_TXBD_DESA_L 0x1128 ++#define R_AX_ACH3_TXBD_DESA_H 0x112C ++#define R_AX_ACH4_TXBD_DESA_L 0x1130 ++#define R_AX_ACH4_TXBD_DESA_H 0x1134 ++#define R_AX_ACH5_TXBD_DESA_L 0x1138 ++#define R_AX_ACH5_TXBD_DESA_H 0x113C ++#define R_AX_ACH6_TXBD_DESA_L 0x1140 ++#define R_AX_ACH6_TXBD_DESA_H 0x1144 ++#define R_AX_ACH7_TXBD_DESA_L 0x1148 ++#define R_AX_ACH7_TXBD_DESA_H 0x114C ++#define R_AX_CH8_TXBD_DESA_L 0x1150 ++#define R_AX_CH8_TXBD_DESA_H 0x1154 ++#define R_AX_CH9_TXBD_DESA_L 0x1158 ++#define R_AX_CH9_TXBD_DESA_H 0x115C ++#define R_AX_CH10_TXBD_DESA_L 0x1358 ++#define R_AX_CH10_TXBD_DESA_H 0x135C ++#define R_AX_CH11_TXBD_DESA_L 0x1360 ++#define R_AX_CH11_TXBD_DESA_H 0x1364 ++#define R_AX_CH12_TXBD_DESA_L 0x1160 ++#define R_AX_CH12_TXBD_DESA_H 0x1164 ++#define R_AX_RXQ_RXBD_DESA_L 0x1100 ++#define R_AX_RXQ_RXBD_DESA_H 0x1104 ++#define R_AX_RPQ_RXBD_DESA_L 0x1108 ++#define R_AX_RPQ_RXBD_DESA_H 0x110C ++#define B_AX_DESC_NUM_MSK GENMASK(11, 0) ++ ++#define R_AX_RXQ_RXBD_NUM 0x1020 ++#define R_AX_RPQ_RXBD_NUM 0x1022 ++#define R_AX_ACH0_TXBD_NUM 0x1024 ++#define R_AX_ACH1_TXBD_NUM 0x1026 ++#define R_AX_ACH2_TXBD_NUM 0x1028 ++#define R_AX_ACH3_TXBD_NUM 0x102A ++#define R_AX_ACH4_TXBD_NUM 0x102C ++#define R_AX_ACH5_TXBD_NUM 0x102E ++#define R_AX_ACH6_TXBD_NUM 0x1030 ++#define R_AX_ACH7_TXBD_NUM 0x1032 ++#define R_AX_CH8_TXBD_NUM 0x1034 ++#define R_AX_CH9_TXBD_NUM 0x1036 ++#define R_AX_CH10_TXBD_NUM 0x1338 ++#define R_AX_CH11_TXBD_NUM 0x133A ++#define R_AX_CH12_TXBD_NUM 0x1038 ++ ++#define R_AX_ACH0_BDRAM_CTRL 0x1200 ++#define R_AX_ACH1_BDRAM_CTRL 0x1204 ++#define R_AX_ACH2_BDRAM_CTRL 0x1208 ++#define R_AX_ACH3_BDRAM_CTRL 0x120C ++#define R_AX_ACH4_BDRAM_CTRL 0x1210 ++#define R_AX_ACH5_BDRAM_CTRL 0x1214 ++#define R_AX_ACH6_BDRAM_CTRL 0x1218 ++#define R_AX_ACH7_BDRAM_CTRL 0x121C ++#define R_AX_CH8_BDRAM_CTRL 0x1220 ++#define R_AX_CH9_BDRAM_CTRL 0x1224 ++#define R_AX_CH10_BDRAM_CTRL 0x1320 ++#define R_AX_CH11_BDRAM_CTRL 0x1324 ++#define R_AX_CH12_BDRAM_CTRL 0x1228 ++#define BDRAM_SIDX_MASK GENMASK(7, 0) ++#define BDRAM_MAX_MASK GENMASK(15, 8) ++#define BDRAM_MIN_MASK GENMASK(23, 16) ++ ++#define R_AX_PCIE_INIT_CFG1 0x1000 ++#define B_AX_PCIE_RXRST_KEEP_REG BIT(23) ++#define B_AX_PCIE_TXRST_KEEP_REG BIT(22) ++#define B_AX_PCIE_PERST_KEEP_REG BIT(21) ++#define B_AX_PCIE_FLR_KEEP_REG BIT(20) ++#define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) ++#define B_AX_RXBD_MODE BIT(18) ++#define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14) ++#define B_AX_RXHCI_EN BIT(13) ++#define B_AX_LATENCY_CONTROL BIT(12) ++#define B_AX_TXHCI_EN BIT(11) ++#define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8) ++#define B_AX_TX_TRUNC_MODE BIT(5) ++#define B_AX_RX_TRUNC_MODE BIT(4) ++#define B_AX_RST_BDRAM BIT(3) ++#define B_AX_DIS_RXDMA_PRE BIT(2) ++ ++#define R_AX_TXDMA_ADDR_H 0x10F0 ++#define R_AX_RXDMA_ADDR_H 0x10F4 ++ ++#define R_AX_PCIE_DMA_STOP1 0x1010 ++#define B_AX_STOP_PCIEIO BIT(20) ++#define B_AX_STOP_WPDMA BIT(19) ++#define B_AX_STOP_CH12 BIT(18) ++#define B_AX_STOP_CH9 BIT(17) ++#define B_AX_STOP_CH8 BIT(16) ++#define B_AX_STOP_ACH7 BIT(15) ++#define B_AX_STOP_ACH6 BIT(14) ++#define B_AX_STOP_ACH5 BIT(13) ++#define B_AX_STOP_ACH4 BIT(12) ++#define B_AX_STOP_ACH3 BIT(11) ++#define B_AX_STOP_ACH2 BIT(10) ++#define B_AX_STOP_ACH1 BIT(9) ++#define B_AX_STOP_ACH0 BIT(8) ++#define B_AX_STOP_RPQ BIT(1) ++#define B_AX_STOP_RXQ BIT(0) ++#define B_AX_TX_STOP1_ALL GENMASK(18, 8) ++ ++#define R_AX_PCIE_DMA_STOP2 0x1310 ++#define B_AX_STOP_CH11 BIT(1) ++#define B_AX_STOP_CH10 BIT(0) ++#define B_AX_TX_STOP2_ALL GENMASK(1, 0) ++ ++#define R_AX_TXBD_RWPTR_CLR1 0x1014 ++#define B_AX_CLR_CH12_IDX BIT(10) ++#define B_AX_CLR_CH9_IDX BIT(9) ++#define B_AX_CLR_CH8_IDX BIT(8) ++#define B_AX_CLR_ACH7_IDX BIT(7) ++#define B_AX_CLR_ACH6_IDX BIT(6) ++#define B_AX_CLR_ACH5_IDX BIT(5) ++#define B_AX_CLR_ACH4_IDX BIT(4) ++#define B_AX_CLR_ACH3_IDX BIT(3) ++#define B_AX_CLR_ACH2_IDX BIT(2) ++#define B_AX_CLR_ACH1_IDX BIT(1) ++#define B_AX_CLR_ACH0_IDX BIT(0) ++#define B_AX_TXBD_CLR1_ALL GENMASK(10, 0) ++ ++#define R_AX_RXBD_RWPTR_CLR 0x1018 ++#define B_AX_CLR_RPQ_IDX BIT(1) ++#define B_AX_CLR_RXQ_IDX BIT(0) ++#define B_AX_RXBD_CLR_ALL GENMASK(1, 0) ++ ++#define R_AX_TXBD_RWPTR_CLR2 0x1314 ++#define B_AX_CLR_CH11_IDX BIT(1) ++#define B_AX_CLR_CH10_IDX BIT(0) ++#define B_AX_TXBD_CLR2_ALL GENMASK(1, 0) ++ ++#define R_AX_PCIE_DMA_BUSY1 0x101C ++#define B_AX_PCIEIO_RX_BUSY BIT(22) ++#define B_AX_PCIEIO_TX_BUSY BIT(21) ++#define B_AX_PCIEIO_BUSY BIT(20) ++#define B_AX_WPDMA_BUSY BIT(19) ++ ++#define R_AX_PCIE_DMA_BUSY2 0x131C ++#define B_AX_CH11_BUSY BIT(1) ++#define B_AX_CH10_BUSY BIT(0) ++ ++/* Configure */ ++#define R_AX_PCIE_INIT_CFG1 0x1000 ++#define B_AX_PCIE_RXRST_KEEP_REG BIT(23) ++#define B_AX_PCIE_TXRST_KEEP_REG BIT(22) ++#define B_AX_DIS_RXDMA_PRE BIT(2) ++ ++#define R_AX_PCIE_INIT_CFG2 0x1004 ++#define B_AX_WD_ITVL_IDLE GENMASK(27, 24) ++#define B_AX_WD_ITVL_ACT GENMASK(19, 16) ++ ++#define R_AX_PCIE_PS_CTRL 0x1008 ++#define B_AX_L1OFF_PWR_OFF_EN BIT(5) ++ ++#define R_AX_INT_MIT_RX 0x10D4 ++#define B_AX_RXMIT_RXP2_SEL BIT(19) ++#define B_AX_RXMIT_RXP1_SEL BIT(18) ++#define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16) ++#define AX_RXTIMER_UNIT_64US 0 ++#define AX_RXTIMER_UNIT_128US 1 ++#define AX_RXTIMER_UNIT_256US 2 ++#define AX_RXTIMER_UNIT_512US 3 ++#define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8) ++#define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0) ++ ++#define R_AX_DBG_ERR_FLAG 0x11C4 ++#define B_AX_PCIE_RPQ_FULL BIT(29) ++#define B_AX_PCIE_RXQ_FULL BIT(28) ++#define B_AX_CPL_STATUS_MASK GENMASK(27, 25) ++#define B_AX_RX_STUCK BIT(22) ++#define B_AX_TX_STUCK BIT(21) ++#define B_AX_PCIEDBG_TXERR0 BIT(16) ++#define B_AX_PCIE_RXP1_ERR0 BIT(4) ++#define B_AX_PCIE_TXBD_LEN0 BIT(1) ++#define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0) ++ ++#define R_AX_LBC_WATCHDOG 0x11D8 ++#define B_AX_LBC_TIMER GENMASK(7, 4) ++#define B_AX_LBC_FLAG BIT(1) ++#define B_AX_LBC_EN BIT(0) ++ ++#define R_AX_PCIE_EXP_CTRL 0x13F0 ++#define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20) ++#define B_AX_MAX_TAG_NUM GENMASK(18, 16) ++#define B_AX_SIC_EN_FORCE_CLKREQ BIT(4) ++ ++#define R_AX_PCIE_RX_PREF_ADV 0x13F4 ++#define B_AX_RXDMA_PREF_ADV_EN BIT(0) ++ ++#define RTW89_PCI_TXBD_NUM_MAX 256 ++#define RTW89_PCI_RXBD_NUM_MAX 256 ++#define RTW89_PCI_TXWD_NUM_MAX 512 ++#define RTW89_PCI_TXWD_PAGE_SIZE 128 ++#define RTW89_PCI_ADDRINFO_MAX 4 ++#define RTW89_PCI_RX_BUF_SIZE 11460 ++ ++#define RTW89_PCI_POLL_BDRAM_RST_CNT 100 ++#define RTW89_PCI_MULTITAG 8 ++ ++/* PCIE CFG register */ ++#define RTW89_PCIE_ASPM_CTRL 0x070F ++#define RTW89_L1DLY_MASK GENMASK(5, 3) ++#define RTW89_L0DLY_MASK GENMASK(2, 0) ++#define RTW89_PCIE_TIMER_CTRL 0x0718 ++#define RTW89_PCIE_BIT_L1SUB BIT(5) ++#define RTW89_PCIE_L1_CTRL 0x0719 ++#define RTW89_PCIE_BIT_CLK BIT(4) ++#define RTW89_PCIE_BIT_L1 BIT(3) ++#define RTW89_PCIE_CLK_CTRL 0x0725 ++#define RTW89_PCIE_RST_MSTATE 0x0B48 ++#define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0) ++#define RTW89_PCIE_PHY_RATE 0x82 ++#define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0) ++#define INTF_INTGRA_MINREF_V1 90 ++#define INTF_INTGRA_HOSTREF_V1 100 ++ ++enum rtw89_pcie_phy { ++ PCIE_PHY_GEN1, ++ PCIE_PHY_GEN2, ++ PCIE_PHY_GEN1_UNDEFINE = 0x7F, ++}; ++ ++enum mac_ax_func_sw { ++ MAC_AX_FUNC_DIS, ++ MAC_AX_FUNC_EN, ++}; ++ ++enum rtw89_pcie_l0sdly { ++ PCIE_L0SDLY_1US = 0, ++ PCIE_L0SDLY_2US = 1, ++ PCIE_L0SDLY_3US = 2, ++ PCIE_L0SDLY_4US = 3, ++ PCIE_L0SDLY_5US = 4, ++ PCIE_L0SDLY_6US = 5, ++ PCIE_L0SDLY_7US = 6, ++}; ++ ++enum rtw89_pcie_l1dly { ++ PCIE_L1DLY_16US = 4, ++ PCIE_L1DLY_32US = 5, ++ PCIE_L1DLY_64US = 6, ++ PCIE_L1DLY_HW_INFI = 7, ++}; ++ ++enum rtw89_pcie_clkdly_hw { ++ PCIE_CLKDLY_HW_0 = 0, ++ PCIE_CLKDLY_HW_30US = 0x1, ++ PCIE_CLKDLY_HW_50US = 0x2, ++ PCIE_CLKDLY_HW_100US = 0x3, ++ PCIE_CLKDLY_HW_150US = 0x4, ++ PCIE_CLKDLY_HW_200US = 0x5, ++}; ++ ++struct rtw89_pci_bd_ram { ++ u8 start_idx; ++ u8 max_num; ++ u8 min_num; ++}; ++ ++struct rtw89_pci_tx_data { ++ dma_addr_t dma; ++}; ++ ++struct rtw89_pci_rx_info { ++ dma_addr_t dma; ++ u32 fs:1, ls:1, tag:11, len:14; ++}; ++ ++#define RTW89_PCI_TXBD_OPTION_LS BIT(14) ++ ++struct rtw89_pci_tx_bd_32 { ++ __le16 length; ++ __le16 option; ++ __le32 dma; ++} __packed; ++ ++#define RTW89_PCI_TXWP_VALID BIT(15) ++ ++struct rtw89_pci_tx_wp_info { ++ __le16 seq0; ++ __le16 seq1; ++ __le16 seq2; ++ __le16 seq3; ++} __packed; ++ ++#define RTW89_PCI_ADDR_MSDU_LS BIT(15) ++#define RTW89_PCI_ADDR_LS BIT(14) ++#define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6)) ++#define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0)) ++ ++struct rtw89_pci_tx_addr_info_32 { ++ __le16 length; ++ __le16 option; ++ __le32 dma; ++} __packed; ++ ++#define RTW89_PCI_RPP_POLLUTED BIT(31) ++#define RTW89_PCI_RPP_SEQ GENMASK(30, 16) ++#define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13) ++#define RTW89_TX_DONE 0x0 ++#define RTW89_TX_RETRY_LIMIT 0x1 ++#define RTW89_TX_LIFE_TIME 0x2 ++#define RTW89_TX_MACID_DROP 0x3 ++#define RTW89_PCI_RPP_QSEL GENMASK(12, 8) ++#define RTW89_PCI_RPP_MACID GENMASK(7, 0) ++ ++struct rtw89_pci_rpp_fmt { ++ __le32 dword; ++} __packed; ++ ++struct rtw89_pci_rx_bd_32 { ++ __le16 buf_size; ++ __le16 rsvd; ++ __le32 dma; ++} __packed; ++ ++#define RTW89_PCI_RXBD_FS BIT(15) ++#define RTW89_PCI_RXBD_LS BIT(14) ++#define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0) ++#define RTW89_PCI_RXBD_TAG GENMASK(28, 16) ++ ++struct rtw89_pci_rxbd_info { ++ __le32 dword; ++}; ++ ++struct rtw89_pci_tx_wd { ++ struct list_head list; ++ struct sk_buff_head queue; ++ ++ void *vaddr; ++ dma_addr_t paddr; ++ u32 len; ++ u32 seq; ++}; ++ ++struct rtw89_pci_dma_ring { ++ void *head; ++ u8 desc_size; ++ dma_addr_t dma; ++ ++ u32 addr_num; ++ u32 addr_idx; ++ u32 addr_bdram; ++ u32 addr_desa_l; ++ u32 addr_desa_h; ++ ++ u32 len; ++ u32 wp; /* host idx */ ++ u32 rp; /* hw idx */ ++}; ++ ++struct rtw89_pci_tx_wd_ring { ++ void *head; ++ dma_addr_t dma; ++ ++ struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX]; ++ struct list_head free_pages; ++ ++ u32 page_size; ++ u32 page_num; ++ u32 curr_num; ++}; ++ ++#define RTW89_RX_TAG_MAX 0x1fff ++ ++struct rtw89_pci_tx_ring { ++ struct rtw89_pci_tx_wd_ring wd_ring; ++ struct rtw89_pci_dma_ring bd_ring; ++ struct list_head busy_pages; ++ u8 txch; ++ bool dma_enabled; ++ u16 tag; /* range from 0x0001 ~ 0x1fff */ ++ ++ u64 tx_cnt; ++ u64 tx_acked; ++ u64 tx_retry_lmt; ++ u64 tx_life_time; ++ u64 tx_mac_id_drop; ++}; ++ ++struct rtw89_pci_rx_ring { ++ struct rtw89_pci_dma_ring bd_ring; ++ struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX]; ++ u32 buf_sz; ++ struct sk_buff *diliver_skb; ++ struct rtw89_rx_desc_info diliver_desc; ++}; ++ ++struct rtw89_pci_isrs { ++ u32 halt_c2h_isrs; ++ u32 isrs[2]; ++}; ++ ++struct rtw89_pci { ++ struct pci_dev *pdev; ++ ++ /* protect HW irq related registers */ ++ spinlock_t irq_lock; ++ /* protect TRX resources (exclude RXQ) */ ++ spinlock_t trx_lock; ++ bool running; ++ struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM]; ++ struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM]; ++ struct sk_buff_head h2c_queue; ++ struct sk_buff_head h2c_release_queue; ++ ++ u32 halt_c2h_intrs; ++ u32 intrs[2]; ++ void __iomem *mmap; ++}; ++ ++static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ ++ BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) > ++ sizeof(info->status.status_driver_data)); ++ ++ return (struct rtw89_pci_rx_info *)skb->cb; ++} ++ ++static inline struct rtw89_pci_rx_bd_32 * ++RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ u8 *head = bd_ring->head; ++ u32 desc_size = bd_ring->desc_size; ++ u32 offset = idx * desc_size; ++ ++ return (struct rtw89_pci_rx_bd_32 *)(head + offset); ++} ++ ++static inline void ++rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; ++ ++ bd_ring->wp += cnt; ++ ++ if (bd_ring->wp >= bd_ring->len) ++ bd_ring->wp -= bd_ring->len; ++} ++ ++static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ ++ return (struct rtw89_pci_tx_data *)info->status.status_driver_data; ++} ++ ++static inline struct rtw89_pci_tx_bd_32 * ++rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; ++ struct rtw89_pci_tx_bd_32 *tx_bd, *head; ++ ++ head = bd_ring->head; ++ tx_bd = head + bd_ring->wp; ++ ++ return tx_bd; ++} ++ ++static inline struct rtw89_pci_tx_wd * ++rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ struct rtw89_pci_tx_wd *txwd; ++ ++ txwd = list_first_entry_or_null(&wd_ring->free_pages, ++ struct rtw89_pci_tx_wd, list); ++ if (!txwd) ++ return NULL; ++ ++ list_del_init(&txwd->list); ++ txwd->len = 0; ++ wd_ring->curr_num--; ++ ++ return txwd; ++} ++ ++static inline void ++rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring, ++ struct rtw89_pci_tx_wd *txwd) ++{ ++ struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; ++ ++ memset(txwd->vaddr, 0, wd_ring->page_size); ++ list_add_tail(&txwd->list, &wd_ring->free_pages); ++ wd_ring->curr_num++; ++} ++ ++static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) ++{ ++ return val == 0xffffffff || val == 0xeaeaeaea; ++} ++ ++extern const struct dev_pm_ops rtw89_pm_ops; ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +new file mode 100644 +index 000000000000..53c36cc82c57 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -0,0 +1,2868 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "fw.h" ++#include "phy.h" ++#include "ps.h" ++#include "reg.h" ++#include "sar.h" ++#include "coex.h" ++ ++static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, ++ const struct rtw89_ra_report *report) ++{ ++ const struct rate_info *txrate = &report->txrate; ++ u32 bit_rate = report->bit_rate; ++ u8 mcs; ++ ++ /* lower than ofdm, do not aggregate */ ++ if (bit_rate < 550) ++ return 1; ++ ++ /* prevent hardware rate fallback to G mode rate */ ++ if (txrate->flags & RATE_INFO_FLAGS_MCS) ++ mcs = txrate->mcs & 0x07; ++ else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS)) ++ mcs = txrate->mcs; ++ else ++ mcs = 0; ++ ++ if (mcs <= 2) ++ return 1; ++ ++ /* lower than 20M vht 2ss mcs8, make it small */ ++ if (bit_rate < 1800) ++ return 1200; ++ ++ /* lower than 40M vht 2ss mcs9, make it medium */ ++ if (bit_rate < 4000) ++ return 2600; ++ ++ /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ ++ if (bit_rate < 7000) ++ return 3500; ++ ++ return rtwdev->chip->max_amsdu_limit; ++} ++ ++static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) ++{ ++ u64 ra_mask = 0; ++ u8 mcs_cap; ++ int i, nss; ++ ++ for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { ++ mcs_cap = mcs_map & 0x3; ++ switch (mcs_cap) { ++ case 2: ++ ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; ++ break; ++ case 1: ++ ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; ++ break; ++ case 0: ++ ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return ra_mask; ++} ++ ++static u64 get_he_ra_mask(struct ieee80211_sta *sta) ++{ ++ struct ieee80211_sta_he_cap cap = sta->he_cap; ++ u16 mcs_map; ++ ++ switch (sta->bandwidth) { ++ case IEEE80211_STA_RX_BW_160: ++ if (cap.he_cap_elem.phy_cap_info[0] & ++ IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) ++ mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); ++ else ++ mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); ++ break; ++ default: ++ mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); ++ } ++ ++ /* MCS11, MCS9, MCS7 */ ++ return get_mcs_ra_mask(mcs_map, 11, 2); ++} ++ ++#define RA_FLOOR_TABLE_SIZE 7 ++#define RA_FLOOR_UP_GAP 3 ++static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, ++ u8 ratr_state) ++{ ++ u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; ++ u8 rssi_lv = 0; ++ u8 i; ++ ++ rssi >>= 1; ++ for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { ++ if (i >= ratr_state) ++ rssi_lv_t[i] += RA_FLOOR_UP_GAP; ++ if (rssi < rssi_lv_t[i]) { ++ rssi_lv = i; ++ break; ++ } ++ } ++ if (rssi_lv == 0) ++ return 0xffffffffffffffffULL; ++ else if (rssi_lv == 1) ++ return 0xfffffffffffffff0ULL; ++ else if (rssi_lv == 2) ++ return 0xffffffffffffffe0ULL; ++ else if (rssi_lv == 3) ++ return 0xffffffffffffffc0ULL; ++ else if (rssi_lv == 4) ++ return 0xffffffffffffff80ULL; ++ else if (rssi_lv >= 5) ++ return 0xffffffffffffff00ULL; ++ ++ return 0xffffffffffffffffULL; ++} ++ ++static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) ++{ ++ struct rtw89_hal *hal = &rtwdev->hal; ++ struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); ++ struct cfg80211_bitrate_mask *mask = &rtwsta->mask; ++ enum nl80211_band band; ++ u64 cfg_mask; ++ ++ if (!rtwsta->use_cfg_mask) ++ return -1; ++ ++ switch (hal->current_band_type) { ++ case RTW89_BAND_2G: ++ band = NL80211_BAND_2GHZ; ++ cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, ++ RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); ++ break; ++ case RTW89_BAND_5G: ++ band = NL80211_BAND_5GHZ; ++ cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, ++ RA_MASK_OFDM_RATES); ++ break; ++ default: ++ rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type); ++ return -1; ++ } ++ ++ if (sta->he_cap.has_he) { ++ cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], ++ RA_MASK_HE_1SS_RATES); ++ cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], ++ RA_MASK_HE_2SS_RATES); ++ } else if (sta->vht_cap.vht_supported) { ++ cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], ++ RA_MASK_VHT_1SS_RATES); ++ cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], ++ RA_MASK_VHT_2SS_RATES); ++ } else if (sta->ht_cap.ht_supported) { ++ cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], ++ RA_MASK_HT_1SS_RATES); ++ cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], ++ RA_MASK_HT_2SS_RATES); ++ } ++ ++ return cfg_mask; ++} ++ ++static const u64 ++rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, ++ RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; ++static const u64 ++rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, ++ RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; ++static const u64 ++rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, ++ RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; ++ ++static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, ++ struct ieee80211_sta *sta, bool csi) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_vif *rtwvif = rtwsta->rtwvif; ++ struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; ++ struct rtw89_ra_info *ra = &rtwsta->ra; ++ const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; ++ u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); ++ u64 high_rate_mask = 0; ++ u64 ra_mask = 0; ++ u8 mode = 0; ++ u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; ++ u8 bw_mode = 0; ++ u8 stbc_en = 0; ++ u8 ldpc_en = 0; ++ u8 i; ++ bool sgi = false; ++ ++ memset(ra, 0, sizeof(*ra)); ++ /* Set the ra mask from sta's capability */ ++ if (sta->he_cap.has_he) { ++ mode |= RTW89_RA_MODE_HE; ++ csi_mode = RTW89_RA_RPT_MODE_HE; ++ ra_mask |= get_he_ra_mask(sta); ++ high_rate_masks = rtw89_ra_mask_he_rates; ++ if (sta->he_cap.he_cap_elem.phy_cap_info[2] & ++ IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) ++ stbc_en = 1; ++ if (sta->he_cap.he_cap_elem.phy_cap_info[1] & ++ IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) ++ ldpc_en = 1; ++ } else if (sta->vht_cap.vht_supported) { ++ u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); ++ ++ mode |= RTW89_RA_MODE_VHT; ++ csi_mode = RTW89_RA_RPT_MODE_VHT; ++ /* MCS9, MCS8, MCS7 */ ++ ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); ++ high_rate_masks = rtw89_ra_mask_vht_rates; ++ if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) ++ stbc_en = 1; ++ if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) ++ ldpc_en = 1; ++ } else if (sta->ht_cap.ht_supported) { ++ mode |= RTW89_RA_MODE_HT; ++ csi_mode = RTW89_RA_RPT_MODE_HT; ++ ra_mask |= ((u64)sta->ht_cap.mcs.rx_mask[3] << 48) | ++ ((u64)sta->ht_cap.mcs.rx_mask[2] << 36) | ++ (sta->ht_cap.mcs.rx_mask[1] << 24) | ++ (sta->ht_cap.mcs.rx_mask[0] << 12); ++ high_rate_masks = rtw89_ra_mask_ht_rates; ++ if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) ++ stbc_en = 1; ++ if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) ++ ldpc_en = 1; ++ } ++ ++ if (rtwdev->hal.current_band_type == RTW89_BAND_2G) { ++ if (sta->supp_rates[NL80211_BAND_2GHZ] <= 0xf) ++ mode |= RTW89_RA_MODE_CCK; ++ else ++ mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; ++ } else { ++ mode |= RTW89_RA_MODE_OFDM; ++ } ++ ++ if (mode >= RTW89_RA_MODE_HT) { ++ for (i = 0; i < rtwdev->hal.tx_nss; i++) ++ high_rate_mask |= high_rate_masks[i]; ++ ra_mask &= high_rate_mask; ++ if (mode & RTW89_RA_MODE_OFDM) ++ ra_mask |= RA_MASK_SUBOFDM_RATES; ++ if (mode & RTW89_RA_MODE_CCK) ++ ra_mask |= RA_MASK_SUBCCK_RATES; ++ } else if (mode & RTW89_RA_MODE_OFDM) { ++ if (mode & RTW89_RA_MODE_CCK) ++ ra_mask |= RA_MASK_SUBCCK_RATES; ++ ra_mask |= RA_MASK_OFDM_RATES; ++ } else { ++ ra_mask = RA_MASK_CCK_RATES; ++ } ++ ++ if (mode != RTW89_RA_MODE_CCK) { ++ ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); ++ ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); ++ } ++ ++ switch (sta->bandwidth) { ++ case IEEE80211_STA_RX_BW_80: ++ bw_mode = RTW89_CHANNEL_WIDTH_80; ++ sgi = sta->vht_cap.vht_supported && ++ (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); ++ break; ++ case IEEE80211_STA_RX_BW_40: ++ bw_mode = RTW89_CHANNEL_WIDTH_40; ++ sgi = sta->ht_cap.ht_supported && ++ (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); ++ break; ++ default: ++ bw_mode = RTW89_CHANNEL_WIDTH_20; ++ sgi = sta->ht_cap.ht_supported && ++ (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); ++ break; ++ } ++ ++ if (sta->he_cap.he_cap_elem.phy_cap_info[3] & ++ IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) ++ ra->dcm_cap = 1; ++ ++ if (rate_pattern->enable) { ++ ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); ++ ra_mask &= rate_pattern->ra_mask; ++ mode = rate_pattern->ra_mode; ++ } ++ ++ ra->bw_cap = bw_mode; ++ ra->mode_ctrl = mode; ++ ra->macid = rtwsta->mac_id; ++ ra->stbc_cap = stbc_en; ++ ra->ldpc_cap = ldpc_en; ++ ra->ss_num = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1; ++ ra->en_sgi = sgi; ++ ra->ra_mask = ra_mask; ++ ++ if (!csi) ++ return; ++ ++ ra->fixed_csi_rate_en = false; ++ ra->ra_csi_rate_en = true; ++ ra->cr_tbl_sel = false; ++ ra->band_num = rtwvif->phy_idx; ++ ra->csi_bw = bw_mode; ++ ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; ++ ra->csi_mcs_ss_idx = 5; ++ ra->csi_mode = csi_mode; ++} ++ ++void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_ra_info *ra = &rtwsta->ra; ++ ++ rtw89_phy_ra_sta_update(rtwdev, sta, false); ++ ra->upd_mask = 1; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", ++ ra->macid, ++ ra->bw_cap, ++ ra->ss_num, ++ ra->en_sgi, ++ ra->giltf); ++ ++ rtw89_fw_h2c_ra(rtwdev, ra, false); ++} ++ ++static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, ++ u16 rate_base, u64 ra_mask, u8 ra_mode, ++ u32 rate_ctrl, u32 ctrl_skip, bool force) ++{ ++ u8 n, c; ++ ++ if (rate_ctrl == ctrl_skip) ++ return true; ++ ++ n = hweight32(rate_ctrl); ++ if (n == 0) ++ return true; ++ ++ if (force && n != 1) ++ return false; ++ ++ if (next->enable) ++ return false; ++ ++ c = __fls(rate_ctrl); ++ next->rate = rate_base + c; ++ next->ra_mode = ra_mode; ++ next->ra_mask = ra_mask; ++ next->enable = true; ++ ++ return true; ++} ++ ++void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ const struct cfg80211_bitrate_mask *mask) ++{ ++ struct ieee80211_supported_band *sband; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_phy_rate_pattern next_pattern = {0}; ++ static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, ++ RTW89_HW_RATE_HE_NSS2_MCS0, ++ RTW89_HW_RATE_HE_NSS3_MCS0, ++ RTW89_HW_RATE_HE_NSS4_MCS0}; ++ static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, ++ RTW89_HW_RATE_VHT_NSS2_MCS0, ++ RTW89_HW_RATE_VHT_NSS3_MCS0, ++ RTW89_HW_RATE_VHT_NSS4_MCS0}; ++ static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, ++ RTW89_HW_RATE_MCS8, ++ RTW89_HW_RATE_MCS16, ++ RTW89_HW_RATE_MCS24}; ++ u8 band = rtwdev->hal.current_band_type; ++ u8 tx_nss = rtwdev->hal.tx_nss; ++ u8 i; ++ ++ for (i = 0; i < tx_nss; i++) ++ if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], ++ RA_MASK_HE_RATES, RTW89_RA_MODE_HE, ++ mask->control[band].he_mcs[i], ++ 0, true)) ++ goto out; ++ ++ for (i = 0; i < tx_nss; i++) ++ if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], ++ RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, ++ mask->control[band].vht_mcs[i], ++ 0, true)) ++ goto out; ++ ++ for (i = 0; i < tx_nss; i++) ++ if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], ++ RA_MASK_HT_RATES, RTW89_RA_MODE_HT, ++ mask->control[band].ht_mcs[i], ++ 0, true)) ++ goto out; ++ ++ /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and ++ * require at least one basic rate for ieee80211_set_bitrate_mask, ++ * so the decision just depends on if all bitrates are set or not. ++ */ ++ sband = rtwdev->hw->wiphy->bands[band]; ++ if (band == RTW89_BAND_2G) { ++ if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, ++ RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, ++ RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, ++ mask->control[band].legacy, ++ BIT(sband->n_bitrates) - 1, false)) ++ goto out; ++ } else { ++ if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, ++ RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, ++ mask->control[band].legacy, ++ BIT(sband->n_bitrates) - 1, false)) ++ goto out; ++ } ++ ++ if (!next_pattern.enable) ++ goto out; ++ ++ rtwvif->rate_pattern = next_pattern; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", ++ next_pattern.rate, ++ next_pattern.ra_mask, ++ next_pattern.ra_mode); ++ return; ++ ++out: ++ rtwvif->rate_pattern.enable = false; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); ++} ++ ++static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; ++ ++ rtw89_phy_ra_updata_sta(rtwdev, sta); ++} ++ ++void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) ++{ ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_phy_ra_updata_sta_iter, ++ rtwdev); ++} ++ ++void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_ra_info *ra = &rtwsta->ra; ++ u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; ++ bool csi = rtw89_sta_has_beamformer_cap(sta); ++ ++ rtw89_phy_ra_sta_update(rtwdev, sta, csi); ++ ++ if (rssi > 40) ++ ra->init_rate_lv = 1; ++ else if (rssi > 20) ++ ra->init_rate_lv = 2; ++ else if (rssi > 1) ++ ra->init_rate_lv = 3; ++ else ++ ra->init_rate_lv = 0; ++ ra->upd_all = 1; ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", ++ ra->macid, ++ ra->mode_ctrl, ++ ra->bw_cap, ++ ra->ss_num, ++ ra->init_rate_lv); ++ rtw89_debug(rtwdev, RTW89_DBG_RA, ++ "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", ++ ra->dcm_cap, ++ ra->er_cap, ++ ra->ldpc_cap, ++ ra->stbc_cap, ++ ra->en_sgi, ++ ra->giltf); ++ ++ rtw89_fw_h2c_ra(rtwdev, ra, csi); ++} ++ ++u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ enum rtw89_bandwidth dbw) ++{ ++ enum rtw89_bandwidth cbw = param->bandwidth; ++ u8 pri_ch = param->primary_chan; ++ u8 central_ch = param->center_chan; ++ u8 txsc_idx = 0; ++ u8 tmp = 0; ++ ++ if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) ++ return txsc_idx; ++ ++ switch (cbw) { ++ case RTW89_CHANNEL_WIDTH_40: ++ txsc_idx = pri_ch > central_ch ? 1 : 2; ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ if (dbw == RTW89_CHANNEL_WIDTH_20) { ++ if (pri_ch > central_ch) ++ txsc_idx = (pri_ch - central_ch) >> 1; ++ else ++ txsc_idx = ((central_ch - pri_ch) >> 1) + 1; ++ } else { ++ txsc_idx = pri_ch > central_ch ? 9 : 10; ++ } ++ break; ++ case RTW89_CHANNEL_WIDTH_160: ++ if (pri_ch > central_ch) ++ tmp = (pri_ch - central_ch) >> 1; ++ else ++ tmp = ((central_ch - pri_ch) >> 1) + 1; ++ ++ if (dbw == RTW89_CHANNEL_WIDTH_20) { ++ txsc_idx = tmp; ++ } else if (dbw == RTW89_CHANNEL_WIDTH_40) { ++ if (tmp == 1 || tmp == 3) ++ txsc_idx = 9; ++ else if (tmp == 5 || tmp == 7) ++ txsc_idx = 11; ++ else if (tmp == 2 || tmp == 4) ++ txsc_idx = 10; ++ else if (tmp == 6 || tmp == 8) ++ txsc_idx = 12; ++ else ++ return 0xff; ++ } else { ++ txsc_idx = pri_ch > central_ch ? 13 : 14; ++ } ++ break; ++ case RTW89_CHANNEL_WIDTH_80_80: ++ if (dbw == RTW89_CHANNEL_WIDTH_20) { ++ if (pri_ch > central_ch) ++ txsc_idx = (10 - (pri_ch - central_ch)) >> 1; ++ else ++ txsc_idx = ((central_ch - pri_ch) >> 1) + 5; ++ } else if (dbw == RTW89_CHANNEL_WIDTH_40) { ++ txsc_idx = pri_ch > central_ch ? 10 : 12; ++ } else { ++ txsc_idx = 14; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ return txsc_idx; ++} ++ ++u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const u32 *base_addr = chip->rf_base_addr; ++ u32 val, direct_addr; ++ ++ if (rf_path >= rtwdev->chip->rf_path_num) { ++ rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); ++ return INV_RF_DATA; ++ } ++ ++ addr &= 0xff; ++ direct_addr = base_addr[rf_path] + (addr << 2); ++ mask &= RFREG_MASK; ++ ++ val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); ++ ++ return val; ++} ++EXPORT_SYMBOL(rtw89_phy_read_rf); ++ ++bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const u32 *base_addr = chip->rf_base_addr; ++ u32 direct_addr; ++ ++ if (rf_path >= rtwdev->chip->rf_path_num) { ++ rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); ++ return false; ++ } ++ ++ addr &= 0xff; ++ direct_addr = base_addr[rf_path] + (addr << 2); ++ mask &= RFREG_MASK; ++ ++ rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); ++ ++ /* delay to ensure writing properly */ ++ udelay(1); ++ ++ return true; ++} ++EXPORT_SYMBOL(rtw89_phy_write_rf); ++ ++static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ chip->ops->bb_reset(rtwdev, phy_idx); ++} ++ ++static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ void *extra_data) ++{ ++ if (reg->addr == 0xfe) ++ mdelay(50); ++ else if (reg->addr == 0xfd) ++ mdelay(5); ++ else if (reg->addr == 0xfc) ++ mdelay(1); ++ else if (reg->addr == 0xfb) ++ udelay(50); ++ else if (reg->addr == 0xfa) ++ udelay(5); ++ else if (reg->addr == 0xf9) ++ udelay(1); ++ else ++ rtw89_phy_write32(rtwdev, reg->addr, reg->data); ++} ++ ++static void ++rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ struct rtw89_fw_h2c_rf_reg_info *info) ++{ ++ u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; ++ u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; ++ ++ info->rtw89_phy_config_rf_h2c[page][idx] = ++ cpu_to_le32((reg->addr << 20) | reg->data); ++ info->curr_idx++; ++} ++ ++static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, ++ struct rtw89_fw_h2c_rf_reg_info *info) ++{ ++ u16 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; ++ u16 len = (info->curr_idx % RTW89_H2C_RF_PAGE_SIZE) * 4; ++ u8 i; ++ int ret = 0; ++ ++ if (page > RTW89_H2C_RF_PAGE_NUM) { ++ rtw89_warn(rtwdev, ++ "rf reg h2c total page num %d larger than %d (RTW89_H2C_RF_PAGE_NUM)\n", ++ page, RTW89_H2C_RF_PAGE_NUM); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < page; i++) { ++ ret = rtw89_fw_h2c_rf_reg(rtwdev, info, ++ RTW89_H2C_RF_PAGE_SIZE * 4, i); ++ if (ret) ++ return ret; ++ } ++ ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len, i); ++ if (ret) ++ return ret; ++ info->curr_idx = 0; ++ ++ return 0; ++} ++ ++static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ void *extra_data) ++{ ++ if (reg->addr == 0xfe) { ++ mdelay(50); ++ } else if (reg->addr == 0xfd) { ++ mdelay(5); ++ } else if (reg->addr == 0xfc) { ++ mdelay(1); ++ } else if (reg->addr == 0xfb) { ++ udelay(50); ++ } else if (reg->addr == 0xfa) { ++ udelay(5); ++ } else if (reg->addr == 0xf9) { ++ udelay(1); ++ } else { ++ rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); ++ rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, ++ (struct rtw89_fw_h2c_rf_reg_info *)extra_data); ++ } ++} ++ ++static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_table *table, ++ u32 *headline_size, u32 *headline_idx, ++ u8 rfe, u8 cv) ++{ ++ const struct rtw89_reg2_def *reg; ++ u32 headline; ++ u32 compare, target; ++ u8 rfe_para, cv_para; ++ u8 cv_max = 0; ++ bool case_matched = false; ++ u32 i; ++ ++ for (i = 0; i < table->n_regs; i++) { ++ reg = &table->regs[i]; ++ headline = get_phy_headline(reg->addr); ++ if (headline != PHY_HEADLINE_VALID) ++ break; ++ } ++ *headline_size = i; ++ if (*headline_size == 0) ++ return 0; ++ ++ /* case 1: RFE match, CV match */ ++ compare = get_phy_compare(rfe, cv); ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ target = get_phy_target(reg->addr); ++ if (target == compare) { ++ *headline_idx = i; ++ return 0; ++ } ++ } ++ ++ /* case 2: RFE match, CV don't care */ ++ compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ target = get_phy_target(reg->addr); ++ if (target == compare) { ++ *headline_idx = i; ++ return 0; ++ } ++ } ++ ++ /* case 3: RFE match, CV max in table */ ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ rfe_para = get_phy_cond_rfe(reg->addr); ++ cv_para = get_phy_cond_cv(reg->addr); ++ if (rfe_para == rfe) { ++ if (cv_para >= cv_max) { ++ cv_max = cv_para; ++ *headline_idx = i; ++ case_matched = true; ++ } ++ } ++ } ++ ++ if (case_matched) ++ return 0; ++ ++ /* case 4: RFE don't care, CV max in table */ ++ for (i = 0; i < *headline_size; i++) { ++ reg = &table->regs[i]; ++ rfe_para = get_phy_cond_rfe(reg->addr); ++ cv_para = get_phy_cond_cv(reg->addr); ++ if (rfe_para == PHY_COND_DONT_CARE) { ++ if (cv_para >= cv_max) { ++ cv_max = cv_para; ++ *headline_idx = i; ++ case_matched = true; ++ } ++ } ++ } ++ ++ if (case_matched) ++ return 0; ++ ++ return -EINVAL; ++} ++ ++static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_table *table, ++ void (*config)(struct rtw89_dev *rtwdev, ++ const struct rtw89_reg2_def *reg, ++ enum rtw89_rf_path rf_path, ++ void *data), ++ void *extra_data) ++{ ++ const struct rtw89_reg2_def *reg; ++ enum rtw89_rf_path rf_path = table->rf_path; ++ u8 rfe = rtwdev->efuse.rfe_type; ++ u8 cv = rtwdev->hal.cv; ++ u32 i; ++ u32 headline_size = 0, headline_idx = 0; ++ u32 target = 0, cfg_target; ++ u8 cond; ++ bool is_matched = true; ++ bool target_found = false; ++ int ret; ++ ++ ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, ++ &headline_idx, rfe, cv); ++ if (ret) { ++ rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); ++ return; ++ } ++ ++ cfg_target = get_phy_target(table->regs[headline_idx].addr); ++ for (i = headline_size; i < table->n_regs; i++) { ++ reg = &table->regs[i]; ++ cond = get_phy_cond(reg->addr); ++ switch (cond) { ++ case PHY_COND_BRANCH_IF: ++ case PHY_COND_BRANCH_ELIF: ++ target = get_phy_target(reg->addr); ++ break; ++ case PHY_COND_BRANCH_ELSE: ++ is_matched = false; ++ if (!target_found) { ++ rtw89_warn(rtwdev, "failed to load CR %x/%x\n", ++ reg->addr, reg->data); ++ return; ++ } ++ break; ++ case PHY_COND_BRANCH_END: ++ is_matched = true; ++ target_found = false; ++ break; ++ case PHY_COND_CHECK: ++ if (target_found) { ++ is_matched = false; ++ break; ++ } ++ ++ if (target == cfg_target) { ++ is_matched = true; ++ target_found = true; ++ } else { ++ is_matched = false; ++ target_found = false; ++ } ++ break; ++ default: ++ if (is_matched) ++ config(rtwdev, reg, rf_path, extra_data); ++ break; ++ } ++ } ++} ++ ++void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_phy_table *bb_table = chip->bb_table; ++ ++ rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); ++ rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); ++ rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); ++} ++ ++static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_write32(rtwdev, 0x8080, 0x4); ++ udelay(1); ++ return rtw89_phy_read32(rtwdev, 0x8080); ++} ++ ++void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_phy_table *rf_table; ++ struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; ++ u8 path; ++ ++ rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); ++ if (!rf_reg_info) ++ return; ++ ++ for (path = RF_PATH_A; path < chip->rf_path_num; path++) { ++ rf_reg_info->rf_path = path; ++ rf_table = chip->rf_table[path]; ++ rtw89_phy_init_reg(rtwdev, rf_table, rtw89_phy_config_rf_reg, ++ (void *)rf_reg_info); ++ if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) ++ rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", ++ path); ++ } ++ kfree(rf_reg_info); ++} ++ ++static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_phy_table *nctl_table; ++ u32 val; ++ int ret; ++ ++ /* IQK/DPK clock & reset */ ++ rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); ++ rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); ++ rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); ++ rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); ++ ++ /* check 0x8080 */ ++ rtw89_phy_write32(rtwdev, 0x8000, 0x8); ++ ++ ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, ++ 1000, false, rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "failed to poll nctl block\n"); ++ ++ nctl_table = chip->nctl_table; ++ rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); ++} ++ ++static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ u32 phy_page = addr >> 8; ++ u32 ofst = 0; ++ ++ switch (phy_page) { ++ case 0x6: ++ case 0x7: ++ case 0x8: ++ case 0x9: ++ case 0xa: ++ case 0xb: ++ case 0xc: ++ case 0xd: ++ case 0x19: ++ case 0x1a: ++ case 0x1b: ++ ofst = 0x2000; ++ break; ++ default: ++ /* warning case */ ++ ofst = 0; ++ break; ++ } ++ ++ if (phy_page >= 0x40 && phy_page <= 0x4f) ++ ofst = 0x2000; ++ ++ return ofst; ++} ++ ++void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 data, enum rtw89_phy_idx phy_idx) ++{ ++ if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) ++ addr += rtw89_phy0_phy1_offset(rtwdev, addr); ++ rtw89_phy_write32_mask(rtwdev, addr, mask, data); ++} ++ ++void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 val) ++{ ++ rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); ++ ++ if (!rtwdev->dbcc_en) ++ return; ++ ++ rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); ++} ++ ++void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_reg3_tbl *tbl) ++{ ++ const struct rtw89_reg3_def *reg3; ++ int i; ++ ++ for (i = 0; i < tbl->size; i++) { ++ reg3 = &tbl->reg3[i]; ++ rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); ++ } ++} ++ ++const u8 rtw89_rs_idx_max[] = { ++ [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, ++ [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, ++ [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, ++ [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, ++ [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, ++}; ++ ++const u8 rtw89_rs_nss_max[] = { ++ [RTW89_RS_CCK] = 1, ++ [RTW89_RS_OFDM] = 1, ++ [RTW89_RS_MCS] = RTW89_NSS_MAX, ++ [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, ++ [RTW89_RS_OFFSET] = 1, ++}; ++ ++static const u8 _byr_of_rs[] = { ++ [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), ++ [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), ++ [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), ++ [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), ++ [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), ++}; ++ ++#define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) ++#define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) ++#define _byr_chk(rs, nss, idx) \ ++ ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) ++ ++void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl) ++{ ++ const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; ++ const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; ++ s8 *byr; ++ u32 data; ++ u8 i, idx; ++ ++ for (; cfg < end; cfg++) { ++ byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); ++ data = cfg->data; ++ ++ for (i = 0; i < cfg->len; i++, data >>= 8) { ++ idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); ++ byr[idx] = (s8)(data & 0xff); ++ } ++ } ++} ++ ++#define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ ++({ \ ++ const struct rtw89_chip_info *__c = (rtwdev)->chip; \ ++ (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ ++}) ++ ++s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_rate_desc *rate_desc) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ s8 *byr; ++ u8 idx; ++ ++ if (rate_desc->rs == RTW89_RS_CCK) ++ band = RTW89_BAND_2G; ++ ++ if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", ++ rate_desc->rs, rate_desc->nss, rate_desc->idx); ++ ++ return 0; ++ } ++ ++ byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); ++ idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); ++ ++ return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); ++} ++ ++static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel) ++{ ++ switch (channel) { ++ case 1 ... 14: ++ return channel - 1; ++ case 36 ... 64: ++ return (channel - 36) / 2; ++ case 100 ... 144: ++ return ((channel - 100) / 2) + 15; ++ case 149 ... 177: ++ return ((channel - 149) / 2) + 38; ++ default: ++ rtw89_warn(rtwdev, "unknown channel: %d\n", channel); ++ return 0; ++ } ++} ++ ++s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, ++ u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch); ++ u8 band = rtwdev->hal.current_band_type; ++ u8 regd = rtw89_regd_get(rtwdev, band); ++ s8 lmt = 0, sar; ++ ++ switch (band) { ++ case RTW89_BAND_2G: ++ lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; ++ break; ++ case RTW89_BAND_5G: ++ lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; ++ break; ++ default: ++ rtw89_warn(rtwdev, "unknown band type: %d\n", band); ++ return 0; ++ } ++ ++ lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); ++ sar = rtw89_query_sar(rtwdev); ++ ++ return min(lmt, sar); ++} ++ ++#define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \ ++ do { \ ++ u8 __i; \ ++ for (__i = 0; __i < RTW89_BF_NUM; __i++) \ ++ ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ ++ bw, ntx, \ ++ rs, __i, \ ++ (ch)); \ ++ } while (0) ++ ++static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx, u8 ch) ++{ ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_CCK, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_CCK, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_OFDM, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch); ++} ++ ++static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx, u8 ch) ++{ ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_CCK, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_CCK, ch); ++ __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_OFDM, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch + 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch); ++} ++ ++static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx, u8 ch) ++{ ++ s8 val_0p5_n[RTW89_BF_NUM]; ++ s8 val_0p5_p[RTW89_BF_NUM]; ++ u8 i; ++ ++ __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_OFDM, ch - 6); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch - 6); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch - 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch + 2); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, ++ ntx, RTW89_RS_MCS, ch + 6); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch - 4); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch + 4); ++ __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, ++ ntx, RTW89_RS_MCS, ch); ++ ++ __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch - 4); ++ __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, ++ ntx, RTW89_RS_MCS, ch + 4); ++ ++ for (i = 0; i < RTW89_BF_NUM; i++) ++ lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); ++} ++ ++void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx) ++{ ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ ++ memset(lmt, 0, sizeof(*lmt)); ++ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch); ++ break; ++ } ++} ++ ++static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ u8 ru, u8 ntx, u8 ch) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch); ++ u8 band = rtwdev->hal.current_band_type; ++ u8 regd = rtw89_regd_get(rtwdev, band); ++ s8 lmt_ru = 0, sar; ++ ++ switch (band) { ++ case RTW89_BAND_2G: ++ lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; ++ break; ++ case RTW89_BAND_5G: ++ lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; ++ break; ++ default: ++ rtw89_warn(rtwdev, "unknown band type: %d\n", band); ++ return 0; ++ } ++ ++ lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); ++ sar = rtw89_query_sar(rtwdev); ++ ++ return min(lmt_ru, sar); ++} ++ ++static void ++rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx, u8 ch) ++{ ++ lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch); ++ lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch); ++ lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch); ++} ++ ++static void ++rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx, u8 ch) ++{ ++ lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch - 2); ++ lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch + 2); ++ lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch - 2); ++ lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch + 2); ++ lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch - 2); ++ lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch + 2); ++} ++ ++static void ++rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx, u8 ch) ++{ ++ lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch - 6); ++ lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch - 2); ++ lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch + 2); ++ lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, ++ ntx, ch + 6); ++ lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch - 6); ++ lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch - 2); ++ lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch + 2); ++ lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, ++ ntx, ch + 6); ++ lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch - 6); ++ lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch - 2); ++ lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch + 2); ++ lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, ++ ntx, ch + 6); ++} ++ ++void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx) ++{ ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ ++ memset(lmt_ru, 0, sizeof(*lmt_ru)); ++ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch); ++ break; ++ } ++} ++ ++struct rtw89_phy_iter_ra_data { ++ struct rtw89_dev *rtwdev; ++ struct sk_buff *c2h; ++}; ++ ++static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) ++{ ++ struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; ++ struct rtw89_dev *rtwdev = ra_data->rtwdev; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_ra_report *ra_report = &rtwsta->ra_report; ++ struct sk_buff *c2h = ra_data->c2h; ++ u8 mode, rate, bw, giltf, mac_id; ++ ++ mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); ++ if (mac_id != rtwsta->mac_id) ++ return; ++ ++ memset(ra_report, 0, sizeof(*ra_report)); ++ ++ rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); ++ bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); ++ giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); ++ mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); ++ ++ switch (mode) { ++ case RTW89_RA_RPT_MODE_LEGACY: ++ ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate); ++ break; ++ case RTW89_RA_RPT_MODE_HT: ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; ++ if (rtwdev->fw.old_ht_ra_format) ++ rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), ++ FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); ++ else ++ rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); ++ ra_report->txrate.mcs = rate; ++ if (giltf) ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; ++ break; ++ case RTW89_RA_RPT_MODE_VHT: ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; ++ ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); ++ ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; ++ if (giltf) ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; ++ break; ++ case RTW89_RA_RPT_MODE_HE: ++ ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; ++ ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); ++ ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; ++ if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) ++ ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; ++ else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) ++ ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; ++ else ++ ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; ++ break; ++ } ++ ++ if (bw == RTW89_CHANNEL_WIDTH_80) ++ ra_report->txrate.bw = RATE_INFO_BW_80; ++ else if (bw == RTW89_CHANNEL_WIDTH_40) ++ ra_report->txrate.bw = RATE_INFO_BW_40; ++ else ++ ra_report->txrate.bw = RATE_INFO_BW_20; ++ ++ ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); ++ ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | ++ FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); ++ sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); ++ rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; ++} ++ ++static void ++rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) ++{ ++ struct rtw89_phy_iter_ra_data ra_data; ++ ++ ra_data.rtwdev = rtwdev; ++ ra_data.c2h = c2h; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_phy_c2h_ra_rpt_iter, ++ &ra_data); ++} ++ ++static ++void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = { ++ [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, ++ [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, ++ [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, ++}; ++ ++void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func) ++{ ++ void (*handler)(struct rtw89_dev *rtwdev, ++ struct sk_buff *c2h, u32 len) = NULL; ++ ++ switch (class) { ++ case RTW89_PHY_C2H_CLASS_RA: ++ if (func < RTW89_PHY_C2H_FUNC_RA_MAX) ++ handler = rtw89_phy_c2h_ra_handler[func]; ++ break; ++ default: ++ rtw89_info(rtwdev, "c2h class %d not support\n", class); ++ return; ++ } ++ if (!handler) { ++ rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, ++ func); ++ return; ++ } ++ handler(rtwdev, skb, len); ++} ++ ++static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) ++{ ++ u32 reg_mask; ++ ++ if (sc_xo) ++ reg_mask = B_AX_XTAL_SC_XO_MASK; ++ else ++ reg_mask = B_AX_XTAL_SC_XI_MASK; ++ ++ return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); ++} ++ ++static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, ++ u8 val) ++{ ++ u32 reg_mask; ++ ++ if (sc_xo) ++ reg_mask = B_AX_XTAL_SC_XO_MASK; ++ else ++ reg_mask = B_AX_XTAL_SC_XI_MASK; ++ ++ rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); ++} ++ ++static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, ++ u8 crystal_cap, bool force) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ u8 sc_xi_val, sc_xo_val; ++ ++ if (!force && cfo->crystal_cap == crystal_cap) ++ return; ++ crystal_cap = clamp_t(u8, crystal_cap, 0, 127); ++ rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); ++ rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); ++ sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); ++ sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); ++ cfo->crystal_cap = sc_xi_val; ++ cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", ++ cfo->x_cap_ofst); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); ++} ++ ++static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ u8 cap; ++ ++ cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; ++ cfo->is_adjust = false; ++ if (cfo->crystal_cap == cfo->def_x_cap) ++ return; ++ cap = cfo->crystal_cap; ++ cap += (cap > cfo->def_x_cap ? -1 : 1); ++ rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, ++ cfo->def_x_cap); ++} ++ ++static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) ++{ ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ s32 cfo_avg_312; ++ s32 dcfo_comp; ++ int sign; ++ ++ if (!is_linked) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", ++ is_linked); ++ return; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); ++ if (curr_cfo == 0) ++ return; ++ dcfo_comp = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); ++ sign = curr_cfo > 0 ? 1 : -1; ++ cfo_avg_312 = (curr_cfo << 3) / 5 + sign * dcfo_comp; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); ++ if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) ++ cfo_avg_312 = -cfo_avg_312; ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK, ++ cfo_avg_312); ++} ++ ++static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); ++ rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); ++} ++ ++static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ ++ cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; ++ cfo->crystal_cap = cfo->crystal_cap_default; ++ cfo->def_x_cap = cfo->crystal_cap; ++ cfo->is_adjust = false; ++ cfo->x_cap_ofst = 0; ++ cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; ++ cfo->apply_compensation = false; ++ cfo->residual_cfo_acc = 0; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", ++ cfo->crystal_cap_default); ++ rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); ++ rtw89_dcfo_comp_init(rtwdev); ++ cfo->cfo_timer_ms = 2000; ++ cfo->cfo_trig_by_timer_en = false; ++ cfo->phy_cfo_trk_cnt = 0; ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; ++} ++ ++static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, ++ s32 curr_cfo) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ s8 crystal_cap = cfo->crystal_cap; ++ s32 cfo_abs = abs(curr_cfo); ++ int sign; ++ ++ if (!cfo->is_adjust) { ++ if (cfo_abs > CFO_TRK_ENABLE_TH) ++ cfo->is_adjust = true; ++ } else { ++ if (cfo_abs < CFO_TRK_STOP_TH) ++ cfo->is_adjust = false; ++ } ++ if (!cfo->is_adjust) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); ++ return; ++ } ++ sign = curr_cfo > 0 ? 1 : -1; ++ if (cfo_abs > CFO_TRK_STOP_TH_4) ++ crystal_cap += 7 * sign; ++ else if (cfo_abs > CFO_TRK_STOP_TH_3) ++ crystal_cap += 5 * sign; ++ else if (cfo_abs > CFO_TRK_STOP_TH_2) ++ crystal_cap += 3 * sign; ++ else if (cfo_abs > CFO_TRK_STOP_TH_1) ++ crystal_cap += 1 * sign; ++ else ++ return; ++ rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "X_cap{Curr,Default}={0x%x,0x%x}\n", ++ cfo->crystal_cap, cfo->def_x_cap); ++} ++ ++static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ s32 cfo_khz_all = 0; ++ s32 cfo_cnt_all = 0; ++ s32 cfo_all_avg = 0; ++ u8 i; ++ ++ if (rtwdev->total_sta_assoc != 1) ++ return 0; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ if (cfo->cfo_cnt[i] == 0) ++ continue; ++ cfo_khz_all += cfo->cfo_tail[i]; ++ cfo_cnt_all += cfo->cfo_cnt[i]; ++ cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); ++ cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "CFO track for macid = %d\n", i); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", ++ cfo_khz_all, cfo_cnt_all, cfo_all_avg); ++ return cfo_all_avg; ++} ++ ++static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ s32 target_cfo = 0; ++ s32 cfo_khz_all = 0; ++ s32 cfo_khz_all_tp_wgt = 0; ++ s32 cfo_avg = 0; ++ s32 max_cfo_lb = BIT(31); ++ s32 min_cfo_ub = GENMASK(30, 0); ++ u16 cfo_cnt_all = 0; ++ u8 active_entry_cnt = 0; ++ u8 sta_cnt = 0; ++ u32 tp_all = 0; ++ u8 i; ++ u8 cfo_tol = 0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); ++ if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ if (cfo->cfo_cnt[i] == 0) ++ continue; ++ cfo_khz_all += cfo->cfo_tail[i]; ++ cfo_cnt_all += cfo->cfo_cnt[i]; ++ cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", ++ cfo_khz_all, cfo_cnt_all, cfo_avg); ++ target_cfo = cfo_avg; ++ } ++ } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ if (cfo->cfo_cnt[i] == 0) ++ continue; ++ cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], ++ (s32)cfo->cfo_cnt[i]); ++ cfo_khz_all += cfo->cfo_avg[i]; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Macid=%d, cfo_avg=%d\n", i, ++ cfo->cfo_avg[i]); ++ } ++ sta_cnt = rtwdev->total_sta_assoc; ++ cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", ++ cfo_khz_all, sta_cnt, cfo_avg); ++ target_cfo = cfo_avg; ++ } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); ++ cfo_tol = cfo->sta_cfo_tolerance; ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) { ++ sta_cnt++; ++ if (cfo->cfo_cnt[i] != 0) { ++ cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], ++ (s32)cfo->cfo_cnt[i]); ++ active_entry_cnt++; ++ } else { ++ cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; ++ } ++ max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); ++ min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); ++ cfo_khz_all += cfo->cfo_avg[i]; ++ /* need tp for each entry */ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "[%d] cfo_avg=%d, tp=tbd\n", ++ i, cfo->cfo_avg[i]); ++ if (sta_cnt >= rtwdev->total_sta_assoc) ++ break; ++ } ++ tp_all = stats->rx_throughput; /* need tp for each entry */ ++ cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", ++ sta_cnt); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", ++ active_entry_cnt); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", ++ cfo_khz_all_tp_wgt, cfo_avg); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", ++ max_cfo_lb, min_cfo_ub); ++ if (max_cfo_lb <= min_cfo_ub) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "cfo win_size=%d\n", ++ min_cfo_ub - max_cfo_lb); ++ target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "No intersection of cfo torlence windows\n"); ++ target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); ++ } ++ for (i = 0; i < CFO_TRACK_MAX_USER; i++) ++ cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); ++ return target_cfo; ++} ++ ++static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ ++ memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); ++ memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); ++ cfo->packet_count = 0; ++ cfo->packet_count_pre = 0; ++ cfo->cfo_avg_pre = 0; ++} ++ ++static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ s32 new_cfo = 0; ++ bool x_cap_update = false; ++ u8 pre_x_cap = cfo->crystal_cap; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", ++ rtwdev->total_sta_assoc); ++ if (rtwdev->total_sta_assoc == 0) { ++ rtw89_phy_cfo_reset(rtwdev); ++ return; ++ } ++ if (cfo->packet_count == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); ++ return; ++ } ++ if (cfo->packet_count == cfo->packet_count_pre) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); ++ return; ++ } ++ if (rtwdev->total_sta_assoc == 1) ++ new_cfo = rtw89_phy_average_cfo_calc(rtwdev); ++ else ++ new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); ++ if (new_cfo == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); ++ return; ++ } ++ rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); ++ cfo->cfo_avg_pre = new_cfo; ++ x_cap_update = cfo->crystal_cap == pre_x_cap ? false : true; ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", ++ cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, ++ cfo->x_cap_ofst); ++ if (x_cap_update) { ++ if (new_cfo > 0) ++ new_cfo -= CFO_SW_COMP_FINE_TUNE; ++ else ++ new_cfo += CFO_SW_COMP_FINE_TUNE; ++ } ++ rtw89_dcfo_comp(rtwdev, new_cfo); ++ rtw89_phy_cfo_statistics_reset(rtwdev); ++} ++ ++void rtw89_phy_cfo_track_work(struct work_struct *work) ++{ ++ struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, ++ cfo_track_work.work); ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ ++ mutex_lock(&rtwdev->mutex); ++ if (!cfo->cfo_trig_by_timer_en) ++ goto out; ++ rtw89_leave_ps_mode(rtwdev); ++ rtw89_phy_cfo_dm(rtwdev); ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, ++ msecs_to_jiffies(cfo->cfo_timer_ms)); ++out: ++ mutex_unlock(&rtwdev->mutex); ++} ++ ++static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ ++ ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, ++ msecs_to_jiffies(cfo->cfo_timer_ms)); ++} ++ ++void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ struct rtw89_traffic_stats *stats = &rtwdev->stats; ++ ++ switch (cfo->phy_cfo_status) { ++ case RTW89_PHY_DCFO_STATE_NORMAL: ++ if (stats->tx_throughput >= CFO_TP_UPPER) { ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; ++ cfo->cfo_trig_by_timer_en = true; ++ cfo->cfo_timer_ms = CFO_COMP_PERIOD; ++ rtw89_phy_cfo_start_work(rtwdev); ++ } ++ break; ++ case RTW89_PHY_DCFO_STATE_ENHANCE: ++ if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) { ++ cfo->phy_cfo_trk_cnt = 0; ++ cfo->cfo_trig_by_timer_en = false; ++ } ++ if (cfo->cfo_trig_by_timer_en == 1) ++ cfo->phy_cfo_trk_cnt++; ++ if (stats->tx_throughput <= CFO_TP_LOWER) { ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; ++ cfo->phy_cfo_trk_cnt = 0; ++ cfo->cfo_trig_by_timer_en = false; ++ } ++ break; ++ default: ++ cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; ++ cfo->phy_cfo_trk_cnt = 0; ++ break; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_CFO, ++ "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", ++ stats->tx_throughput, cfo->phy_cfo_status, ++ cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); ++ if (cfo->cfo_trig_by_timer_en) ++ return; ++ rtw89_phy_cfo_dm(rtwdev); ++} ++ ++void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, ++ struct rtw89_rx_phy_ppdu *phy_ppdu) ++{ ++ struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; ++ u8 macid = phy_ppdu->mac_id; ++ ++ cfo->cfo_tail[macid] += cfo_val; ++ cfo->cfo_cnt[macid]++; ++ cfo->packet_count++; ++} ++ ++static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_stat *phystat = &rtwdev->phystat; ++ int i; ++ u8 th; ++ ++ for (i = 0; i < rtwdev->chip->rf_path_num; i++) { ++ th = rtw89_chip_get_thermal(rtwdev, i); ++ if (th) ++ ewma_thermal_add(&phystat->avg_thermal[i], th); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "path(%d) thermal cur=%u avg=%ld", i, th, ++ ewma_thermal_read(&phystat->avg_thermal[i])); ++ } ++} ++ ++struct rtw89_phy_iter_rssi_data { ++ struct rtw89_dev *rtwdev; ++ struct rtw89_phy_ch_info *ch_info; ++ bool rssi_changed; ++}; ++ ++static void rtw89_phy_stat_rssi_update_iter(void *data, ++ struct ieee80211_sta *sta) ++{ ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_phy_iter_rssi_data *rssi_data = ++ (struct rtw89_phy_iter_rssi_data *)data; ++ struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; ++ unsigned long rssi_curr; ++ ++ rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); ++ ++ if (rssi_curr < ch_info->rssi_min) { ++ ch_info->rssi_min = rssi_curr; ++ ch_info->rssi_min_macid = rtwsta->mac_id; ++ } ++ ++ if (rtwsta->prev_rssi == 0) { ++ rtwsta->prev_rssi = rssi_curr; ++ } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { ++ rtwsta->prev_rssi = rssi_curr; ++ rssi_data->rssi_changed = true; ++ } ++} ++ ++static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_iter_rssi_data rssi_data = {0}; ++ ++ rssi_data.rtwdev = rtwdev; ++ rssi_data.ch_info = &rtwdev->ch_info; ++ rssi_data.ch_info->rssi_min = U8_MAX; ++ ieee80211_iterate_stations_atomic(rtwdev->hw, ++ rtw89_phy_stat_rssi_update_iter, ++ &rssi_data); ++ if (rssi_data.rssi_changed) ++ rtw89_btc_ntfy_wl_sta(rtwdev); ++} ++ ++static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_stat *phystat = &rtwdev->phystat; ++ int i; ++ ++ for (i = 0; i < rtwdev->chip->rf_path_num; i++) ++ ewma_thermal_init(&phystat->avg_thermal[i]); ++ ++ rtw89_phy_stat_thermal_update(rtwdev); ++ ++ memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); ++ memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); ++} ++ ++void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_stat *phystat = &rtwdev->phystat; ++ ++ rtw89_phy_stat_thermal_update(rtwdev); ++ rtw89_phy_stat_rssi_update(rtwdev); ++ ++ phystat->last_pkt_stat = phystat->cur_pkt_stat; ++ memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); ++} ++ ++static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); ++} ++ ++static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); ++} ++ ++static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ env->ccx_manual_ctrl = false; ++ env->ccx_ongoing = false; ++ env->ccx_rac_lv = RTW89_RAC_RELEASE; ++ env->ccx_rpt_stamp = 0; ++ env->ccx_period = 0; ++ env->ccx_unit_idx = RTW89_CCX_32_US; ++ env->ccx_trigger_time = 0; ++ env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, ++ RTW89_CCX_EDCCA_BW20_0); ++} ++ ++static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, ++ u16 score) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u32 numer = 0; ++ u16 ret = 0; ++ ++ numer = report * score + (env->ccx_period >> 1); ++ if (env->ccx_period) ++ ret = numer / env->ccx_period; ++ ++ return ret >= score ? score - 1 : ret; ++} ++ ++static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, ++ u16 time_ms, u32 *period, ++ u32 *unit_idx) ++{ ++ u32 idx; ++ u8 quotient; ++ ++ if (time_ms >= CCX_MAX_PERIOD) ++ time_ms = CCX_MAX_PERIOD; ++ ++ quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; ++ ++ if (quotient < 4) ++ idx = RTW89_CCX_4_US; ++ else if (quotient < 8) ++ idx = RTW89_CCX_8_US; ++ else if (quotient < 16) ++ idx = RTW89_CCX_16_US; ++ else ++ idx = RTW89_CCX_32_US; ++ ++ *unit_idx = idx; ++ *period = (time_ms * MS_TO_4US_RATIO) >> idx; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "[Trigger Time] period:%d, unit_idx:%d\n", ++ *period, *unit_idx); ++} ++ ++static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "lv:(%d)->(0)\n", env->ccx_rac_lv); ++ ++ env->ccx_ongoing = false; ++ env->ccx_rac_lv = RTW89_RAC_RELEASE; ++ env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; ++} ++ ++static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, ++ struct rtw89_ccx_para_info *para) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ bool is_update = env->ifs_clm_app != para->ifs_clm_app; ++ u8 i = 0; ++ u16 *ifs_th_l = env->ifs_clm_th_l; ++ u16 *ifs_th_h = env->ifs_clm_th_h; ++ u32 ifs_th0_us = 0, ifs_th_times = 0; ++ u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; ++ ++ if (!is_update) ++ goto ifs_update_finished; ++ ++ switch (para->ifs_clm_app) { ++ case RTW89_IFS_CLM_INIT: ++ case RTW89_IFS_CLM_BACKGROUND: ++ case RTW89_IFS_CLM_ACS: ++ case RTW89_IFS_CLM_DBG: ++ case RTW89_IFS_CLM_DIG: ++ case RTW89_IFS_CLM_TDMA_DIG: ++ ifs_th0_us = IFS_CLM_TH0_UPPER; ++ ifs_th_times = IFS_CLM_TH_MUL; ++ break; ++ case RTW89_IFS_CLM_DBG_MANUAL: ++ ifs_th0_us = para->ifs_clm_manual_th0; ++ ifs_th_times = para->ifs_clm_manual_th_times; ++ break; ++ default: ++ break; ++ } ++ ++ /* Set sampling threshold for 4 different regions, unit in idx_cnt. ++ * low[i] = high[i-1] + 1 ++ * high[i] = high[i-1] * ifs_th_times ++ */ ++ ifs_th_l[IFS_CLM_TH_START_IDX] = 0; ++ ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; ++ ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, ++ ifs_th0_us); ++ for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { ++ ifs_th_l[i] = ifs_th_h[i - 1] + 1; ++ ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; ++ ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); ++ } ++ ++ifs_update_finished: ++ if (!is_update) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "No need to update IFS_TH\n"); ++ ++ return is_update; ++} ++ ++static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u8 i = 0; ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, ++ env->ifs_clm_th_l[0]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, ++ env->ifs_clm_th_l[1]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, ++ env->ifs_clm_th_l[2]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, ++ env->ifs_clm_th_l[3]); ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, ++ env->ifs_clm_th_h[0]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, ++ env->ifs_clm_th_h[1]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, ++ env->ifs_clm_th_h[2]); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, ++ env->ifs_clm_th_h[3]); ++ ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Update IFS_T%d_th{low, high} : {%d, %d}\n", ++ i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); ++} ++ ++static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ struct rtw89_ccx_para_info para = {0}; ++ ++ env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; ++ env->ifs_clm_mntr_time = 0; ++ ++ para.ifs_clm_app = RTW89_IFS_CLM_INIT; ++ if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) ++ rtw89_phy_ifs_clm_set_th_reg(rtwdev); ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, ++ true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); ++} ++ ++static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, ++ enum rtw89_env_racing_lv level) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ int ret = 0; ++ ++ if (level >= RTW89_RAC_MAX_NUM) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "[WARNING] Wrong LV=%d\n", level); ++ return -EINVAL; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, ++ env->ccx_rac_lv, level); ++ ++ if (env->ccx_ongoing) { ++ if (level <= env->ccx_rac_lv) ++ ret = -EINVAL; ++ else ++ env->ccx_ongoing = false; ++ } ++ ++ if (ret == 0) ++ env->ccx_rac_lv = level; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", ++ !ret); ++ ++ return ret; ++} ++ ++static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); ++ rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); ++ ++ env->ccx_rpt_stamp++; ++ env->ccx_ongoing = true; ++} ++ ++static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u8 i = 0; ++ u32 res = 0; ++ ++ env->ifs_clm_tx_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); ++ env->ifs_clm_edcca_excl_cca_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, ++ PERCENT); ++ env->ifs_clm_cck_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); ++ env->ifs_clm_ofdm_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); ++ env->ifs_clm_cck_cca_excl_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, ++ PERCENT); ++ env->ifs_clm_ofdm_cca_excl_fa_ratio = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, ++ PERCENT); ++ env->ifs_clm_cck_fa_permil = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); ++ env->ifs_clm_ofdm_fa_permil = ++ rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); ++ ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { ++ if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { ++ env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; ++ } else { ++ env->ifs_clm_ifs_avg[i] = ++ rtw89_phy_ccx_idx_to_us(rtwdev, ++ env->ifs_clm_avg[i]); ++ } ++ ++ res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); ++ res += env->ifs_clm_his[i] >> 1; ++ if (env->ifs_clm_his[i]) ++ res /= env->ifs_clm_his[i]; ++ else ++ res = 0; ++ env->ifs_clm_cca_avg[i] = res; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", ++ env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cck_cca_excl_fa_ratio, ++ env->ifs_clm_ofdm_cca_excl_fa_ratio); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Time:[his, ifs_avg(us), cca_avg(us)]\n"); ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", ++ i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], ++ env->ifs_clm_cca_avg[i]); ++} ++ ++static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u8 i = 0; ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Get IFS_CLM report Fail\n"); ++ return false; ++ } ++ ++ env->ifs_clm_tx = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, ++ B_IFS_CLM_TX_CNT_MSK); ++ env->ifs_clm_edcca_excl_cca = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, ++ B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); ++ env->ifs_clm_cckcca_excl_fa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, ++ B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); ++ env->ifs_clm_ofdmcca_excl_fa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, ++ B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); ++ env->ifs_clm_cckfa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, ++ B_IFS_CLM_CCK_FA_MSK); ++ env->ifs_clm_ofdmfa = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, ++ B_IFS_CLM_OFDM_FA_MSK); ++ ++ env->ifs_clm_his[0] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); ++ env->ifs_clm_his[1] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); ++ env->ifs_clm_his[2] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); ++ env->ifs_clm_his[3] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); ++ ++ env->ifs_clm_avg[0] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); ++ env->ifs_clm_avg[1] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); ++ env->ifs_clm_avg[2] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); ++ env->ifs_clm_avg[3] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); ++ ++ env->ifs_clm_cca[0] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); ++ env->ifs_clm_cca[1] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); ++ env->ifs_clm_cca[2] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); ++ env->ifs_clm_cca[3] = ++ rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); ++ ++ env->ifs_clm_total_ifs = ++ rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", ++ env->ifs_clm_total_ifs); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", ++ env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", ++ env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); ++ for (i = 0; i < RTW89_IFS_CLM_NUM; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], ++ env->ifs_clm_avg[i], env->ifs_clm_cca[i]); ++ ++ rtw89_phy_ifs_clm_get_utility(rtwdev); ++ ++ return true; ++} ++ ++static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, ++ struct rtw89_ccx_para_info *para) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ u32 period = 0; ++ u32 unit_idx = 0; ++ ++ if (para->mntr_time == 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "[WARN] MNTR_TIME is 0\n"); ++ return -EINVAL; ++ } ++ ++ if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) ++ return -EINVAL; ++ ++ if (para->mntr_time != env->ifs_clm_mntr_time) { ++ rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, ++ &period, &unit_idx); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, ++ B_IFS_CLM_PERIOD_MSK, period); ++ rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, ++ B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "Update IFS-CLM time ((%d)) -> ((%d))\n", ++ env->ifs_clm_mntr_time, para->mntr_time); ++ ++ env->ifs_clm_mntr_time = para->mntr_time; ++ env->ccx_period = (u16)period; ++ env->ccx_unit_idx = (u8)unit_idx; ++ } ++ ++ if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { ++ env->ifs_clm_app = para->ifs_clm_app; ++ rtw89_phy_ifs_clm_set_th_reg(rtwdev); ++ } ++ ++ return 0; ++} ++ ++void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ struct rtw89_ccx_para_info para = {0}; ++ u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; ++ ++ env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; ++ if (env->ccx_manual_ctrl) { ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "CCX in manual ctrl\n"); ++ return; ++ } ++ ++ /* only ifs_clm for now */ ++ if (rtw89_phy_ifs_clm_get_result(rtwdev)) ++ env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; ++ ++ rtw89_phy_ccx_racing_release(rtwdev); ++ para.mntr_time = 1900; ++ para.rac_lv = RTW89_RAC_LV_1; ++ para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; ++ ++ if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) ++ chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; ++ if (chk_result) ++ rtw89_phy_ccx_trigger(rtwdev); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, ++ "get_result=0x%x, chk_result:0x%x\n", ++ env->ccx_watchdog_result, chk_result); ++} ++ ++static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ const struct rtw89_phy_dig_gain_cfg *cfg; ++ const char *msg; ++ u8 i; ++ s8 gain_base; ++ s8 *gain_arr; ++ u32 tmp; ++ ++ switch (type) { ++ case RTW89_DIG_GAIN_LNA_G: ++ gain_arr = dig->lna_gain_g; ++ gain_base = LNA0_GAIN; ++ cfg = chip->dig_table->cfg_lna_g; ++ msg = "lna_gain_g"; ++ break; ++ case RTW89_DIG_GAIN_TIA_G: ++ gain_arr = dig->tia_gain_g; ++ gain_base = TIA0_GAIN_G; ++ cfg = chip->dig_table->cfg_tia_g; ++ msg = "tia_gain_g"; ++ break; ++ case RTW89_DIG_GAIN_LNA_A: ++ gain_arr = dig->lna_gain_a; ++ gain_base = LNA0_GAIN; ++ cfg = chip->dig_table->cfg_lna_a; ++ msg = "lna_gain_a"; ++ break; ++ case RTW89_DIG_GAIN_TIA_A: ++ gain_arr = dig->tia_gain_a; ++ gain_base = TIA0_GAIN_A; ++ cfg = chip->dig_table->cfg_tia_a; ++ msg = "tia_gain_a"; ++ break; ++ default: ++ return; ++ } ++ ++ for (i = 0; i < cfg->size; i++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, ++ cfg->table[i].mask); ++ tmp >>= DIG_GAIN_SHIFT; ++ gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; ++ gain_base += DIG_GAIN; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", ++ msg, i, gain_arr[i]); ++ } ++} ++ ++static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u32 tmp; ++ u8 i; ++ ++ tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, ++ B_PATH0_IB_PKPW_MSK); ++ dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); ++ dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, ++ B_PATH0_IB_PBK_MSK); ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", ++ dig->ib_pkpwr, dig->ib_pbk); ++ ++ for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) ++ rtw89_phy_dig_read_gain_table(rtwdev, i); ++} ++ ++static const u8 rssi_nolink = 22; ++static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; ++static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; ++static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; ++static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; ++ ++static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ ++ if (is_linked) { ++ dig->igi_rssi = ch_info->rssi_min >> 1; ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); ++ dig->igi_rssi = rssi_nolink; ++ } ++} ++ ++static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ const u16 *fa_th_src = NULL; ++ ++ switch (rtwdev->hal.current_band_type) { ++ case RTW89_BAND_2G: ++ dig->lna_gain = dig->lna_gain_g; ++ dig->tia_gain = dig->tia_gain_g; ++ fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; ++ dig->force_gaincode_idx_en = false; ++ dig->dyn_pd_th_en = true; ++ break; ++ case RTW89_BAND_5G: ++ default: ++ dig->lna_gain = dig->lna_gain_a; ++ dig->tia_gain = dig->tia_gain_a; ++ fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; ++ dig->force_gaincode_idx_en = true; ++ dig->dyn_pd_th_en = true; ++ break; ++ } ++ memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); ++ memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); ++} ++ ++static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; ++static const u8 igi_max_performance_mode = 0x5a; ++static const u8 dynamic_pd_threshold_max; ++ ++static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ ++ dig->cur_gaincode.lna_idx = LNA_IDX_MAX; ++ dig->cur_gaincode.tia_idx = TIA_IDX_MAX; ++ dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; ++ dig->force_gaincode.lna_idx = LNA_IDX_MAX; ++ dig->force_gaincode.tia_idx = TIA_IDX_MAX; ++ dig->force_gaincode.rxb_idx = RXB_IDX_MAX; ++ ++ dig->dyn_igi_max = igi_max_performance_mode; ++ dig->dyn_igi_min = dynamic_igi_min; ++ dig->dyn_pd_th_max = dynamic_pd_threshold_max; ++ dig->pd_low_th_ofst = pd_low_th_offset; ++ dig->is_linked_pre = false; ++} ++ ++static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_dig_update_gain_para(rtwdev); ++ rtw89_phy_dig_reset(rtwdev); ++} ++ ++static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u8 lna_idx; ++ ++ if (rssi < dig->igi_rssi_th[0]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX6; ++ else if (rssi < dig->igi_rssi_th[1]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX5; ++ else if (rssi < dig->igi_rssi_th[2]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX4; ++ else if (rssi < dig->igi_rssi_th[3]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX3; ++ else if (rssi < dig->igi_rssi_th[4]) ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX2; ++ else ++ lna_idx = RTW89_DIG_GAIN_LNA_IDX1; ++ ++ return lna_idx; ++} ++ ++static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u8 tia_idx; ++ ++ if (rssi < dig->igi_rssi_th[0]) ++ tia_idx = RTW89_DIG_GAIN_TIA_IDX1; ++ else ++ tia_idx = RTW89_DIG_GAIN_TIA_IDX0; ++ ++ return tia_idx; ++} ++ ++#define IB_PBK_BASE 110 ++#define WB_RSSI_BASE 10 ++static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, ++ struct rtw89_agc_gaincode_set *set) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ s8 lna_gain = dig->lna_gain[set->lna_idx]; ++ s8 tia_gain = dig->tia_gain[set->tia_idx]; ++ s32 wb_rssi = rssi + lna_gain + tia_gain; ++ s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; ++ u8 rxb_idx; ++ ++ rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; ++ rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", ++ wb_rssi, rxb_idx_tmp); ++ ++ return rxb_idx; ++} ++ ++static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, ++ struct rtw89_agc_gaincode_set *set) ++{ ++ set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); ++ set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); ++ set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", ++ rssi, set->lna_idx, set->tia_idx, set->rxb_idx); ++} ++ ++#define IGI_OFFSET_MAX 25 ++#define IGI_OFFSET_MUL 2 ++static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; ++ enum rtw89_dig_noisy_level noisy_lv; ++ u8 igi_offset = dig->fa_rssi_ofst; ++ u16 fa_ratio = 0; ++ ++ fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; ++ ++ if (fa_ratio < dig->fa_th[0]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL0; ++ else if (fa_ratio < dig->fa_th[1]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL1; ++ else if (fa_ratio < dig->fa_th[2]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL2; ++ else if (fa_ratio < dig->fa_th[3]) ++ noisy_lv = RTW89_DIG_NOISY_LEVEL3; ++ else ++ noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; ++ ++ if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) ++ igi_offset = 0; ++ else ++ igi_offset += noisy_lv * IGI_OFFSET_MUL; ++ ++ igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); ++ dig->fa_rssi_ofst = igi_offset; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", ++ dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", ++ env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, ++ env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, ++ noisy_lv, igi_offset); ++} ++ ++static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, ++ B_PATH0_LNA_INIT_IDX_MSK, lna_idx); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, ++ B_PATH1_LNA_INIT_IDX_MSK, lna_idx); ++} ++ ++static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, ++ B_PATH0_TIA_INIT_IDX_MSK, tia_idx); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, ++ B_PATH1_TIA_INIT_IDX_MSK, tia_idx); ++} ++ ++static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, ++ B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, ++ B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); ++} ++ ++static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, ++ const struct rtw89_agc_gaincode_set set) ++{ ++ rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); ++ rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); ++ rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", ++ set.lna_idx, set.tia_idx, set.rxb_idx); ++} ++ ++static const struct rtw89_reg_def sdagc_config[4] = { ++ {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++ {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++ {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++ {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, ++}; ++ ++static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, ++ bool enable) ++{ ++ u8 i = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) ++ rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, ++ sdagc_config[i].mask, enable); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); ++} ++ ++static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, ++ bool enable) ++{ ++ enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width; ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; ++ u32 val = 0; ++ ++ under_region += PD_TH_SB_FLTR_CMP_VAL; ++ ++ switch (cbw) { ++ case RTW89_CHANNEL_WIDTH_40: ++ under_region += PD_TH_BW40_CMP_VAL; ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ under_region += PD_TH_BW80_CMP_VAL; ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ fallthrough; ++ default: ++ under_region += PD_TH_BW20_CMP_VAL; ++ break; ++ } ++ ++ dig->dyn_pd_th_max = dig->igi_rssi; ++ ++ final_rssi = min_t(u8, rssi, dig->igi_rssi); ++ final_rssi = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, ++ PD_TH_MAX_RSSI + under_region); ++ ++ if (enable) { ++ val = (final_rssi - under_region - PD_TH_MIN_RSSI) >> 1; ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "dyn_max=%d, final_rssi=%d, total=%d, PD_low=%d\n", ++ dig->igi_rssi, final_rssi, under_region, val); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "Dynamic PD th dsiabled, Set PD_low_bd=0\n"); ++ } ++ ++ rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, ++ val); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, ++ B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); ++} ++ ++void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ ++ dig->bypass_dig = false; ++ rtw89_phy_dig_para_reset(rtwdev); ++ rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); ++ rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); ++ rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); ++ rtw89_phy_dig_update_para(rtwdev); ++} ++ ++#define IGI_RSSI_MIN 10 ++void rtw89_phy_dig(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dig_info *dig = &rtwdev->dig; ++ bool is_linked = rtwdev->total_sta_assoc > 0; ++ ++ if (unlikely(dig->bypass_dig)) { ++ dig->bypass_dig = false; ++ return; ++ } ++ ++ if (!dig->is_linked_pre && is_linked) { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); ++ rtw89_phy_dig_update_para(rtwdev); ++ } else if (dig->is_linked_pre && !is_linked) { ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); ++ rtw89_phy_dig_update_para(rtwdev); ++ } ++ dig->is_linked_pre = is_linked; ++ ++ rtw89_phy_dig_igi_offset_by_env(rtwdev); ++ rtw89_phy_dig_update_rssi_info(rtwdev); ++ ++ dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? ++ dig->igi_rssi - IGI_RSSI_MIN : 0; ++ dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; ++ dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; ++ ++ dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, ++ dig->dyn_igi_max); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", ++ dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, ++ dig->igi_fa_rssi); ++ ++ if (dig->force_gaincode_idx_en) { ++ rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); ++ rtw89_debug(rtwdev, RTW89_DBG_DIG, ++ "Force gaincode index enabled.\n"); ++ } else { ++ rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, ++ &dig->cur_gaincode); ++ rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); ++ } ++ ++ rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); ++ ++ if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) ++ rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); ++ else ++ rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); ++} ++ ++static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_ccx_top_setting_init(rtwdev); ++ rtw89_phy_ifs_clm_setting_init(rtwdev); ++} ++ ++void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ ++ rtw89_phy_stat_init(rtwdev); ++ ++ rtw89_chip_bb_sethw(rtwdev); ++ ++ rtw89_phy_env_monitor_init(rtwdev); ++ rtw89_phy_dig_init(rtwdev); ++ rtw89_phy_cfo_init(rtwdev); ++ ++ rtw89_phy_init_rf_nctl(rtwdev); ++ rtw89_chip_rfk_init(rtwdev); ++ rtw89_load_txpwr_table(rtwdev, chip->byr_table); ++ rtw89_chip_set_txpwr_ctrl(rtwdev); ++ rtw89_chip_power_trim(rtwdev); ++} ++ ++void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) ++{ ++ enum rtw89_phy_idx phy_idx = RTW89_PHY_0; ++ u8 bss_color; ++ ++ if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) ++ return; ++ ++ bss_color = vif->bss_conf.he_bss_color.color; ++ ++ rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, ++ vif->bss_conf.aid, phy_idx); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h +new file mode 100644 +index 000000000000..370129345e0f +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/phy.h +@@ -0,0 +1,311 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_PHY_H__ ++#define __RTW89_PHY_H__ ++ ++#include "core.h" ++ ++#define RTW89_PHY_ADDR_OFFSET 0x10000 ++ ++#define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) ++#define PHY_HEADLINE_VALID 0xf ++#define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) ++#define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ ++ FIELD_PREP(GENMASK(7, 0), cv)) ++ ++#define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) ++#define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) ++#define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) ++#define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) ++#define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) ++#define PHY_COND_BRANCH_IF 0x8 ++#define PHY_COND_BRANCH_ELIF 0x9 ++#define PHY_COND_BRANCH_ELSE 0xa ++#define PHY_COND_BRANCH_END 0xb ++#define PHY_COND_CHECK 0x4 ++#define PHY_COND_DONT_CARE 0xff ++ ++#define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) ++#define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) ++#define RA_MASK_SUBCCK_RATES 0x5ULL ++#define RA_MASK_SUBOFDM_RATES 0x10ULL ++#define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) ++#define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) ++#define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) ++#define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) ++#define RA_MASK_HT_RATES GENMASK_ULL(55, 12) ++#define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) ++#define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) ++#define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) ++#define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) ++#define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) ++#define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) ++#define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) ++#define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) ++#define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) ++#define RA_MASK_HE_RATES GENMASK_ULL(59, 12) ++ ++#define CFO_TRK_ENABLE_TH (2 << 2) ++#define CFO_TRK_STOP_TH_4 (30 << 2) ++#define CFO_TRK_STOP_TH_3 (20 << 2) ++#define CFO_TRK_STOP_TH_2 (10 << 2) ++#define CFO_TRK_STOP_TH_1 (00 << 2) ++#define CFO_TRK_STOP_TH (2 << 2) ++#define CFO_SW_COMP_FINE_TUNE (2 << 2) ++#define CFO_PERIOD_CNT 15 ++#define CFO_TP_UPPER 100 ++#define CFO_TP_LOWER 50 ++#define CFO_COMP_PERIOD 250 ++#define CFO_COMP_WEIGHT 8 ++#define MAX_CFO_TOLERANCE 30 ++ ++#define CCX_MAX_PERIOD 2097 ++#define CCX_MAX_PERIOD_UNIT 32 ++#define MS_TO_4US_RATIO 250 ++#define ENV_MNTR_FAIL_DWORD 0xffffffff ++#define ENV_MNTR_IFSCLM_HIS_MAX 127 ++#define PERMIL 1000 ++#define PERCENT 100 ++#define IFS_CLM_TH0_UPPER 64 ++#define IFS_CLM_TH_MUL 4 ++#define IFS_CLM_TH_START_IDX 0 ++ ++#define TIA0_GAIN_A 12 ++#define TIA0_GAIN_G 16 ++#define LNA0_GAIN (-24) ++#define U4_MAX_BIT 3 ++#define U8_MAX_BIT 7 ++#define DIG_GAIN_SHIFT 2 ++#define DIG_GAIN 8 ++ ++#define LNA_IDX_MAX 6 ++#define LNA_IDX_MIN 0 ++#define TIA_IDX_MAX 1 ++#define TIA_IDX_MIN 0 ++#define RXB_IDX_MAX 31 ++#define RXB_IDX_MIN 0 ++ ++#define PD_TH_MAX_RSSI 70 ++#define PD_TH_MIN_RSSI 8 ++#define PD_TH_BW80_CMP_VAL 6 ++#define PD_TH_BW40_CMP_VAL 3 ++#define PD_TH_BW20_CMP_VAL 0 ++#define PD_TH_CMP_VAL 3 ++#define PD_TH_SB_FLTR_CMP_VAL 7 ++ ++#define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) ++#define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) ++#define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) ++#define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) ++#define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) ++ ++enum rtw89_phy_c2h_ra_func { ++ RTW89_PHY_C2H_FUNC_STS_RPT, ++ RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, ++ RTW89_PHY_C2H_FUNC_TXSTS, ++ RTW89_PHY_C2H_FUNC_RA_MAX, ++}; ++ ++enum rtw89_phy_c2h_class { ++ RTW89_PHY_C2H_CLASS_RUA, ++ RTW89_PHY_C2H_CLASS_RA, ++ RTW89_PHY_C2H_CLASS_DM, ++ RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, ++ RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, ++ RTW89_PHY_C2H_CLASS_MAX, ++}; ++ ++enum rtw89_env_monitor_result_level { ++ RTW89_PHY_ENV_MON_CCX_FAIL = 0, ++ RTW89_PHY_ENV_MON_NHM = BIT(0), ++ RTW89_PHY_ENV_MON_CLM = BIT(1), ++ RTW89_PHY_ENV_MON_FAHM = BIT(2), ++ RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), ++ RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), ++}; ++ ++#define CCX_US_BASE_RATIO 4 ++enum rtw89_ccx_unit { ++ RTW89_CCX_4_US = 0, ++ RTW89_CCX_8_US = 1, ++ RTW89_CCX_16_US = 2, ++ RTW89_CCX_32_US = 3 ++}; ++ ++enum rtw89_dig_gain_type { ++ RTW89_DIG_GAIN_LNA_G = 0, ++ RTW89_DIG_GAIN_TIA_G = 1, ++ RTW89_DIG_GAIN_LNA_A = 2, ++ RTW89_DIG_GAIN_TIA_A = 3, ++ RTW89_DIG_GAIN_MAX = 4 ++}; ++ ++enum rtw89_dig_gain_lna_idx { ++ RTW89_DIG_GAIN_LNA_IDX1 = 1, ++ RTW89_DIG_GAIN_LNA_IDX2 = 2, ++ RTW89_DIG_GAIN_LNA_IDX3 = 3, ++ RTW89_DIG_GAIN_LNA_IDX4 = 4, ++ RTW89_DIG_GAIN_LNA_IDX5 = 5, ++ RTW89_DIG_GAIN_LNA_IDX6 = 6 ++}; ++ ++enum rtw89_dig_gain_tia_idx { ++ RTW89_DIG_GAIN_TIA_IDX0 = 0, ++ RTW89_DIG_GAIN_TIA_IDX1 = 1 ++}; ++ ++struct rtw89_txpwr_byrate_cfg { ++ enum rtw89_band band; ++ enum rtw89_nss nss; ++ enum rtw89_rate_section rs; ++ u8 shf; ++ u8 len; ++ u32 data; ++}; ++ ++#define DELTA_SWINGIDX_SIZE 30 ++ ++struct rtw89_txpwr_track_cfg { ++ const u8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; ++ const u8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; ++ const u8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; ++ const u8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; ++ const u8 *delta_swingidx_2gb_n; ++ const u8 *delta_swingidx_2gb_p; ++ const u8 *delta_swingidx_2ga_n; ++ const u8 *delta_swingidx_2ga_p; ++ const u8 *delta_swingidx_2g_cck_b_n; ++ const u8 *delta_swingidx_2g_cck_b_p; ++ const u8 *delta_swingidx_2g_cck_a_n; ++ const u8 *delta_swingidx_2g_cck_a_p; ++}; ++ ++struct rtw89_phy_dig_gain_cfg { ++ const struct rtw89_reg_def *table; ++ u8 size; ++}; ++ ++struct rtw89_phy_dig_gain_table { ++ const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; ++ const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; ++ const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; ++ const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; ++}; ++ ++struct rtw89_phy_reg3_tbl { ++ const struct rtw89_reg3_def *reg3; ++ int size; ++}; ++ ++#define DECLARE_PHY_REG3_TBL(_name) \ ++const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ ++ .reg3 = _name, \ ++ .size = ARRAY_SIZE(_name), \ ++} ++ ++static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, ++ u32 addr, u8 data) ++{ ++ rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); ++} ++ ++static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, ++ u32 addr, u16 data) ++{ ++ rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); ++} ++ ++static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, ++ u32 addr, u32 data) ++{ ++ rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); ++} ++ ++static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, ++ u32 addr, u32 bits) ++{ ++ rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); ++} ++ ++static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, ++ u32 addr, u32 bits) ++{ ++ rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); ++} ++ ++static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, ++ u32 addr, u32 mask, u32 data) ++{ ++ rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); ++} ++ ++static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); ++} ++ ++static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); ++} ++ ++static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) ++{ ++ return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); ++} ++ ++static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, ++ u32 addr, u32 mask) ++{ ++ return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); ++} ++ ++void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, ++ const struct rtw89_phy_reg3_tbl *tbl); ++u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ enum rtw89_bandwidth dbw); ++u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask); ++bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, ++ u32 addr, u32 mask, u32 data); ++void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); ++void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev); ++void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); ++void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 data, enum rtw89_phy_idx phy_idx); ++void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_txpwr_table *tbl); ++s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, ++ const struct rtw89_rate_desc *rate_desc); ++void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit *lmt, ++ u8 ntx); ++void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ struct rtw89_txpwr_limit_ru *lmt_ru, ++ u8 ntx); ++s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, ++ u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); ++void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); ++void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); ++void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); ++void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, ++ struct ieee80211_vif *vif, ++ const struct cfg80211_bitrate_mask *mask); ++void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, ++ u32 len, u8 class, u8 func); ++void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); ++void rtw89_phy_cfo_track_work(struct work_struct *work); ++void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, ++ struct rtw89_rx_phy_ppdu *phy_ppdu); ++void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); ++void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); ++void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, ++ u32 val); ++void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); ++void rtw89_phy_dig(struct rtw89_dev *rtwdev); ++void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/ps.c b/drivers/net/wireless/realtek/rtw89/ps.c +new file mode 100644 +index 000000000000..7eaa01e41ef2 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ps.c +@@ -0,0 +1,150 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "core.h" ++#include "debug.h" ++#include "fw.h" ++#include "mac.h" ++#include "ps.h" ++#include "reg.h" ++#include "util.h" ++ ++static int rtw89_fw_leave_lps_check(struct rtw89_dev *rtwdev, u8 macid) ++{ ++ u32 pwr_en_bit = 0xE; ++ u32 chk_msk = pwr_en_bit << (4 * macid); ++ u32 polling; ++ int ret; ++ ++ ret = read_poll_timeout_atomic(rtw89_read32_mask, polling, !polling, ++ 1000, 50000, false, rtwdev, ++ R_AX_PPWRBIT_SETTING, chk_msk); ++ if (ret) { ++ rtw89_info(rtwdev, "rtw89: failed to leave lps state\n"); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ if (!rtwdev->ps_mode) ++ return; ++ ++ if (test_and_set_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) ++ return; ++ ++ rtw89_mac_power_mode_change(rtwdev, true); ++} ++ ++void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ if (!rtwdev->ps_mode) ++ return; ++ ++ if (test_and_clear_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) ++ rtw89_mac_power_mode_change(rtwdev, false); ++} ++ ++static void __rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id) ++{ ++ struct rtw89_lps_parm lps_param = { ++ .macid = mac_id, ++ .psmode = RTW89_MAC_AX_PS_MODE_LEGACY, ++ .lastrpwm = RTW89_LAST_RPWM_PS, ++ }; ++ ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_FW_CTRL); ++ rtw89_fw_h2c_lps_parm(rtwdev, &lps_param); ++} ++ ++static void __rtw89_leave_lps(struct rtw89_dev *rtwdev, u8 mac_id) ++{ ++ struct rtw89_lps_parm lps_param = { ++ .macid = mac_id, ++ .psmode = RTW89_MAC_AX_PS_MODE_ACTIVE, ++ .lastrpwm = RTW89_LAST_RPWM_ACTIVE, ++ }; ++ ++ rtw89_fw_h2c_lps_parm(rtwdev, &lps_param); ++ rtw89_fw_leave_lps_check(rtwdev, 0); ++ rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); ++} ++ ++void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev) ++{ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ __rtw89_leave_ps_mode(rtwdev); ++} ++ ++void rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id) ++{ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (test_and_set_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) ++ return; ++ ++ __rtw89_enter_lps(rtwdev, mac_id); ++ __rtw89_enter_ps_mode(rtwdev); ++} ++ ++static void rtw89_leave_lps_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) ++ return; ++ ++ __rtw89_leave_ps_mode(rtwdev); ++ __rtw89_leave_lps(rtwdev, rtwvif->mac_id); ++} ++ ++void rtw89_leave_lps(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (!test_and_clear_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) ++ return; ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_leave_lps_vif(rtwdev, rtwvif); ++} ++ ++void rtw89_enter_ips(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ set_bit(RTW89_FLAG_INACTIVE_PS, rtwdev->flags); ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_mac_vif_deinit(rtwdev, rtwvif); ++ ++ rtw89_core_stop(rtwdev); ++} ++ ++void rtw89_leave_ips(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ int ret; ++ ++ ret = rtw89_core_start(rtwdev); ++ if (ret) ++ rtw89_err(rtwdev, "failed to leave idle state\n"); ++ ++ rtw89_set_channel(rtwdev); ++ ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ rtw89_mac_vif_init(rtwdev, rtwvif); ++ ++ clear_bit(RTW89_FLAG_INACTIVE_PS, rtwdev->flags); ++} ++ ++void rtw89_set_coex_ctrl_lps(struct rtw89_dev *rtwdev, bool btc_ctrl) ++{ ++ if (btc_ctrl) ++ rtw89_leave_lps(rtwdev); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/ps.h b/drivers/net/wireless/realtek/rtw89/ps.h +new file mode 100644 +index 000000000000..a184b68994aa +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ps.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_PS_H_ ++#define __RTW89_PS_H_ ++ ++void rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id); ++void rtw89_leave_lps(struct rtw89_dev *rtwdev); ++void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev); ++void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev); ++void rtw89_enter_ips(struct rtw89_dev *rtwdev); ++void rtw89_leave_ips(struct rtw89_dev *rtwdev); ++void rtw89_set_coex_ctrl_lps(struct rtw89_dev *rtwdev, bool btc_ctrl); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h +new file mode 100644 +index 000000000000..365d8c8ce57b +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/reg.h +@@ -0,0 +1,2159 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_REG_H__ ++#define __RTW89_REG_H__ ++ ++#define R_AX_SYS_WL_EFUSE_CTRL 0x000A ++#define B_AX_AUTOLOAD_SUS BIT(5) ++ ++#define R_AX_SYS_FUNC_EN 0x0002 ++#define B_AX_FEN_BB_GLB_RSTN BIT(1) ++#define B_AX_FEN_BBRSTB BIT(0) ++ ++#define R_AX_SYS_PW_CTRL 0x0004 ++#define B_AX_PSUS_OFF_CAPC_EN BIT(14) ++ ++#define R_AX_SYS_CLK_CTRL 0x0008 ++#define B_AX_CPU_CLK_EN BIT(14) ++ ++#define R_AX_RSV_CTRL 0x001C ++#define B_AX_R_DIS_PRST BIT(6) ++#define B_AX_WLOCK_1C_BIT6 BIT(5) ++ ++#define R_AX_EFUSE_CTRL_1 0x0038 ++#define B_AX_EF_PGPD_MASK GENMASK(30, 28) ++#define B_AX_EF_RDT BIT(27) ++#define B_AX_EF_VDDQST_MASK GENMASK(26, 24) ++#define B_AX_EF_PGTS_MASK GENMASK(23, 20) ++#define B_AX_EF_PD_DIS BIT(11) ++#define B_AX_EF_POR BIT(10) ++#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8) ++ ++#define R_AX_SPSLDO_ON_CTRL0 0x0200 ++#define B_AX_OCP_L1_MASK GENMASK(15, 13) ++ ++#define R_AX_EFUSE_CTRL 0x0030 ++#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30) ++#define B_AX_EF_RDY BIT(29) ++#define B_AX_EF_COMP_RESULT BIT(28) ++#define B_AX_EF_ADDR_MASK GENMASK(26, 16) ++#define B_AX_EF_DATA_MASK GENMASK(15, 0) ++ ++#define R_AX_GPIO_MUXCFG 0x0040 ++#define B_AX_BOOT_MODE BIT(19) ++#define B_AX_WL_EECS_EXT_32K_SEL BIT(18) ++#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17) ++#define B_AX_SECSIC_SEL BIT(16) ++#define B_AX_ENHTP BIT(14) ++#define B_AX_BT_AOD_GPIO3 BIT(13) ++#define B_AX_ENSIC BIT(12) ++#define B_AX_SIC_SWRST BIT(11) ++#define B_AX_PO_WIFI_PTA_PINS BIT(10) ++#define B_AX_PO_BT_PTA_PINS BIT(9) ++#define B_AX_ENUARTTX BIT(8) ++#define B_AX_BTMODE_MASK GENMASK(7, 6) ++#define MAC_AX_BT_MODE_0_3 0 ++#define MAC_AX_BT_MODE_2 2 ++#define B_AX_ENBT BIT(5) ++#define B_AX_EROM_EN BIT(4) ++#define B_AX_ENUARTRX BIT(2) ++#define B_AX_GPIOSEL_MASK GENMASK(1, 0) ++ ++#define R_AX_DBG_CTRL 0x0058 ++#define B_AX_DBG_SEL1_4BIT GENMASK(31, 30) ++#define B_AX_DBG_SEL1_16BIT BIT(27) ++#define B_AX_DBG_SEL1 GENMASK(23, 16) ++#define B_AX_DBG_SEL0_4BIT GENMASK(15, 14) ++#define B_AX_DBG_SEL0_16BIT BIT(11) ++#define B_AX_DBG_SEL0 GENMASK(7, 0) ++ ++#define R_AX_SYS_SDIO_CTRL 0x0070 ++#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15) ++#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14) ++#define B_AX_PCIE_AUXCLK_GATE BIT(11) ++#define B_AX_LTE_MUX_CTRL_PATH BIT(26) ++ ++#define R_AX_PLATFORM_ENABLE 0x0088 ++#define B_AX_WCPU_EN BIT(1) ++ ++#define R_AX_SCOREBOARD 0x00AC ++#define B_AX_TOGGLE BIT(31) ++#define B_MAC_AX_SB_FW_MASK GENMASK(30, 24) ++#define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0) ++#define B_MAC_AX_BTGS1_NOTIFY BIT(0) ++#define MAC_AX_NOTIFY_TP_MAJOR 0x81 ++#define MAC_AX_NOTIFY_PWR_MAJOR 0x80 ++ ++#define R_AX_DBG_PORT_SEL 0x00C0 ++#define B_AX_DEBUG_ST_MASK GENMASK(31, 0) ++ ++#define R_AX_SYS_CFG1 0x00F0 ++#define B_AX_CHIP_VER_MASK GENMASK(15, 12) ++ ++#define R_AX_SYS_STATUS1 0x00F4 ++#define B_AX_SEL_0XC0_MASK GENMASK(17, 16) ++ ++#define R_AX_HALT_H2C_CTRL 0x0160 ++#define R_AX_HALT_H2C 0x0168 ++#define B_AX_HALT_H2C_TRIGGER BIT(0) ++#define R_AX_HALT_C2H_CTRL 0x0164 ++#define R_AX_HALT_C2H 0x016C ++ ++#define R_AX_WCPU_FW_CTRL 0x01E0 ++#define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5) ++#define B_AX_FWDL_PATH_RDY BIT(2) ++#define B_AX_H2C_PATH_RDY BIT(1) ++#define B_AX_WCPU_FWDL_EN BIT(0) ++ ++#define R_AX_RPWM 0x01E4 ++#define R_AX_PCIE_HRPWM 0x10C0 ++#define PS_RPWM_TOGGLE BIT(15) ++#define PS_RPWM_ACK BIT(14) ++#define PS_RPWM_SEQ_NUM GENMASK(13, 12) ++#define PS_RPWM_STATE 0x7 ++#define RPWM_SEQ_NUM_MAX 3 ++#define PS_CPWM_SEQ_NUM GENMASK(13, 12) ++#define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8) ++#define PS_CPWM_STATE GENMASK(2, 0) ++#define CPWM_SEQ_NUM_MAX 3 ++ ++#define R_AX_BOOT_REASON 0x01E6 ++#define B_AX_BOOT_REASON_MASK GENMASK(2, 0) ++ ++#define R_AX_LDM 0x01E8 ++#define B_AX_EN_32K BIT(31) ++ ++#define R_AX_UDM0 0x01F0 ++#define R_AX_UDM1 0x01F4 ++#define R_AX_UDM2 0x01F8 ++#define R_AX_UDM3 0x01FC ++ ++#define R_AX_XTAL_ON_CTRL0 0x0280 ++#define B_AX_XTAL_SC_LPS BIT(31) ++#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17) ++#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10) ++#define B_AX_XTAL_SC_MASK GENMASK(6, 0) ++ ++#define R_AX_GPIO0_7_FUNC_SEL 0x02D0 ++ ++#define R_AX_WLRF_CTRL 0x02F0 ++#define B_AX_WLRF1_CTRL_7 BIT(15) ++#define B_AX_WLRF1_CTRL_1 BIT(9) ++#define B_AX_WLRF_CTRL_7 BIT(7) ++#define B_AX_WLRF_CTRL_1 BIT(1) ++ ++#define R_AX_IC_PWR_STATE 0x03F0 ++#define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16) ++#define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8) ++#define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6) ++#define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4) ++#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2) ++#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0) ++ ++#define R_AX_FILTER_MODEL_ADDR 0x0C04 ++ ++#define R_AX_PCIE_DBG_CTRL 0x11C0 ++#define B_AX_DBG_DUMMY_MASK GENMASK(23, 16) ++#define B_AX_DBG_SEL_MASK GENMASK(15, 13) ++#define B_AX_PCIE_DBG_SEL BIT(12) ++#define B_AX_MRD_TIMEOUT_EN BIT(10) ++#define B_AX_ASFF_FULL_NO_STK BIT(1) ++#define B_AX_EN_STUCK_DBG BIT(0) ++ ++#define R_AX_PHYREG_SET 0x8040 ++#define PHYREG_SET_ALL_CYCLE 0x8 ++ ++#define R_AX_HD0IMR 0x8110 ++#define B_AX_WDT_PTFM_INT_EN BIT(5) ++#define B_AX_CPWM_INT_EN BIT(2) ++#define B_AX_GT3_INT_EN BIT(1) ++#define B_AX_C2H_INT_EN BIT(0) ++#define R_AX_HD0ISR 0x8114 ++#define B_AX_C2H_INT BIT(0) ++ ++#define R_AX_H2CREG_DATA0 0x8140 ++#define R_AX_H2CREG_DATA1 0x8144 ++#define R_AX_H2CREG_DATA2 0x8148 ++#define R_AX_H2CREG_DATA3 0x814C ++#define R_AX_C2HREG_DATA0 0x8150 ++#define R_AX_C2HREG_DATA1 0x8154 ++#define R_AX_C2HREG_DATA2 0x8158 ++#define R_AX_C2HREG_DATA3 0x815C ++#define R_AX_H2CREG_CTRL 0x8160 ++#define B_AX_H2CREG_TRIGGER BIT(0) ++#define R_AX_C2HREG_CTRL 0x8164 ++#define B_AX_C2HREG_TRIGGER BIT(0) ++#define R_AX_CPWM 0x8170 ++ ++#define R_AX_HCI_FUNC_EN 0x8380 ++#define B_AX_HCI_RXDMA_EN BIT(1) ++#define B_AX_HCI_TXDMA_EN BIT(0) ++ ++#define R_AX_BOOT_DBG 0x83F0 ++ ++#define R_AX_DMAC_FUNC_EN 0x8400 ++#define B_AX_MAC_FUNC_EN BIT(30) ++#define B_AX_DMAC_FUNC_EN BIT(29) ++#define B_AX_MPDU_PROC_EN BIT(28) ++#define B_AX_WD_RLS_EN BIT(27) ++#define B_AX_DLE_WDE_EN BIT(26) ++#define B_AX_TXPKT_CTRL_EN BIT(25) ++#define B_AX_STA_SCH_EN BIT(24) ++#define B_AX_DLE_PLE_EN BIT(23) ++#define B_AX_PKT_BUF_EN BIT(22) ++#define B_AX_DMAC_TBL_EN BIT(21) ++#define B_AX_PKT_IN_EN BIT(20) ++#define B_AX_DLE_CPUIO_EN BIT(19) ++#define B_AX_DISPATCHER_EN BIT(18) ++#define B_AX_MAC_SEC_EN BIT(16) ++ ++#define R_AX_DMAC_CLK_EN 0x8404 ++#define B_AX_WD_RLS_CLK_EN BIT(27) ++#define B_AX_DLE_WDE_CLK_EN BIT(26) ++#define B_AX_TXPKT_CTRL_CLK_EN BIT(25) ++#define B_AX_STA_SCH_CLK_EN BIT(24) ++#define B_AX_DLE_PLE_CLK_EN BIT(23) ++#define B_AX_PKT_IN_CLK_EN BIT(20) ++#define B_AX_DLE_CPUIO_CLK_EN BIT(19) ++#define B_AX_DISPATCHER_CLK_EN BIT(18) ++#define B_AX_MAC_SEC_CLK_EN BIT(16) ++ ++#define PCI_LTR_IDLE_TIMER_1US 0 ++#define PCI_LTR_IDLE_TIMER_10US 1 ++#define PCI_LTR_IDLE_TIMER_100US 2 ++#define PCI_LTR_IDLE_TIMER_200US 3 ++#define PCI_LTR_IDLE_TIMER_400US 4 ++#define PCI_LTR_IDLE_TIMER_800US 5 ++#define PCI_LTR_IDLE_TIMER_1_6MS 6 ++#define PCI_LTR_IDLE_TIMER_3_2MS 7 ++#define PCI_LTR_IDLE_TIMER_R_ERR 0xFD ++#define PCI_LTR_IDLE_TIMER_DEF 0xFE ++#define PCI_LTR_IDLE_TIMER_IGNORE 0xFF ++ ++#define PCI_LTR_SPC_10US 0 ++#define PCI_LTR_SPC_100US 1 ++#define PCI_LTR_SPC_500US 2 ++#define PCI_LTR_SPC_1MS 3 ++#define PCI_LTR_SPC_R_ERR 0xFD ++#define PCI_LTR_SPC_DEF 0xFE ++#define PCI_LTR_SPC_IGNORE 0xFF ++ ++#define R_AX_LTR_CTRL_0 0x8410 ++#define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12) ++#define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) ++#define B_AX_APP_LTR_ACT BIT(5) ++#define B_AX_APP_LTR_IDLE BIT(4) ++#define B_AX_LTR_EN BIT(1) ++#define B_AX_LTR_HW_EN BIT(0) ++ ++#define R_AX_LTR_CTRL_1 0x8414 ++#define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16) ++#define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0) ++ ++#define R_AX_LTR_IDLE_LATENCY 0x8418 ++ ++#define R_AX_LTR_ACTIVE_LATENCY 0x841C ++ ++#define R_AX_SER_DBG_INFO 0x8424 ++#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28) ++ ++#define R_AX_DLE_EMPTY0 0x8430 ++#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) ++#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) ++#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) ++#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23) ++#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) ++#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) ++#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) ++#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) ++#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) ++#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) ++#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16) ++#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) ++#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) ++#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) ++#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) ++#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) ++#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) ++ ++#define R_AX_DMAC_ERR_ISR 0x8524 ++#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) ++#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) ++#define B_AX_DISPATCH_ERR_FLAG BIT(8) ++#define B_AX_PKTIN_ERR_FLAG BIT(7) ++#define B_AX_PLE_DLE_ERR_FLAG BIT(6) ++#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5) ++#define B_AX_WDE_DLE_ERR_FLAG BIT(4) ++#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3) ++#define B_AX_MPDU_ERR_FLAG BIT(2) ++#define B_AX_WSEC_ERR_FLAG BIT(1) ++#define B_AX_WDRLS_ERR_FLAG BIT(0) ++ ++#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800 ++#define B_AX_PL_PAGE_128B_SEL BIT(9) ++#define B_AX_WD_PAGE_64B_SEL BIT(8) ++#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804 ++#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808 ++#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C ++#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810 ++#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0) ++ ++#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850 ++#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7) ++#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2) ++ ++#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854 ++#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25) ++ ++#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858 ++ ++#define R_AX_HCI_FC_CTRL 0x8A00 ++#define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10) ++#define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8) ++#define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6) ++#define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4) ++#define B_AX_HCI_FC_CH12_EN BIT(3) ++#define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1) ++#define B_AX_HCI_FC_EN BIT(0) ++ ++#define R_AX_CH_PAGE_CTRL 0x8A04 ++#define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16) ++#define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0) ++ ++#define B_AX_MAX_PG_MASK GENMASK(28, 16) ++#define B_AX_MIN_PG_MASK GENMASK(12, 0) ++#define B_AX_GRP BIT(31) ++#define R_AX_ACH0_PAGE_CTRL 0x8A10 ++#define R_AX_ACH1_PAGE_CTRL 0x8A14 ++#define R_AX_ACH2_PAGE_CTRL 0x8A18 ++#define R_AX_ACH3_PAGE_CTRL 0x8A1C ++#define R_AX_ACH4_PAGE_CTRL 0x8A20 ++#define R_AX_ACH5_PAGE_CTRL 0x8A24 ++#define R_AX_ACH6_PAGE_CTRL 0x8A28 ++#define R_AX_ACH7_PAGE_CTRL 0x8A2C ++#define R_AX_CH8_PAGE_CTRL 0x8A30 ++#define R_AX_CH9_PAGE_CTRL 0x8A34 ++#define R_AX_CH10_PAGE_CTRL 0x8A38 ++#define R_AX_CH11_PAGE_CTRL 0x8A3C ++ ++#define B_AX_AVAL_PG_MASK GENMASK(27, 16) ++#define B_AX_USE_PG_MASK GENMASK(12, 0) ++#define R_AX_ACH0_PAGE_INFO 0x8A50 ++#define R_AX_ACH1_PAGE_INFO 0x8A54 ++#define R_AX_ACH2_PAGE_INFO 0x8A58 ++#define R_AX_ACH3_PAGE_INFO 0x8A5C ++#define R_AX_ACH4_PAGE_INFO 0x8A60 ++#define R_AX_ACH5_PAGE_INFO 0x8A64 ++#define R_AX_ACH6_PAGE_INFO 0x8A68 ++#define R_AX_ACH7_PAGE_INFO 0x8A6C ++#define R_AX_CH8_PAGE_INFO 0x8A70 ++#define R_AX_CH9_PAGE_INFO 0x8A74 ++#define R_AX_CH10_PAGE_INFO 0x8A78 ++#define R_AX_CH11_PAGE_INFO 0x8A7C ++#define R_AX_CH12_PAGE_INFO 0x8A80 ++ ++#define R_AX_PUB_PAGE_INFO3 0x8A8C ++#define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16) ++#define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_CTRL1 0x8A90 ++#define B_AX_PUBPG_G1_MASK GENMASK(28, 16) ++#define B_AX_PUBPG_G0_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_CTRL2 0x8A94 ++#define B_AX_PUBPG_ALL_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_INFO1 0x8A98 ++#define B_AX_G1_USE_PG_MASK GENMASK(28, 16) ++#define B_AX_G0_USE_PG_MASK GENMASK(12, 0) ++ ++#define R_AX_PUB_PAGE_INFO2 0x8A9C ++#define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0) ++ ++#define R_AX_WP_PAGE_CTRL1 0x8AA0 ++#define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16) ++#define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0) ++ ++#define R_AX_WP_PAGE_CTRL2 0x8AA4 ++#define B_AX_WP_THRD_MASK GENMASK(12, 0) ++ ++#define R_AX_WP_PAGE_INFO1 0x8AA8 ++#define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16) ++ ++#define R_AX_WDE_PKTBUF_CFG 0x8C08 ++#define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8) ++#define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0) ++#define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) ++#define R_AX_WDE_ERR_FLAG_CFG 0x8C34 ++#define R_AX_WDE_ERR_IMR 0x8C38 ++#define R_AX_WDE_ERR_ISR 0x8C3C ++ ++#define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16) ++#define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0) ++#define R_AX_WDE_QTA0_CFG 0x8C40 ++#define R_AX_WDE_QTA1_CFG 0x8C44 ++#define R_AX_WDE_QTA2_CFG 0x8C48 ++#define R_AX_WDE_QTA3_CFG 0x8C4C ++#define R_AX_WDE_QTA4_CFG 0x8C50 ++ ++#define B_AX_DLE_PUB_PGNUM GENMASK(12, 0) ++#define B_AX_DLE_FREE_HEADPG GENMASK(11, 0) ++#define B_AX_DLE_FREE_TAILPG GENMASK(27, 16) ++#define B_AX_DLE_USE_PGNUM GENMASK(27, 16) ++#define B_AX_DLE_RSV_PGNUM GENMASK(11, 0) ++#define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0) ++ ++#define R_AX_WDE_INI_STATUS 0x8D00 ++#define B_AX_WDE_Q_MGN_INI_RDY BIT(1) ++#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0) ++#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY) ++#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10 ++#define B_AX_WDE_DFI_ACTIVE BIT(31) ++#define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16) ++#define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0) ++#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14 ++#define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0) ++ ++#define R_AX_PLE_PKTBUF_CFG 0x9008 ++#define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8) ++#define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0) ++#define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16) ++#define R_AX_PLE_ERR_FLAG_CFG 0x9034 ++ ++#define R_AX_PLE_ERR_IMR 0x9038 ++#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5) ++ ++#define R_AX_PLE_ERR_FLAG_ISR 0x903C ++#define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16) ++#define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0) ++#define R_AX_PLE_QTA0_CFG 0x9040 ++#define R_AX_PLE_QTA1_CFG 0x9044 ++#define R_AX_PLE_QTA2_CFG 0x9048 ++#define R_AX_PLE_QTA3_CFG 0x904C ++#define R_AX_PLE_QTA4_CFG 0x9050 ++#define R_AX_PLE_QTA5_CFG 0x9054 ++#define R_AX_PLE_QTA6_CFG 0x9058 ++#define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16) ++#define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0) ++#define R_AX_PLE_QTA7_CFG 0x905C ++#define R_AX_PLE_QTA8_CFG 0x9060 ++#define R_AX_PLE_QTA9_CFG 0x9064 ++#define R_AX_PLE_QTA10_CFG 0x9068 ++ ++#define R_AX_PLE_INI_STATUS 0x9100 ++#define B_AX_PLE_Q_MGN_INI_RDY BIT(1) ++#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0) ++#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY) ++#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110 ++#define B_AX_PLE_DFI_ACTIVE BIT(31) ++#define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) ++#define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0) ++#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114 ++#define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0) ++ ++#define R_AX_WDRLS_CFG 0x9408 ++#define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8) ++#define B_AX_WDRLS_MODE_MASK GENMASK(1, 0) ++ ++#define R_AX_RLSRPT0_CFG0 0x9410 ++#define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24) ++#define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16) ++#define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8) ++#define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0) ++ ++#define R_AX_RLSRPT0_CFG1 0x9414 ++#define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16) ++#define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0) ++ ++#define R_AX_WDRLS_ERR_IMR 0x9430 ++#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) ++#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) ++#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) ++#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) ++#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) ++#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) ++#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) ++#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) ++#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) ++#define R_AX_WDRLS_ERR_ISR 0x9434 ++ ++#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C ++#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C ++#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C ++#define R_AX_LA_ERRFLAG 0x966C ++ ++#define R_AX_WD_BUF_REQ 0x9800 ++#define R_AX_PL_BUF_REQ 0x9820 ++#define B_AX_WD_BUF_REQ_EXEC BIT(31) ++#define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16) ++#define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0) ++ ++#define R_AX_WD_BUF_STATUS 0x9804 ++#define R_AX_PL_BUF_STATUS 0x9824 ++#define B_AX_WD_BUF_STAT_DONE BIT(31) ++#define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0) ++ ++#define R_AX_WD_CPUQ_OP_0 0x9810 ++#define R_AX_PL_CPUQ_OP_0 0x9830 ++#define B_AX_WD_CPUQ_OP_EXEC BIT(31) ++#define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) ++#define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16) ++#define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) ++ ++#define R_AX_WD_CPUQ_OP_1 0x9814 ++#define R_AX_PL_CPUQ_OP_1 0x9834 ++#define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22) ++#define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16) ++#define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6) ++#define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0) ++ ++#define R_AX_WD_CPUQ_OP_2 0x9818 ++#define R_AX_PL_CPUQ_OP_2 0x9838 ++#define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) ++#define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) ++ ++#define R_AX_WD_CPUQ_OP_STATUS 0x981C ++#define R_AX_PL_CPUQ_OP_STATUS 0x983C ++#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31) ++#define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0) ++#define R_AX_CPUIO_ERR_IMR 0x9840 ++#define R_AX_CPUIO_ERR_ISR 0x9844 ++ ++#define R_AX_SEC_ERR_IMR_ISR 0x991C ++ ++#define R_AX_PKTIN_SETTING 0x9A00 ++#define B_AX_WD_ADDR_INFO_LENGTH BIT(1) ++#define R_AX_PKTIN_ERR_IMR 0x9A20 ++#define R_AX_PKTIN_ERR_ISR 0x9A24 ++ ++#define R_AX_MPDU_TX_ERR_ISR 0x9BF0 ++#define R_AX_MPDU_TX_ERR_IMR 0x9BF4 ++ ++#define R_AX_MPDU_PROC 0x9C00 ++#define B_AX_A_ICV_ERR BIT(1) ++#define B_AX_APPEND_FCS BIT(0) ++ ++#define R_AX_ACTION_FWD0 0x9C04 ++#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95 ++ ++#define R_AX_TF_FWD 0x9C14 ++#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55 ++ ++#define R_AX_HW_RPT_FWD 0x9C18 ++#define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0) ++#define RTW89_PRPT_DEST_HOST 1 ++#define RTW89_PRPT_DEST_WLCPU 2 ++ ++#define R_AX_CUT_AMSDU_CTRL 0x9C40 ++#define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0 ++ ++#define R_AX_MPDU_RX_ERR_ISR 0x9CF0 ++#define R_AX_MPDU_RX_ERR_IMR 0x9CF4 ++ ++#define R_AX_SEC_ENG_CTRL 0x9D00 ++#define B_AX_TX_PARTIAL_MODE BIT(11) ++#define B_AX_CLK_EN_CGCMP BIT(10) ++#define B_AX_CLK_EN_WAPI BIT(9) ++#define B_AX_CLK_EN_WEP_TKIP BIT(8) ++#define B_AX_BMC_MGNT_DEC BIT(5) ++#define B_AX_UC_MGNT_DEC BIT(4) ++#define B_AX_MC_DEC BIT(3) ++#define B_AX_BC_DEC BIT(2) ++#define B_AX_SEC_RX_DEC BIT(1) ++#define B_AX_SEC_TX_ENC BIT(0) ++ ++#define R_AX_SEC_MPDU_PROC 0x9D04 ++#define B_AX_APPEND_ICV BIT(1) ++#define B_AX_APPEND_MIC BIT(0) ++ ++#define R_AX_SEC_CAM_ACCESS 0x9D10 ++#define R_AX_SEC_CAM_RDATA 0x9D14 ++#define R_AX_SEC_CAM_WDATA 0x9D18 ++#define R_AX_SEC_DEBUG 0x9D1C ++#define R_AX_SEC_TX_DEBUG 0x9D20 ++#define R_AX_SEC_RX_DEBUG 0x9D24 ++#define R_AX_SEC_TRX_PKT_CNT 0x9D28 ++#define R_AX_SEC_TRX_BLK_CNT 0x9D2C ++ ++#define R_AX_SS_CTRL 0x9E10 ++#define B_AX_SS_INIT_DONE_1 BIT(31) ++#define B_AX_SS_WARM_INIT_FLG BIT(29) ++#define B_AX_SS_EN BIT(0) ++ ++#define R_AX_SS_MACID_PAUSE_0 0x9EB0 ++#define B_AX_SS_MACID31_0_PAUSE_SH 0 ++#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_SS_MACID_PAUSE_1 0x9EB4 ++#define B_AX_SS_MACID63_32_PAUSE_SH 0 ++#define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_SS_MACID_PAUSE_2 0x9EB8 ++#define B_AX_SS_MACID95_64_PAUSE_SH 0 ++#define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_SS_MACID_PAUSE_3 0x9EBC ++#define B_AX_SS_MACID127_96_PAUSE_SH 0 ++#define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0) ++ ++#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0 ++#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4 ++ ++#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C ++#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C ++#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) ++#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) ++#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) ++#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) ++ ++#define R_AX_DBG_FUN_INTF_CTL 0x9F30 ++#define B_AX_DFI_ACTIVE BIT(31) ++#define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16) ++#define B_AX_DFI_ADDR_MASK GENMASK(15, 0) ++#define R_AX_DBG_FUN_INTF_DATA 0x9F34 ++#define B_AX_DFI_DATA_MASK GENMASK(31, 0) ++ ++#define R_AX_AFE_CTRL1 0x0024 ++ ++#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4) ++#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3) ++#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2) ++#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1) ++#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0) ++ ++#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080 ++#define B_AX_CMAC1_FEN BIT(30) ++#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17) ++#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16) ++#define B_AX_R_SYM_ISO_CMAC12PP BIT(5) ++ ++#define R_AX_CMAC_REG_START 0xC000 ++ ++#define R_AX_CMAC_FUNC_EN 0xC000 ++#define R_AX_CMAC_FUNC_EN_C1 0xE000 ++#define B_AX_CMAC_CRPRT BIT(31) ++#define B_AX_CMAC_EN BIT(30) ++#define B_AX_CMAC_TXEN BIT(29) ++#define B_AX_CMAC_RXEN BIT(28) ++#define B_AX_FORCE_CMACREG_GCKEN BIT(15) ++#define B_AX_PHYINTF_EN BIT(5) ++#define B_AX_CMAC_DMA_EN BIT(4) ++#define B_AX_PTCLTOP_EN BIT(3) ++#define B_AX_SCHEDULER_EN BIT(2) ++#define B_AX_TMAC_EN BIT(1) ++#define B_AX_RMAC_EN BIT(0) ++ ++#define R_AX_CK_EN 0xC004 ++#define R_AX_CK_EN_C1 0xE004 ++#define B_AX_CMAC_ALLCKEN GENMASK(31, 0) ++#define B_AX_CMAC_CKEN BIT(30) ++#define B_AX_PHYINTF_CKEN BIT(5) ++#define B_AX_CMAC_DMA_CKEN BIT(4) ++#define B_AX_PTCLTOP_CKEN BIT(3) ++#define B_AX_SCHEDULER_CKEN BIT(2) ++#define B_AX_TMAC_CKEN BIT(1) ++#define B_AX_RMAC_CKEN BIT(0) ++ ++#define R_AX_WMAC_RFMOD 0xC010 ++#define R_AX_WMAC_RFMOD_C1 0xE010 ++#define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0) ++ ++#define R_AX_GID_POSITION0 0xC070 ++#define R_AX_GID_POSITION0_C1 0xE070 ++#define R_AX_GID_POSITION1 0xC074 ++#define R_AX_GID_POSITION1_C1 0xE074 ++#define R_AX_GID_POSITION2 0xC078 ++#define R_AX_GID_POSITION2_C1 0xE078 ++#define R_AX_GID_POSITION3 0xC07C ++#define R_AX_GID_POSITION3_C1 0xE07C ++#define R_AX_GID_POSITION_EN0 0xC080 ++#define R_AX_GID_POSITION_EN0_C1 0xE080 ++#define R_AX_GID_POSITION_EN1 0xC084 ++#define R_AX_GID_POSITION_EN1_C1 0xE084 ++ ++#define R_AX_TX_SUB_CARRIER_VALUE 0xC088 ++#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088 ++#define B_AX_TXSC_80M_MASK GENMASK(11, 8) ++#define B_AX_TXSC_40M_MASK GENMASK(7, 4) ++#define B_AX_TXSC_20M_MASK GENMASK(3, 0) ++ ++#define R_AX_CMAC_ERR_ISR 0xC164 ++#define R_AX_CMAC_ERR_ISR_C1 0xE164 ++#define B_AX_WMAC_TX_ERR_IND BIT(7) ++#define B_AX_WMAC_RX_ERR_IND BIT(6) ++#define B_AX_TXPWR_CTRL_ERR_IND BIT(5) ++#define B_AX_PHYINTF_ERR_IND BIT(4) ++#define B_AX_DMA_TOP_ERR_IND BIT(3) ++#define B_AX_PTCL_TOP_ERR_IND BIT(1) ++#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0) ++ ++#define R_AX_MACID_SLEEP_0 0xC2C0 ++#define R_AX_MACID_SLEEP_0_C1 0xE2C0 ++#define B_AX_MACID31_0_SLEEP_SH 0 ++#define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0) ++ ++#define R_AX_MACID_SLEEP_1 0xC2C4 ++#define R_AX_MACID_SLEEP_1_C1 0xE2C4 ++#define B_AX_MACID63_32_SLEEP_SH 0 ++#define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0) ++ ++#define R_AX_MACID_SLEEP_2 0xC2C8 ++#define R_AX_MACID_SLEEP_2_C1 0xE2C8 ++#define B_AX_MACID95_64_SLEEP_SH 0 ++#define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0) ++ ++#define R_AX_MACID_SLEEP_3 0xC2CC ++#define R_AX_MACID_SLEEP_3_C1 0xE2CC ++#define B_AX_MACID127_96_SLEEP_SH 0 ++#define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0) ++ ++#define SCH_PREBKF_24US 0x18 ++#define R_AX_PREBKF_CFG_0 0xC338 ++#define R_AX_PREBKF_CFG_0_C1 0xE338 ++#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0) ++ ++#define R_AX_CCA_CFG_0 0xC340 ++#define R_AX_CCA_CFG_0_C1 0xE340 ++#define B_AX_BTCCA_BRK_TXOP_EN BIT(9) ++#define B_AX_BTCCA_EN BIT(5) ++#define B_AX_EDCCA_EN BIT(4) ++#define B_AX_SEC80_EN BIT(3) ++#define B_AX_SEC40_EN BIT(2) ++#define B_AX_SEC20_EN BIT(1) ++#define B_AX_CCA_EN BIT(0) ++ ++#define R_AX_CTN_TXEN 0xC348 ++#define R_AX_CTN_TXEN_C1 0xE348 ++#define B_AX_CTN_TXEN_TWT_1 BIT(15) ++#define B_AX_CTN_TXEN_TWT_0 BIT(14) ++#define B_AX_CTN_TXEN_ULQ BIT(13) ++#define B_AX_CTN_TXEN_BCNQ BIT(12) ++#define B_AX_CTN_TXEN_HGQ BIT(11) ++#define B_AX_CTN_TXEN_CPUMGQ BIT(10) ++#define B_AX_CTN_TXEN_MGQ1 BIT(9) ++#define B_AX_CTN_TXEN_MGQ BIT(8) ++#define B_AX_CTN_TXEN_VO_1 BIT(7) ++#define B_AX_CTN_TXEN_VI_1 BIT(6) ++#define B_AX_CTN_TXEN_BK_1 BIT(5) ++#define B_AX_CTN_TXEN_BE_1 BIT(4) ++#define B_AX_CTN_TXEN_VO_0 BIT(3) ++#define B_AX_CTN_TXEN_VI_0 BIT(2) ++#define B_AX_CTN_TXEN_BK_0 BIT(1) ++#define B_AX_CTN_TXEN_BE_0 BIT(0) ++ ++#define R_AX_MUEDCA_BE_PARAM_0 0xC350 ++#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350 ++#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16) ++#define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8) ++#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0) ++ ++#define R_AX_MUEDCA_BK_PARAM_0 0xC354 ++#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354 ++#define R_AX_MUEDCA_VI_PARAM_0 0xC358 ++#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358 ++#define R_AX_MUEDCA_VO_PARAM_0 0xC35C ++#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C ++ ++#define R_AX_MUEDCA_EN 0xC370 ++#define R_AX_MUEDCA_EN_C1 0xE370 ++#define B_AX_MUEDCA_WMM_SEL BIT(8) ++#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4) ++#define B_AX_MUEDCA_EN_0 BIT(0) ++ ++#define R_AX_CCA_CONTROL 0xC390 ++#define R_AX_CCA_CONTROL_C1 0xE390 ++#define B_AX_TB_CHK_TX_NAV BIT(31) ++#define B_AX_TB_CHK_BASIC_NAV BIT(30) ++#define B_AX_TB_CHK_BTCCA BIT(29) ++#define B_AX_TB_CHK_EDCCA BIT(28) ++#define B_AX_TB_CHK_CCA_S80 BIT(27) ++#define B_AX_TB_CHK_CCA_S40 BIT(26) ++#define B_AX_TB_CHK_CCA_S20 BIT(25) ++#define B_AX_TB_CHK_CCA_P20 BIT(24) ++#define B_AX_SIFS_CHK_BTCCA BIT(21) ++#define B_AX_SIFS_CHK_EDCCA BIT(20) ++#define B_AX_SIFS_CHK_CCA_S80 BIT(19) ++#define B_AX_SIFS_CHK_CCA_S40 BIT(18) ++#define B_AX_SIFS_CHK_CCA_S20 BIT(17) ++#define B_AX_SIFS_CHK_CCA_P20 BIT(16) ++#define B_AX_CTN_CHK_TXNAV BIT(8) ++#define B_AX_CTN_CHK_INTRA_NAV BIT(7) ++#define B_AX_CTN_CHK_BASIC_NAV BIT(6) ++#define B_AX_CTN_CHK_BTCCA BIT(5) ++#define B_AX_CTN_CHK_EDCCA BIT(4) ++#define B_AX_CTN_CHK_CCA_S80 BIT(3) ++#define B_AX_CTN_CHK_CCA_S40 BIT(2) ++#define B_AX_CTN_CHK_CCA_S20 BIT(1) ++#define B_AX_CTN_CHK_CCA_P20 BIT(0) ++ ++#define R_AX_SCHEDULE_ERR_IMR 0xC3E8 ++#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8 ++#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1) ++#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) ++ ++#define R_AX_SCHEDULE_ERR_ISR 0xC3EC ++#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC ++ ++#define R_AX_SCH_DBG_SEL 0xC3F4 ++#define R_AX_SCH_DBG_SEL_C1 0xE3F4 ++#define B_AX_SCH_DBG_EN BIT(16) ++#define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8) ++#define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0) ++ ++#define R_AX_SCH_DBG 0xC3F8 ++#define R_AX_SCH_DBG_C1 0xE3F8 ++#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0) ++ ++#define R_AX_PORT_CFG_P0 0xC400 ++#define R_AX_PORT_CFG_P1 0xC440 ++#define R_AX_PORT_CFG_P2 0xC480 ++#define R_AX_PORT_CFG_P3 0xC4C0 ++#define R_AX_PORT_CFG_P4 0xC500 ++#define B_AX_BRK_SETUP BIT(16) ++#define B_AX_TBTT_UPD_SHIFT_SEL BIT(15) ++#define B_AX_BCN_DROP_ALLOW BIT(14) ++#define B_AX_TBTT_PROHIB_EN BIT(13) ++#define B_AX_BCNTX_EN BIT(12) ++#define B_AX_NET_TYPE_MASK GENMASK(11, 10) ++#define B_AX_BCN_FORCETX_EN BIT(9) ++#define B_AX_TXBCN_BTCCA_EN BIT(8) ++#define B_AX_BCNERR_CNT_EN BIT(7) ++#define B_AX_BCN_AGRES BIT(6) ++#define B_AX_TSFTR_RST BIT(5) ++#define B_AX_RX_BSSID_FIT_EN BIT(4) ++#define B_AX_TSF_UDT_EN BIT(3) ++#define B_AX_PORT_FUNC_EN BIT(2) ++#define B_AX_TXBCN_RPT_EN BIT(1) ++#define B_AX_RXBCN_RPT_EN BIT(0) ++ ++#define R_AX_TBTT_PROHIB_P0 0xC404 ++#define R_AX_TBTT_PROHIB_P1 0xC444 ++#define R_AX_TBTT_PROHIB_P2 0xC484 ++#define R_AX_TBTT_PROHIB_P3 0xC4C4 ++#define R_AX_TBTT_PROHIB_P4 0xC504 ++#define B_AX_TBTT_HOLD_MASK GENMASK(27, 16) ++#define B_AX_TBTT_SETUP_MASK GENMASK(7, 0) ++ ++#define R_AX_BCN_AREA_P0 0xC408 ++#define R_AX_BCN_AREA_P1 0xC448 ++#define R_AX_BCN_AREA_P2 0xC488 ++#define R_AX_BCN_AREA_P3 0xC4C8 ++#define R_AX_BCN_AREA_P4 0xC508 ++#define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16) ++#define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0) ++ ++#define R_AX_BCNERLYINT_CFG_P0 0xC40C ++#define R_AX_BCNERLYINT_CFG_P1 0xC44C ++#define R_AX_BCNERLYINT_CFG_P2 0xC48C ++#define R_AX_BCNERLYINT_CFG_P3 0xC4CC ++#define R_AX_BCNERLYINT_CFG_P4 0xC50C ++#define B_AX_BCNERLY_MASK GENMASK(11, 0) ++ ++#define R_AX_TBTTERLYINT_CFG_P0 0xC40E ++#define R_AX_TBTTERLYINT_CFG_P1 0xC44E ++#define R_AX_TBTTERLYINT_CFG_P2 0xC48E ++#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE ++#define R_AX_TBTTERLYINT_CFG_P4 0xC50E ++#define B_AX_TBTTERLY_MASK GENMASK(11, 0) ++ ++#define R_AX_TBTT_AGG_P0 0xC412 ++#define R_AX_TBTT_AGG_P1 0xC452 ++#define R_AX_TBTT_AGG_P2 0xC492 ++#define R_AX_TBTT_AGG_P3 0xC4D2 ++#define R_AX_TBTT_AGG_P4 0xC512 ++#define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8) ++ ++#define R_AX_BCN_SPACE_CFG_P0 0xC414 ++#define R_AX_BCN_SPACE_CFG_P1 0xC454 ++#define R_AX_BCN_SPACE_CFG_P2 0xC494 ++#define R_AX_BCN_SPACE_CFG_P3 0xC4D4 ++#define R_AX_BCN_SPACE_CFG_P4 0xC514 ++#define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16) ++#define B_AX_BCN_SPACE_MASK GENMASK(15, 0) ++ ++#define R_AX_BCN_FORCETX_P0 0xC418 ++#define R_AX_BCN_FORCETX_P1 0xC458 ++#define R_AX_BCN_FORCETX_P2 0xC498 ++#define R_AX_BCN_FORCETX_P3 0xC4D8 ++#define R_AX_BCN_FORCETX_P4 0xC518 ++#define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16) ++#define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0) ++#define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0) ++ ++#define R_AX_BCN_ERR_CNT_P0 0xC420 ++#define R_AX_BCN_ERR_CNT_P1 0xC460 ++#define R_AX_BCN_ERR_CNT_P2 0xC4A0 ++#define R_AX_BCN_ERR_CNT_P3 0xC4E0 ++#define R_AX_BCN_ERR_CNT_P4 0xC520 ++#define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24) ++#define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16) ++#define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0) ++#define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0) ++ ++#define R_AX_BCN_ERR_FLAG_P0 0xC424 ++#define R_AX_BCN_ERR_FLAG_P1 0xC464 ++#define R_AX_BCN_ERR_FLAG_P2 0xC4A4 ++#define R_AX_BCN_ERR_FLAG_P3 0xC4E4 ++#define R_AX_BCN_ERR_FLAG_P4 0xC524 ++#define B_AX_BCN_ERR_FLAG_OTHERS BIT(6) ++#define B_AX_BCN_ERR_FLAG_MAC BIT(5) ++#define B_AX_BCN_ERR_FLAG_TXON BIT(4) ++#define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3) ++#define B_AX_BCN_ERR_FLAG_INVALID BIT(2) ++#define B_AX_BCN_ERR_FLAG_CMP BIT(1) ++#define B_AX_BCN_ERR_FLAG_LOCK BIT(0) ++ ++#define R_AX_DTIM_CTRL_P0 0xC426 ++#define R_AX_DTIM_CTRL_P1 0xC466 ++#define R_AX_DTIM_CTRL_P2 0xC4A6 ++#define R_AX_DTIM_CTRL_P3 0xC4E6 ++#define R_AX_DTIM_CTRL_P4 0xC526 ++#define B_AX_DTIM_NUM_MASK GENMASK(15, 0) ++#define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0) ++ ++#define R_AX_TBTT_SHIFT_P0 0xC428 ++#define R_AX_TBTT_SHIFT_P1 0xC468 ++#define R_AX_TBTT_SHIFT_P2 0xC4A8 ++#define R_AX_TBTT_SHIFT_P3 0xC4E8 ++#define R_AX_TBTT_SHIFT_P4 0xC528 ++#define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0) ++ ++#define R_AX_BCN_CNT_TMR_P0 0xC434 ++#define R_AX_BCN_CNT_TMR_P1 0xC474 ++#define R_AX_BCN_CNT_TMR_P2 0xC4B4 ++#define R_AX_BCN_CNT_TMR_P3 0xC4F4 ++#define R_AX_BCN_CNT_TMR_P4 0xC534 ++#define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0) ++ ++#define R_AX_TSFTR_LOW_P0 0xC438 ++#define R_AX_TSFTR_LOW_P1 0xC478 ++#define R_AX_TSFTR_LOW_P2 0xC4B8 ++#define R_AX_TSFTR_LOW_P3 0xC4F8 ++#define R_AX_TSFTR_LOW_P4 0xC538 ++#define B_AX_TSFTR_LOW_MASK GENMASK(31, 0) ++ ++#define R_AX_TSFTR_HIGH_P0 0xC43C ++#define R_AX_TSFTR_HIGH_P1 0xC47C ++#define R_AX_TSFTR_HIGH_P2 0xC4BC ++#define R_AX_TSFTR_HIGH_P3 0xC4FC ++#define R_AX_TSFTR_HIGH_P4 0xC53C ++#define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0) ++ ++#define R_AX_MBSSID_CTRL 0xC568 ++#define R_AX_MBSSID_CTRL_C1 0xE568 ++#define B_AX_P0MB_ALL_MASK GENMASK(23, 1) ++#define B_AX_P0MB_NUM_MASK GENMASK(19, 16) ++#define B_AX_P0MB15_EN BIT(15) ++#define B_AX_P0MB14_EN BIT(14) ++#define B_AX_P0MB13_EN BIT(13) ++#define B_AX_P0MB12_EN BIT(12) ++#define B_AX_P0MB11_EN BIT(11) ++#define B_AX_P0MB10_EN BIT(10) ++#define B_AX_P0MB9_EN BIT(9) ++#define B_AX_P0MB8_EN BIT(8) ++#define B_AX_P0MB7_EN BIT(7) ++#define B_AX_P0MB6_EN BIT(6) ++#define B_AX_P0MB5_EN BIT(5) ++#define B_AX_P0MB4_EN BIT(4) ++#define B_AX_P0MB3_EN BIT(3) ++#define B_AX_P0MB2_EN BIT(2) ++#define B_AX_P0MB1_EN BIT(1) ++ ++#define R_AX_AMPDU_AGG_LIMIT 0xC610 ++#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24) ++#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) ++#define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) ++#define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0) ++ ++#define R_AX_AGG_LEN_HT_0 0xC614 ++#define R_AX_AGG_LEN_HT_0_C1 0xE614 ++#define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) ++#define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8) ++#define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0) ++ ++#define S_AX_CTS2S_TH_SEC_256B 1 ++#define R_AX_SIFS_SETTING 0xC624 ++#define R_AX_SIFS_SETTING_C1 0xE624 ++#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) ++#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) ++#define B_AX_HW_CTS2SELF_EN BIT(16) ++#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8 ++#define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) ++#define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) ++#define S_AX_CTS2S_TH_1K 4 ++ ++#define R_AX_TXRATE_CHK 0xC628 ++#define R_AX_TXRATE_CHK_C1 0xE628 ++#define B_AX_DEFT_RATE_MASK GENMASK(15, 7) ++#define B_AX_BAND_MODE BIT(4) ++#define B_AX_MAX_TXNSS_MASK GENMASK(3, 2) ++#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1) ++#define B_AX_CHECK_CCK_EN BIT(0) ++ ++#define R_AX_TXCNT 0xC62C ++#define R_AX_TXCNT_C1 0xE62C ++#define B_AX_ADD_TXCNT_BY BIT(31) ++#define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24) ++#define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16) ++ ++#define R_AX_MBSSID_DROP_0 0xC63C ++#define R_AX_MBSSID_DROP_0_C1 0xE63C ++#define B_AX_GI_LTF_FB_SEL BIT(30) ++#define B_AX_RATE_SEL_MASK GENMASK(29, 24) ++#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16) ++#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0) ++ ++#define R_AX_BT_PLT 0xC67C ++#define R_AX_BT_PLT_C1 0xE67C ++#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) ++#define B_AX_BT_PLT_RST BIT(9) ++#define B_AX_PLT_EN BIT(8) ++#define B_AX_RX_PLT_GNT_LTE_RX BIT(7) ++#define B_AX_RX_PLT_GNT_BT_RX BIT(6) ++#define B_AX_RX_PLT_GNT_BT_TX BIT(5) ++#define B_AX_RX_PLT_GNT_WL BIT(4) ++#define B_AX_TX_PLT_GNT_LTE_RX BIT(3) ++#define B_AX_TX_PLT_GNT_BT_RX BIT(2) ++#define B_AX_TX_PLT_GNT_BT_TX BIT(1) ++#define B_AX_TX_PLT_GNT_WL BIT(0) ++ ++#define R_AX_PTCL_BSS_COLOR_0 0xC6A0 ++#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0 ++#define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24) ++#define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16) ++#define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8) ++#define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0) ++ ++#define R_AX_PTCL_BSS_COLOR_1 0xC6A4 ++#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4 ++#define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0) ++ ++#define R_AX_PTCL_IMR0 0xC6C0 ++#define R_AX_PTCL_IMR0_C1 0xE6C0 ++#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28) ++#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23) ++ ++#define R_AX_PTCL_ISR0 0xC6C4 ++#define R_AX_PTCL_ISR0_C1 0xE6C4 ++ ++#define S_AX_PTCL_TO_2MS 0x3F ++#define R_AX_PTCL_FSM_MON 0xC6E8 ++#define R_AX_PTCL_FSM_MON_C1 0xE6E8 ++#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6) ++#define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) ++ ++#define R_AX_PTCL_TX_CTN_SEL 0xC6EC ++#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC ++#define B_AX_PTCL_TX_ON_STAT BIT(7) ++ ++#define R_AX_PTCL_DBG_INFO 0xC6F0 ++#define R_AX_PTCL_DBG_INFO_C1 0xE6F0 ++#define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0) ++#define R_AX_PTCL_DBG 0xC6F4 ++#define R_AX_PTCL_DBG_C1 0xE6F4 ++#define B_AX_PTCL_DBG_EN BIT(8) ++#define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0) ++ ++#define R_AX_DLE_CTRL 0xC800 ++#define R_AX_DLE_CTRL_C1 0xE800 ++#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23) ++#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15) ++#define R_AX_RXDMA_PKT_INFO_0 0xC814 ++#define R_AX_RXDMA_PKT_INFO_1 0xC818 ++#define R_AX_RXDMA_PKT_INFO_2 0xC81C ++ ++#define R_AX_TCR1 0xCA04 ++#define R_AX_TCR1_C1 0xEA04 ++#define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28) ++#define B_AX_TCR_CCK_LOCK_CLK BIT(27) ++#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26) ++#define B_AX_TCR_USTIME GENMASK(23, 16) ++#define B_AX_TCR_SMOOTH_VAL BIT(15) ++#define B_AX_TCR_SMOOTH_CTRL BIT(14) ++#define B_AX_CS_REQ_VAL BIT(13) ++#define B_AX_CS_REQ_SEL BIT(12) ++#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8) ++#define B_AX_TCR_TXTIMEOUT GENMASK(7, 0) ++ ++#define R_AX_PPWRBIT_SETTING 0xCA0C ++#define R_AX_PPWRBIT_SETTING_C1 0xEA0C ++ ++#define R_AX_MACTX_DBG_SEL_CNT 0xCA20 ++#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20 ++#define B_AX_MACTX_MPDU_CNT GENMASK(31, 24) ++#define B_AX_MACTX_DMA_CNT GENMASK(23, 16) ++#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11) ++#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10) ++#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9) ++#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8) ++#define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0) ++ ++#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4 ++#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4 ++#define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0) ++ ++#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8 ++#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8 ++#define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0) ++ ++#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC ++#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC ++#define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0) ++ ++#define R_AX_RSP_CHK_SIG 0xCC00 ++#define R_AX_RSP_CHK_SIG_C1 0xEC00 ++#define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) ++#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29) ++#define B_AX_RSP_CHK_BASIC_NAV BIT(21) ++#define B_AX_RSP_CHK_INTRA_NAV BIT(20) ++#define B_AX_RSP_CHK_TXNAV BIT(19) ++#define B_AX_TXDATA_END_PS_OPT BIT(18) ++#define B_AX_CHECK_SOUNDING_SEQ BIT(17) ++#define B_AX_RXBA_IGNOREA2 BIT(16) ++#define B_AX_ACKTO_CCK_MASK GENMASK(15, 8) ++#define B_AX_ACKTO_MASK GENMASK(7, 0) ++ ++#define R_AX_TRXPTCL_RESP_0 0xCC04 ++#define R_AX_TRXPTCL_RESP_0_C1 0xEC04 ++#define B_AX_WMAC_RESP_STBC_EN BIT(31) ++#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30) ++#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29) ++#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28) ++#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27) ++#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26) ++#define B_AX_RSP_CHK_BTCCA BIT(25) ++#define B_AX_RSP_CHK_EDCCA BIT(24) ++#define B_AX_RSP_CHK_CCA BIT(23) ++#define B_AX_WMAC_LDPC_EN BIT(22) ++#define B_AX_WMAC_SGIEN BIT(21) ++#define B_AX_WMAC_SPLCPEN BIT(20) ++#define B_AX_WMAC_BESP_EARLY_TXBA BIT(17) ++#define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8) ++#define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) ++#define WMAC_SPEC_SIFS_OFDM_52A 0x15 ++#define WMAC_SPEC_SIFS_OFDM_52B 0x11 ++#define WMAC_SPEC_SIFS_OFDM_52C 0x11 ++#define WMAC_SPEC_SIFS_CCK 0xA ++ ++#define R_AX_MAC_LOOPBACK 0xCC20 ++#define R_AX_MAC_LOOPBACK_C1 0xEC20 ++#define B_AX_MACLBK_EN BIT(0) ++ ++#define R_AX_RXTRIG_TEST_USER_2 0xCCB0 ++#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0 ++#define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24) ++#define B_AX_RXTRIG_RU26_DIS BIT(21) ++#define B_AX_RXTRIG_FCSCHK_EN BIT(20) ++#define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) ++#define B_AX_RXTRIG_EN BIT(16) ++#define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) ++ ++#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0 ++#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0 ++#define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0) ++ ++#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4 ++#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4 ++#define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0) ++ ++#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8 ++#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8 ++#define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0) ++ ++#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC ++#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC ++ ++#define R_AX_DBGSEL_TRXPTCL 0xCCF4 ++#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4 ++#define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0) ++ ++#define R_AX_PHYINFO_ERR_IMR 0xCCFC ++#define R_AX_PHYINFO_ERR_IMR_C1 0xECFC ++#define B_AX_CSI_ON_TIMEOUT BIT(29) ++#define B_AX_STS_ON_TIMEOUT BIT(28) ++#define B_AX_DATA_ON_TIMEOUT BIT(27) ++#define B_AX_OFDM_CCA_TIMEOUT BIT(26) ++#define B_AX_CCK_CCA_TIMEOUT BIT(25) ++#define B_AXC_PHY_TXON_TIMEOUT BIT(24) ++#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21) ++#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20) ++#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19) ++#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18) ++#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17) ++#define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16) ++#define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0) ++ ++#define R_AX_PHYINFO_ERR_ISR 0xCCFC ++#define R_AX_PHYINFO_ERR_ISR_C1 0xECFC ++ ++#define R_AX_BFMER_CTRL_0 0xCD78 ++#define R_AX_BFMER_CTRL_0_C1 0xED78 ++#define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24) ++#define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16) ++#define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8) ++#define B_AX_BFMER_NDP_BFEN BIT(2) ++#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0) ++ ++#define R_AX_BFMEE_RESP_OPTION 0xCD80 ++#define R_AX_BFMEE_RESP_OPTION_C1 0xED80 ++#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24) ++#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20) ++#define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17) ++#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16) ++#define BFRP_RX_STANDBY_TIMER 0x0 ++#define NDP_RX_STANDBY_TIMER 0xFF ++#define B_AX_BFMEE_HE_NDPA_EN BIT(2) ++#define B_AX_BFMEE_VHT_NDPA_EN BIT(1) ++#define B_AX_BFMEE_HT_NDPA_EN BIT(0) ++ ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88 ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88 ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94 ++#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94 ++#define B_AX_BFMEE_CSISEQ_SEL BIT(29) ++#define B_AX_BFMEE_BFPARAM_SEL BIT(28) ++#define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) ++#define B_AX_BFMEE_BF_PORT_SEL BIT(23) ++#define B_AX_BFMEE_USE_NSTS BIT(22) ++#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21) ++#define B_AX_BFMEE_CSI_GID_SEL BIT(20) ++#define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18) ++#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17) ++#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16) ++#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15) ++#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14) ++#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13) ++#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12) ++#define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) ++#define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) ++#define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) ++#define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) ++#define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) ++ ++#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C ++#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C ++#define CSI_RRSC_BMAP 0x29292911 ++ ++#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90 ++#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90 ++#define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16) ++#define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8) ++#define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0) ++#define CSI_INIT_RATE_HE 0x3 ++#define CSI_INIT_RATE_VHT 0x3 ++#define CSI_INIT_RATE_HT 0x3 ++ ++#define R_AX_RCR 0xCE00 ++#define R_AX_RCR_C1 0xEE00 ++#define B_AX_STOP_RX_IN BIT(11) ++#define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8) ++#define B_AX_CH_EN_MASK GENMASK(3, 0) ++ ++#define R_AX_DLK_PROTECT_CTL 0xCE02 ++#define R_AX_DLK_PROTECT_CTL_C1 0xEE02 ++#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) ++#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) ++ ++#define R_AX_PLCP_HDR_FLTR 0xCE04 ++#define R_AX_PLCP_HDR_FLTR_C1 0xEE04 ++#define B_AX_DIS_CHK_MIN_LEN BIT(8) ++#define B_AX_HE_SIGB_CRC_CHK BIT(6) ++#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5) ++#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4) ++#define B_AX_SIGA_CRC_CHK BIT(3) ++#define B_AX_LSIG_PARITY_CHK_EN BIT(2) ++#define B_AX_CCK_SIG_CHK BIT(1) ++#define B_AX_CCK_CRC_CHK BIT(0) ++ ++#define R_AX_RX_FLTR_OPT 0xCE20 ++#define R_AX_RX_FLTR_OPT_C1 0xEE20 ++#define B_AX_UID_FILTER_MASK GENMASK(31, 24) ++#define B_AX_UNSPT_FILTER_SH 22 ++#define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22) ++#define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) ++#define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f ++#define B_AX_A_FTM_REQ BIT(14) ++#define B_AX_A_ERR_PKT BIT(13) ++#define B_AX_A_UNSUP_PKT BIT(12) ++#define B_AX_A_CRC32_ERR BIT(11) ++#define B_AX_A_PWR_MGNT BIT(10) ++#define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8) ++#define B_AX_A_BCN_CHK_EN BIT(7) ++#define B_AX_A_MC_LIST_CAM_MATCH BIT(6) ++#define B_AX_A_BC_CAM_MATCH BIT(5) ++#define B_AX_A_UC_CAM_MATCH BIT(4) ++#define B_AX_A_MC BIT(3) ++#define B_AX_A_BC BIT(2) ++#define B_AX_A_A1_MATCH BIT(1) ++#define B_AX_SNIFFER_MODE BIT(0) ++#define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC | \ ++ B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH | \ ++ B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ | \ ++ u32_encode_bits(3, B_AX_UID_FILTER_MASK) | \ ++ B_AX_A_BCN_CHK_EN) ++#define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK) ++ ++#define R_AX_CTRL_FLTR 0xCE24 ++#define R_AX_CTRL_FLTR_C1 0xEE24 ++#define R_AX_MGNT_FLTR 0xCE28 ++#define R_AX_MGNT_FLTR_C1 0xEE28 ++#define R_AX_DATA_FLTR 0xCE2C ++#define R_AX_DATA_FLTR_C1 0xEE2C ++#define RX_FLTR_FRAME_DROP 0x00000000 ++#define RX_FLTR_FRAME_TO_HOST 0x55555555 ++#define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA ++ ++#define R_AX_ADDR_CAM_CTRL 0xCE34 ++#define R_AX_ADDR_CAM_CTRL_C1 0xEE34 ++#define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16) ++#define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) ++#define B_AX_ADDR_CAM_CLR BIT(8) ++#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2) ++#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1) ++#define B_AX_ADDR_CAM_EN BIT(0) ++ ++#define R_AX_RESPBA_CAM_CTRL 0xCE3C ++#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C ++#define B_AX_SSN_SEL BIT(2) ++ ++#define R_AX_PPDU_STAT 0xCE40 ++#define R_AX_PPDU_STAT_C1 0xEE40 ++#define B_AX_PPDU_STAT_RPT_TRIG BIT(8) ++#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5) ++#define B_AX_PPDU_STAT_RPT_A1M BIT(4) ++#define B_AX_APP_PLCP_HDR_RPT BIT(3) ++#define B_AX_APP_RX_CNT_RPT BIT(2) ++#define B_AX_APP_MAC_INFO_RPT BIT(1) ++#define B_AX_PPDU_STAT_RPT_EN BIT(0) ++ ++#define R_AX_RX_SR_CTRL 0xCE4A ++#define R_AX_RX_SR_CTRL_C1 0xEE4A ++#define B_AX_SR_EN BIT(0) ++ ++#define R_AX_RX_STATE_MONITOR 0xCEF0 ++#define R_AX_RX_STATE_MONITOR_C1 0xEEF0 ++#define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0) ++#define B_AX_STATE_CUR_MASK GENMASK(31, 16) ++#define B_AX_STATE_NXT_MASK GENMASK(13, 8) ++#define B_AX_STATE_UPD BIT(7) ++#define B_AX_STATE_SEL_MASK GENMASK(4, 0) ++ ++#define R_AX_RMAC_ERR_ISR 0xCEF4 ++#define R_AX_RMAC_ERR_ISR_C1 0xEEF4 ++#define B_AX_RXERR_INTPS_EN BIT(31) ++#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19) ++#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18) ++#define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17) ++#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16) ++#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15) ++#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14) ++#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13) ++#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12) ++#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7) ++#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6) ++#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5) ++#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4) ++#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3) ++#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2) ++#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1) ++#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0) ++ ++#define R_AX_RMAC_PLCP_MON 0xCEF8 ++#define R_AX_RMAC_PLCP_MON_C1 0xEEF8 ++#define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0) ++#define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28) ++#define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0) ++ ++#define R_AX_RX_DEBUG_SELECT 0xCEFC ++#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC ++#define B_AX_DEBUG_SEL_MASK GENMASK(7, 0) ++ ++#define R_AX_PWR_RATE_CTRL 0xD200 ++#define R_AX_PWR_RATE_CTRL_C1 0xF200 ++#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) ++#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0) ++ ++#define R_AX_PWR_RATE_OFST_CTRL 0xD204 ++#define R_AX_PWR_COEXT_CTRL 0xD220 ++#define B_AX_TXAGC_BT_EN BIT(1) ++#define B_AX_TXAGC_BT_MASK GENMASK(11, 3) ++ ++#define R_AX_PWR_UL_CTRL0 0xD240 ++#define R_AX_PWR_UL_CTRL2 0xD248 ++#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0) ++#define B_AX_PWR_UL_CTRL2_MASK 0x07700007 ++#define R_AX_PWR_UL_TB_CTRL 0xD288 ++#define B_AX_PWR_UL_TB_CTRL_EN BIT(31) ++#define R_AX_PWR_UL_TB_1T 0xD28C ++#define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0) ++#define R_AX_PWR_UL_TB_2T 0xD290 ++#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) ++#define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 ++#define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 ++#define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0 ++#define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10 ++#define R_AX_PWR_LMT_TABLE0 0xD2EC ++#define R_AX_PWR_LMT_TABLE19 0xD338 ++#define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0 ++#define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19 ++#define R_AX_PWR_RU_LMT_TABLE0 0xD33C ++#define R_AX_PWR_RU_LMT_TABLE11 0xD368 ++#define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0 ++#define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11 ++#define R_AX_PWR_MACID_LMT_TABLE0 0xD36C ++#define R_AX_PWR_MACID_LMT_TABLE127 0xD568 ++ ++#define R_AX_TXPWR_IMR 0xD9E0 ++#define R_AX_TXPWR_IMR_C1 0xF9E0 ++#define R_AX_TXPWR_ISR 0xD9E4 ++#define R_AX_TXPWR_ISR_C1 0xF9E4 ++ ++#define R_AX_BTC_CFG 0xDA00 ++#define B_AX_DIS_BTC_CLK_G BIT(2) ++ ++#define R_AX_WL_PRI_MSK 0xDA10 ++#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8) ++ ++#define R_AX_BTC_FUNC_EN 0xDA20 ++#define R_AX_BTC_FUNC_EN_C1 0xFA20 ++#define B_AX_PTA_WL_TX_EN BIT(1) ++#define B_AX_PTA_EDCCA_EN BIT(0) ++ ++#define R_BTC_BREAK_TABLE 0xDA2C ++#define BTC_BREAK_PARAM 0xf0ffffff ++ ++#define R_BTC_BT_COEX_MSK_TABLE 0xDA30 ++#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) ++ ++#define R_AX_BT_COEX_CFG_2 0xDA34 ++#define R_AX_BT_COEX_CFG_2_C1 0xFA34 ++#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12) ++#define B_AX_GNT_BT_POLARITY BIT(8) ++#define B_AX_TIMER_MASK GENMASK(7, 0) ++#define MAC_AX_CSR_RATE 80 ++ ++#define R_AX_CSR_MODE 0xDA40 ++#define R_AX_CSR_MODE_C1 0xFA40 ++#define B_AX_BT_CNT_RST BIT(16) ++#define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12) ++#define MAC_AX_CSR_DELAY 0 ++#define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8) ++#define MAC_AX_CSR_TRX_TO 4 ++#define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4) ++#define MAC_AX_CSR_PRI_TO 5 ++#define B_AX_WL_ACT_MSK BIT(3) ++#define B_AX_STATIS_BT_EN BIT(2) ++#define B_AX_WL_ACT_MASK_ENABLE BIT(1) ++#define B_AX_ENHANCED_BT BIT(0) ++ ++#define R_AX_BT_STAST_HIGH 0xDA44 ++#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16) ++#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0) ++#define R_AX_BT_STAST_LOW 0xDA48 ++#define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0) ++#define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16) ++ ++#define R_AX_TDMA_MODE 0xDA4C ++#define R_AX_TDMA_MODE_C1 0xFA4C ++#define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16) ++#define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8) ++#define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6) ++#define B_AX_TDMA_BT_START_NOTIFY BIT(5) ++#define B_AX_ENABLE_TDMA_FW_MODE BIT(4) ++#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3) ++#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) ++#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) ++#define B_AX_RTK_BT_ENABLE BIT(0) ++ ++#define R_AX_BT_COEX_CFG_5 0xDA6C ++#define R_AX_BT_COEX_CFG_5_C1 0xFA6C ++#define B_AX_BT_TIME_MASK GENMASK(31, 6) ++#define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0) ++#define MAC_AX_RTK_RATE 5 ++ ++#define R_AX_LTE_CTRL 0xDAF0 ++#define R_AX_LTE_WDATA 0xDAF4 ++#define R_AX_LTE_RDATA 0xDAF8 ++ ++#define CMAC1_START_ADDR 0xE000 ++#define CMAC1_END_ADDR 0xFFFF ++#define R_AX_CMAC_REG_END 0xFFFF ++ ++#define R_AX_LTE_SW_CFG_1 0x0038 ++#define R_AX_LTE_SW_CFG_1_C1 0x2038 ++#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31) ++#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30) ++#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29) ++#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28) ++#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27) ++#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26) ++#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25) ++#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24) ++#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19) ++#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18) ++#define B_AX_LTE_PATTERN_2_EN BIT(17) ++#define B_AX_LTE_PATTERN_1_EN BIT(16) ++#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15) ++#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14) ++#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13) ++#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12) ++#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11) ++#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10) ++#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9) ++#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8) ++#define B_AX_LTECOEX_FUN_EN BIT(7) ++#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6) ++#define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4) ++#define B_AX_LTECOEX_UART_MUX BIT(3) ++#define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0) ++ ++#define R_AX_LTE_SW_CFG_2 0x003C ++#define R_AX_LTE_SW_CFG_2_C1 0x203C ++#define B_AX_WL_RX_CTRL BIT(8) ++#define B_AX_GNT_WL_RX_SW_VAL BIT(7) ++#define B_AX_GNT_WL_RX_SW_CTRL BIT(6) ++#define B_AX_GNT_WL_TX_SW_VAL BIT(5) ++#define B_AX_GNT_WL_TX_SW_CTRL BIT(4) ++#define B_AX_GNT_BT_RX_SW_VAL BIT(3) ++#define B_AX_GNT_BT_RX_SW_CTRL BIT(2) ++#define B_AX_GNT_BT_TX_SW_VAL BIT(1) ++#define B_AX_GNT_BT_TX_SW_CTRL BIT(0) ++ ++#define RR_MOD 0x00 ++#define RR_MOD_IQK GENMASK(19, 4) ++#define RR_MOD_DPK GENMASK(19, 5) ++#define RR_MOD_MASK GENMASK(19, 16) ++#define RR_MOD_V_DOWN 0x0 ++#define RR_MOD_V_STANDBY 0x1 ++#define RR_MOD_V_TX 0x2 ++#define RR_MOD_V_RX 0x3 ++#define RR_MOD_V_TXIQK 0x4 ++#define RR_MOD_V_DPK 0x5 ++#define RR_MOD_V_RXK1 0x6 ++#define RR_MOD_V_RXK2 0x7 ++#define RR_MOD_M_RXG GENMASK(13, 4) ++#define RR_MOD_M_RXBB GENMASK(9, 5) ++#define RR_MODOPT 0x01 ++#define RR_MODOPT_M_TXPWR GENMASK(5, 0) ++#define RR_WLSEL 0x02 ++#define RR_WLSEL_AG GENMASK(18, 16) ++#define RR_RSV1 0x05 ++#define RR_RSV1_RST BIT(0) ++#define RR_DTXLOK 0x08 ++#define RR_RSV2 0x09 ++#define RR_CFGCH 0x18 ++#define RR_BTC 0x1a ++#define RR_BTC_TXBB GENMASK(14, 12) ++#define RR_BTC_RXBB GENMASK(11, 10) ++#define RR_RCKC 0x1b ++#define RR_RCKC_CA GENMASK(14, 10) ++#define RR_RCKS 0x1c ++#define RR_RCKO 0x1d ++#define RR_RCKO_OFF GENMASK(13, 9) ++#define RR_RXKPLL 0x1e ++#define RR_RXKPLL_OFF GENMASK(5, 0) ++#define RR_RXKPLL_POW BIT(19) ++#define RR_RSV4 0x1f ++#define RR_RXK 0x20 ++#define RR_RXK_PLLEN BIT(5) ++#define RR_RXK_SEL5G BIT(7) ++#define RR_RXK_SEL2G BIT(8) ++#define RR_LUTWA 0x33 ++#define RR_LUTWA_MASK GENMASK(9, 0) ++#define RR_LUTWD1 0x3e ++#define RR_LUTWD0 0x3f ++#define RR_TM 0x42 ++#define RR_TM_TRI BIT(19) ++#define RR_TM_VAL GENMASK(6, 1) ++#define RR_TM2 0x43 ++#define RR_TM2_OFF GENMASK(19, 16) ++#define RR_TXG1 0x51 ++#define RR_TXG1_ATT2 BIT(19) ++#define RR_TXG1_ATT1 BIT(11) ++#define RR_TXG2 0x52 ++#define RR_TXG2_ATT0 BIT(11) ++#define RR_BSPAD 0x54 ++#define RR_TXGA 0x55 ++#define RR_TXGA_LOK_EN BIT(0) ++#define RR_TXGA_TRK_EN BIT(7) ++#define RR_GAINTX 0x56 ++#define RR_GAINTX_ALL GENMASK(15, 0) ++#define RR_GAINTX_PAD GENMASK(9, 5) ++#define RR_GAINTX_BB GENMASK(4, 0) ++#define RR_TXMO 0x58 ++#define RR_TXMO_COI GENMASK(19, 15) ++#define RR_TXMO_COQ GENMASK(14, 10) ++#define RR_TXMO_FII GENMASK(9, 6) ++#define RR_TXMO_FIQ GENMASK(5, 2) ++#define RR_TXA 0x5d ++#define RR_TXA_TRK GENMASK(19, 14) ++#define RR_TXRSV 0x5c ++#define RR_TXRSV_GAPK BIT(19) ++#define RR_BIAS 0x5e ++#define RR_BIAS_GAPK BIT(19) ++#define RR_BIASA 0x60 ++#define RR_BIASA_TXG GENMASK(15, 12) ++#define RR_BIASA_TXA GENMASK(19, 16) ++#define RR_BIASA_A GENMASK(2, 0) ++#define RR_BIASA2 0x63 ++#define RR_BIASA2_LB GENMASK(4, 2) ++#define RR_TXATANK 0x64 ++#define RR_TXATANK_LBSW GENMASK(16, 15) ++#define RR_TRXIQ 0x66 ++#define RR_RSV6 0x6d ++#define RR_TXPOW 0x7f ++#define RR_TXPOW_TXG BIT(1) ++#define RR_TXPOW_TXA BIT(8) ++#define RR_RXPOW 0x80 ++#define RR_RXPOW_IQK GENMASK(17, 16) ++#define RR_RXBB 0x83 ++#define RR_RXBB_C2G GENMASK(16, 10) ++#define RR_RXBB_C1G GENMASK(9, 8) ++#define RR_RXBB_ATTR GENMASK(7, 4) ++#define RR_RXBB_ATTC GENMASK(2, 0) ++#define RR_XGLNA2 0x85 ++#define RR_XGLNA2_SW GENMASK(1, 0) ++#define RR_RXA 0x8a ++#define RR_RXA_DPK GENMASK(9, 8) ++#define RR_RXA2 0x8c ++#define RR_RXA2_C2 GENMASK(9, 3) ++#define RR_RXA2_C1 GENMASK(12, 10) ++#define RR_RXIQGEN 0x8d ++#define RR_RXIQGEN_ATTL GENMASK(12, 8) ++#define RR_RXIQGEN_ATTH GENMASK(14, 13) ++#define RR_RXBB2 0x8f ++#define RR_EN_TIA_IDA GENMASK(11, 10) ++#define RR_RXBB2_DAC_EN BIT(13) ++#define RR_XALNA2 0x90 ++#define RR_XALNA2_SW GENMASK(1, 0) ++#define RR_DCK 0x92 ++#define RR_DCK_FINE BIT(1) ++#define RR_DCK_LV BIT(0) ++#define RR_DCK1 0x93 ++#define RR_DCK1_SEL BIT(3) ++#define RR_DCK2 0x94 ++#define RR_DCK2_CYCLE GENMASK(7, 2) ++#define RR_MIXER 0x9f ++#define RR_MIXER_GN GENMASK(4, 3) ++#define RR_XTALX2 0xb8 ++#define RR_MALSEL 0xbe ++#define RR_RCKD 0xde ++#define RR_RCKD_POW GENMASK(19, 13) ++#define RR_RCKD_BW BIT(2) ++#define RR_TXADBG 0xde ++#define RR_LUTDBG 0xdf ++#define RR_LUTDBG_LOK BIT(2) ++#define RR_LUTWE2 0xee ++#define RR_LUTWE 0xef ++#define RR_LUTWE_LOK BIT(2) ++#define RR_RFC 0xf0 ++#define RR_RFC_CKEN BIT(1) ++ ++#define R_UPD_P0 0x0000 ++#define R_RSTB_WATCH_DOG 0x000C ++#define B_P0_RSTB_WATCH_DOG BIT(0) ++#define B_P1_RSTB_WATCH_DOG BIT(1) ++#define B_UPD_P0_EN BIT(30) ++#define R_ANAPAR_PW15 0x030C ++#define B_ANAPAR_PW15 GENMASK(31, 24) ++#define B_ANAPAR_PW15_H GENMASK(27, 24) ++#define B_ANAPAR_PW15_H2 GENMASK(27, 26) ++#define R_ANAPAR 0x032C ++#define B_ANAPAR_15 GENMASK(31, 16) ++#define B_ANAPAR_ADCCLK BIT(30) ++#define B_ANAPAR_FLTRST BIT(22) ++#define B_ANAPAR_CRXBB GENMASK(18, 16) ++#define B_ANAPAR_14 GENMASK(15, 0) ++#define R_UPD_CLK_ADC 0x0700 ++#define B_UPD_CLK_ADC_ON BIT(24) ++#define B_UPD_CLK_ADC_VAL GENMASK(26, 25) ++#define R_RSTB_ASYNC 0x0704 ++#define B_RSTB_ASYNC_ALL BIT(1) ++#define R_PMAC_GNT 0x0980 ++#define B_PMAC_GNT_TXEN BIT(0) ++#define B_PMAC_GNT_RXEN BIT(16) ++#define B_PMAC_GNT_P1 GENMASK(20, 17) ++#define B_PMAC_GNT_P2 GENMASK(29, 26) ++#define R_PMAC_RX_CFG1 0x0988 ++#define B_PMAC_OPT1_MSK GENMASK(11, 0) ++#define R_PMAC_RXMOD 0x0994 ++#define B_PMAC_RXMOD_MSK GENMASK(7, 4) ++#define R_MAC_SEL 0x09A4 ++#define B_MAC_SEL_MOD GENMASK(4, 2) ++#define B_MAC_SEL_DPD_EN BIT(10) ++#define B_MAC_SEL_PWR_EN BIT(16) ++#define R_PMAC_TX_CTRL 0x09C0 ++#define B_PMAC_TXEN_DIS BIT(0) ++#define R_PMAC_TX_PRD 0x09C4 ++#define B_PMAC_TX_PRD_MSK GENMASK(31, 8) ++#define B_PMAC_CTX_EN BIT(0) ++#define B_PMAC_PTX_EN BIT(4) ++#define R_PMAC_TX_CNT 0x09C8 ++#define B_PMAC_TX_CNT_MSK GENMASK(31, 0) ++#define R_CCX 0x0C00 ++#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) ++#define B_MEASUREMENT_TRIG_MSK BIT(2) ++#define B_CCX_TRIG_OPT_MSK BIT(1) ++#define B_CCX_EN_MSK BIT(0) ++#define R_IFS_COUNTER 0x0C28 ++#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) ++#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) ++#define B_IFS_COUNTER_CLR_MSK BIT(13) ++#define B_IFS_COLLECT_EN BIT(12) ++#define R_IFS_T1 0x0C2C ++#define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T1_EN_MSK BIT(15) ++#define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) ++#define R_IFS_T2 0x0C30 ++#define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T2_EN_MSK BIT(15) ++#define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) ++#define R_IFS_T3 0x0C34 ++#define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T3_EN_MSK BIT(15) ++#define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) ++#define R_IFS_T4 0x0C38 ++#define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) ++#define B_IFS_T4_EN_MSK BIT(15) ++#define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) ++#define R_PD_CTRL 0x0C3C ++#define B_PD_HIT_DIS BIT(9) ++#define R_IOQ_IQK_DPK 0x0C60 ++#define B_IOQ_IQK_DPK_EN BIT(1) ++#define R_P0_EN_SOUND_WO_NDP 0x0D7C ++#define B_P0_EN_SOUND_WO_NDP BIT(1) ++#define R_SPOOF_ASYNC_RST 0x0D84 ++#define B_SPOOF_ASYNC_RST BIT(15) ++#define R_NDP_BRK0 0xDA0 ++#define R_NDP_BRK1 0xDA4 ++#define B_NDP_RU_BRK BIT(0) ++#define R_BRK_ASYNC_RST_EN_1 0x0DC0 ++#define R_BRK_ASYNC_RST_EN_2 0x0DC4 ++#define R_BRK_ASYNC_RST_EN_3 0x0DC8 ++#define R_P0_RXCK 0x12A0 ++#define B_P0_RXCK_VAL GENMASK(18, 16) ++#define B_P0_RXCK_ON BIT(19) ++#define B_P0_RXCK_BW3 BIT(30) ++#define R_P0_NRBW 0x12B8 ++#define B_P0_NRBW_DBG BIT(30) ++#define R_S0_RXDC 0x12D4 ++#define B_S0_RXDC_I GENMASK(25, 16) ++#define B_S0_RXDC_Q GENMASK(31, 26) ++#define R_S0_RXDC2 0x12D8 ++#define B_S0_RXDC2_SEL GENMASK(9, 8) ++#define B_S0_RXDC2_AVG GENMASK(7, 6) ++#define B_S0_RXDC2_MEN GENMASK(5, 4) ++#define B_S0_RXDC2_Q2 GENMASK(3, 0) ++#define R_CFO_COMP_SEG0_L 0x1384 ++#define R_CFO_COMP_SEG0_H 0x1388 ++#define R_CFO_COMP_SEG0_CTRL 0x138C ++#define R_DBG32_D 0x1730 ++#define R_TX_COUNTER 0x1A40 ++#define R_IFS_CLM_TX_CNT 0x1ACC ++#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) ++#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) ++#define R_IFS_CLM_CCA 0x1AD0 ++#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) ++#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) ++#define R_IFS_CLM_FA 0x1AD4 ++#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) ++#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) ++#define R_IFS_HIS 0x1AD8 ++#define B_IFS_T4_HIS_MSK GENMASK(31, 24) ++#define B_IFS_T3_HIS_MSK GENMASK(23, 16) ++#define B_IFS_T2_HIS_MSK GENMASK(15, 8) ++#define B_IFS_T1_HIS_MSK GENMASK(7, 0) ++#define R_IFS_AVG_L 0x1ADC ++#define B_IFS_T2_AVG_MSK GENMASK(31, 16) ++#define B_IFS_T1_AVG_MSK GENMASK(15, 0) ++#define R_IFS_AVG_H 0x1AE0 ++#define B_IFS_T4_AVG_MSK GENMASK(31, 16) ++#define B_IFS_T3_AVG_MSK GENMASK(15, 0) ++#define R_IFS_CCA_L 0x1AE4 ++#define B_IFS_T2_CCA_MSK GENMASK(31, 16) ++#define B_IFS_T1_CCA_MSK GENMASK(15, 0) ++#define R_IFS_CCA_H 0x1AE8 ++#define B_IFS_T4_CCA_MSK GENMASK(31, 16) ++#define B_IFS_T3_CCA_MSK GENMASK(15, 0) ++#define R_IFSCNT 0x1AEC ++#define B_IFSCNT_DONE_MSK BIT(16) ++#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0) ++#define R_TXAGC_TP 0x1C04 ++#define B_TXAGC_TP GENMASK(2, 0) ++#define R_TSSI_THER 0x1C10 ++#define B_TSSI_THER GENMASK(29, 24) ++#define R_TXAGC_BB 0x1C60 ++#define B_TXAGC_BB_OFT GENMASK(31, 16) ++#define B_TXAGC_BB GENMASK(31, 24) ++#define R_S0_ADDCK 0x1E00 ++#define B_S0_ADDCK_I GENMASK(9, 0) ++#define B_S0_ADDCK_Q GENMASK(19, 10) ++#define R_ADC_FIFO 0x20fc ++#define B_ADC_FIFO_RST GENMASK(31, 24) ++#define R_TXFIR0 0x2300 ++#define B_TXFIR_C01 GENMASK(23, 0) ++#define R_TXFIR2 0x2304 ++#define B_TXFIR_C23 GENMASK(23, 0) ++#define R_TXFIR4 0x2308 ++#define B_TXFIR_C45 GENMASK(23, 0) ++#define R_TXFIR6 0x230c ++#define B_TXFIR_C67 GENMASK(23, 0) ++#define R_TXFIR8 0x2310 ++#define B_TXFIR_C89 GENMASK(23, 0) ++#define R_TXFIRA 0x2314 ++#define B_TXFIR_CAB GENMASK(23, 0) ++#define R_TXFIRC 0x2318 ++#define B_TXFIR_CCD GENMASK(23, 0) ++#define R_TXFIRE 0x231c ++#define B_TXFIR_CEF GENMASK(23, 0) ++#define R_RXCCA 0x2344 ++#define B_RXCCA_DIS BIT(31) ++#define R_RXSC 0x237C ++#define B_RXSC_EN BIT(0) ++#define R_RXSCOBC 0x23B0 ++#define B_RXSCOBC_TH GENMASK(18, 0) ++#define R_RXSCOCCK 0x23B4 ++#define B_RXSCOCCK_TH GENMASK(18, 0) ++#define R_P1_EN_SOUND_WO_NDP 0x2D7C ++#define B_P1_EN_SOUND_WO_NDP BIT(1) ++#define R_P1_DBGMOD 0x32B8 ++#define B_P1_DBGMOD_ON BIT(30) ++#define R_S1_RXDC 0x32D4 ++#define B_S1_RXDC_I GENMASK(25, 16) ++#define B_S1_RXDC_Q GENMASK(31, 26) ++#define R_S1_RXDC2 0x32D8 ++#define B_S1_RXDC2_EN GENMASK(5, 4) ++#define B_S1_RXDC2_SEL GENMASK(9, 8) ++#define B_S1_RXDC2_Q2 GENMASK(3, 0) ++#define R_TXAGC_BB_S1 0x3C60 ++#define B_TXAGC_BB_S1_OFT GENMASK(31, 16) ++#define B_TXAGC_BB_S1 GENMASK(31, 24) ++#define R_S1_ADDCK 0x3E00 ++#define B_S1_ADDCK_I GENMASK(9, 0) ++#define B_S1_ADDCK_Q GENMASK(19, 10) ++#define R_DCFO 0x4264 ++#define B_DCFO GENMASK(1, 0) ++#define R_SEG0CSI 0x42AC ++#define B_SEG0CSI_IDX GENMASK(10, 0) ++#define R_SEG0CSI_EN 0x42C4 ++#define B_SEG0CSI_EN BIT(23) ++#define R_BSS_CLR_MAP 0x43ac ++#define B_BSS_CLR_MAP_VLD0 BIT(28) ++#define B_BSS_CLR_MAP_TGT GENMASK(27, 22) ++#define B_BSS_CLR_MAP_STAID GENMASK(21, 11) ++#define R_CFO_TRK0 0x4404 ++#define R_CFO_TRK1 0x440C ++#define B_CFO_TRK_MSK GENMASK(14, 10) ++#define R_DCFO_COMP_S0 0x448C ++#define B_DCFO_COMP_S0_MSK GENMASK(11, 0) ++#define R_DCFO_WEIGHT 0x4490 ++#define B_DCFO_WEIGHT_MSK GENMASK(27, 24) ++#define R_DCFO_OPT 0x4494 ++#define B_DCFO_OPT_EN BIT(29) ++#define R_BANDEDGE 0x4498 ++#define B_BANDEDGE_EN BIT(30) ++#define R_TXPATH_SEL 0x458C ++#define B_TXPATH_SEL_MSK GENMASK(31, 28) ++#define R_TXPWR 0x4594 ++#define B_TXPWR_MSK GENMASK(30, 22) ++#define R_TXNSS_MAP 0x45B4 ++#define B_TXNSS_MAP_MSK GENMASK(20, 17) ++#define R_PATH0_IB_PKPW 0x4628 ++#define B_PATH0_IB_PKPW_MSK GENMASK(11, 6) ++#define R_PATH0_LNA_ERR1 0x462C ++#define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24) ++#define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12) ++#define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6) ++#define R_PATH0_LNA_ERR2 0x4630 ++#define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18) ++#define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12) ++#define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0) ++#define R_PATH0_LNA_ERR3 0x4634 ++#define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24) ++#define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18) ++#define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6) ++#define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0) ++#define R_PATH0_LNA_ERR4 0x4638 ++#define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24) ++#define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12) ++#define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6) ++#define R_PATH0_LNA_ERR5 0x463C ++#define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0) ++#define R_PATH0_TIA_ERR_G0 0x4640 ++#define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18) ++#define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12) ++#define R_PATH0_TIA_ERR_G1 0x4644 ++#define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30) ++#define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6) ++#define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0) ++#define R_PATH0_IB_PBK 0x4650 ++#define B_PATH0_IB_PBK_MSK GENMASK(14, 10) ++#define R_PATH0_RXB_INIT 0x4658 ++#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5) ++#define R_PATH0_LNA_INIT 0x4668 ++#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24) ++#define R_PATH0_BTG 0x466C ++#define B_PATH0_BTG_SHEN GENMASK(18, 17) ++#define R_PATH0_TIA_INIT 0x4674 ++#define B_PATH0_TIA_INIT_IDX_MSK BIT(17) ++#define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0 ++#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4 ++#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_P0_NBIIDX 0x469C ++#define B_P0_NBIIDX_VAL GENMASK(11, 0) ++#define B_P0_NBIIDX_NOTCH_EN BIT(12) ++#define R_P1_MODE 0x4718 ++#define B_P1_MODE_SEL GENMASK(31, 30) ++#define R_PATH1_LNA_INIT 0x473C ++#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24) ++#define R_PATH1_TIA_INIT 0x4748 ++#define B_PATH1_TIA_INIT_IDX_MSK BIT(17) ++#define R_PATH1_BTG 0x4740 ++#define B_PATH1_BTG_SHEN GENMASK(18, 17) ++#define R_PATH1_RXB_INIT 0x472C ++#define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5) ++#define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774 ++#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778 ++#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) ++#define R_P1_NBIIDX 0x4770 ++#define B_P1_NBIIDX_VAL GENMASK(11, 0) ++#define B_P1_NBIIDX_NOTCH_EN BIT(12) ++#define R_SEG0R_PD 0x481C ++#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29) ++#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6) ++#define R_2P4G_BAND 0x4970 ++#define B_2P4G_BAND_SEL BIT(1) ++#define R_FC0_BW 0x4974 ++#define B_FC0_BW_INV GENMASK(6, 0) ++#define B_FC0_BW_SET GENMASK(31, 30) ++#define R_CHBW_MOD 0x4978 ++#define B_CHBW_MOD_PRICH GENMASK(11, 8) ++#define B_CHBW_MOD_SBW GENMASK(13, 12) ++#define R_CFO_COMP_SEG1_L 0x5384 ++#define R_CFO_COMP_SEG1_H 0x5388 ++#define R_CFO_COMP_SEG1_CTRL 0x538C ++#define B_CFO_COMP_VALID_BIT BIT(29) ++#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) ++#define B_CFO_COMP_VAL_MSK GENMASK(11, 0) ++#define R_DPD_OFT_EN 0x5800 ++#define B_DPD_OFT_EN BIT(28) ++#define R_DPD_OFT_ADDR 0x5804 ++#define B_DPD_OFT_ADDR GENMASK(31, 27) ++#define R_P0_TMETER 0x5810 ++#define B_P0_TMETER GENMASK(15, 10) ++#define B_P0_TMETER_DIS BIT(16) ++#define B_P0_TMETER_TRK BIT(24) ++#define R_P0_TSSI_TRK 0x5818 ++#define B_P0_TSSI_TRK_EN BIT(30) ++#define B_P0_TSSI_OFT_EN BIT(28) ++#define B_P0_TSSI_OFT GENMASK(7, 0) ++#define R_P0_TSSI_AVG 0x5820 ++#define B_P0_TSSI_AVG GENMASK(15, 12) ++#define R_P0_RFCTM 0x5864 ++#define B_P0_RFCTM_VAL GENMASK(25, 20) ++#define R_P0_RFCTM_RDY BIT(26) ++#define R_P0_TXDPD 0x58D4 ++#define B_P0_TXDPD GENMASK(31, 28) ++#define R_P0_TXPW_RSTB 0x58DC ++#define B_P0_TXPW_RSTB_MANON BIT(30) ++#define B_P0_TXPW_RSTB_TSSI BIT(31) ++#define R_P0_TSSI_MV_AVG 0x58E4 ++#define B_P0_TSSI_MV_AVG GENMASK(13, 11) ++#define R_TXGAIN_SCALE 0x58F0 ++#define B_TXGAIN_SCALE_EN BIT(19) ++#define B_TXGAIN_SCALE_OFT GENMASK(31, 24) ++#define R_P0_TSSI_BASE 0x5C00 ++#define R_S0_DACKI 0x5E00 ++#define B_S0_DACKI_AR GENMASK(31, 28) ++#define B_S0_DACKI_EN BIT(3) ++#define R_S0_DACKI2 0x5E30 ++#define B_S0_DACKI2_K GENMASK(21, 12) ++#define R_S0_DACKI7 0x5E44 ++#define B_S0_DACKI7_K GENMASK(15, 8) ++#define R_S0_DACKI8 0x5E48 ++#define B_S0_DACKI8_K GENMASK(15, 8) ++#define R_S0_DACKQ 0x5E50 ++#define B_S0_DACKQ_AR GENMASK(31, 28) ++#define B_S0_DACKQ_EN BIT(3) ++#define R_S0_DACKQ2 0x5E80 ++#define B_S0_DACKQ2_K GENMASK(21, 12) ++#define R_S0_DACKQ7 0x5E94 ++#define B_S0_DACKQ7_K GENMASK(15, 8) ++#define R_S0_DACKQ8 0x5E98 ++#define B_S0_DACKQ8_K GENMASK(15, 8) ++#define R_P1_TMETER 0x7810 ++#define B_P1_TMETER GENMASK(15, 10) ++#define B_P1_TMETER_DIS BIT(16) ++#define B_P1_TMETER_TRK BIT(24) ++#define R_P1_TSSI_TRK 0x7818 ++#define B_P1_TSSI_TRK_EN BIT(30) ++#define B_P1_TSSI_OFT_EN BIT(28) ++#define B_P1_TSSI_OFT GENMASK(7, 0) ++#define R_P1_TSSI_AVG 0x7820 ++#define B_P1_TSSI_AVG GENMASK(15, 12) ++#define R_P1_RFCTM 0x7864 ++#define R_P1_RFCTM_RDY BIT(26) ++#define B_P1_RFCTM_VAL GENMASK(25, 20) ++#define R_P1_TXPW_RSTB 0x78DC ++#define B_P1_TXPW_RSTB_MANON BIT(30) ++#define B_P1_TXPW_RSTB_TSSI BIT(31) ++#define R_P1_TSSI_MV_AVG 0x78E4 ++#define B_P1_TSSI_MV_AVG GENMASK(13, 11) ++#define R_TSSI_THOF 0x7C00 ++#define R_S1_DACKI 0x7E00 ++#define B_S1_DACKI_AR GENMASK(31, 28) ++#define B_S1_DACKI_EN BIT(3) ++#define R_S1_DACKI2 0x7E30 ++#define B_S1_DACKI2_K GENMASK(21, 12) ++#define R_S1_DACKI7 0x7E44 ++#define B_S1_DACKI_K GENMASK(15, 8) ++#define R_S1_DACKI8 0x7E48 ++#define B_S1_DACKI8_K GENMASK(15, 8) ++#define R_S1_DACKQ 0x7E50 ++#define B_S1_DACKQ_AR GENMASK(31, 28) ++#define B_S1_DACKQ_EN BIT(3) ++#define R_S1_DACKQ2 0x7E80 ++#define B_S1_DACKQ2_K GENMASK(21, 12) ++#define R_S1_DACKQ7 0x7E94 ++#define B_S1_DACKQ7_K GENMASK(15, 8) ++#define R_S1_DACKQ8 0x7E98 ++#define B_S1_DACKQ8_K GENMASK(15, 8) ++#define R_NCTL_CFG 0x8000 ++#define B_NCTL_CFG_SPAGE GENMASK(2, 1) ++#define R_NCTL_RPT 0x8008 ++#define B_NCTL_RPT_FLG BIT(26) ++#define R_NCTL_N1 0x8010 ++#define B_NCTL_N1_CIP GENMASK(7, 0) ++#define R_NCTL_N2 0x8014 ++#define R_IQK_COM 0x8018 ++#define R_IQK_DIF 0x801C ++#define B_IQK_DIF_TRX GENMASK(1, 0) ++#define R_IQK_DIF1 0x8020 ++#define B_IQK_DIF1_TXPI GENMASK(19, 0) ++#define R_IQK_DIF2 0x8024 ++#define B_IQK_DIF2_RXPI GENMASK(19, 0) ++#define R_IQK_DIF4 0x802C ++#define B_IQK_DIF4_TXT GENMASK(11, 0) ++#define B_IQK_DIF4_RXT GENMASK(27, 16) ++#define R_IQK_CFG 0x8034 ++#define B_IQK_CFG_SET GENMASK(5, 4) ++#define R_TPG_MOD 0x806C ++#define B_TPG_MOD_F GENMASK(2, 1) ++#define R_MDPK_SYNC 0x8070 ++#define B_MDPK_SYNC_SEL BIT(31) ++#define B_MDPK_SYNC_MAN GENMASK(31, 28) ++#define R_MDPK_RX_DCK 0x8074 ++#define R_NCTL_RW 0x8080 ++#define R_KIP_SYSCFG 0x8088 ++#define R_KIP_CLK 0x808C ++#define R_LDL_NORM 0x80A0 ++#define B_LDL_NORM_PN GENMASK(12, 8) ++#define B_LDL_NORM_OP GENMASK(1, 0) ++#define R_DPK_CTL 0x80B0 ++#define B_DPK_CTL_EN BIT(28) ++#define R_DPK_CFG 0x80B8 ++#define B_DPK_CFG_IDX GENMASK(14, 12) ++#define R_DPK_CFG2 0x80BC ++#define B_DPK_CFG2_ST BIT(14) ++#define R_DPK_CFG3 0x80C0 ++#define R_KPATH_CFG 0x80D0 ++#define R_KIP_RPT1 0x80D4 ++#define B_KIP_RPT1_SEL GENMASK(21, 16) ++#define R_SRAM_IQRX 0x80D8 ++#define R_GAPK 0x80E0 ++#define B_GAPK_ADR BIT(0) ++#define R_SRAM_IQRX2 0x80E8 ++#define R_DPK_TRK 0x80f0 ++#define B_DPK_TRK_DIS BIT(31) ++#define R_RPT_COM 0x80FC ++#define B_PRT_COM_SYNERR BIT(30) ++#define B_PRT_COM_DCI GENMASK(27, 16) ++#define B_PRT_COM_CORV GENMASK(15, 8) ++#define B_PRT_COM_DCQ GENMASK(11, 0) ++#define B_PRT_COM_GL GENMASK(7, 4) ++#define B_PRT_COM_CORI GENMASK(7, 0) ++#define R_COEF_SEL 0x8104 ++#define B_COEF_SEL_IQC BIT(0) ++#define B_COEF_SEL_MDPD BIT(8) ++#define R_CFIR_SYS 0x8120 ++#define R_IQK_RES 0x8124 ++#define B_IQK_RES_TXCFIR GENMASK(11, 8) ++#define B_IQK_RES_RXCFIR GENMASK(3, 0) ++#define R_TXIQC 0x8138 ++#define R_RXIQC 0x813c ++#define B_RXIQC_BYPASS BIT(0) ++#define B_RXIQC_BYPASS2 BIT(2) ++#define B_RXIQC_NEWP GENMASK(19, 8) ++#define B_RXIQC_NEWX GENMASK(31, 20) ++#define R_KIP 0x8140 ++#define B_KIP_DBCC BIT(0) ++#define B_KIP_RFGAIN BIT(8) ++#define R_RFGAIN 0x8144 ++#define B_RFGAIN_PAD GENMASK(4, 0) ++#define B_RFGAIN_TXBB GENMASK(12, 8) ++#define R_RFGAIN_BND 0x8148 ++#define B_RFGAIN_BND GENMASK(4, 0) ++#define R_CFIR_MAP 0x8150 ++#define R_CFIR_LUT 0x8154 ++#define B_CFIR_LUT_SEL BIT(8) ++#define B_CFIR_LUT_G3 BIT(3) ++#define B_CFIR_LUT_G2 BIT(2) ++#define B_CFIR_LUT_GP GENMASK(1, 0) ++#define R_DPD_V1 0x81a0 ++#define R_DPD_CH0 0x81AC ++#define R_DPD_BND 0x81B4 ++#define R_DPD_CH0A 0x81BC ++#define R_TXAGC_RFK 0x81C4 ++#define B_TXAGC_RFK_CH0 GENMASK(5, 0) ++#define R_DPD_COM 0x81C8 ++#define R_KIP_IQP 0x81CC ++#define B_KIP_IQP_IQSW GENMASK(5, 0) ++#define R_KIP_RPT 0x81D4 ++#define B_KIP_RPT_SEL GENMASK(21, 16) ++#define R_W_COEF 0x81D8 ++#define R_LOAD_COEF 0x81DC ++#define B_LOAD_COEF_MDPD BIT(16) ++#define B_LOAD_COEF_CFIR GENMASK(1, 0) ++#define B_LOAD_COEF_AUTO BIT(0) ++#define R_RPT_PER 0x81FC ++#define R_RXCFIR_P0C0 0x8D40 ++#define R_RXCFIR_P0C1 0x8D84 ++#define R_RXCFIR_P0C2 0x8DC8 ++#define R_RXCFIR_P0C3 0x8E0C ++#define R_TXCFIR_P0C0 0x8F50 ++#define R_TXCFIR_P0C1 0x8F84 ++#define R_TXCFIR_P0C2 0x8FB8 ++#define R_TXCFIR_P0C3 0x8FEC ++#define R_RXCFIR_P1C0 0x9140 ++#define R_RXCFIR_P1C1 0x9184 ++#define R_RXCFIR_P1C2 0x91C8 ++#define R_RXCFIR_P1C3 0x920C ++#define R_TXCFIR_P1C0 0x9350 ++#define R_TXCFIR_P1C1 0x9384 ++#define R_TXCFIR_P1C2 0x93B8 ++#define R_TXCFIR_P1C3 0x93EC ++#define R_IQKINF 0x9FE0 ++#define B_IQKINF_VER GENMASK(31, 24) ++#define B_IQKINF_FAIL_RXGRP GENMASK(23, 16) ++#define B_IQKINF_FAIL_TXGRP GENMASK(15, 8) ++#define B_IQKINF_FAIL GENMASK(3, 0) ++#define B_IQKINF_F_RX BIT(3) ++#define B_IQKINF_FTX BIT(2) ++#define B_IQKINF_FFIN BIT(1) ++#define B_IQKINF_FCOR BIT(0) ++#define R_IQKCH 0x9FE4 ++#define B_IQKCH_CH GENMASK(15, 8) ++#define B_IQKCH_BW GENMASK(7, 4) ++#define B_IQKCH_BAND GENMASK(3, 0) ++#define R_IQKINF2 0x9FE8 ++#define B_IQKINF2_FCNT GENMASK(23, 16) ++#define B_IQKINF2_KCNT GENMASK(15, 8) ++#define B_IQKINF2_NCTLV GENMAKS(7, 0) ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/regd.c b/drivers/net/wireless/realtek/rtw89/regd.c +new file mode 100644 +index 000000000000..f00b94ecfff4 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/regd.c +@@ -0,0 +1,353 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "ps.h" ++ ++#define COUNTRY_REGD(_alpha2, _txpwr_regd_2g, _txpwr_regd_5g) \ ++ {.alpha2 = (_alpha2), \ ++ .txpwr_regd[RTW89_BAND_2G] = (_txpwr_regd_2g), \ ++ .txpwr_regd[RTW89_BAND_5G] = (_txpwr_regd_5g) \ ++ } ++ ++static const struct rtw89_regulatory rtw89_ww_regd = ++ COUNTRY_REGD("00", RTW89_WW, RTW89_WW); ++ ++static const struct rtw89_regulatory rtw89_regd_map[] = { ++ COUNTRY_REGD("AR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BO", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("BR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("CL", RTW89_WW, RTW89_CHILE), ++ COUNTRY_REGD("CO", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("CR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("EC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SV", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("GT", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("HN", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("MX", RTW89_FCC, RTW89_MEXICO), ++ COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("US", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("UY", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("VE", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("PR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("DO", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("AT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("EE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ES", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GB", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("EG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("JO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LB", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("OM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("QA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ME", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ZA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("UA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("YE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ZW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KR", RTW89_KCC, RTW89_KCC), ++ COUNTRY_REGD("MY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("TH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AU", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("NZ", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("PG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CA", RTW89_IC, RTW89_IC), ++ COUNTRY_REGD("JP", RTW89_MKK, RTW89_MKK), ++ COUNTRY_REGD("JM", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("TT", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("TN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("DZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AS", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("AD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AG", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("AM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AW", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BS", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BB", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BZ", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BM", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VG", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("BN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KY", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("CF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CX", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("CC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("DJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ER", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ET", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FJ", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GP", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("GG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GY", RTW89_FCC, RTW89_NCC), ++ COUNTRY_REGD("HT", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("HM", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("VA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("JE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KI", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LA", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("LY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ML", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MH", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("YT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MD", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NP", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("NU", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("NF", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("MP", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PW", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("RE", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RW", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("KN", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("LC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MF", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SX", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("PM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("WS", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ST", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SC", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SB", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SR", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("SJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TK", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("TO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TV", RTW89_ETSI, RTW89_NA), ++ COUNTRY_REGD("UG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VI", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("UZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("VU", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("WF", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("EH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("ZM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("IR", RTW89_WW, RTW89_ETSI), ++}; ++ ++static const struct rtw89_regulatory *rtw89_regd_find_reg_by_name(char *alpha2) ++{ ++ u32 i; ++ ++ for (i = 0; i < ARRAY_SIZE(rtw89_regd_map); i++) { ++ if (!memcmp(rtw89_regd_map[i].alpha2, alpha2, 2)) ++ return &rtw89_regd_map[i]; ++ } ++ ++ return &rtw89_ww_regd; ++} ++ ++static bool rtw89_regd_is_ww(const struct rtw89_regulatory *regd) ++{ ++ return regd == &rtw89_ww_regd; ++} ++ ++int rtw89_regd_init(struct rtw89_dev *rtwdev, ++ void (*reg_notifier)(struct wiphy *wiphy, ++ struct regulatory_request *request)) ++{ ++ const struct rtw89_regulatory *chip_regd; ++ struct wiphy *wiphy = rtwdev->hw->wiphy; ++ int ret; ++ ++ if (!wiphy) ++ return -EINVAL; ++ ++ chip_regd = rtw89_regd_find_reg_by_name(rtwdev->efuse.country_code); ++ if (!rtw89_regd_is_ww(chip_regd)) { ++ rtwdev->regd = chip_regd; ++ /* Ignore country ie if there is a country domain programmed in chip */ ++ wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE; ++ wiphy->regulatory_flags |= REGULATORY_STRICT_REG; ++ ++ ret = regulatory_hint(rtwdev->hw->wiphy, rtwdev->regd->alpha2); ++ if (ret) ++ rtw89_warn(rtwdev, "failed to hint regulatory:%d\n", ret); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "efuse country code %c%c, mapping to 2g txregd %d, 5g txregd %d\n", ++ rtwdev->efuse.country_code[0], rtwdev->efuse.country_code[1], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_2G], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_5G]); ++ ++ return 0; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "worldwide roaming chip, follow the setting of stack(%c%c), mapping to 2g txregd %d, 5g txregd %d\n", ++ rtwdev->regd->alpha2[0], rtwdev->regd->alpha2[1], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_2G], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_5G]); ++ ++ return 0; ++} ++ ++static void rtw89_regd_notifier_apply(struct rtw89_dev *rtwdev, ++ struct wiphy *wiphy, ++ struct regulatory_request *request) ++{ ++ rtwdev->regd = rtw89_regd_find_reg_by_name(request->alpha2); ++ /* This notification might be set from the system of distros, ++ * and it does not expect the regulatory will be modified by ++ * connecting to an AP (i.e. country ie). ++ */ ++ if (request->initiator == NL80211_REGDOM_SET_BY_USER && ++ !rtw89_regd_is_ww(rtwdev->regd)) ++ wiphy->regulatory_flags |= REGULATORY_COUNTRY_IE_IGNORE; ++ else ++ wiphy->regulatory_flags &= ~REGULATORY_COUNTRY_IE_IGNORE; ++} ++ ++void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request) ++{ ++ struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); ++ struct rtw89_dev *rtwdev = hw->priv; ++ ++ mutex_lock(&rtwdev->mutex); ++ rtw89_leave_ps_mode(rtwdev); ++ ++ if (wiphy->regd) { ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "There is a country domain programmed in chip, ignore notifications\n"); ++ goto exit; ++ } ++ rtw89_regd_notifier_apply(rtwdev, wiphy, request); ++ rtw89_debug(rtwdev, RTW89_DBG_REGD, ++ "get alpha2 %c%c from initiator %d, mapping to 2g txregd %d, 5g txregd %d\n", ++ request->alpha2[0], request->alpha2[1], request->initiator, ++ rtwdev->regd->txpwr_regd[RTW89_BAND_2G], ++ rtwdev->regd->txpwr_regd[RTW89_BAND_5G]); ++ ++ rtw89_chip_set_txpwr(rtwdev); ++ ++exit: ++ mutex_unlock(&rtwdev->mutex); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +new file mode 100644 +index 000000000000..b1b87f0aadbb +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -0,0 +1,2036 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "mac.h" ++#include "phy.h" ++#include "reg.h" ++#include "rtw8852a.h" ++#include "rtw8852a_rfk.h" ++#include "rtw8852a_table.h" ++#include "txrx.h" ++ ++static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { ++ {128, 1896, grp_0}, /* ACH 0 */ ++ {128, 1896, grp_0}, /* ACH 1 */ ++ {128, 1896, grp_0}, /* ACH 2 */ ++ {128, 1896, grp_0}, /* ACH 3 */ ++ {128, 1896, grp_1}, /* ACH 4 */ ++ {128, 1896, grp_1}, /* ACH 5 */ ++ {128, 1896, grp_1}, /* ACH 6 */ ++ {128, 1896, grp_1}, /* ACH 7 */ ++ {32, 1896, grp_0}, /* B0MGQ */ ++ {128, 1896, grp_0}, /* B0HIQ */ ++ {32, 1896, grp_1}, /* B1MGQ */ ++ {128, 1896, grp_1}, /* B1HIQ */ ++ {40, 0, 0} /* FWCMDQ */ ++}; ++ ++static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { ++ 1896, /* Group 0 */ ++ 1896, /* Group 1 */ ++ 3792, /* Public Max */ ++ 0 /* WP threshold */ ++}; ++ ++static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { ++ [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, ++ &rtw_hfc_preccfg_pcie, RTW89_HCIFC_POH}, ++ [RTW89_QTA_DLFW] = {NULL, NULL, &rtw_hfc_preccfg_pcie, RTW89_HCIFC_POH}, ++ [RTW89_QTA_INVALID] = {NULL}, ++}; ++ ++static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { ++ [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &wde_size0, &ple_size0, &wde_qt0, ++ &wde_qt0, &ple_qt4, &ple_qt5}, ++ [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &wde_size4, &ple_size4, ++ &wde_qt4, &wde_qt4, &ple_qt13, &ple_qt13}, ++ [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, ++ NULL}, ++}; ++ ++static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { ++ {0x44AC, 0x00000000}, ++ {0x44B0, 0x00000000}, ++ {0x44B4, 0x00000000}, ++ {0x44B8, 0x00000000}, ++ {0x44BC, 0x00000000}, ++ {0x44C0, 0x00000000}, ++ {0x44C4, 0x00000000}, ++ {0x44C8, 0x00000000}, ++ {0x44CC, 0x00000000}, ++ {0x44D0, 0x00000000}, ++ {0x44D4, 0x00000000}, ++ {0x44D8, 0x00000000}, ++ {0x44DC, 0x00000000}, ++ {0x44E0, 0x00000000}, ++ {0x44E4, 0x00000000}, ++ {0x44E8, 0x00000000}, ++ {0x44EC, 0x00000000}, ++ {0x44F0, 0x00000000}, ++ {0x44F4, 0x00000000}, ++ {0x44F8, 0x00000000}, ++ {0x44FC, 0x00000000}, ++ {0x4500, 0x00000000}, ++ {0x4504, 0x00000000}, ++ {0x4508, 0x00000000}, ++ {0x450C, 0x00000000}, ++ {0x4510, 0x00000000}, ++ {0x4514, 0x00000000}, ++ {0x4518, 0x00000000}, ++ {0x451C, 0x00000000}, ++ {0x4520, 0x00000000}, ++ {0x4524, 0x00000000}, ++ {0x4528, 0x00000000}, ++ {0x452C, 0x00000000}, ++ {0x4530, 0x4E1F3E81}, ++ {0x4534, 0x00000000}, ++ {0x4538, 0x0000005A}, ++ {0x453C, 0x00000000}, ++ {0x4540, 0x00000000}, ++ {0x4544, 0x00000000}, ++ {0x4548, 0x00000000}, ++ {0x454C, 0x00000000}, ++ {0x4550, 0x00000000}, ++ {0x4554, 0x00000000}, ++ {0x4558, 0x00000000}, ++ {0x455C, 0x00000000}, ++ {0x4560, 0x4060001A}, ++ {0x4564, 0x40000000}, ++ {0x4568, 0x00000000}, ++ {0x456C, 0x00000000}, ++ {0x4570, 0x04000007}, ++ {0x4574, 0x0000DC87}, ++ {0x4578, 0x00000BAB}, ++ {0x457C, 0x03E00000}, ++ {0x4580, 0x00000048}, ++ {0x4584, 0x00000000}, ++ {0x4588, 0x000003E8}, ++ {0x458C, 0x30000000}, ++ {0x4590, 0x00000000}, ++ {0x4594, 0x10000000}, ++ {0x4598, 0x00000001}, ++ {0x459C, 0x00030000}, ++ {0x45A0, 0x01000000}, ++ {0x45A4, 0x03000200}, ++ {0x45A8, 0xC00001C0}, ++ {0x45AC, 0x78018000}, ++ {0x45B0, 0x80000000}, ++ {0x45B4, 0x01C80600}, ++ {0x45B8, 0x00000002}, ++ {0x4594, 0x10000000} ++}; ++ ++static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { ++ {0x4624, GENMASK(20, 14), 0x40}, ++ {0x46f8, GENMASK(20, 14), 0x40}, ++ {0x4674, GENMASK(20, 19), 0x2}, ++ {0x4748, GENMASK(20, 19), 0x2}, ++ {0x4650, GENMASK(14, 10), 0x18}, ++ {0x4724, GENMASK(14, 10), 0x18}, ++ {0x4688, GENMASK(1, 0), 0x3}, ++ {0x475c, GENMASK(1, 0), 0x3}, ++}; ++ ++static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); ++ ++static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { ++ {0x4624, GENMASK(20, 14), 0x1a}, ++ {0x46f8, GENMASK(20, 14), 0x1a}, ++ {0x4674, GENMASK(20, 19), 0x1}, ++ {0x4748, GENMASK(20, 19), 0x1}, ++ {0x4650, GENMASK(14, 10), 0x12}, ++ {0x4724, GENMASK(14, 10), 0x12}, ++ {0x4688, GENMASK(1, 0), 0x0}, ++ {0x475c, GENMASK(1, 0), 0x0}, ++}; ++ ++static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); ++ ++static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { ++ {0x00C6, ++ PWR_CV_MSK_B, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), BIT(6)}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), BIT(1)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(7), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(2), 0}, ++ {0x0006, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), BIT(1)}, ++ {0x0006, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(0), 0}, ++ {0x106D, ++ PWR_CV_MSK_B | PWR_CV_MSK_C, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), 0}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x0088, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0083, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), 0}, ++ {0x0080, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(5), BIT(5)}, ++ {0x0024, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, ++ {0x02A0, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1), BIT(1)}, ++ {0x02A2, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, ++ {0x0071, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4), 0}, ++ {0x0010, ++ PWR_CV_MSK_A, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(2), BIT(2)}, ++ {0x02A0, ++ PWR_CV_MSK_A, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, ++ {0xFFFF, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ 0, ++ PWR_CMD_END, 0, 0}, ++}; ++ ++static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { ++ {0x02F0, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, 0xFF, 0}, ++ {0x02F1, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, 0xFF, 0}, ++ {0x0006, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x0002, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, ++ {0x0082, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, ++ {0x106D, ++ PWR_CV_MSK_B | PWR_CV_MSK_C, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6), BIT(6)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(1), BIT(1)}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), 0}, ++ {0x0091, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_PCIE, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(2), BIT(2)}, ++ {0x0007, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4), 0}, ++ {0x0007, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, ++ {0x0005, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, ++ {0x0005, ++ PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | ++ PWR_CV_MSK_G, ++ PWR_INTF_MSK_USB, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_WRITE, BIT(0), BIT(0)}, ++ {0x1086, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_SDIO, ++ PWR_BASE_MAC, ++ PWR_CMD_POLL, BIT(1), 0}, ++ {0xFFFF, ++ PWR_CV_MSK_ALL, ++ PWR_INTF_MSK_ALL, ++ 0, ++ PWR_CMD_END, 0, 0}, ++}; ++ ++static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { ++ rtw8852a_pwron, NULL ++}; ++ ++static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { ++ rtw8852a_pwroff, NULL ++}; ++ ++static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, ++ struct rtw8852a_efuse *map) ++{ ++ ether_addr_copy(efuse->addr, map->e.mac_addr); ++ efuse->rfe_type = map->rfe_type; ++ efuse->xtal_cap = map->xtal_k; ++} ++ ++static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, ++ struct rtw8852a_efuse *map) ++{ ++ struct rtw89_tssi_info *tssi = &rtwdev->tssi; ++ struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; ++ u8 i, j; ++ ++ tssi->thermal[RF_PATH_A] = map->path_a_therm; ++ tssi->thermal[RF_PATH_B] = map->path_b_therm; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, ++ sizeof(ofst[i]->cck_tssi)); ++ ++ for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", ++ i, j, tssi->tssi_cck[i][j]); ++ ++ memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, ++ sizeof(ofst[i]->bw40_tssi)); ++ memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, ++ ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); ++ ++ for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", ++ i, j, tssi->tssi_mcs[i][j]); ++ } ++} ++ ++static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) ++{ ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ struct rtw8852a_efuse *map; ++ ++ map = (struct rtw8852a_efuse *)log_map; ++ ++ efuse->country_code[0] = map->country_code[0]; ++ efuse->country_code[1] = map->country_code[1]; ++ rtw8852a_efuse_parsing_tssi(rtwdev, map); ++ ++ switch (rtwdev->hci.type) { ++ case RTW89_HCI_TYPE_PCIE: ++ rtw8852ae_efuse_parsing(efuse, map); ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); ++ ++ return 0; ++} ++ ++static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) ++{ ++ struct rtw89_tssi_info *tssi = &rtwdev->tssi; ++ static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; ++ u32 addr = rtwdev->chip->phycap_addr; ++ bool pg = false; ++ u32 ofst; ++ u8 i, j; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { ++ /* addrs are in decreasing order */ ++ ofst = tssi_trim_addr[i] - addr - j; ++ tssi->tssi_trim[i][j] = phycap_map[ofst]; ++ ++ if (phycap_map[ofst] != 0xff) ++ pg = true; ++ } ++ } ++ ++ if (!pg) { ++ memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM] no PG, set all trim info to 0\n"); ++ } ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) ++ for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", ++ i, j, tssi->tssi_trim[i][j], ++ tssi_trim_addr[i] - j); ++} ++ ++static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, ++ u8 *phycap_map) ++{ ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; ++ u32 addr = rtwdev->chip->phycap_addr; ++ u8 i; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", ++ i, info->thermal_trim[i]); ++ ++ if (info->thermal_trim[i] != 0xff) ++ info->pg_thermal_trim = true; ++ } ++} ++ ++static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) ++{ ++#define __thm_setting(raw) \ ++({ \ ++ u8 __v = (raw); \ ++ ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ ++}) ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ u8 i, val; ++ ++ if (!info->pg_thermal_trim) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[THERMAL][TRIM] no PG, do nothing\n"); ++ ++ return; ++ } ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ val = __thm_setting(info->thermal_trim[i]); ++ rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", ++ i, val); ++ } ++#undef __thm_setting ++} ++ ++static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, ++ u8 *phycap_map) ++{ ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; ++ u32 addr = rtwdev->chip->phycap_addr; ++ u8 i; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", ++ i, info->pa_bias_trim[i]); ++ ++ if (info->pa_bias_trim[i] != 0xff) ++ info->pg_pa_bias_trim = true; ++ } ++} ++ ++static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; ++ u8 pabias_2g, pabias_5g; ++ u8 i; ++ ++ if (!info->pg_pa_bias_trim) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[PA_BIAS][TRIM] no PG, do nothing\n"); ++ ++ return; ++ } ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); ++ pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", ++ i, pabias_2g, pabias_5g); ++ ++ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); ++ rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); ++ } ++} ++ ++static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) ++{ ++ rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); ++ rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); ++ rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); ++ ++ return 0; ++} ++ ++static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_thermal_trim(rtwdev); ++ rtw8852a_pa_bias_trim(rtwdev); ++} ++ ++static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ u8 mac_idx) ++{ ++ u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); ++ u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, ++ mac_idx); ++ u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); ++ u8 txsc20 = 0, txsc40 = 0; ++ ++ switch (param->bandwidth) { ++ case RTW89_CHANNEL_WIDTH_80: ++ txsc40 = rtw89_phy_get_txsc(rtwdev, param, ++ RTW89_CHANNEL_WIDTH_40); ++ fallthrough; ++ case RTW89_CHANNEL_WIDTH_40: ++ txsc20 = rtw89_phy_get_txsc(rtwdev, param, ++ RTW89_CHANNEL_WIDTH_20); ++ break; ++ default: ++ break; ++ } ++ ++ switch (param->bandwidth) { ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); ++ rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); ++ rtw89_write32(rtwdev, sub_carr, txsc20); ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); ++ rtw89_write32(rtwdev, sub_carr, 0); ++ break; ++ default: ++ break; ++ } ++ ++ if (param->center_chan > 14) ++ rtw89_write8_set(rtwdev, chk_rate, ++ B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); ++ else ++ rtw89_write8_clr(rtwdev, chk_rate, ++ B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); ++} ++ ++static const u32 rtw8852a_sco_barker_threshold[14] = { ++ 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, ++ 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 ++}; ++ ++static const u32 rtw8852a_sco_cck_threshold[14] = { ++ 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, ++ 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed ++}; ++ ++static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, ++ u8 primary_ch, enum rtw89_bandwidth bw) ++{ ++ u8 ch_element; ++ ++ if (bw == RTW89_CHANNEL_WIDTH_20) { ++ ch_element = central_ch - 1; ++ } else if (bw == RTW89_CHANNEL_WIDTH_40) { ++ if (primary_ch == 1) ++ ch_element = central_ch - 1 + 2; ++ else ++ ch_element = central_ch - 1 - 2; ++ } else { ++ rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); ++ return -EINVAL; ++ } ++ rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, ++ rtw8852a_sco_barker_threshold[ch_element]); ++ rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, ++ rtw8852a_sco_cck_threshold[ch_element]); ++ ++ return 0; ++} ++ ++static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, ++ u8 path) ++{ ++ u32 val; ++ ++ val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ if (val == INV_RF_DATA) { ++ rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); ++ return; ++ } ++ val &= ~0x303ff; ++ val |= central_ch; ++ if (central_ch > 14) ++ val |= (BIT(16) | BIT(8)); ++ rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); ++} ++ ++static u8 rtw8852a_sco_mapping(u8 central_ch) ++{ ++ if (central_ch == 1) ++ return 109; ++ else if (central_ch >= 2 && central_ch <= 6) ++ return 108; ++ else if (central_ch >= 7 && central_ch <= 10) ++ return 107; ++ else if (central_ch >= 11 && central_ch <= 14) ++ return 106; ++ else if (central_ch == 36 || central_ch == 38) ++ return 51; ++ else if (central_ch >= 40 && central_ch <= 58) ++ return 50; ++ else if (central_ch >= 60 && central_ch <= 64) ++ return 49; ++ else if (central_ch == 100 || central_ch == 102) ++ return 48; ++ else if (central_ch >= 104 && central_ch <= 126) ++ return 47; ++ else if (central_ch >= 128 && central_ch <= 151) ++ return 46; ++ else if (central_ch >= 153 && central_ch <= 177) ++ return 45; ++ else ++ return 0; ++} ++ ++static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, ++ enum rtw89_phy_idx phy_idx) ++{ ++ u8 sco_comp; ++ bool is_2g = central_ch <= 14; ++ ++ if (phy_idx == RTW89_PHY_0) { ++ /* Path A */ ++ rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, ++ B_PATH0_TIA_ERR_G1_SEL, 1, ++ phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, ++ B_PATH0_TIA_ERR_G1_SEL, 0, ++ phy_idx); ++ ++ /* Path B */ ++ if (!rtwdev->dbcc_en) { ++ rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 1, phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 0, phy_idx); ++ } else { ++ if (is_2g) ++ rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, ++ B_2P4G_BAND_SEL); ++ else ++ rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, ++ B_2P4G_BAND_SEL); ++ } ++ /* SCO compensate FC setting */ ++ sco_comp = rtw8852a_sco_mapping(central_ch); ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, ++ sco_comp, phy_idx); ++ } else { ++ /* Path B */ ++ rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 1, phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_P1_MODE, ++ B_P1_MODE_SEL, ++ 1, phy_idx); ++ /* SCO compensate FC setting */ ++ sco_comp = rtw8852a_sco_mapping(central_ch); ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, ++ sco_comp, phy_idx); ++ } ++ ++ /* Band edge */ ++ if (is_2g) ++ rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, ++ phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, ++ phy_idx); ++ ++ /* CCK parameters */ ++ if (central_ch == 14) { ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, ++ 0x3b13ff); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, ++ 0x1c42de); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, ++ 0xfdb0ad); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, ++ 0xf60f6e); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, ++ 0xfd8f92); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, ++ 0xfff00a); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, ++ 0x3d23ff); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, ++ 0x29b354); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, ++ 0xfdb053); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, ++ 0xf86f9a); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, ++ 0xfaef92); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, ++ 0xfe5fcc); ++ rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, ++ 0xffdff5); ++ } ++} ++ ++static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) ++{ ++ u32 val = 0; ++ u32 adc_sel[2] = {0x12d0, 0x32d0}; ++ u32 wbadc_sel[2] = {0x12ec, 0x32ec}; ++ ++ val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ if (val == INV_RF_DATA) { ++ rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); ++ return; ++ } ++ val &= ~(BIT(11) | BIT(10)); ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_5: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); ++ val |= (BIT(11) | BIT(10)); ++ break; ++ case RTW89_CHANNEL_WIDTH_10: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); ++ val |= (BIT(11) | BIT(10)); ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); ++ val |= (BIT(11) | BIT(10)); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); ++ val |= BIT(11); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); ++ rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); ++ val |= BIT(10); ++ break; ++ default: ++ rtw89_warn(rtwdev, "Fail to set ADC\n"); ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); ++} ++ ++static void ++rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, ++ enum rtw89_phy_idx phy_idx) ++{ ++ /* Switch bandwidth */ ++ switch (bw) { ++ case RTW89_CHANNEL_WIDTH_5: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ 0x0, phy_idx); ++ break; ++ case RTW89_CHANNEL_WIDTH_10: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ 0x0, phy_idx); ++ break; ++ case RTW89_CHANNEL_WIDTH_20: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ 0x0, phy_idx); ++ break; ++ case RTW89_CHANNEL_WIDTH_40: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ pri_ch, ++ phy_idx); ++ if (pri_ch == RTW89_SC_20_UPPER) ++ rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); ++ break; ++ case RTW89_CHANNEL_WIDTH_80: ++ rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, ++ pri_ch, ++ phy_idx); ++ break; ++ default: ++ rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, ++ pri_ch); ++ } ++ ++ if (phy_idx == RTW89_PHY_0) { ++ rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); ++ if (!rtwdev->dbcc_en) ++ rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); ++ } else { ++ rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); ++ } ++} ++ ++static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) ++{ ++ if (central_ch == 153) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x1); ++ } else if (central_ch == 151) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, ++ 0x210); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x1); ++ } else if (central_ch == 155) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, ++ 0x2d0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, ++ 0x2d0); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x1); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, ++ B_P0_NBIIDX_NOTCH_EN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, ++ B_P1_NBIIDX_NOTCH_EN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, ++ 0x0); ++ } ++} ++ ++static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, ++ phy_idx); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, ++ phy_idx); ++} ++ ++static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, bool en) ++{ ++ if (en) ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, ++ 1, ++ phy_idx); ++ else ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, ++ 0, ++ phy_idx); ++} ++ ++static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); ++ rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); ++ rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++ rtw8852a_bb_reset_all(rtwdev, phy_idx); ++ rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); ++ rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); ++ rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++} ++ ++static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ u32 addr; ++ ++ for (addr = R_AX_PWR_MACID_LMT_TABLE0; ++ addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); ++} ++ ++static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); ++ rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); ++ ++ if (rtwdev->hal.cv <= CHIP_CCV) { ++ rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); ++ rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); ++ rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F); ++ rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); ++ rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); ++ rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); ++ rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); ++ } ++ rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); ++ rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); ++ rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); ++ rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); ++ ++ rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); ++} ++ ++static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++ rtw8852a_bb_reset_all(rtwdev, phy_idx); ++ rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); ++ udelay(1); ++} ++ ++static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *param, ++ enum rtw89_phy_idx phy_idx) ++{ ++ bool cck_en = param->center_chan > 14 ? false : true; ++ u8 pri_ch_idx = param->pri_ch_idx; ++ ++ if (param->center_chan <= 14) ++ rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan, ++ param->primary_chan, param->bandwidth); ++ ++ rtw8852a_ctrl_ch(rtwdev, param->center_chan, phy_idx); ++ rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx); ++ if (cck_en) { ++ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); ++ rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); ++ } ++ rtw8852a_spur_elimination(rtwdev, param->center_chan); ++ rtw8852a_bb_reset_all(rtwdev, phy_idx); ++} ++ ++static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, ++ struct rtw89_channel_params *params) ++{ ++ rtw8852a_set_channel_mac(rtwdev, params, RTW89_MAC_0); ++ rtw8852a_set_channel_bb(rtwdev, params, RTW89_PHY_0); ++} ++ ++static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) ++{ ++ if (en) ++ rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); ++} ++ ++static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, ++ enum rtw89_rf_path path) ++{ ++ static const u32 tssi_trk[2] = {0x5818, 0x7818}; ++ static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; ++ ++ if (en) { ++ rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); ++ rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); ++ rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); ++ } ++} ++ ++static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, ++ u8 phy_idx) ++{ ++ if (!rtwdev->dbcc_en) { ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); ++ } else { ++ if (phy_idx == RTW89_PHY_0) ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); ++ else ++ rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); ++ } ++} ++ ++static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) ++{ ++ if (en) ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, ++ 0x0); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, ++ 0xf); ++} ++ ++static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, ++ struct rtw89_channel_help_params *p) ++{ ++ u8 phy_idx = RTW89_PHY_0; ++ ++ if (enter) { ++ rtw89_mac_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); ++ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); ++ rtw8852a_dfs_en(rtwdev, false); ++ rtw8852a_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); ++ rtw8852a_adc_en(rtwdev, false); ++ fsleep(40); ++ rtw8852a_bb_reset_en(rtwdev, phy_idx, false); ++ } else { ++ rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); ++ rtw8852a_adc_en(rtwdev, true); ++ rtw8852a_dfs_en(rtwdev, true); ++ rtw8852a_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); ++ rtw8852a_bb_reset_en(rtwdev, phy_idx, true); ++ rtw89_mac_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); ++ } ++} ++ ++static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_efuse *efuse = &rtwdev->efuse; ++ ++ switch (efuse->rfe_type) { ++ case 11: ++ case 12: ++ case 17: ++ case 18: ++ case 51: ++ case 53: ++ rtwdev->fem.epa_2g = true; ++ rtwdev->fem.elna_2g = true; ++ fallthrough; ++ case 9: ++ case 10: ++ case 15: ++ case 16: ++ rtwdev->fem.epa_5g = true; ++ rtwdev->fem.elna_5g = true; ++ break; ++ default: ++ break; ++ } ++} ++ ++static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) ++{ ++ rtwdev->is_tssi_mode[RF_PATH_A] = false; ++ rtwdev->is_tssi_mode[RF_PATH_B] = false; ++ ++ rtw8852a_rck(rtwdev); ++ rtw8852a_dack(rtwdev); ++ rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); ++} ++ ++static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) ++{ ++ enum rtw89_phy_idx phy_idx = RTW89_PHY_0; ++ ++ rtw8852a_rx_dck(rtwdev, phy_idx, true); ++ rtw8852a_iqk(rtwdev, phy_idx); ++ rtw8852a_tssi(rtwdev, phy_idx); ++ rtw8852a_dpk(rtwdev, phy_idx); ++} ++ ++static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_tssi_scan(rtwdev, RTW89_PHY_0); ++} ++ ++static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) ++{ ++ rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); ++} ++ ++static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_dpk_track(rtwdev); ++ rtw8852a_iqk_track(rtwdev); ++ rtw8852a_tssi_track(rtwdev); ++} ++ ++static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, s16 ref) ++{ ++ s8 ofst_int = 0; ++ u8 base_cw_0db = 0x27; ++ u16 tssi_16dbm_cw = 0x12c; ++ s16 pwr_s10_3 = 0; ++ s16 rf_pwr_cw = 0; ++ u16 bb_pwr_cw = 0; ++ u32 pwr_cw = 0; ++ u32 tssi_ofst_cw = 0; ++ ++ pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); ++ bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); ++ rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); ++ rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); ++ pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; ++ ++ tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", ++ tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); ++ ++ return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); ++} ++ ++static ++void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, ++ s16 pw_ofst, enum rtw89_mac_idx mac_idx) ++{ ++ s32 val_1t = 0; ++ s32 val_2t = 0; ++ u32 reg; ++ ++ if (pw_ofst < -16 || pw_ofst > 15) { ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", ++ pw_ofst); ++ return; ++ } ++ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); ++ rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); ++ val_1t = (s32)pw_ofst; ++ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); ++ val_2t = max(val_1t - 3, -16); ++ reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); ++ rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", ++ val_1t, val_2t); ++} ++ ++static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; ++ const u32 mask = 0x7FFFFFF; ++ const u8 ofst_ofdm = 0x4; ++ const u8 ofst_cck = 0x8; ++ s16 ref_ofdm = 0; ++ s16 ref_cck = 0; ++ u32 val; ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); ++ ++ rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, ++ GENMASK(27, 10), 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); ++ val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) ++ rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, ++ phy_idx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); ++ val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) ++ rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, ++ phy_idx); ++} ++ ++static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ u8 ch = rtwdev->hal.current_channel; ++ static const u8 rs[] = { ++ RTW89_RS_CCK, ++ RTW89_RS_OFDM, ++ RTW89_RS_MCS, ++ RTW89_RS_HEDCM, ++ }; ++ s8 tmp; ++ u8 i, j; ++ u32 val, shf, addr = R_AX_PWR_BY_RATE; ++ struct rtw89_rate_desc cur; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] set txpwr byrate with ch=%d\n", ch); ++ ++ for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { ++ for (i = 0; i < ARRAY_SIZE(rs); i++) { ++ if (cur.nss >= rtw89_rs_nss_max[rs[i]]) ++ continue; ++ ++ val = 0; ++ cur.rs = rs[i]; ++ ++ for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { ++ cur.idx = j; ++ shf = (j % 4) * 8; ++ tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur); ++ val |= (tmp << shf); ++ ++ if ((j + 1) % 4) ++ continue; ++ ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); ++ val = 0; ++ addr += 4; ++ } ++ } ++ } ++} ++ ++static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++ struct rtw89_rate_desc desc = { ++ .nss = RTW89_NSS_1, ++ .rs = RTW89_RS_OFFSET, ++ }; ++ u32 val = 0; ++ s8 v; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); ++ ++ for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { ++ v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc); ++ val |= ((v & 0xf) << (4 * desc.idx)); ++ } ++ ++ rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, ++ GENMASK(19, 0), val); ++} ++ ++static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++#define __MAC_TXPWR_LMT_PAGE_SIZE 40 ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; ++ u32 addr, val; ++ const s8 *ptr; ++ u8 i, j, k; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); ++ ++ for (i = 0; i < NTX_NUM_8852A; i++) { ++ rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i); ++ ++ for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { ++ addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; ++ ptr = (s8 *)&lmt[i] + j; ++ val = 0; ++ ++ for (k = 0; k < 4; k++) ++ val |= (ptr[k] << (8 * k)); ++ ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); ++ } ++ } ++#undef __MAC_TXPWR_LMT_PAGE_SIZE ++} ++ ++static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx) ++{ ++#define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 ++ u8 ch = rtwdev->hal.current_channel; ++ u8 bw = rtwdev->hal.current_band_width; ++ struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; ++ u32 addr, val; ++ const s8 *ptr; ++ u8 i, j, k; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, ++ "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); ++ ++ for (i = 0; i < NTX_NUM_8852A; i++) { ++ rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i); ++ ++ for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { ++ addr = R_AX_PWR_RU_LMT + j + ++ __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; ++ ptr = (s8 *)&lmt_ru[i] + j; ++ val = 0; ++ ++ for (k = 0; k < 4; k++) ++ val |= (ptr[k] << (8 * k)); ++ ++ rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); ++ } ++ } ++ ++#undef __MAC_TXPWR_LMT_RU_PAGE_SIZE ++} ++ ++static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_set_txpwr_byrate(rtwdev, RTW89_PHY_0); ++ rtw8852a_set_txpwr_limit(rtwdev, RTW89_PHY_0); ++ rtw8852a_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0); ++} ++ ++static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev) ++{ ++ rtw8852a_set_txpwr_ref(rtwdev, RTW89_PHY_0); ++ rtw8852a_set_txpwr_offset(rtwdev, RTW89_PHY_0); ++} ++ ++static int ++rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ int ret; ++ ++ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); ++ if (ret) ++ return ret; ++ ++ ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) ++{ ++ u8 i = 0; ++ u32 addr, val; ++ ++ for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { ++ addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; ++ val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; ++ rtw89_phy_write32(rtwdev, addr, val); ++ } ++} ++ ++static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); ++ if (tx_info->mode == CONT_TX) ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, ++ idx); ++ else if (tx_info->mode == PKTS_TX) ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, ++ idx); ++} ++ ++static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx) ++{ ++ enum rtw8852a_pmac_mode mode = tx_info->mode; ++ u32 pkt_cnt = tx_info->tx_cnt; ++ u16 period = tx_info->period; ++ ++ if (mode == CONT_TX && !tx_info->is_cck) { ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, ++ idx); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); ++ } else if (mode == PKTS_TX) { ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, ++ idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, ++ B_PMAC_TX_PRD_MSK, period, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, ++ pkt_cnt, idx); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); ++ } ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); ++} ++ ++void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx) ++{ ++ if (!tx_info->en_pmac_tx) { ++ rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); ++ if (rtwdev->hal.current_band_type == RTW89_BAND_2G) ++ rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ return; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, ++ idx); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); ++ rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); ++ rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); ++} ++ ++void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, ++ u16 tx_cnt, u16 period, u16 tx_time, ++ enum rtw89_phy_idx idx) ++{ ++ struct rtw8852a_bb_pmac_info tx_info = {0}; ++ ++ tx_info.en_pmac_tx = enable; ++ tx_info.is_cck = 0; ++ tx_info.mode = PKTS_TX; ++ tx_info.tx_cnt = tx_cnt; ++ tx_info.period = period; ++ tx_info.tx_time = tx_time; ++ rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); ++} ++ ++void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, ++ enum rtw89_phy_idx idx) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); ++ rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); ++} ++ ++void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) ++{ ++ u32 rst_mask0 = 0; ++ u32 rst_mask1 = 0; ++ ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); ++ if (!rtwdev->dbcc_en) { ++ if (tx_path == RF_PATH_A) { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, ++ B_TXPATH_SEL_MSK, 1); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, ++ B_TXNSS_MAP_MSK, 0); ++ } else if (tx_path == RF_PATH_B) { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, ++ B_TXPATH_SEL_MSK, 2); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, ++ B_TXNSS_MAP_MSK, 0); ++ } else if (tx_path == RF_PATH_AB) { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, ++ B_TXPATH_SEL_MSK, 3); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, ++ B_TXNSS_MAP_MSK, 4); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); ++ } ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, ++ 1); ++ rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, ++ RTW89_PHY_1); ++ rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, ++ 0); ++ rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, ++ RTW89_PHY_1); ++ } ++ rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; ++ rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; ++ if (tx_path == RF_PATH_A) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); ++ } ++} ++ ++void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx idx, u8 mode) ++{ ++ if (mode != 0) ++ return; ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); ++ rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); ++} ++ ++static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) ++{ ++ rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : ++ &rtw8852a_btc_preagc_dis_defs_tbl); ++} ++ ++static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) ++{ ++ if (rtwdev->is_tssi_mode[rf_path]) { ++ u32 addr = 0x1c10 + (rf_path << 13); ++ ++ return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); ++ } ++ ++ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); ++ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); ++ rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); ++ ++ fsleep(200); ++ ++ return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); ++} ++ ++static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ ++ module->rfe_type = rtwdev->efuse.rfe_type; ++ module->cv = rtwdev->hal.cv; ++ module->bt_solo = 0; ++ module->switch_type = BTC_SWITCH_INTERNAL; ++ ++ if (module->rfe_type > 0) ++ module->ant.num = (module->rfe_type % 2 ? 2 : 3); ++ else ++ module->ant.num = 2; ++ ++ module->ant.diversity = 0; ++ module->ant.isolation = 10; ++ ++ if (module->ant.num == 3) { ++ module->ant.type = BTC_ANT_DEDICATED; ++ module->bt_pos = BTC_BT_ALONE; ++ } else { ++ module->ant.type = BTC_ANT_SHARED; ++ module->bt_pos = BTC_BT_BTG; ++ } ++} ++ ++static ++void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) ++{ ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); ++} ++ ++static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) ++{ ++ if (btg) { ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); ++ rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); ++ } ++} ++ ++static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_module *module = &btc->mdinfo; ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ const struct rtw89_mac_ax_coex coex_params = { ++ .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, ++ .direction = RTW89_MAC_AX_COEX_INNER, ++ }; ++ ++ /* PTA init */ ++ rtw89_mac_coex_init(rtwdev, &coex_params); ++ ++ /* set WL Tx response = Hi-Pri */ ++ chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); ++ chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); ++ ++ /* set rf gnt debug off */ ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); ++ ++ /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ ++ if (module->ant.type == BTC_ANT_SHARED) { ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); ++ } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); ++ rtw8852a_set_trx_mask(rtwdev, ++ RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); ++ } ++ ++ /* set PTA break table */ ++ rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); ++ ++ /* enable BT counter 0xda40[16,2] = 2b'11 */ ++ rtw89_write32_set(rtwdev, ++ R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); ++ btc->cx.wl.status.map.init_ok = true; ++} ++ ++static ++void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) ++{ ++ u32 bitmap = 0; ++ u32 reg = 0; ++ ++ switch (map) { ++ case BTC_PRI_MASK_TX_RESP: ++ reg = R_BTC_BT_COEX_MSK_TABLE; ++ bitmap = B_BTC_PRI_MASK_TX_RESP_V1; ++ break; ++ case BTC_PRI_MASK_BEACON: ++ reg = R_AX_WL_PRI_MSK; ++ bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; ++ break; ++ default: ++ return; ++ } ++ ++ if (state) ++ rtw89_write32_set(rtwdev, reg, bitmap); ++ else ++ rtw89_write32_clr(rtwdev, reg, bitmap); ++} ++ ++static inline u32 __btc_ctrl_val_all_time(u32 ctrl) ++{ ++ return FIELD_GET(GENMASK(15, 0), ctrl); ++} ++ ++static inline u32 __btc_ctrl_rst_all_time(u32 cur) ++{ ++ return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; ++} ++ ++static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) ++{ ++ u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; ++ u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; ++ ++ return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; ++} ++ ++static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) ++{ ++ return FIELD_GET(GENMASK(31, 16), ctrl); ++} ++ ++static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) ++{ ++ return cur & ~B_AX_TXAGC_BT_EN; ++} ++ ++static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) ++{ ++ u32 ov = cur & ~B_AX_TXAGC_BT_MASK; ++ u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); ++ ++ return ov | iv | B_AX_TXAGC_BT_EN; ++} ++ ++static void ++rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) ++{ ++ const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; ++ const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; ++ ++#define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) ++#define __handle(_case) \ ++ do { \ ++ const u32 _reg = __btc_cr_ ## _case; \ ++ u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ ++ u32 _cur, _wrt; \ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ ++ "btc ctrl %s: 0x%x\n", #_case, _val); \ ++ rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ ++ "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ ++ _wrt = __do_clr(_val) ? \ ++ __btc_ctrl_rst_ ## _case(_cur) : \ ++ __btc_ctrl_gen_ ## _case(_cur, _val); \ ++ rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ ++ rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ ++ "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ ++ } while (0) ++ ++ __handle(all_time); ++ __handle(gnt_bt); ++ ++#undef __handle ++#undef __do_clr ++} ++ ++static ++s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) ++{ ++ return clamp_t(s8, val, -100, 0) + 100; ++} ++ ++static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { ++ {255, 0, 0, 7}, /* 0 -> original */ ++ {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ ++ {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ ++ {6, 1, 0, 7}, ++ {13, 1, 0, 7}, ++ {13, 1, 0, 7} ++}; ++ ++static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { ++ {255, 0, 0, 7}, /* 0 -> original */ ++ {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ ++ {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ ++ {255, 1, 0, 7}, ++ {255, 1, 0, 7}, ++ {255, 1, 0, 7} ++}; ++ ++static const ++u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; ++static const ++u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; ++ ++static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), ++ RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), ++ RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), ++ RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), ++}; ++ ++static ++void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_dm *dm = &btc->dm; ++ struct rtw89_btc_bt_info *bt = &btc->cx.bt; ++ struct rtw89_btc_bt_link_info *b = &bt->link_info; ++ ++ /* fix LNA2 = level-5 for BT ACI issue at BTG */ ++ if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) ++ dm->trx_para_level = 1; ++} ++ ++static ++void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ u32 val; ++ ++ val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); ++ cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); ++ cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); ++ ++ val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); ++ cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); ++ ++ /* clock-gate off before reset counter*/ ++ rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); ++ rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); ++ rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); ++ rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); ++} ++ ++static ++void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) ++{ ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); ++ ++ /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ ++ if (state) ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, ++ RFREG_MASK, 0xa2d7c); ++ else ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, ++ RFREG_MASK, 0xa2020); ++ ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); ++} ++ ++static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status) ++{ ++ u8 path; ++ s8 *rx_power = phy_ppdu->rssi; ++ ++ status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]); ++ for (path = 0; path < rtwdev->chip->rf_path_num; path++) { ++ status->chains |= BIT(path); ++ status->chain_signal[path] = rx_power[path]; ++ } ++} ++ ++static const struct rtw89_chip_ops rtw8852a_chip_ops = { ++ .bb_reset = rtw8852a_bb_reset, ++ .bb_sethw = rtw8852a_bb_sethw, ++ .read_rf = rtw89_phy_read_rf, ++ .write_rf = rtw89_phy_write_rf, ++ .set_channel = rtw8852a_set_channel, ++ .set_channel_help = rtw8852a_set_channel_help, ++ .read_efuse = rtw8852a_read_efuse, ++ .read_phycap = rtw8852a_read_phycap, ++ .fem_setup = rtw8852a_fem_setup, ++ .rfk_init = rtw8852a_rfk_init, ++ .rfk_channel = rtw8852a_rfk_channel, ++ .rfk_band_changed = rtw8852a_rfk_band_changed, ++ .rfk_scan = rtw8852a_rfk_scan, ++ .rfk_track = rtw8852a_rfk_track, ++ .power_trim = rtw8852a_power_trim, ++ .set_txpwr = rtw8852a_set_txpwr, ++ .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, ++ .init_txpwr_unit = rtw8852a_init_txpwr_unit, ++ .get_thermal = rtw8852a_get_thermal, ++ .ctrl_btg = rtw8852a_ctrl_btg, ++ .query_ppdu = rtw8852a_query_ppdu, ++ .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, ++ .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, ++ ++ .btc_set_rfe = rtw8852a_btc_set_rfe, ++ .btc_init_cfg = rtw8852a_btc_init_cfg, ++ .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, ++ .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, ++ .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, ++ .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, ++ .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, ++ .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, ++}; ++ ++const struct rtw89_chip_info rtw8852a_chip_info = { ++ .chip_id = RTL8852A, ++ .ops = &rtw8852a_chip_ops, ++ .fw_name = "rtw89/rtw8852a_fw.bin", ++ .fifo_size = 458752, ++ .max_amsdu_limit = 3500, ++ .dis_2g_40m_ul_ofdma = true, ++ .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, ++ .dle_mem = rtw8852a_dle_mem_pcie, ++ .rf_base_addr = {0xc000, 0xd000}, ++ .pwr_on_seq = pwr_on_seq_8852a, ++ .pwr_off_seq = pwr_off_seq_8852a, ++ .bb_table = &rtw89_8852a_phy_bb_table, ++ .rf_table = {&rtw89_8852a_phy_radioa_table, ++ &rtw89_8852a_phy_radiob_table,}, ++ .nctl_table = &rtw89_8852a_phy_nctl_table, ++ .byr_table = &rtw89_8852a_byr_table, ++ .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, ++ .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, ++ .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, ++ .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, ++ .txpwr_factor_rf = 2, ++ .txpwr_factor_mac = 1, ++ .dig_table = &rtw89_8852a_phy_dig_table, ++ .rf_path_num = 2, ++ .tx_nss = 2, ++ .rx_nss = 2, ++ .acam_num = 128, ++ .bcam_num = 10, ++ .scam_num = 128, ++ .sec_ctrl_efuse_size = 4, ++ .physical_efuse_size = 1216, ++ .logical_efuse_size = 1536, ++ .limit_efuse_size = 1152, ++ .phycap_addr = 0x580, ++ .phycap_size = 128, ++ .para_ver = 0x05050764, ++ .wlcx_desired = 0x05050000, ++ .btcx_desired = 0x5, ++ .scbd = 0x1, ++ .mailbox = 0x1, ++ .afh_guard_ch = 6, ++ .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, ++ .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, ++ .rssi_tol = 2, ++ .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), ++ .mon_reg = rtw89_btc_8852a_mon_reg, ++ .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), ++ .rf_para_ulink = rtw89_btc_8852a_rf_ul, ++ .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), ++ .rf_para_dlink = rtw89_btc_8852a_rf_dl, ++ .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | ++ BIT(RTW89_PS_MODE_CLK_GATED) | ++ BIT(RTW89_PS_MODE_PWR_GATED), ++}; ++EXPORT_SYMBOL(rtw8852a_chip_info); ++ ++MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.h b/drivers/net/wireless/realtek/rtw89/rtw8852a.h +new file mode 100644 +index 000000000000..633384374de0 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.h +@@ -0,0 +1,109 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_H__ ++#define __RTW89_8852A_H__ ++ ++#include "core.h" ++ ++#define RF_PATH_NUM_8852A 2 ++#define NTX_NUM_8852A 2 ++ ++enum rtw8852a_pmac_mode { ++ NONE_TEST, ++ PKTS_TX, ++ PKTS_RX, ++ CONT_TX ++}; ++ ++struct rtw8852au_efuse { ++ u8 rsvd[0x38]; ++ u8 mac_addr[ETH_ALEN]; ++}; ++ ++struct rtw8852ae_efuse { ++ u8 mac_addr[ETH_ALEN]; ++}; ++ ++struct rtw8852a_tssi_offset { ++ u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; ++ u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; ++ u8 rsvd[7]; ++ u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; ++} __packed; ++ ++struct rtw8852a_efuse { ++ u8 rsvd[0x210]; ++ struct rtw8852a_tssi_offset path_a_tssi; ++ u8 rsvd1[10]; ++ struct rtw8852a_tssi_offset path_b_tssi; ++ u8 rsvd2[94]; ++ u8 channel_plan; ++ u8 xtal_k; ++ u8 rsvd3; ++ u8 iqk_lck; ++ u8 rsvd4[5]; ++ u8 reg_setting:2; ++ u8 tx_diversity:1; ++ u8 rx_diversity:2; ++ u8 ac_mode:1; ++ u8 module_type:2; ++ u8 rsvd5; ++ u8 shared_ant:1; ++ u8 coex_type:3; ++ u8 ant_iso:1; ++ u8 radio_on_off:1; ++ u8 rsvd6:2; ++ u8 eeprom_version; ++ u8 customer_id; ++ u8 tx_bb_swing_2g; ++ u8 tx_bb_swing_5g; ++ u8 tx_cali_pwr_trk_mode; ++ u8 trx_path_selection; ++ u8 rfe_type; ++ u8 country_code[2]; ++ u8 rsvd7[3]; ++ u8 path_a_therm; ++ u8 path_b_therm; ++ u8 rsvd8[46]; ++ u8 path_a_cck_pwr_idx[6]; ++ u8 path_a_bw40_1tx_pwr_idx[5]; ++ u8 path_a_ofdm_1tx_pwr_idx_diff:4; ++ u8 path_a_bw20_1tx_pwr_idx_diff:4; ++ u8 path_a_bw20_2tx_pwr_idx_diff:4; ++ u8 path_a_bw40_2tx_pwr_idx_diff:4; ++ u8 path_a_cck_2tx_pwr_idx_diff:4; ++ u8 path_a_ofdm_2tx_pwr_idx_diff:4; ++ u8 rsvd9[0xf2]; ++ union { ++ struct rtw8852au_efuse u; ++ struct rtw8852ae_efuse e; ++ }; ++} __packed; ++ ++struct rtw8852a_bb_pmac_info { ++ u8 en_pmac_tx:1; ++ u8 is_cck:1; ++ u8 mode:3; ++ u8 rsvd:3; ++ u16 tx_cnt; ++ u16 period; ++ u16 tx_time; ++ u8 duty_cycle; ++}; ++ ++void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev); ++void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, ++ struct rtw8852a_bb_pmac_info *tx_info, ++ enum rtw89_phy_idx idx); ++void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, ++ u16 tx_cnt, u16 period, u16 tx_time, ++ enum rtw89_phy_idx idx); ++void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, ++ enum rtw89_phy_idx idx); ++void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path); ++void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx idx, u8 mode); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c +new file mode 100644 +index 000000000000..c021e93eb07b +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.c +@@ -0,0 +1,3911 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "coex.h" ++#include "debug.h" ++#include "mac.h" ++#include "phy.h" ++#include "reg.h" ++#include "rtw8852a.h" ++#include "rtw8852a_rfk.h" ++#include "rtw8852a_rfk_table.h" ++#include "rtw8852a_table.h" ++ ++static void ++_rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); ++} ++ ++static void ++_rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); ++} ++ ++static void ++_rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_phy_write32_set(rtwdev, def->addr, def->mask); ++} ++ ++static void ++_rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); ++} ++ ++static void ++_rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) ++{ ++ udelay(def->data); ++} ++ ++static void ++(*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { ++ [RTW89_RFK_F_WRF] = _rfk_write_rf, ++ [RTW89_RFK_F_WM] = _rfk_write32_mask, ++ [RTW89_RFK_F_WS] = _rfk_write32_set, ++ [RTW89_RFK_F_WC] = _rfk_write32_clr, ++ [RTW89_RFK_F_DELAY] = _rfk_delay, ++}; ++ ++static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); ++ ++static void ++rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) ++{ ++ const struct rtw89_reg5_def *p = tbl->defs; ++ const struct rtw89_reg5_def *end = tbl->defs + tbl->size; ++ ++ for (; p < end; p++) ++ _rfk_handler[p->flag](rtwdev, p); ++} ++ ++#define rtw89_rfk_parser_by_cond(rtwdev, cond, tbl_t, tbl_f) \ ++ do { \ ++ typeof(rtwdev) _dev = (rtwdev); \ ++ if (cond) \ ++ rtw89_rfk_parser(_dev, (tbl_t)); \ ++ else \ ++ rtw89_rfk_parser(_dev, (tbl_f)); \ ++ } while (0) ++ ++static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]dbcc_en: %x, PHY%d\n", ++ rtwdev->dbcc_en, phy_idx); ++ ++ if (!rtwdev->dbcc_en) ++ return RF_AB; ++ ++ if (phy_idx == RTW89_PHY_0) ++ return RF_A; ++ else ++ return RF_B; ++} ++ ++static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0}; ++static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5}; ++#define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8852a_backup_bb_regs) ++#define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8852a_backup_rf_regs) ++ ++static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[]) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_BB_REGS_NR; i++) { ++ backup_bb_reg_val[i] = ++ rtw89_phy_read32_mask(rtwdev, rtw8852a_backup_bb_regs[i], ++ MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]backup bb reg : %x, value =%x\n", ++ rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]); ++ } ++} ++ ++static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[], ++ u8 rf_path) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_RF_REGS_NR; i++) { ++ backup_rf_reg_val[i] = ++ rtw89_read_rf(rtwdev, rf_path, ++ rtw8852a_backup_rf_regs[i], RFREG_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]backup rf S%d reg : %x, value =%x\n", rf_path, ++ rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]); ++ } ++} ++ ++static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev, ++ u32 backup_bb_reg_val[]) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_BB_REGS_NR; i++) { ++ rtw89_phy_write32_mask(rtwdev, rtw8852a_backup_bb_regs[i], ++ MASKDWORD, backup_bb_reg_val[i]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]restore bb reg : %x, value =%x\n", ++ rtw8852a_backup_bb_regs[i], backup_bb_reg_val[i]); ++ } ++} ++ ++static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev, ++ u32 backup_rf_reg_val[], u8 rf_path) ++{ ++ u32 i; ++ ++ for (i = 0; i < BACKUP_RF_REGS_NR; i++) { ++ rtw89_write_rf(rtwdev, rf_path, rtw8852a_backup_rf_regs[i], ++ RFREG_MASK, backup_rf_reg_val[i]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]restore rf S%d reg: %x, value =%x\n", rf_path, ++ rtw8852a_backup_rf_regs[i], backup_rf_reg_val[i]); ++ } ++} ++ ++static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath) ++{ ++ u8 path; ++ u32 rf_mode; ++ int ret; ++ ++ for (path = 0; path < RF_PATH_MAX; path++) { ++ if (!(kpath & BIT(path))) ++ continue; ++ ++ ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2, ++ 2, 5000, false, rtwdev, path, 0x00, ++ RR_MOD_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RFK] Wait S%d to Rx mode!! (ret = %d)\n", ++ path, ret); ++ } ++} ++ ++static void _dack_dump(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u8 i; ++ u8 t; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->addck_d[0][0], dack->addck_d[0][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S1 ADC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->addck_d[1][0], dack->addck_d[1][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->dadck_d[0][0], dack->dadck_d[0][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", ++ dack->dadck_d[1][0], dack->dadck_d[1][1]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n", ++ dack->biask_d[0][0], dack->biask_d[0][1]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S1 biask ic = 0x%x, qc = 0x%x\n", ++ dack->biask_d[1][0], dack->biask_d[1][1]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[0][0][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[0][1][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[1][0][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n"); ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ t = dack->msbk_d[1][1][i]; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t); ++ } ++} ++ ++static void _afe_init(struct rtw89_dev *rtwdev) ++{ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_afe_init_defs_tbl); ++} ++ ++static void _addck_backup(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ ++ rtw89_phy_write32_clr(rtwdev, R_S0_RXDC2, B_S0_RXDC2_SEL); ++ dack->addck_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK, ++ B_S0_ADDCK_Q); ++ dack->addck_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_ADDCK, ++ B_S0_ADDCK_I); ++ ++ rtw89_phy_write32_clr(rtwdev, R_S1_RXDC2, B_S1_RXDC2_SEL); ++ dack->addck_d[1][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK, ++ B_S1_ADDCK_Q); ++ dack->addck_d[1][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S1_ADDCK, ++ B_S1_ADDCK_I); ++} ++ ++static void _addck_reload(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_I, dack->addck_d[0][0]); ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2, B_S0_RXDC2_Q2, ++ (dack->addck_d[0][1] >> 6)); ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC, B_S0_RXDC_Q, ++ (dack->addck_d[0][1] & 0x3f)); ++ rtw89_phy_write32_set(rtwdev, R_S0_RXDC2, B_S0_RXDC2_MEN); ++ rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_I, dack->addck_d[1][0]); ++ rtw89_phy_write32_mask(rtwdev, R_S1_RXDC2, B_S1_RXDC2_Q2, ++ (dack->addck_d[1][1] >> 6)); ++ rtw89_phy_write32_mask(rtwdev, R_S1_RXDC, B_S1_RXDC_Q, ++ (dack->addck_d[1][1] & 0x3f)); ++ rtw89_phy_write32_set(rtwdev, R_S1_RXDC2, B_S1_RXDC2_EN); ++} ++ ++static void _dack_backup_s0(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u8 i; ++ ++ rtw89_phy_write32_set(rtwdev, R_S0_DACKI, B_S0_DACKI_EN); ++ rtw89_phy_write32_set(rtwdev, R_S0_DACKQ, B_S0_DACKQ_EN); ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG); ++ ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_S0_DACKI, B_S0_DACKI_AR, i); ++ dack->msbk_d[0][0][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI7, B_S0_DACKI7_K); ++ rtw89_phy_write32_mask(rtwdev, R_S0_DACKQ, B_S0_DACKQ_AR, i); ++ dack->msbk_d[0][1][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ7, B_S0_DACKQ7_K); ++ } ++ dack->biask_d[0][0] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI2, ++ B_S0_DACKI2_K); ++ dack->biask_d[0][1] = (u16)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ2, ++ B_S0_DACKQ2_K); ++ dack->dadck_d[0][0] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKI8, ++ B_S0_DACKI8_K) - 8; ++ dack->dadck_d[0][1] = (u8)rtw89_phy_read32_mask(rtwdev, R_S0_DACKQ8, ++ B_S0_DACKQ8_K) - 8; ++} ++ ++static void _dack_backup_s1(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u8 i; ++ ++ rtw89_phy_write32_set(rtwdev, R_S1_DACKI, B_S1_DACKI_EN); ++ rtw89_phy_write32_set(rtwdev, R_S1_DACKQ, B_S1_DACKQ_EN); ++ rtw89_phy_write32_set(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON); ++ ++ for (i = 0; i < RTW89_DACK_MSBK_NR; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_S1_DACKI, B_S1_DACKI_AR, i); ++ dack->msbk_d[1][0][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI7, B_S1_DACKI_K); ++ rtw89_phy_write32_mask(rtwdev, R_S1_DACKQ, B_S1_DACKQ_AR, i); ++ dack->msbk_d[1][1][i] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ7, B_S1_DACKQ7_K); ++ } ++ dack->biask_d[1][0] = ++ (u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI2, B_S1_DACKI2_K); ++ dack->biask_d[1][1] = ++ (u16)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ2, B_S1_DACKQ2_K); ++ dack->dadck_d[1][0] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKI8, B_S1_DACKI8_K) - 8; ++ dack->dadck_d[1][1] = ++ (u8)rtw89_phy_read32_mask(rtwdev, R_S1_DACKQ8, B_S1_DACKQ8_K) - 8; ++} ++ ++static void _dack_reload_by_path(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 index) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 tmp = 0, tmp_offset, tmp_reg; ++ u8 i; ++ u32 idx_offset, path_offset; ++ ++ if (index == 0) ++ idx_offset = 0; ++ else ++ idx_offset = 0x50; ++ ++ if (path == RF_PATH_A) ++ path_offset = 0; ++ else ++ path_offset = 0x2000; ++ ++ tmp_offset = idx_offset + path_offset; ++ /* msbk_d: 15/14/13/12 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i + 12] << (i * 8); ++ tmp_reg = 0x5e14 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* msbk_d: 11/10/9/8 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i + 8] << (i * 8); ++ tmp_reg = 0x5e18 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* msbk_d: 7/6/5/4 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i + 4] << (i * 8); ++ tmp_reg = 0x5e1c + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* msbk_d: 3/2/1/0 */ ++ tmp = 0x0; ++ for (i = 0; i < RTW89_DACK_MSBK_NR / 4; i++) ++ tmp |= dack->msbk_d[path][index][i] << (i * 8); ++ tmp_reg = 0x5e20 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, ++ rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); ++ /* dadak_d/biask_d */ ++ tmp = 0x0; ++ tmp = (dack->biask_d[path][index] << 22) | ++ (dack->dadck_d[path][index] << 14); ++ tmp_reg = 0x5e24 + tmp_offset; ++ rtw89_phy_write32(rtwdev, tmp_reg, tmp); ++} ++ ++static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ u8 i; ++ ++ for (i = 0; i < 2; i++) ++ _dack_reload_by_path(rtwdev, path, i); ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_dack_reload_defs_a_tbl, ++ &rtw8852a_rfk_dack_reload_defs_b_tbl); ++} ++ ++#define ADDC_T_AVG 100 ++static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ s32 dc_re = 0, dc_im = 0; ++ u32 tmp; ++ u32 i; ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_check_addc_defs_a_tbl, ++ &rtw8852a_rfk_check_addc_defs_b_tbl); ++ ++ for (i = 0; i < ADDC_T_AVG; i++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, R_DBG32_D, MASKDWORD); ++ dc_re += sign_extend32(FIELD_GET(0xfff000, tmp), 11); ++ dc_im += sign_extend32(FIELD_GET(0xfff, tmp), 11); ++ } ++ ++ dc_re /= ADDC_T_AVG; ++ dc_im /= ADDC_T_AVG; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); ++} ++ ++static void _addck(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 val; ++ int ret; ++ ++ /* S0 */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_a_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S0 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_A); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_a_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x1e00, BIT(0)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n"); ++ dack->addck_timeout[0] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_A); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_a_tbl); ++ ++ /* S1 */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_reset_defs_b_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]before S1 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_B); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_trigger_defs_b_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x3e00, BIT(0)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADDCK timeout\n"); ++ dack->addck_timeout[1] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 ADDCK\n"); ++ _check_addc(rtwdev, RF_PATH_B); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_addck_restore_defs_b_tbl); ++} ++ ++static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_check_dadc_defs_f_a_tbl, ++ &rtw8852a_rfk_check_dadc_defs_f_b_tbl); ++ ++ _check_addc(rtwdev, path); ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_rfk_check_dadc_defs_r_a_tbl, ++ &rtw8852a_rfk_check_dadc_defs_r_b_tbl); ++} ++ ++static void _dack_s0(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 val; ++ int ret; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_a_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e28, BIT(15)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e78, BIT(15)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK timeout\n"); ++ dack->msbk_timeout[0] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_a_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e48, BIT(17)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x5e98, BIT(17)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADACK timeout\n"); ++ dack->dadck_timeout[0] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_a_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n"); ++ _check_dadc(rtwdev, RF_PATH_A); ++ ++ _dack_backup_s0(rtwdev); ++ _dack_reload(rtwdev, RF_PATH_A); ++ ++ rtw89_phy_write32_clr(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG); ++} ++ ++static void _dack_s1(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 val; ++ int ret; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_f_b_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e28, BIT(15)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e78, BIT(15)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK timeout\n"); ++ dack->msbk_timeout[1] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_m_b_tbl); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e48, BIT(17)); ++ ret |= read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val, 1, 10000, ++ false, rtwdev, 0x7e98, BIT(17)); ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DADCK timeout\n"); ++ dack->dadck_timeout[1] = true; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dack_defs_r_b_tbl); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S1 DADCK\n"); ++ _check_dadc(rtwdev, RF_PATH_B); ++ ++ _dack_backup_s1(rtwdev); ++ _dack_reload(rtwdev, RF_PATH_B); ++ ++ rtw89_phy_write32_clr(rtwdev, R_P1_DBGMOD, B_P1_DBGMOD_ON); ++} ++ ++static void _dack(struct rtw89_dev *rtwdev) ++{ ++ _dack_s0(rtwdev); ++ _dack_s1(rtwdev); ++} ++ ++static void _dac_cal(struct rtw89_dev *rtwdev, bool force) ++{ ++ struct rtw89_dack_info *dack = &rtwdev->dack; ++ u32 rf0_0, rf1_0; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, RF_AB); ++ ++ dack->dack_done = false; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK b\n"); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n"); ++ rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK); ++ rf1_0 = rtw89_read_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK); ++ _afe_init(rtwdev); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x30001); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x30001); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START); ++ _addck(rtwdev); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP); ++ _addck_backup(rtwdev); ++ _addck_reload(rtwdev); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, 0x40001); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MODOPT, RFREG_MASK, 0x0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MODOPT, RFREG_MASK, 0x0); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_START); ++ _dack(rtwdev); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_ONESHOT_STOP); ++ _dack_dump(rtwdev); ++ dack->dack_done = true; ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, rf0_0); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_MOD, RFREG_MASK, rf1_0); ++ rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1); ++ rtw89_write_rf(rtwdev, RF_PATH_B, RR_RSV1, RR_RSV1_RST, 0x1); ++ dack->dack_cnt++; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n"); ++} ++ ++#define RTW8852A_NCTL_VER 0xd ++#define RTW8852A_IQK_VER 0x2a ++#define RTW8852A_IQK_SS 2 ++#define RTW8852A_IQK_THR_REK 8 ++#define RTW8852A_IQK_CFIR_GROUP_NR 4 ++ ++enum rtw8852a_iqk_type { ++ ID_TXAGC, ++ ID_FLOK_COARSE, ++ ID_FLOK_FINE, ++ ID_TXK, ++ ID_RXAGC, ++ ID_RXK, ++ ID_NBTXK, ++ ID_NBRXK, ++}; ++ ++static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path) ++{ ++ u8 i = 0x0; ++ u32 fft[6] = {0x0}; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00160000); ++ fft[0] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00170000); ++ fft[1] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00180000); ++ fft[2] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00190000); ++ fft[3] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001a0000); ++ fft[4] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x001b0000); ++ fft[5] = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD); ++ for (i = 0; i < 6; i++) ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x,fft[%x]= %x\n", ++ path, i, fft[i]); ++} ++ ++static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path) ++{ ++ u8 i = 0x0; ++ u32 tmp = 0x0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX, 0x1); ++ ++ for (i = 0x0; i < 0x18; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x000000c0 + i); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N2, MASKDWORD); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = %x\n", ++ path, BIT(path), tmp); ++ udelay(1); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_IQK_DIF, B_IQK_DIF_TRX); ++ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_N2, MASKDWORD, 0x80010100); ++ udelay(1); ++} ++ ++static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, ++ u8 group) ++{ ++ static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = { ++ {0x8f20, 0x8f54, 0x8f88, 0x8fbc}, ++ {0x9320, 0x9354, 0x9388, 0x93bc}, ++ }; ++ u8 idx = 0x0; ++ u32 tmp = 0x0; ++ u32 base_addr; ++ ++ if (path >= RTW8852A_IQK_SS) { ++ rtw89_warn(rtwdev, "cfir path %d out of range\n", path); ++ return; ++ } ++ if (group >= RTW8852A_IQK_CFIR_GROUP_NR) { ++ rtw89_warn(rtwdev, "cfir group %d out of range\n", group); ++ return; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); ++ ++ base_addr = base_addrs[path][group]; ++ ++ for (idx = 0; idx < 0x0d; idx++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK] %x = %x\n", ++ base_addr + (idx << 2), tmp); ++ } ++ ++ if (path == 0x0) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f50 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8f84 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fb8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P0C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8fec = %x\n", tmp); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9350 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9384 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93b8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXCFIR_P1C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x93ec = %x\n", tmp); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc); ++ udelay(1); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, ++ BIT(path), tmp); ++} ++ ++static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, ++ u8 group) ++{ ++ static const u32 base_addrs[RTW8852A_IQK_SS][RTW8852A_IQK_CFIR_GROUP_NR] = { ++ {0x8d00, 0x8d44, 0x8d88, 0x8dcc}, ++ {0x9100, 0x9144, 0x9188, 0x91cc}, ++ }; ++ u8 idx = 0x0; ++ u32 tmp = 0x0; ++ u32 base_addr; ++ ++ if (path >= RTW8852A_IQK_SS) { ++ rtw89_warn(rtwdev, "cfir path %d out of range\n", path); ++ return; ++ } ++ if (group >= RTW8852A_IQK_CFIR_GROUP_NR) { ++ rtw89_warn(rtwdev, "cfir group %d out of range\n", group); ++ return; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); ++ ++ base_addr = base_addrs[path][group]; ++ for (idx = 0; idx < 0x10; idx++) { ++ tmp = rtw89_phy_read32_mask(rtwdev, base_addr + (idx << 2), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]%x = %x\n", ++ base_addr + (idx << 2), tmp); ++ } ++ ++ if (path == 0x0) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d40 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8d84 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8dc8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P0C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x8e0c = %x\n", tmp); ++ } else { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]\n"); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C0, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9140 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C1, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x9184 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C2, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x91c8 = %x\n", tmp); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXCFIR_P1C3, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] 0x920c = %x\n", tmp); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, ++ BIT(path), tmp); ++} ++ ++static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path) ++{ ++ u32 tmp = 0x0; ++ u32 i = 0x0; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000); ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080); ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); ++ ++ for (i = 0; i <= 0x9f; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp); ++ } ++ ++ for (i = 0; i <= 0x9f; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000 + i); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n", tmp); ++ } ++ rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX2, MASKDWORD); ++ rtw89_phy_write32_clr(rtwdev, R_SRAM_IQRX, MASKDWORD); ++} ++ ++static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 tmp = 0x0; ++ ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0xa041); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x0); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H2, 0x0); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000); ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); ++ rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5); ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); ++ break; ++ default: ++ break; ++ } ++ tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); ++ fsleep(128); ++} ++ ++static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype) ++{ ++ u32 tmp; ++ u32 val; ++ int ret; ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, 1, 8200, ++ false, rtwdev, 0xbff8, MASKBYTE0); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]IQK timeout!!!\n"); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); ++ tmp = rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp); ++ ++ return false; ++} ++ ++static bool _iqk_one_shot(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path, u8 ktype) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ bool fail = false; ++ u32 iqk_cmd = 0x0; ++ u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path); ++ u32 addr_rfc_ctl = 0x0; ++ ++ if (path == RF_PATH_A) ++ addr_rfc_ctl = 0x5864; ++ else ++ addr_rfc_ctl = 0x7864; ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START); ++ switch (ktype) { ++ case ID_TXAGC: ++ iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); ++ break; ++ case ID_FLOK_COARSE: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); ++ iqk_cmd = 0x108 | (1 << (4 + path)); ++ break; ++ case ID_FLOK_FINE: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009); ++ iqk_cmd = 0x208 | (1 << (4 + path)); ++ break; ++ case ID_TXK: ++ rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025); ++ iqk_cmd = 0x008 | (1 << (path + 4)) | ++ (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); ++ break; ++ case ID_RXAGC: ++ iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); ++ break; ++ case ID_RXK: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); ++ iqk_cmd = 0x008 | (1 << (path + 4)) | ++ (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); ++ break; ++ case ID_NBTXK: ++ rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x025); ++ iqk_cmd = 0x308 | (1 << (4 + path)); ++ break; ++ case ID_NBRXK: ++ rtw89_phy_write32_set(rtwdev, addr_rfc_ctl, 0x20000000); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011); ++ iqk_cmd = 0x608 | (1 << (4 + path)); ++ break; ++ default: ++ return false; ++ } ++ ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1); ++ rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN); ++ udelay(1); ++ fail = _iqk_check_cal(rtwdev, path, ktype); ++ if (iqk_info->iqk_xym_en) ++ _iqk_read_xym_dbcc0(rtwdev, path); ++ if (iqk_info->iqk_fft_en) ++ _iqk_read_fft_dbcc0(rtwdev, path); ++ if (iqk_info->iqk_sram_en) ++ _iqk_sram(rtwdev, path); ++ if (iqk_info->iqk_cfir_en) { ++ if (ktype == ID_TXK) { ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0); ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1); ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2); ++ _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3); ++ } else { ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0); ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1); ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2); ++ _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3); ++ } ++ } ++ ++ rtw89_phy_write32_clr(rtwdev, addr_rfc_ctl, 0x20000000); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP); ++ ++ return fail; ++} ++ ++static bool _rxk_group_sel(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ static const u32 rxgn_a[4] = {0x18C, 0x1A0, 0x28C, 0x2A0}; ++ static const u32 attc2_a[4] = {0x0, 0x0, 0x07, 0x30}; ++ static const u32 attc1_a[4] = {0x7, 0x5, 0x1, 0x1}; ++ static const u32 rxgn_g[4] = {0x1CC, 0x1E0, 0x2CC, 0x2E0}; ++ static const u32 attc2_g[4] = {0x0, 0x15, 0x3, 0x1a}; ++ static const u32 attc1_g[4] = {0x1, 0x0, 0x1, 0x0}; ++ u8 gp = 0x0; ++ bool fail = false; ++ u32 rf0 = 0x0; ++ ++ for (gp = 0; gp < 0x4; gp++) { ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET); ++ rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, ++ rf0 | iqk_info->syn1to2); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100); ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp); ++ rtw89_phy_write32_mask(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN, 0x1); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail); ++ } ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); ++ break; ++ default: ++ break; ++ } ++ iqk_info->nb_rxcfir[path] = 0x40000000; ++ rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), ++ B_IQK_RES_RXCFIR, 0x5); ++ iqk_info->is_wb_rxiqk[path] = true; ++ return false; ++} ++ ++static bool _iqk_nbrxk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 group = 0x0; ++ u32 rf0 = 0x0, tmp = 0x0; ++ u32 idxrxgain_a = 0x1a0; ++ u32 idxattc2_a = 0x00; ++ u32 idxattc1_a = 0x5; ++ u32 idxrxgain_g = 0x1E0; ++ u32 idxattc2_g = 0x15; ++ u32 idxattc1_g = 0x0; ++ bool fail = false; ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a); ++ rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET); ++ rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, ++ rf0 | iqk_info->syn1to2); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_COM, MASKDWORD, 0x40010100); ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_GP, group); ++ rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); ++ break; ++ default: ++ break; ++ } ++ if (!fail) { ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); ++ iqk_info->nb_rxcfir[path] = tmp | 0x2; ++ } else { ++ iqk_info->nb_rxcfir[path] = 0x40000002; ++ } ++ return fail; ++} ++ ++static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), ++ MASKDWORD, 0x4d000a08); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ B_P0_RXCK_VAL, 0x2); ++ rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); ++ rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON); ++ rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL, 0x1); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), ++ MASKDWORD, 0x44000a08); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ B_P0_RXCK_VAL, 0x1); ++ rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); ++ rtw89_phy_write32_set(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_ON); ++ rtw89_phy_write32_clr(rtwdev, R_UPD_CLK_ADC, B_UPD_CLK_ADC_VAL); ++ } ++} ++ ++static bool _txk_group_sel(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ static const u32 a_txgain[4] = {0xE466, 0x646D, 0xE4E2, 0x64ED}; ++ static const u32 g_txgain[4] = {0x60e8, 0x60f0, 0x61e8, 0x61ED}; ++ static const u32 a_itqt[4] = {0x12, 0x12, 0x12, 0x1b}; ++ static const u32 g_itqt[4] = {0x09, 0x12, 0x12, 0x12}; ++ static const u32 g_attsmxr[4] = {0x0, 0x1, 0x1, 0x1}; ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ bool fail = false; ++ u8 gp = 0x0; ++ u32 tmp = 0x0; ++ ++ for (gp = 0x0; gp < 0x4; gp++) { ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x08); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, ++ g_txgain[gp]); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, ++ g_attsmxr[gp]); ++ rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, ++ g_attsmxr[gp]); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), ++ MASKDWORD, g_itqt[gp]); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x04); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, ++ a_txgain[gp]); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), ++ MASKDWORD, a_itqt[gp]); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_GP, gp); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(8 + gp + path * 4), fail); ++ } ++ ++ iqk_info->nb_txcfir[path] = 0x40000000; ++ rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), ++ B_IQK_RES_TXCFIR, 0x5); ++ iqk_info->is_wb_txiqk[path] = true; ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, ++ BIT(path), tmp); ++ return false; ++} ++ ++static bool _iqk_nbtxk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 group = 0x2; ++ u32 a_mode_txgain = 0x64e2; ++ u32 g_mode_txgain = 0x61e8; ++ u32 attsmxr = 0x1; ++ u32 itqt = 0x12; ++ u32 tmp = 0x0; ++ bool fail = false; ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x08); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, g_mode_txgain); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, attsmxr); ++ rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, attsmxr); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), ++ B_RFGAIN_BND, 0x04); ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, a_mode_txgain); ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, group); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); ++ if (!fail) { ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ iqk_info->nb_txcfir[path] = tmp | 0x2; ++ } else { ++ iqk_info->nb_txcfir[path] = 0x40000002; ++ } ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, ++ BIT(path), tmp); ++ return fail; ++} ++ ++static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); ++ if (iqk_info->iqk_band[path] == RTW89_BAND_2G) ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); ++ else ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); ++} ++ ++static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) ++{ ++ bool is_fail = false; ++ u32 tmp = 0x0; ++ u32 core_i = 0x0; ++ u32 core_q = 0x0; ++ ++ tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK][FineLOK] S%x, 0x58 = 0x%x\n", ++ path, tmp); ++ core_i = FIELD_GET(RR_TXMO_COI, tmp); ++ core_q = FIELD_GET(RR_TXMO_COQ, tmp); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q); ++ ++ if (core_i < 0x2 || core_i > 0x1d || core_q < 0x2 || core_q > 0x1d) ++ is_fail = true; ++ return is_fail; ++} ++ ++static bool _iqk_lok(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 rf0 = 0x0; ++ u8 itqt = 0x12; ++ bool fail = false; ++ bool tmp = false; ++ ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0); ++ itqt = 0x09; ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0); ++ itqt = 0x12; ++ break; ++ default: ++ break; ++ } ++ rtw89_phy_write32_set(rtwdev, R_IQK_CFG, B_IQK_CFG_SET); ++ rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF1, B_IQK_DIF1_TXPI, ++ rf0 | iqk_info->syn1to2); ++ rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0); ++ rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, B_IOQ_IQK_DPK_EN); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); ++ tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE); ++ iqk_info->lok_cor_fail[0][path] = tmp; ++ fsleep(10); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); ++ tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE); ++ iqk_info->lok_fin_fail[0][path] = tmp; ++ fail = _lok_finetune_check(rtwdev, path); ++ return fail; ++} ++ ++static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041); ++ udelay(1); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0303); ++ rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0000); ++ switch (iqk_info->iqk_band[path]) { ++ case RTW89_BAND_2G: ++ rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00); ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000); ++ rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, ++ 0x403e0 | iqk_info->syn1to2); ++ udelay(1); ++ break; ++ case RTW89_BAND_5G: ++ rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); ++ rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7); ++ rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100); ++ rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, ++ 0x403e0 | iqk_info->syn1to2); ++ udelay(1); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); ++} ++ ++static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 tmp = 0x0; ++ bool flag = 0x0; ++ ++ iqk_info->thermal[path] = ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ iqk_info->thermal_rek_en = false; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %d\n", path, ++ iqk_info->thermal[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path, ++ iqk_info->lok_cor_fail[0][path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path, ++ iqk_info->lok_fin_fail[0][path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path, ++ iqk_info->iqk_tx_fail[0][path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path, ++ iqk_info->iqk_rx_fail[0][path]); ++ flag = iqk_info->lok_cor_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag); ++ flag = iqk_info->lok_fin_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(1) << (path * 4), flag); ++ flag = iqk_info->iqk_tx_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(2) << (path * 4), flag); ++ flag = iqk_info->iqk_rx_fail[0][path]; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(3) << (path * 4), flag); ++ ++ tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); ++ iqk_info->bp_iqkenable[path] = tmp; ++ tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); ++ iqk_info->bp_txkresult[path] = tmp; ++ tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); ++ iqk_info->bp_rxkresult[path] = tmp; ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, ++ (u8)iqk_info->iqk_times); ++ ++ tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4)); ++ if (tmp != 0x0) ++ iqk_info->iqk_fail_cnt++; ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4), ++ iqk_info->iqk_fail_cnt); ++} ++ ++static ++void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ bool lok_is_fail = false; ++ u8 ibias = 0x1; ++ u8 i = 0; ++ ++ _iqk_txclk_setting(rtwdev, path); ++ ++ for (i = 0; i < 3; i++) { ++ _lok_res_table(rtwdev, path, ibias++); ++ _iqk_txk_setting(rtwdev, path); ++ lok_is_fail = _iqk_lok(rtwdev, phy_idx, path); ++ if (!lok_is_fail) ++ break; ++ } ++ if (iqk_info->is_nbiqk) ++ iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); ++ else ++ iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); ++ ++ _iqk_rxclk_setting(rtwdev, path); ++ _iqk_rxk_setting(rtwdev, path); ++ if (iqk_info->is_nbiqk || rtwdev->dbcc_en || iqk_info->iqk_band[path] == RTW89_BAND_2G) ++ iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); ++ else ++ iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); ++ ++ _iqk_info_iqk(rtwdev, phy_idx, path); ++} ++ ++static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ u32 reg_rf18 = 0x0, reg_35c = 0x0; ++ u8 idx = 0; ++ u8 get_empty_table = false; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) { ++ if (iqk_info->iqk_mcc_ch[idx][path] == 0) { ++ get_empty_table = true; ++ break; ++ } ++ } ++ if (!get_empty_table) { ++ idx = iqk_info->iqk_table_idx[path] + 1; ++ if (idx > RTW89_IQK_CHS_NR - 1) ++ idx = 0; ++ } ++ reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]cfg ch = %d\n", reg_rf18); ++ reg_35c = rtw89_phy_read32_mask(rtwdev, 0x35c, 0x00000c00); ++ ++ iqk_info->iqk_band[path] = hal->current_band_type; ++ iqk_info->iqk_bw[path] = hal->current_band_width; ++ iqk_info->iqk_ch[path] = hal->current_channel; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, ++ iqk_info->iqk_band[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_bw[%x] = 0x%x\n", ++ path, iqk_info->iqk_bw[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]iqk_info->iqk_ch[%x] = 0x%x\n", ++ path, iqk_info->iqk_ch[path]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy, ++ rtwdev->dbcc_en ? "on" : "off", ++ iqk_info->iqk_band[path] == 0 ? "2G" : ++ iqk_info->iqk_band[path] == 1 ? "5G" : "6G", ++ iqk_info->iqk_ch[path], ++ iqk_info->iqk_bw[path] == 0 ? "20M" : ++ iqk_info->iqk_bw[path] == 1 ? "40M" : "80M"); ++ if (reg_35c == 0x01) ++ iqk_info->syn1to2 = 0x1; ++ else ++ iqk_info->syn1to2 = 0x0; ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF, B_IQKINF_VER, RTW8852A_IQK_VER); ++ rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16), ++ (u8)iqk_info->iqk_band[path]); ++ rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16), ++ (u8)iqk_info->iqk_bw[path]); ++ rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16), ++ (u8)iqk_info->iqk_ch[path]); ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x000000ff, RTW8852A_NCTL_VER); ++} ++ ++static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ u8 path) ++{ ++ _iqk_by_path(rtwdev, phy_idx, path); ++} ++ ++static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ ++ rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, ++ iqk_info->nb_txcfir[path]); ++ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, ++ iqk_info->nb_rxcfir[path]); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_RPT, MASKDWORD); ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_RX_DCK, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); ++ rtw89_phy_write32_clr(rtwdev, R_KPATH_CFG, MASKDWORD); ++ rtw89_phy_write32_clr(rtwdev, R_GAPK, B_GAPK_ADR); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); ++ rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4); ++ rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); ++ rtw89_phy_write32_clr(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW); ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); ++} ++ ++static void _iqk_afebb_restore(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ const struct rtw89_rfk_tbl *tbl; ++ ++ switch (_kpath(rtwdev, phy_idx)) { ++ case RF_A: ++ tbl = &rtw8852a_rfk_iqk_restore_defs_dbcc_path0_tbl; ++ break; ++ case RF_B: ++ tbl = &rtw8852a_rfk_iqk_restore_defs_dbcc_path1_tbl; ++ break; ++ default: ++ tbl = &rtw8852a_rfk_iqk_restore_defs_nondbcc_path01_tbl; ++ break; ++ } ++ ++ rtw89_rfk_parser(rtwdev, tbl); ++} ++ ++static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 idx = iqk_info->iqk_table_idx[path]; ++ ++ if (rtwdev->dbcc_en) { ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), ++ B_COEF_SEL_IQC, path & 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_G2, path & 0x1); ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), ++ B_COEF_SEL_IQC, idx); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), ++ B_CFIR_LUT_G2, idx); ++ } ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_RW, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a); ++ rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, MASKDWORD, 0x00200000); ++ rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000); ++ rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD); ++} ++ ++static void _iqk_macbb_setting(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ const struct rtw89_rfk_tbl *tbl; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===> %s\n", __func__); ++ ++ switch (_kpath(rtwdev, phy_idx)) { ++ case RF_A: ++ tbl = &rtw8852a_rfk_iqk_set_defs_dbcc_path0_tbl; ++ break; ++ case RF_B: ++ tbl = &rtw8852a_rfk_iqk_set_defs_dbcc_path1_tbl; ++ break; ++ default: ++ tbl = &rtw8852a_rfk_iqk_set_defs_nondbcc_path01_tbl; ++ break; ++ } ++ ++ rtw89_rfk_parser(rtwdev, tbl); ++} ++ ++static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 phy_idx = 0x0; ++ ++ iqk_info->iqk_times++; ++ ++ if (path == 0x0) ++ phy_idx = RTW89_PHY_0; ++ else ++ phy_idx = RTW89_PHY_1; ++ ++ _iqk_get_ch_info(rtwdev, phy_idx, path); ++ _iqk_macbb_setting(rtwdev, phy_idx, path); ++ _iqk_preset(rtwdev, path); ++ _iqk_start_iqk(rtwdev, phy_idx, path); ++ _iqk_restore(rtwdev, path); ++ _iqk_afebb_restore(rtwdev, phy_idx, path); ++} ++ ++static void _iqk_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_iqk_info *iqk = &rtwdev->iqk; ++ u8 path = 0x0; ++ u8 cur_ther; ++ ++ if (iqk->iqk_band[0] == RTW89_BAND_2G) ++ return; ++ if (iqk->iqk_bw[0] < RTW89_CHANNEL_WIDTH_80) ++ return; ++ ++ /* only check path 0 */ ++ for (path = 0; path < 1; path++) { ++ cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ ++ if (abs(cur_ther - iqk->thermal[path]) > RTW8852A_IQK_THR_REK) ++ iqk->thermal_rek_en = true; ++ else ++ iqk->thermal_rek_en = false; ++ } ++} ++ ++static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) ++{ ++ u32 rf_reg5, rck_val = 0; ++ u32 val; ++ int ret; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); ++ ++ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); ++ ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%x\n", ++ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); ++ ++ /* RCK trigger */ ++ rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); ++ ++ ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 20, ++ false, rtwdev, path, 0x1c, BIT(3)); ++ if (ret) ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RCK timeout\n"); ++ ++ rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); ++ rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); ++ ++ /* RCK_ADC_OFFSET */ ++ rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4); ++ ++ rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0); ++ ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RCK] RF 0x1b / 0x1c / 0x1d = 0x%x / 0x%x / 0x%x\n", ++ rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_RCKO, RFREG_MASK)); ++} ++ ++static void _iqk_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u8 ch, path; ++ ++ rtw89_phy_write32_clr(rtwdev, R_IQKINF, MASKDWORD); ++ if (iqk_info->is_iqk_init) ++ return; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__); ++ iqk_info->is_iqk_init = true; ++ iqk_info->is_nbiqk = false; ++ iqk_info->iqk_fft_en = false; ++ iqk_info->iqk_sram_en = false; ++ iqk_info->iqk_cfir_en = false; ++ iqk_info->iqk_xym_en = false; ++ iqk_info->thermal_rek_en = false; ++ iqk_info->iqk_times = 0x0; ++ ++ for (ch = 0; ch < RTW89_IQK_CHS_NR; ch++) { ++ iqk_info->iqk_channel[ch] = 0x0; ++ for (path = 0; path < RTW8852A_IQK_SS; path++) { ++ iqk_info->lok_cor_fail[ch][path] = false; ++ iqk_info->lok_fin_fail[ch][path] = false; ++ iqk_info->iqk_tx_fail[ch][path] = false; ++ iqk_info->iqk_rx_fail[ch][path] = false; ++ iqk_info->iqk_mcc_ch[ch][path] = 0x0; ++ iqk_info->iqk_table_idx[path] = 0x0; ++ } ++ } ++} ++ ++static void _doiqk(struct rtw89_dev *rtwdev, bool force, ++ enum rtw89_phy_idx phy_idx, u8 path) ++{ ++ struct rtw89_iqk_info *iqk_info = &rtwdev->iqk; ++ u32 backup_bb_val[BACKUP_BB_REGS_NR]; ++ u32 backup_rf_val[RTW8852A_IQK_SS][BACKUP_RF_REGS_NR]; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[IQK]==========IQK strat!!!!!==========\n"); ++ iqk_info->iqk_times++; ++ iqk_info->kcount = 0; ++ iqk_info->version = RTW8852A_IQK_VER; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version); ++ _iqk_get_ch_info(rtwdev, phy_idx, path); ++ _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); ++ _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ _iqk_macbb_setting(rtwdev, phy_idx, path); ++ _iqk_preset(rtwdev, path); ++ _iqk_start_iqk(rtwdev, phy_idx, path); ++ _iqk_restore(rtwdev, path); ++ _iqk_afebb_restore(rtwdev, phy_idx, path); ++ _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); ++ _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP); ++} ++ ++static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force) ++{ ++ switch (_kpath(rtwdev, phy_idx)) { ++ case RF_A: ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_A); ++ break; ++ case RF_B: ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_B); ++ break; ++ case RF_AB: ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_A); ++ _doiqk(rtwdev, force, phy_idx, RF_PATH_B); ++ break; ++ default: ++ break; ++ } ++} ++ ++#define RXDCK_VER_8852A 0xe ++ ++static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, bool is_afe) ++{ ++ u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path); ++ u32 ori_val; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RX_DCK] ==== S%d RX DCK (by %s)====\n", ++ path, is_afe ? "AFE" : "RFC"); ++ ++ ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD); ++ ++ if (is_afe) { ++ rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ B_P0_RXCK_VAL, 0x3); ++ rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN); ++ rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2 + (path << 13), ++ B_S0_RXDC2_AVG, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15_H, 0x3); ++ rtw89_phy_write32_clr(rtwdev, R_ANAPAR, B_ANAPAR_ADCCLK); ++ rtw89_phy_write32_clr(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST); ++ rtw89_phy_write32_set(rtwdev, R_ANAPAR, B_ANAPAR_FLTRST); ++ rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_CRXBB, 0x1); ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f); ++ rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_SEL, is_afe); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_ONESHOT_START); ++ ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); ++ ++ fsleep(600); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_ONESHOT_STOP); ++ ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); ++ ++ if (is_afe) { ++ rtw89_phy_write32_clr(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), ++ MASKDWORD, ori_val); ++ } ++} ++ ++static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ bool is_afe) ++{ ++ u8 path, kpath, dck_tune; ++ u32 rf_reg5; ++ u32 addr; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n", ++ RXDCK_VER_8852A, rtwdev->hal.cv); ++ ++ kpath = _kpath(rtwdev, phy); ++ ++ for (path = 0; path < 2; path++) { ++ if (!(kpath & BIT(path))) ++ continue; ++ ++ rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); ++ dck_tune = (u8)rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); ++ ++ if (rtwdev->is_tssi_mode[path]) { ++ addr = 0x5818 + (path << 13); ++ /* TSSI pause */ ++ rtw89_phy_write32_set(rtwdev, addr, BIT(30)); ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ _set_rx_dck(rtwdev, phy, path, is_afe); ++ rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); ++ ++ if (rtwdev->is_tssi_mode[path]) { ++ addr = 0x5818 + (path << 13); ++ /* TSSI resume */ ++ rtw89_phy_write32_clr(rtwdev, addr, BIT(30)); ++ } ++ } ++} ++ ++#define RTW8852A_RF_REL_VERSION 34 ++#define RTW8852A_DPK_VER 0x10 ++#define RTW8852A_DPK_TH_AVG_NUM 4 ++#define RTW8852A_DPK_RF_PATH 2 ++#define RTW8852A_DPK_KIP_REG_NUM 2 ++ ++enum rtw8852a_dpk_id { ++ LBK_RXIQK = 0x06, ++ SYNC = 0x10, ++ MDPK_IDL = 0x11, ++ MDPK_MPA = 0x12, ++ GAIN_LOSS = 0x13, ++ GAIN_CAL = 0x14, ++}; ++ ++static void _rf_direct_cntrl(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_bybb) ++{ ++ if (is_bybb) ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); ++ else ++ rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); ++} ++ ++static void _dpk_onoff(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool off); ++ ++static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, u32 *reg, ++ u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], ++ u8 path) ++{ ++ u8 i; ++ ++ for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) { ++ reg_bkup[path][i] = rtw89_phy_read32_mask(rtwdev, ++ reg[i] + (path << 8), ++ MASKDWORD); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n", ++ reg[i] + (path << 8), reg_bkup[path][i]); ++ } ++} ++ ++static void _dpk_reload_kip(struct rtw89_dev *rtwdev, u32 *reg, ++ u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], u8 path) ++{ ++ u8 i; ++ ++ for (i = 0; i < RTW8852A_DPK_KIP_REG_NUM; i++) { ++ rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), ++ MASKDWORD, reg_bkup[path][i]); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Reload 0x%x = %x\n", ++ reg[i] + (path << 8), reg_bkup[path][i]); ++ } ++} ++ ++static u8 _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, enum rtw8852a_dpk_id id) ++{ ++ u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path); ++ u16 dpk_cmd = 0x0; ++ u32 val; ++ int ret; ++ ++ dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4))); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_ONESHOT_START); ++ ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd); ++ rtw89_phy_write32_set(rtwdev, R_DPK_CTL, B_DPK_CTL_EN); ++ ++ ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55, ++ 10, 20000, false, rtwdev, 0xbff8, MASKBYTE0); ++ ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_N1, MASKBYTE0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_ONESHOT_STOP); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] one-shot for %s = 0x%x (ret=%d)\n", ++ id == 0x06 ? "LBK_RXIQK" : ++ id == 0x10 ? "SYNC" : ++ id == 0x11 ? "MDPK_IDL" : ++ id == 0x12 ? "MDPK_MPA" : ++ id == 0x13 ? "GAIN_LOSS" : "PWR_CAL", ++ dpk_cmd, ret); ++ ++ if (ret) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] one-shot over 20ms!!!!\n"); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void _dpk_rx_dck(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); ++ _set_rx_dck(rtwdev, phy, path, false); ++} ++ ++static void _dpk_information(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ struct rtw89_hal *hal = &rtwdev->hal; ++ ++ u8 kidx = dpk->cur_idx[path]; ++ ++ dpk->bp[path][kidx].band = hal->current_band_type; ++ dpk->bp[path][kidx].ch = hal->current_channel; ++ dpk->bp[path][kidx].bw = hal->current_band_width; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n", ++ path, dpk->cur_idx[path], phy, ++ rtwdev->is_tssi_mode[path] ? "on" : "off", ++ rtwdev->dbcc_en ? "on" : "off", ++ dpk->bp[path][kidx].band == 0 ? "2G" : ++ dpk->bp[path][kidx].band == 1 ? "5G" : "6G", ++ dpk->bp[path][kidx].ch, ++ dpk->bp[path][kidx].bw == 0 ? "20M" : ++ dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); ++} ++ ++static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kpath) ++{ ++ switch (kpath) { ++ case RF_A: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sf_defs_a_tbl); ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x0) ++ rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sr_defs_a_tbl); ++ break; ++ case RF_B: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sf_defs_b_tbl); ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL) == 0x1) ++ rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_sr_defs_b_tbl); ++ break; ++ case RF_AB: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_s_defs_ab_tbl); ++ break; ++ default: ++ break; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Set BB/AFE for PHY%d (kpath=%d)\n", phy, kpath); ++} ++ ++static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kpath) ++{ ++ switch (kpath) { ++ case RF_A: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_a_tbl); ++ break; ++ case RF_B: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_b_tbl); ++ break; ++ case RF_AB: ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_bb_afe_r_defs_ab_tbl); ++ break; ++ default: ++ break; ++ } ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Restore BB/AFE for PHY%d (kpath=%d)\n", phy, kpath); ++} ++ ++static void _dpk_tssi_pause(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_pause) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), ++ B_P0_TSSI_TRK_EN, is_pause); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, ++ is_pause ? "pause" : "resume"); ++} ++ ++static void _dpk_kip_setting(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 kidx) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_CLK, MASKDWORD, 0x00093f3f); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG, B_DPK_CFG_IDX, 0x2); ++ rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); /*subpage_id*/ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8) + (kidx << 2), ++ MASKDWORD, 0x003f2e2e); ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), ++ MASKDWORD, 0x005b5b5b); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] KIP setting for S%d[%d]!!\n", ++ path, kidx); ++} ++ ++static void _dpk_kip_restore(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path) ++{ ++ rtw89_phy_write32_clr(rtwdev, R_NCTL_RPT, MASKDWORD); ++ rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000); ++ rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); ++ rtw89_phy_write32_clr(rtwdev, R_KIP_CLK, MASKDWORD); ++ ++ if (rtwdev->hal.cv > CHIP_CBV) ++ rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); ++} ++ ++static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ u8 cur_rxbb; ++ ++ cur_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_lbk_rxiqk_defs_f_tbl); ++ ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2); ++ rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, ++ rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK)); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); ++ ++ fsleep(70); ++ ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f); ++ ++ if (cur_rxbb <= 0xa) ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3); ++ else if (cur_rxbb <= 0x10 && cur_rxbb >= 0xb) ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1); ++ else ++ rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0); ++ ++ rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11); ++ ++ _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, ++ rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD)); ++ ++ rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/ ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_DPK); ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_lbk_rxiqk_defs_r_tbl); ++} ++ ++static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ dpk->bp[path][kidx].ther_dpk = ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] thermal@DPK = 0x%x\n", ++ dpk->bp[path][kidx].ther_dpk); ++} ++ ++static u8 _dpk_set_tx_pwr(struct rtw89_dev *rtwdev, u8 gain, ++ enum rtw89_rf_path path) ++{ ++ u8 txagc_ori = 0x38; ++ ++ rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc_ori); ++ ++ return txagc_ori; ++} ++ ++static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain, ++ enum rtw89_rf_path path, u8 kidx) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0); ++ rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4); ++ rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0); ++ } else { ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e); ++ rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7); ++ rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3); ++ rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3); ++ } ++ rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); ++ rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); ++ rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] RF 0x0/0x1/0x1a = 0x%x/ 0x%x/ 0x%x\n", ++ rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK), ++ rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK)); ++} ++ ++static void _dpk_manual_txcfir(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_manual) ++{ ++ u8 tmp_pad, tmp_txbb; ++ ++ if (is_manual) { ++ rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1); ++ tmp_pad = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_PAD); ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), ++ B_RFGAIN_PAD, tmp_pad); ++ ++ tmp_txbb = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_BB); ++ rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), ++ B_RFGAIN_TXBB, tmp_txbb); ++ ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), ++ B_LOAD_COEF_CFIR, 0x1); ++ rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), ++ B_LOAD_COEF_CFIR); ++ ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] PAD_man / TXBB_man = 0x%x / 0x%x\n", tmp_pad, ++ tmp_txbb); ++ } else { ++ rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] disable manual switch TXCFIR\n"); ++ } ++} ++ ++static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool is_bypass) ++{ ++ if (is_bypass) { ++ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), ++ B_RXIQC_BYPASS2, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), ++ B_RXIQC_BYPASS, 0x1); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, ++ rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), ++ MASKDWORD)); ++ } else { ++ rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2); ++ rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, ++ rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), ++ MASKDWORD)); ++ } ++} ++ ++static ++void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) ++ rtw89_phy_write32_clr(rtwdev, R_TPG_MOD, B_TPG_MOD_F); ++ else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) ++ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2); ++ else ++ rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG_Select for %s\n", ++ dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : ++ dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); ++} ++ ++static void _dpk_table_select(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 kidx, u8 gain) ++{ ++ u8 val; ++ ++ val = 0x80 + kidx * 0x20 + gain * 0x10; ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] table select for Kidx[%d], Gain[%d] (0x%x)\n", kidx, ++ gain, val); ++} ++ ++static bool _dpk_sync_check(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path) ++{ ++#define DPK_SYNC_TH_DC_I 200 ++#define DPK_SYNC_TH_DC_Q 200 ++#define DPK_SYNC_TH_CORR 170 ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u16 dc_i, dc_q; ++ u8 corr_val, corr_idx; ++ ++ rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL); ++ ++ corr_idx = (u8)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI); ++ corr_val = (u8)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", path, corr_idx, ++ corr_val); ++ ++ dpk->corr_idx[path] = corr_idx; ++ dpk->corr_val[path] = corr_val; ++ ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9); ++ ++ dc_i = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); ++ dc_q = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ); ++ ++ dc_i = abs(sign_extend32(dc_i, 11)); ++ dc_q = abs(sign_extend32(dc_q, 11)); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d DC I/Q, = %d / %d\n", ++ path, dc_i, dc_q); ++ ++ dpk->dc_i[path] = dc_i; ++ dpk->dc_q[path] = dc_q; ++ ++ if (dc_i > DPK_SYNC_TH_DC_I || dc_q > DPK_SYNC_TH_DC_Q || ++ corr_val < DPK_SYNC_TH_CORR) ++ return true; ++ else ++ return false; ++} ++ ++static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kidx) ++{ ++ _dpk_tpg_sel(rtwdev, path, kidx); ++ _dpk_one_shot(rtwdev, phy, path, SYNC); ++ return _dpk_sync_check(rtwdev, path); /*1= fail*/ ++} ++ ++static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev) ++{ ++ u16 dgain = 0x0; ++ ++ rtw89_phy_write32_clr(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL); ++ ++ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_SYNERR); ++ ++ dgain = (u16)rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x (%d)\n", dgain, ++ dgain); ++ ++ return dgain; ++} ++ ++static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain) ++{ ++ s8 offset; ++ ++ if (dgain >= 0x783) ++ offset = 0x6; ++ else if (dgain <= 0x782 && dgain >= 0x551) ++ offset = 0x3; ++ else if (dgain <= 0x550 && dgain >= 0x3c4) ++ offset = 0x0; ++ else if (dgain <= 0x3c3 && dgain >= 0x2aa) ++ offset = -3; ++ else if (dgain <= 0x2a9 && dgain >= 0x1e3) ++ offset = -6; ++ else if (dgain <= 0x1e2 && dgain >= 0x156) ++ offset = -9; ++ else if (dgain <= 0x155) ++ offset = -12; ++ else ++ offset = 0x0; ++ ++ return offset; ++} ++ ++static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev) ++{ ++ rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6); ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1); ++ return rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL); ++} ++ ++static void _dpk_gainloss(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, enum rtw89_rf_path path, ++ u8 kidx) ++{ ++ _dpk_table_select(rtwdev, path, kidx, 1); ++ _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS); ++} ++ ++#define DPK_TXAGC_LOWER 0x2e ++#define DPK_TXAGC_UPPER 0x3f ++#define DPK_TXAGC_INVAL 0xff ++ ++static u8 _dpk_set_offset(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, s8 gain_offset) ++{ ++ u8 txagc; ++ ++ txagc = (u8)rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK); ++ ++ if (txagc - gain_offset < DPK_TXAGC_LOWER) ++ txagc = DPK_TXAGC_LOWER; ++ else if (txagc - gain_offset > DPK_TXAGC_UPPER) ++ txagc = DPK_TXAGC_UPPER; ++ else ++ txagc = txagc - gain_offset; ++ ++ rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp_txagc (GL=%d) = 0x%x\n", ++ gain_offset, txagc); ++ return txagc; ++} ++ ++enum dpk_agc_step { ++ DPK_AGC_STEP_SYNC_DGAIN, ++ DPK_AGC_STEP_GAIN_ADJ, ++ DPK_AGC_STEP_GAIN_LOSS_IDX, ++ DPK_AGC_STEP_GL_GT_CRITERION, ++ DPK_AGC_STEP_GL_LT_CRITERION, ++ DPK_AGC_STEP_SET_TX_GAIN, ++}; ++ ++static u8 _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check) ++{ ++ u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0; ++ u8 i; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_rfk_dpk_pas_read_defs_tbl); ++ ++ if (is_check) { ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00); ++ val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD); ++ val1_i = abs(sign_extend32(val1_i, 11)); ++ val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD); ++ val1_q = abs(sign_extend32(val1_q, 11)); ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f); ++ val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD); ++ val2_i = abs(sign_extend32(val2_i, 11)); ++ val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD); ++ val2_q = abs(sign_extend32(val2_q, 11)); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n", ++ (val1_i * val1_i + val1_q * val1_q) / ++ (val2_i * val2_i + val2_q * val2_q)); ++ ++ } else { ++ for (i = 0; i < 32; i++) { ++ rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] PAS_Read[%02d]= 0x%08x\n", i, ++ rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD)); ++ } ++ } ++ if ((val1_i * val1_i + val1_q * val1_q) >= ++ ((val2_i * val2_i + val2_q * val2_q) * 8 / 5)) ++ return 1; ++ else ++ return 0; ++} ++ ++static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kidx, u8 init_txagc, ++ bool loss_only) ++{ ++#define DPK_AGC_ADJ_LMT 6 ++#define DPK_DGAIN_UPPER 1922 ++#define DPK_DGAIN_LOWER 342 ++#define DPK_RXBB_UPPER 0x1f ++#define DPK_RXBB_LOWER 0 ++#define DPK_GL_CRIT 7 ++ u8 tmp_txagc, tmp_rxbb = 0, tmp_gl_idx = 0; ++ u8 agc_cnt = 0; ++ bool limited_rxbb = false; ++ s8 offset = 0; ++ u16 dgain = 0; ++ u8 step = DPK_AGC_STEP_SYNC_DGAIN; ++ bool goout = false; ++ ++ tmp_txagc = init_txagc; ++ ++ do { ++ switch (step) { ++ case DPK_AGC_STEP_SYNC_DGAIN: ++ if (_dpk_sync(rtwdev, phy, path, kidx)) { ++ tmp_txagc = DPK_TXAGC_INVAL; ++ goout = true; ++ break; ++ } ++ ++ dgain = _dpk_dgain_read(rtwdev); ++ ++ if (loss_only || limited_rxbb) ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ else ++ step = DPK_AGC_STEP_GAIN_ADJ; ++ break; ++ ++ case DPK_AGC_STEP_GAIN_ADJ: ++ tmp_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); ++ offset = _dpk_dgain_mapping(rtwdev, dgain); ++ ++ if (tmp_rxbb + offset > DPK_RXBB_UPPER) { ++ tmp_rxbb = DPK_RXBB_UPPER; ++ limited_rxbb = true; ++ } else if (tmp_rxbb + offset < DPK_RXBB_LOWER) { ++ tmp_rxbb = DPK_RXBB_LOWER; ++ limited_rxbb = true; ++ } else { ++ tmp_rxbb = tmp_rxbb + offset; ++ } ++ ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb); ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Adjust RXBB (%d) = 0x%x\n", offset, ++ tmp_rxbb); ++ if (offset != 0 || agc_cnt == 0) { ++ if (rtwdev->hal.current_band_width < RTW89_CHANNEL_WIDTH_80) ++ _dpk_bypass_rxcfir(rtwdev, path, true); ++ else ++ _dpk_lbk_rxiqk(rtwdev, phy, path); ++ } ++ if (dgain > DPK_DGAIN_UPPER || dgain < DPK_DGAIN_LOWER) ++ step = DPK_AGC_STEP_SYNC_DGAIN; ++ else ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ ++ agc_cnt++; ++ break; ++ ++ case DPK_AGC_STEP_GAIN_LOSS_IDX: ++ _dpk_gainloss(rtwdev, phy, path, kidx); ++ tmp_gl_idx = _dpk_gainloss_read(rtwdev); ++ ++ if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true)) || ++ tmp_gl_idx > DPK_GL_CRIT) ++ step = DPK_AGC_STEP_GL_GT_CRITERION; ++ else if (tmp_gl_idx == 0) ++ step = DPK_AGC_STEP_GL_LT_CRITERION; ++ else ++ step = DPK_AGC_STEP_SET_TX_GAIN; ++ break; ++ ++ case DPK_AGC_STEP_GL_GT_CRITERION: ++ if (tmp_txagc == DPK_TXAGC_LOWER) { ++ goout = true; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Txagc@lower bound!!\n"); ++ } else { ++ tmp_txagc = _dpk_set_offset(rtwdev, path, 3); ++ } ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ agc_cnt++; ++ break; ++ ++ case DPK_AGC_STEP_GL_LT_CRITERION: ++ if (tmp_txagc == DPK_TXAGC_UPPER) { ++ goout = true; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Txagc@upper bound!!\n"); ++ } else { ++ tmp_txagc = _dpk_set_offset(rtwdev, path, -2); ++ } ++ step = DPK_AGC_STEP_GAIN_LOSS_IDX; ++ agc_cnt++; ++ break; ++ ++ case DPK_AGC_STEP_SET_TX_GAIN: ++ tmp_txagc = _dpk_set_offset(rtwdev, path, tmp_gl_idx); ++ goout = true; ++ agc_cnt++; ++ break; ++ ++ default: ++ goout = true; ++ break; ++ } ++ } while (!goout && (agc_cnt < DPK_AGC_ADJ_LMT)); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Txagc / RXBB for DPK = 0x%x / 0x%x\n", tmp_txagc, ++ tmp_rxbb); ++ ++ return tmp_txagc; ++} ++ ++static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order) ++{ ++ switch (order) { ++ case 0: ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order); ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3); ++ rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN, 0x1); ++ break; ++ case 1: ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order); ++ rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN); ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN); ++ break; ++ case 2: ++ rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, order); ++ rtw89_phy_write32_clr(rtwdev, R_LDL_NORM, B_LDL_NORM_PN); ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_MAN); ++ break; ++ default: ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Wrong MDPD order!!(0x%x)\n", order); ++ break; ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Set MDPD order to 0x%x for IDL\n", order); ++} ++ ++static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 kidx, u8 gain) ++{ ++ _dpk_set_mdpd_para(rtwdev, 0x0); ++ _dpk_table_select(rtwdev, path, kidx, 1); ++ _dpk_one_shot(rtwdev, phy, path, MDPK_IDL); ++} ++ ++static void _dpk_fill_result(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, u8 kidx, u8 gain, ++ u8 txagc) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ ++ u16 pwsf = 0x78; ++ u8 gs = 0x5b; ++ ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Fill txagc/ pwsf/ gs = 0x%x/ 0x%x/ 0x%x\n", txagc, ++ pwsf, gs); ++ ++ dpk->bp[path][kidx].txagc_dpk = txagc; ++ rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), ++ 0x3F << ((gain << 3) + (kidx << 4)), txagc); ++ ++ dpk->bp[path][kidx].pwsf = pwsf; ++ rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), ++ 0x1FF << (gain << 4), pwsf); ++ ++ rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); ++ rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD); ++ ++ dpk->bp[path][kidx].gs = gs; ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), ++ MASKDWORD, 0x065b5b5b); ++ ++ rtw89_phy_write32_clr(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD); ++ ++ rtw89_phy_write32_clr(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_SEL); ++} ++ ++static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ bool is_reload = false; ++ u8 idx, cur_band, cur_ch; ++ ++ cur_band = rtwdev->hal.current_band_type; ++ cur_ch = rtwdev->hal.current_channel; ++ ++ for (idx = 0; idx < RTW89_DPK_BKUP_NUM; idx++) { ++ if (cur_band != dpk->bp[path][idx].band || ++ cur_ch != dpk->bp[path][idx].ch) ++ continue; ++ ++ rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), ++ B_COEF_SEL_MDPD, idx); ++ dpk->cur_idx[path] = idx; ++ is_reload = true; ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] reload S%d[%d] success\n", path, idx); ++ } ++ ++ return is_reload; ++} ++ ++static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path, u8 gain) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u8 txagc = 0, kidx = dpk->cur_idx[path]; ++ bool is_fail = false; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] ========= S%d[%d] DPK Start =========\n", path, ++ kidx); ++ ++ _rf_direct_cntrl(rtwdev, path, false); ++ txagc = _dpk_set_tx_pwr(rtwdev, gain, path); ++ _dpk_rf_setting(rtwdev, gain, path, kidx); ++ _dpk_rx_dck(rtwdev, phy, path); ++ ++ _dpk_kip_setting(rtwdev, path, kidx); ++ _dpk_manual_txcfir(rtwdev, path, true); ++ txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false); ++ if (txagc == DPK_TXAGC_INVAL) ++ is_fail = true; ++ _dpk_get_thermal(rtwdev, kidx, path); ++ ++ _dpk_idl_mpa(rtwdev, phy, path, kidx, gain); ++ rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); ++ _dpk_fill_result(rtwdev, path, kidx, gain, txagc); ++ _dpk_manual_txcfir(rtwdev, path, false); ++ ++ if (!is_fail) ++ dpk->bp[path][kidx].path_ok = true; ++ else ++ dpk->bp[path][kidx].path_ok = false; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, ++ is_fail ? "Check" : "Success"); ++ ++ return is_fail; ++} ++ ++static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force, ++ enum rtw89_phy_idx phy, u8 kpath) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u32 backup_bb_val[BACKUP_BB_REGS_NR]; ++ u32 backup_rf_val[RTW8852A_DPK_RF_PATH][BACKUP_RF_REGS_NR]; ++ u32 kip_bkup[RTW8852A_DPK_RF_PATH][RTW8852A_DPK_KIP_REG_NUM] = {{0}}; ++ u32 kip_reg[] = {R_RXIQC, R_IQK_RES}; ++ u8 path; ++ bool is_fail = true, reloaded[RTW8852A_DPK_RF_PATH] = {false}; ++ ++ if (dpk->is_dpk_reload_en) { ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path))) ++ continue; ++ ++ reloaded[path] = _dpk_reload_check(rtwdev, phy, path); ++ if (!reloaded[path] && dpk->bp[path][0].ch != 0) ++ dpk->cur_idx[path] = !dpk->cur_idx[path]; ++ else ++ _dpk_onoff(rtwdev, path, false); ++ } ++ } else { ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) ++ dpk->cur_idx[path] = 0; ++ } ++ ++ if ((kpath == RF_A && reloaded[RF_PATH_A]) || ++ (kpath == RF_B && reloaded[RF_PATH_B]) || ++ (kpath == RF_AB && reloaded[RF_PATH_A] && reloaded[RF_PATH_B])) ++ return; ++ ++ _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path)) || reloaded[path]) ++ continue; ++ if (rtwdev->is_tssi_mode[path]) ++ _dpk_tssi_pause(rtwdev, path, true); ++ _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); ++ _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ _dpk_information(rtwdev, phy, path); ++ } ++ ++ _dpk_bb_afe_setting(rtwdev, phy, path, kpath); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path)) || reloaded[path]) ++ continue; ++ ++ is_fail = _dpk_main(rtwdev, phy, path, 1); ++ _dpk_onoff(rtwdev, path, is_fail); ++ } ++ ++ _dpk_bb_afe_restore(rtwdev, phy, path, kpath); ++ _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (!(kpath & BIT(path)) || reloaded[path]) ++ continue; ++ ++ _dpk_kip_restore(rtwdev, path); ++ _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); ++ _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); ++ if (rtwdev->is_tssi_mode[path]) ++ _dpk_tssi_pause(rtwdev, path, false); ++ } ++} ++ ++static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_fem_info *fem = &rtwdev->fem; ++ ++ if (fem->epa_2g && rtwdev->hal.current_band_type == RTW89_BAND_2G) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Skip DPK due to 2G_ext_PA exist!!\n"); ++ return true; ++ } else if (fem->epa_5g && rtwdev->hal.current_band_type == RTW89_BAND_5G) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] Skip DPK due to 5G_ext_PA exist!!\n"); ++ return true; ++ } ++ ++ return false; ++} ++ ++static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ u8 path, kpath; ++ ++ kpath = _kpath(rtwdev, phy); ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ if (kpath & BIT(path)) ++ _dpk_onoff(rtwdev, path, true); ++ } ++} ++ ++static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force) ++{ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, ++ "[DPK] ****** DPK Start (Ver: 0x%x, Cv: %d, RF_para: %d) ******\n", ++ RTW8852A_DPK_VER, rtwdev->hal.cv, ++ RTW8852A_RF_REL_VERSION); ++ ++ if (_dpk_bypass_check(rtwdev, phy)) ++ _dpk_force_bypass(rtwdev, phy); ++ else ++ _dpk_cal_select(rtwdev, force, phy, _kpath(rtwdev, phy)); ++} ++ ++static void _dpk_onoff(struct rtw89_dev *rtwdev, ++ enum rtw89_rf_path path, bool off) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ u8 val, kidx = dpk->cur_idx[path]; ++ ++ val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), ++ MASKBYTE3, 0x6 | val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, ++ kidx, dpk->is_dpk_enable && !off ? "enable" : "disable"); ++} ++ ++static void _dpk_track(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_dpk_info *dpk = &rtwdev->dpk; ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 path, kidx; ++ u8 trk_idx = 0, txagc_rf = 0; ++ s8 txagc_bb = 0, txagc_bb_tp = 0, ini_diff = 0, txagc_ofst = 0; ++ u16 pwsf[2]; ++ u8 cur_ther; ++ s8 delta_ther[2] = {0}; ++ ++ for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { ++ kidx = dpk->cur_idx[path]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n", ++ path, kidx, dpk->bp[path][kidx].ch); ++ ++ cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] thermal now = %d\n", cur_ther); ++ ++ if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) ++ delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; ++ ++ if (dpk->bp[path][kidx].band == RTW89_BAND_2G) ++ delta_ther[path] = delta_ther[path] * 3 / 2; ++ else ++ delta_ther[path] = delta_ther[path] * 5 / 2; ++ ++ txagc_rf = (u8)rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), ++ RR_MODOPT_M_TXPWR); ++ ++ if (rtwdev->is_tssi_mode[path]) { ++ trk_idx = (u8)rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] txagc_RF / track_idx = 0x%x / %d\n", ++ txagc_rf, trk_idx); ++ ++ txagc_bb = ++ (s8)rtw89_phy_read32_mask(rtwdev, ++ R_TXAGC_BB + (path << 13), ++ MASKBYTE2); ++ txagc_bb_tp = ++ (u8)rtw89_phy_read32_mask(rtwdev, ++ R_TXAGC_TP + (path << 13), ++ B_TXAGC_TP); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n", ++ txagc_bb_tp, txagc_bb); ++ ++ txagc_ofst = ++ (s8)rtw89_phy_read32_mask(rtwdev, ++ R_TXAGC_BB + (path << 13), ++ MASKBYTE3); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] txagc_offset / delta_ther = %d / %d\n", ++ txagc_ofst, delta_ther[path]); ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), ++ BIT(15)) == 0x1) ++ txagc_ofst = 0; ++ ++ if (txagc_rf != 0 && cur_ther != 0) ++ ini_diff = txagc_ofst + delta_ther[path]; ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_P0_TXDPD + (path << 13), ++ B_P0_TXDPD) == 0x0) { ++ pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - ++ txagc_bb + ini_diff + ++ tssi_info->extra_ofst[path]; ++ pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - ++ txagc_bb + ini_diff + ++ tssi_info->extra_ofst[path]; ++ } else { ++ pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff + ++ tssi_info->extra_ofst[path]; ++ pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff + ++ tssi_info->extra_ofst[path]; ++ } ++ ++ } else { ++ pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; ++ pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; ++ } ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_DPK_TRK, B_DPK_TRK_DIS) == 0x0 && ++ txagc_rf != 0) { ++ rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, ++ "[DPK_TRK] New pwsf[0] / pwsf[1] = 0x%x / 0x%x\n", ++ pwsf[0], pwsf[1]); ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), ++ 0x000001FF, pwsf[0]); ++ rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), ++ 0x01FF0000, pwsf[1]); ++ } ++ } ++} ++ ++static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ ++ if (band == RTW89_BAND_2G) ++ rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); ++ else ++ rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); ++} ++ ++static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_sys_defs_tbl); ++ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, ++ &rtw8852a_tssi_sys_defs_2g_tbl, ++ &rtw8852a_tssi_sys_defs_5g_tbl); ++} ++ ++static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ enum rtw89_band band = rtwdev->hal.current_band_type; ++ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_a_tbl, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_b_tbl); ++ rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_2g_tbl, ++ &rtw8852a_tssi_txpwr_ctrl_bb_defs_5g_tbl); ++} ++ ++static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl, ++ &rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl); ++} ++ ++static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_dck_defs_a_tbl, ++ &rtw8852a_tssi_dck_defs_b_tbl); ++} ++ ++static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++#define __get_val(ptr, idx) \ ++({ \ ++ s8 *__ptr = (ptr); \ ++ u8 __idx = (idx), __i, __v; \ ++ u32 __val = 0; \ ++ for (__i = 0; __i < 4; __i++) { \ ++ __v = (__ptr[__idx + __i]); \ ++ __val |= (__v << (8 * __i)); \ ++ } \ ++ __val; \ ++}) ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel; ++ u8 subband = rtwdev->hal.current_subband; ++ const u8 *thm_up_a = NULL; ++ const u8 *thm_down_a = NULL; ++ const u8 *thm_up_b = NULL; ++ const u8 *thm_down_b = NULL; ++ u8 thermal = 0xff; ++ s8 thm_ofst[64] = {0}; ++ u32 tmp = 0; ++ u8 i, j; ++ ++ switch (subband) { ++ case RTW89_CH_2G: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_p; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_n; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_p; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_n; ++ break; ++ case RTW89_CH_5G_BAND_1: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[0]; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[0]; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[0]; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[0]; ++ break; ++ case RTW89_CH_5G_BAND_3: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[1]; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[1]; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[1]; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[1]; ++ break; ++ case RTW89_CH_5G_BAND_4: ++ thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[2]; ++ thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[2]; ++ thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[2]; ++ thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[2]; ++ break; ++ } ++ ++ if (path == RF_PATH_A) { ++ thermal = tssi_info->thermal[RF_PATH_A]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1); ++ ++ if (thermal == 0xff) { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32); ++ ++ for (i = 0; i < 64; i += 4) { ++ rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x5c00 + i, 0x0); ++ } ++ ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, thermal); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, ++ thermal); ++ ++ i = 0; ++ for (j = 0; j < 32; j++) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ -thm_down_a[i++] : ++ -thm_down_a[DELTA_SWINGIDX_SIZE - 1]; ++ ++ i = 1; ++ for (j = 63; j >= 32; j--) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ thm_up_a[i++] : ++ thm_up_a[DELTA_SWINGIDX_SIZE - 1]; ++ ++ for (i = 0; i < 64; i += 4) { ++ tmp = __get_val(thm_ofst, i); ++ rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x5c00 + i, tmp); ++ } ++ } ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0); ++ ++ } else { ++ thermal = tssi_info->thermal[RF_PATH_B]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] ch=%d thermal_pathB=0x%x\n", ch, thermal); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_DIS, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER_TRK, 0x1); ++ ++ if (thermal == 0xff) { ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, 32); ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, 32); ++ ++ for (i = 0; i < 64; i += 4) { ++ rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, 0x0); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x7c00 + i, 0x0); ++ } ++ ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P1_TMETER, B_P1_TMETER, thermal); ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, B_P1_RFCTM_VAL, ++ thermal); ++ ++ i = 0; ++ for (j = 0; j < 32; j++) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ -thm_down_b[i++] : ++ -thm_down_b[DELTA_SWINGIDX_SIZE - 1]; ++ ++ i = 1; ++ for (j = 63; j >= 32; j--) ++ thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? ++ thm_up_b[i++] : ++ thm_up_b[DELTA_SWINGIDX_SIZE - 1]; ++ ++ for (i = 0; i < 64; i += 4) { ++ tmp = __get_val(thm_ofst, i); ++ rtw89_phy_write32(rtwdev, R_TSSI_THOF + i, tmp); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] write 0x%x val=0x%08x\n", ++ 0x7c00 + i, tmp); ++ } ++ } ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x1); ++ rtw89_phy_write32_mask(rtwdev, R_P1_RFCTM, R_P1_RFCTM_RDY, 0x0); ++ } ++#undef __get_val ++} ++ ++static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_dac_gain_tbl_defs_a_tbl, ++ &rtw8852a_tssi_dac_gain_tbl_defs_b_tbl); ++} ++ ++static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_slope_cal_org_defs_a_tbl, ++ &rtw8852a_tssi_slope_cal_org_defs_b_tbl); ++} ++ ++static void _tssi_set_rf_gap_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_rf_gap_tbl_defs_a_tbl, ++ &rtw8852a_tssi_rf_gap_tbl_defs_b_tbl); ++} ++ ++static void _tssi_set_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_slope_defs_a_tbl, ++ &rtw8852a_tssi_slope_defs_b_tbl); ++} ++ ++static void _tssi_set_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_track_defs_a_tbl, ++ &rtw8852a_tssi_track_defs_b_tbl); ++} ++ ++static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_txagc_ofst_mv_avg_defs_a_tbl, ++ &rtw8852a_tssi_txagc_ofst_mv_avg_defs_b_tbl); ++} ++ ++static void _tssi_pak(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ u8 subband = rtwdev->hal.current_subband; ++ ++ switch (subband) { ++ case RTW89_CH_2G: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_2g_tbl, ++ &rtw8852a_tssi_pak_defs_b_2g_tbl); ++ break; ++ case RTW89_CH_5G_BAND_1: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_5g_1_tbl, ++ &rtw8852a_tssi_pak_defs_b_5g_1_tbl); ++ break; ++ case RTW89_CH_5G_BAND_3: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_5g_3_tbl, ++ &rtw8852a_tssi_pak_defs_b_5g_3_tbl); ++ break; ++ case RTW89_CH_5G_BAND_4: ++ rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, ++ &rtw8852a_tssi_pak_defs_a_5g_4_tbl, ++ &rtw8852a_tssi_pak_defs_b_5g_4_tbl); ++ break; ++ } ++} ++ ++static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 i; ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ _tssi_set_track(rtwdev, phy, i); ++ _tssi_set_txagc_offset_mv_avg(rtwdev, phy, i); ++ ++ rtw89_rfk_parser_by_cond(rtwdev, i == RF_PATH_A, ++ &rtw8852a_tssi_enable_defs_a_tbl, ++ &rtw8852a_tssi_enable_defs_b_tbl); ++ ++ tssi_info->base_thermal[i] = ++ ewma_thermal_read(&rtwdev->phystat.avg_thermal[i]); ++ rtwdev->is_tssi_mode[i] = true; ++ } ++} ++ ++static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl); ++ ++ rtwdev->is_tssi_mode[RF_PATH_A] = false; ++ rtwdev->is_tssi_mode[RF_PATH_B] = false; ++} ++ ++static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ switch (ch) { ++ case 1 ... 2: ++ return 0; ++ case 3 ... 5: ++ return 1; ++ case 6 ... 8: ++ return 2; ++ case 9 ... 11: ++ return 3; ++ case 12 ... 13: ++ return 4; ++ case 14: ++ return 5; ++ } ++ ++ return 0; ++} ++ ++#define TSSI_EXTRA_GROUP_BIT (BIT(31)) ++#define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx)) ++#define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT) ++#define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT) ++#define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) ++ ++static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ switch (ch) { ++ case 1 ... 2: ++ return 0; ++ case 3 ... 5: ++ return 1; ++ case 6 ... 8: ++ return 2; ++ case 9 ... 11: ++ return 3; ++ case 12 ... 14: ++ return 4; ++ case 36 ... 40: ++ return 5; ++ case 41 ... 43: ++ return TSSI_EXTRA_GROUP(5); ++ case 44 ... 48: ++ return 6; ++ case 49 ... 51: ++ return TSSI_EXTRA_GROUP(6); ++ case 52 ... 56: ++ return 7; ++ case 57 ... 59: ++ return TSSI_EXTRA_GROUP(7); ++ case 60 ... 64: ++ return 8; ++ case 100 ... 104: ++ return 9; ++ case 105 ... 107: ++ return TSSI_EXTRA_GROUP(9); ++ case 108 ... 112: ++ return 10; ++ case 113 ... 115: ++ return TSSI_EXTRA_GROUP(10); ++ case 116 ... 120: ++ return 11; ++ case 121 ... 123: ++ return TSSI_EXTRA_GROUP(11); ++ case 124 ... 128: ++ return 12; ++ case 129 ... 131: ++ return TSSI_EXTRA_GROUP(12); ++ case 132 ... 136: ++ return 13; ++ case 137 ... 139: ++ return TSSI_EXTRA_GROUP(13); ++ case 140 ... 144: ++ return 14; ++ case 149 ... 153: ++ return 15; ++ case 154 ... 156: ++ return TSSI_EXTRA_GROUP(15); ++ case 157 ... 161: ++ return 16; ++ case 162 ... 164: ++ return TSSI_EXTRA_GROUP(16); ++ case 165 ... 169: ++ return 17; ++ case 170 ... 172: ++ return TSSI_EXTRA_GROUP(17); ++ case 173 ... 177: ++ return 18; ++ } ++ ++ return 0; ++} ++ ++static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch) ++{ ++ switch (ch) { ++ case 1 ... 8: ++ return 0; ++ case 9 ... 14: ++ return 1; ++ case 36 ... 48: ++ return 2; ++ case 52 ... 64: ++ return 3; ++ case 100 ... 112: ++ return 4; ++ case 116 ... 128: ++ return 5; ++ case 132 ... 144: ++ return 6; ++ case 149 ... 177: ++ return 7; ++ } ++ ++ return 0; ++} ++ ++static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel; ++ u32 gidx, gidx_1st, gidx_2nd; ++ s8 de_1st = 0; ++ s8 de_2nd = 0; ++ s8 val; ++ ++ gidx = _tssi_get_ofdm_group(rtwdev, ch); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", ++ path, gidx); ++ ++ if (IS_TSSI_EXTRA_GROUP(gidx)) { ++ gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx); ++ gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx); ++ de_1st = tssi_info->tssi_mcs[path][gidx_1st]; ++ de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; ++ val = (de_1st + de_2nd) / 2; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", ++ path, val, de_1st, de_2nd); ++ } else { ++ val = tssi_info->tssi_mcs[path][gidx]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); ++ } ++ ++ return val; ++} ++ ++static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, ++ enum rtw89_rf_path path) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel; ++ u32 tgidx, tgidx_1st, tgidx_2nd; ++ s8 tde_1st = 0; ++ s8 tde_2nd = 0; ++ s8 val; ++ ++ tgidx = _tssi_get_trim_group(rtwdev, ch); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", ++ path, tgidx); ++ ++ if (IS_TSSI_EXTRA_GROUP(tgidx)) { ++ tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx); ++ tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx); ++ tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; ++ tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; ++ val = (tde_1st + tde_2nd) / 2; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", ++ path, val, tde_1st, tde_2nd); ++ } else { ++ val = tssi_info->tssi_trim[path][tgidx]; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", ++ path, val); ++ } ++ ++ return val; ++} ++ ++static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy) ++{ ++#define __DE_MASK 0x003ff000 ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ static const u32 r_cck_long[RF_PATH_NUM_8852A] = {0x5858, 0x7858}; ++ static const u32 r_cck_short[RF_PATH_NUM_8852A] = {0x5860, 0x7860}; ++ static const u32 r_mcs_20m[RF_PATH_NUM_8852A] = {0x5838, 0x7838}; ++ static const u32 r_mcs_40m[RF_PATH_NUM_8852A] = {0x5840, 0x7840}; ++ static const u32 r_mcs_80m[RF_PATH_NUM_8852A] = {0x5848, 0x7848}; ++ static const u32 r_mcs_80m_80m[RF_PATH_NUM_8852A] = {0x5850, 0x7850}; ++ static const u32 r_mcs_5m[RF_PATH_NUM_8852A] = {0x5828, 0x7828}; ++ static const u32 r_mcs_10m[RF_PATH_NUM_8852A] = {0x5830, 0x7830}; ++ u8 ch = rtwdev->hal.current_channel; ++ u8 i, gidx; ++ s8 ofdm_de; ++ s8 trim_de; ++ s32 val; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", ++ phy, ch); ++ ++ for (i = 0; i < RF_PATH_NUM_8852A; i++) { ++ gidx = _tssi_get_cck_group(rtwdev, ch); ++ trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i); ++ val = tssi_info->tssi_cck[i][gidx] + trim_de; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n", ++ i, gidx, tssi_info->tssi_cck[i][gidx], trim_de); ++ ++ rtw89_phy_write32_mask(rtwdev, r_cck_long[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_cck_short[i], __DE_MASK, val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n", ++ r_cck_long[i], ++ rtw89_phy_read32_mask(rtwdev, r_cck_long[i], ++ __DE_MASK)); ++ ++ ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i); ++ trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i); ++ val = ofdm_de + trim_de; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n", ++ i, ofdm_de, trim_de); ++ ++ rtw89_phy_write32_mask(rtwdev, r_mcs_20m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_40m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_80m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_80m_80m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_5m[i], __DE_MASK, val); ++ rtw89_phy_write32_mask(rtwdev, r_mcs_10m[i], __DE_MASK, val); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n", ++ r_mcs_20m[i], ++ rtw89_phy_read32_mask(rtwdev, r_mcs_20m[i], ++ __DE_MASK)); ++ } ++#undef __DE_MASK ++} ++ ++static void _tssi_track(struct rtw89_dev *rtwdev) ++{ ++ static const u32 tx_gain_scale_table[] = { ++ 0x400, 0x40e, 0x41d, 0x427, 0x43c, 0x44c, 0x45c, 0x46c, ++ 0x400, 0x39d, 0x3ab, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f1 ++ }; ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 path; ++ u8 cur_ther; ++ s32 delta_ther = 0, gain_offset_int, gain_offset_float; ++ s8 gain_offset; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRK] %s:\n", ++ __func__); ++ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A]) ++ return; ++ if (!rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ for (path = RF_PATH_A; path < RF_PATH_NUM_8852A; path++) { ++ if (!tssi_info->tssi_tracking_check[path]) { ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRK] return!!!\n"); ++ continue; ++ } ++ ++ cur_ther = (u8)rtw89_phy_read32_mask(rtwdev, ++ R_TSSI_THER + (path << 13), ++ B_TSSI_THER); ++ ++ if (cur_ther == 0 || tssi_info->base_thermal[path] == 0) ++ continue; ++ ++ delta_ther = cur_ther - tssi_info->base_thermal[path]; ++ ++ gain_offset = (s8)delta_ther * 15 / 10; ++ ++ tssi_info->extra_ofst[path] = gain_offset; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI][TRK] base_thermal=%d gain_offset=0x%x path=%d\n", ++ tssi_info->base_thermal[path], gain_offset, path); ++ ++ gain_offset_int = gain_offset >> 3; ++ gain_offset_float = gain_offset & 7; ++ ++ if (gain_offset_int > 15) ++ gain_offset_int = 15; ++ else if (gain_offset_int < -16) ++ gain_offset_int = -16; ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN + (path << 13), ++ B_DPD_OFT_EN, 0x1); ++ ++ rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), ++ B_TXGAIN_SCALE_EN, 0x1); ++ ++ rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_ADDR + (path << 13), ++ B_DPD_OFT_ADDR, gain_offset_int); ++ ++ rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), ++ B_TXGAIN_SCALE_OFT, ++ tx_gain_scale_table[gain_offset_float]); ++ } ++} ++ ++static void _tssi_high_power(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 ch = rtwdev->hal.current_channel, ch_tmp; ++ u8 bw = rtwdev->hal.current_band_width; ++ u8 subband = rtwdev->hal.current_subband; ++ s8 power; ++ s32 xdbm; ++ ++ if (bw == RTW89_CHANNEL_WIDTH_40) ++ ch_tmp = ch - 2; ++ else if (bw == RTW89_CHANNEL_WIDTH_80) ++ ch_tmp = ch - 6; ++ else ++ ch_tmp = ch; ++ ++ power = rtw89_phy_read_txpwr_limit(rtwdev, bw, RTW89_1TX, ++ RTW89_RS_MCS, RTW89_NONBF, ch_tmp); ++ ++ xdbm = power * 100 / 4; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d xdbm=%d\n", ++ __func__, phy, xdbm); ++ ++ if (xdbm > 1800 && subband == RTW89_CH_2G) { ++ tssi_info->tssi_tracking_check[RF_PATH_A] = true; ++ tssi_info->tssi_tracking_check[RF_PATH_B] = true; ++ } else { ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_tracking_defs_tbl); ++ tssi_info->extra_ofst[RF_PATH_A] = 0; ++ tssi_info->extra_ofst[RF_PATH_B] = 0; ++ tssi_info->tssi_tracking_check[RF_PATH_A] = false; ++ tssi_info->tssi_tracking_check[RF_PATH_B] = false; ++ } ++} ++ ++static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, ++ u8 path, s16 pwr_dbm, u8 enable) ++{ ++ rtw8852a_bb_set_plcp_tx(rtwdev); ++ rtw8852a_bb_cfg_tx_path(rtwdev, path); ++ rtw8852a_bb_set_power(rtwdev, pwr_dbm, phy); ++ rtw8852a_bb_set_pmac_pkt_tx(rtwdev, enable, 20, 5000, 0, phy); ++} ++ ++static void _tssi_pre_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ const struct rtw89_chip_info *mac_reg = rtwdev->chip; ++ u8 ch = rtwdev->hal.current_channel, ch_tmp; ++ u8 bw = rtwdev->hal.current_band_width; ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy, 0); ++ s8 power; ++ s16 xdbm; ++ u32 i, tx_counter = 0; ++ ++ if (bw == RTW89_CHANNEL_WIDTH_40) ++ ch_tmp = ch - 2; ++ else if (bw == RTW89_CHANNEL_WIDTH_80) ++ ch_tmp = ch - 6; ++ else ++ ch_tmp = ch; ++ ++ power = rtw89_phy_read_txpwr_limit(rtwdev, RTW89_CHANNEL_WIDTH_20, RTW89_1TX, ++ RTW89_RS_OFDM, RTW89_NONBF, ch_tmp); ++ ++ xdbm = (power * 100) >> mac_reg->txpwr_factor_mac; ++ ++ if (xdbm > 1800) ++ xdbm = 68; ++ else ++ xdbm = power * 2; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] %s: phy=%d org_power=%d xdbm=%d\n", ++ __func__, phy, power, xdbm); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy)); ++ tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD); ++ ++ _tssi_hw_tx(rtwdev, phy, RF_PATH_AB, xdbm, true); ++ mdelay(15); ++ _tssi_hw_tx(rtwdev, phy, RF_PATH_AB, xdbm, false); ++ ++ tx_counter = rtw89_phy_read32_mask(rtwdev, R_TX_COUNTER, MASKLWORD) - ++ tx_counter; ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0xc000 && ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, MASKHWORD) != 0x0) { ++ for (i = 0; i < 6; i++) { ++ tssi_info->default_txagc_offset[RF_PATH_A] = ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, ++ MASKBYTE3); ++ ++ if (tssi_info->default_txagc_offset[RF_PATH_A] != 0x0) ++ break; ++ } ++ } ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0xc000 && ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, MASKHWORD) != 0x0) { ++ for (i = 0; i < 6; i++) { ++ tssi_info->default_txagc_offset[RF_PATH_B] = ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, ++ MASKBYTE3); ++ ++ if (tssi_info->default_txagc_offset[RF_PATH_B] != 0x0) ++ break; ++ } ++ } ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] %s: tx counter=%d\n", ++ __func__, tx_counter); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, ++ "[TSSI] Backup R_TXAGC_BB=0x%x R_TXAGC_BB_S1=0x%x\n", ++ tssi_info->default_txagc_offset[RF_PATH_A], ++ tssi_info->default_txagc_offset[RF_PATH_B]); ++ ++ rtw8852a_bb_tx_mode_switch(rtwdev, phy, 0); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_rck(struct rtw89_dev *rtwdev) ++{ ++ u8 path; ++ ++ for (path = 0; path < 2; path++) ++ _rck(rtwdev, path); ++} ++ ++void rtw8852a_dack(struct rtw89_dev *rtwdev) ++{ ++ u8 phy_map = rtw89_btc_phymap(rtwdev, RTW89_PHY_0, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_START); ++ _dac_cal(rtwdev, false); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DACK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); ++ ++ _iqk_init(rtwdev); ++ if (rtwdev->dbcc_en) ++ _iqk_dbcc(rtwdev, phy_idx); ++ else ++ _iqk(rtwdev, phy_idx, false); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy_idx, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_iqk_track(struct rtw89_dev *rtwdev) ++{ ++ _iqk_track(rtwdev); ++} ++ ++void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ bool is_afe) ++{ ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); ++ ++ _rx_dck(rtwdev, phy_idx, is_afe); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy_idx, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) ++{ ++ u16 tx_en; ++ u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0); ++ ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START); ++ rtw89_mac_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL); ++ _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx)); ++ ++ rtwdev->dpk.is_dpk_enable = true; ++ rtwdev->dpk.is_dpk_reload_en = false; ++ _dpk(rtwdev, phy_idx, false); ++ ++ rtw89_mac_resume_sch_tx(rtwdev, phy_idx, tx_en); ++ rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP); ++} ++ ++void rtw8852a_dpk_track(struct rtw89_dev *rtwdev) ++{ ++ _dpk_track(rtwdev); ++} ++ ++void rtw8852a_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", ++ __func__, phy); ++ ++ _tssi_disable(rtwdev, phy); ++ ++ for (i = RF_PATH_A; i < RF_PATH_NUM_8852A; i++) { ++ _tssi_rf_setting(rtwdev, phy, i); ++ _tssi_set_sys(rtwdev, phy); ++ _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i); ++ _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i); ++ _tssi_set_dck(rtwdev, phy, i); ++ _tssi_set_tmeter_tbl(rtwdev, phy, i); ++ _tssi_set_dac_gain_tbl(rtwdev, phy, i); ++ _tssi_slope_cal_org(rtwdev, phy, i); ++ _tssi_set_rf_gap_tbl(rtwdev, phy, i); ++ _tssi_set_slope(rtwdev, phy, i); ++ _tssi_pak(rtwdev, phy, i); ++ } ++ ++ _tssi_enable(rtwdev, phy); ++ _tssi_set_efuse_to_de(rtwdev, phy); ++ _tssi_high_power(rtwdev, phy); ++ _tssi_pre_tx(rtwdev, phy); ++} ++ ++void rtw8852a_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ u8 i; ++ ++ rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", ++ __func__, phy); ++ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A]) ++ return; ++ if (!rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ _tssi_disable(rtwdev, phy); ++ ++ for (i = RF_PATH_A; i < RF_PATH_NUM_8852A; i++) { ++ _tssi_rf_setting(rtwdev, phy, i); ++ _tssi_set_sys(rtwdev, phy); ++ _tssi_set_tmeter_tbl(rtwdev, phy, i); ++ _tssi_pak(rtwdev, phy, i); ++ } ++ ++ _tssi_enable(rtwdev, phy); ++ _tssi_set_efuse_to_de(rtwdev, phy); ++} ++ ++void rtw8852a_tssi_track(struct rtw89_dev *rtwdev) ++{ ++ _tssi_track(rtwdev); ++} ++ ++static ++void _rtw8852a_tssi_avg_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ /* disable */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x0); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x0); ++ ++ /* enable */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_enable_defs_ab_tbl); ++} ++ ++static ++void _rtw8852a_tssi_set_avg(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy) ++{ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ /* disable */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_disable_defs_tbl); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_AVG, 0x4); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_AVG, 0x2); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_AVG, B_P1_TSSI_AVG, 0x4); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_MV_AVG, B_P1_TSSI_MV_AVG, 0x2); ++ ++ /* enable */ ++ rtw89_rfk_parser(rtwdev, &rtw8852a_tssi_enable_defs_ab_tbl); ++} ++ ++static void rtw8852a_tssi_set_avg(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, bool enable) ++{ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ if (enable) { ++ /* SCAN_START */ ++ _rtw8852a_tssi_avg_scan(rtwdev, phy); ++ } else { ++ /* SCAN_END */ ++ _rtw8852a_tssi_set_avg(rtwdev, phy); ++ } ++} ++ ++static void rtw8852a_tssi_default_txagc(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_idx phy, bool enable) ++{ ++ struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; ++ u8 i; ++ ++ if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B]) ++ return; ++ ++ if (enable) { ++ if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0xc000 && ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, B_TXAGC_BB_OFT) != 0x0) { ++ for (i = 0; i < 6; i++) { ++ tssi_info->default_txagc_offset[RF_PATH_A] = ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB, ++ B_TXAGC_BB); ++ if (tssi_info->default_txagc_offset[RF_PATH_A]) ++ break; ++ } ++ } ++ ++ if (rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0xc000 && ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, B_TXAGC_BB_S1_OFT) != 0x0) { ++ for (i = 0; i < 6; i++) { ++ tssi_info->default_txagc_offset[RF_PATH_B] = ++ rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB_S1, ++ B_TXAGC_BB_S1); ++ if (tssi_info->default_txagc_offset[RF_PATH_B]) ++ break; ++ } ++ } ++ } else { ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, ++ tssi_info->default_txagc_offset[RF_PATH_A]); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT, ++ tssi_info->default_txagc_offset[RF_PATH_B]); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1); ++ ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x0); ++ rtw89_phy_write32_mask(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_OFT_EN, 0x1); ++ } ++} ++ ++void rtw8852a_wifi_scan_notify(struct rtw89_dev *rtwdev, ++ bool scan_start, enum rtw89_phy_idx phy_idx) ++{ ++ if (scan_start) { ++ rtw8852a_tssi_default_txagc(rtwdev, phy_idx, true); ++ rtw8852a_tssi_set_avg(rtwdev, phy_idx, true); ++ } else { ++ rtw8852a_tssi_default_txagc(rtwdev, phy_idx, false); ++ rtw8852a_tssi_set_avg(rtwdev, phy_idx, false); ++ } ++} +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h +new file mode 100644 +index 000000000000..ea36553a76b7 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_RFK_H__ ++#define __RTW89_8852A_RFK_H__ ++ ++#include "core.h" ++ ++void rtw8852a_rck(struct rtw89_dev *rtwdev); ++void rtw8852a_dack(struct rtw89_dev *rtwdev); ++void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); ++void rtw8852a_iqk_track(struct rtw89_dev *rtwdev); ++void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, ++ bool is_afe); ++void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy); ++void rtw8852a_dpk_track(struct rtw89_dev *rtwdev); ++void rtw8852a_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy); ++void rtw8852a_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy); ++void rtw8852a_tssi_track(struct rtw89_dev *rtwdev); ++void rtw8852a_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start, ++ enum rtw89_phy_idx phy_idx); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c +new file mode 100644 +index 000000000000..510570090502 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.c +@@ -0,0 +1,1607 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "rtw8852a_rfk_table.h" ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs[] = { ++ DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002), ++ DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002), ++ DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005), ++ DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005), ++ DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005), ++ DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005), ++ DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), ++ DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x32bc, 0x000000f0, 0x00000005), ++ DECL_RFK_WM(0x32bc, 0x00000f00, 0x00000005), ++ DECL_RFK_WM(0x32bc, 0x000f0000, 0x00000005), ++ DECL_RFK_WM(0x32bc, 0x0000f000, 0x00000005), ++ DECL_RFK_WM(0x320c, 0x000000ff, 0x00000033), ++ DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x0300, 0xff000000, 0x00000019), ++ DECL_RFK_WM(0x0304, 0x000000ff, 0x00000019), ++ DECL_RFK_WM(0x0304, 0x0000ff00, 0x0000001d), ++ DECL_RFK_WM(0x0314, 0xffff0000, 0x00002044), ++ DECL_RFK_WM(0x0318, 0x0000ffff, 0x00002042), ++ DECL_RFK_WM(0x0318, 0xffff0000, 0x00002002), ++ DECL_RFK_WM(0x0020, 0x00006000, 0x00000003), ++ DECL_RFK_WM(0x0024, 0x00006000, 0x00000003), ++ DECL_RFK_WM(0x0704, 0xffff0000, 0x0000601e), ++ DECL_RFK_WM(0x2704, 0xffff0000, 0x0000601e), ++ DECL_RFK_WM(0x0700, 0xf0000000, 0x00000004), ++ DECL_RFK_WM(0x2700, 0xf0000000, 0x00000004), ++ DECL_RFK_WM(0x0650, 0x3c000000, 0x00000000), ++ DECL_RFK_WM(0x2650, 0x3c000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_2g[] = { ++ DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033), ++ DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000033), ++ DECL_RFK_WM(0x320c, 0x000000ff, 0x00000033), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_5g[] = { ++ DECL_RFK_WM(0x120c, 0x000000ff, 0x00000044), ++ DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000044), ++ DECL_RFK_WM(0x32c0, 0x0ff00000, 0x00000044), ++ DECL_RFK_WM(0x320c, 0x000000ff, 0x00000044), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_5g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_a[] = { ++ DECL_RFK_WM(0x5800, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x5800, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x5800, 0x003f0000, 0x0000003f), ++ DECL_RFK_WM(0x5800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x5800, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x5800, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x5804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x580c, 0x0000007f, 0x00000040), ++ DECL_RFK_WM(0x580c, 0x00007f00, 0x00000040), ++ DECL_RFK_WM(0x580c, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x580c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x0000fc00, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x00010000, 0x00000001), ++ DECL_RFK_WM(0x5810, 0x00fe0000, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x5810, 0x06000000, 0x00000000), ++ DECL_RFK_WM(0x5810, 0x38000000, 0x00000003), ++ DECL_RFK_WM(0x5810, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x5810, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00000c00, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00002000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x5814, 0x003c0000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x01c00000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0xe0000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x0001ff00, 0x00000018), ++ DECL_RFK_WM(0x5818, 0x03fe0000, 0x00000016), ++ DECL_RFK_WM(0x5818, 0xfc000000, 0x00000000), ++ DECL_RFK_WM(0x581c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x581c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x581c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x581c, 0x01e00000, 0x00000008), ++ DECL_RFK_WM(0x581c, 0x01e00000, 0x0000000e), ++ DECL_RFK_WM(0x581c, 0x1e000000, 0x00000008), ++ DECL_RFK_WM(0x581c, 0x1e000000, 0x0000000e), ++ DECL_RFK_WM(0x581c, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x5820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x5820, 0x0000f000, 0x0000000f), ++ DECL_RFK_WM(0x5820, 0x001f0000, 0x00000000), ++ DECL_RFK_WM(0x5820, 0xffe00000, 0x00000000), ++ DECL_RFK_WM(0x5824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x582c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x582c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x583c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x583c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x584c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x584c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x585c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x585c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5828, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x5864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x5864, 0x03f00000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x5898, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x589c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x58a0, 0x000000ff, 0x000000fd), ++ DECL_RFK_WM(0x58a0, 0x0000ff00, 0x000000e5), ++ DECL_RFK_WM(0x58a0, 0x00ff0000, 0x000000cd), ++ DECL_RFK_WM(0x58a0, 0xff000000, 0x000000b5), ++ DECL_RFK_WM(0x58a4, 0x000000ff, 0x00000016), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58b0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x0000001f, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x00000020, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x000001c0, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x0000f000, 0x00000002), ++ DECL_RFK_WM(0x58b4, 0x00ff0000, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x58b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x58b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x58b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x58b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x58bc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x58bc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x58bc, 0x00030000, 0x00000003), ++ DECL_RFK_WM(0x58bc, 0x000c0000, 0x00000001), ++ DECL_RFK_WM(0x58bc, 0x00300000, 0x00000002), ++ DECL_RFK_WM(0x58bc, 0x00c00000, 0x00000002), ++ DECL_RFK_WM(0x58bc, 0x07000000, 0x00000007), ++ DECL_RFK_WM(0x58c0, 0x00fe0000, 0x0000003f), ++ DECL_RFK_WM(0x58c0, 0xff000000, 0x00000000), ++ DECL_RFK_WM(0x58c4, 0x0003ffff, 0x0003ffff), ++ DECL_RFK_WM(0x58c4, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x58c4, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0x00ffffff, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0xf0000000, 0x00000000), ++ DECL_RFK_WM(0x58cc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x58d0, 0x00001fff, 0x00000101), ++ DECL_RFK_WM(0x58d0, 0x0001e000, 0x00000004), ++ DECL_RFK_WM(0x58d0, 0x03fe0000, 0x00000100), ++ DECL_RFK_WM(0x58d0, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x58d4, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x58d4, 0x0003fe00, 0x000000ff), ++ DECL_RFK_WM(0x58d4, 0x07fc0000, 0x00000100), ++ DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000016c), ++ DECL_RFK_WM(0x58d8, 0x0003fe00, 0x0000005c), ++ DECL_RFK_WM(0x58d8, 0x000c0000, 0x00000002), ++ DECL_RFK_WM(0x58d8, 0xfff00000, 0x00000800), ++ DECL_RFK_WM(0x58dc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x58dc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x58dc, 0x00010000, 0x00000000), ++ DECL_RFK_WM(0x58dc, 0x3ff00000, 0x00000000), ++ DECL_RFK_WM(0x58dc, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x58f0, 0x000001ff, 0x000001ff), ++ DECL_RFK_WM(0x58f0, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_b[] = { ++ DECL_RFK_WM(0x7800, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x7800, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x7800, 0x003f0000, 0x0000003f), ++ DECL_RFK_WM(0x7800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x7800, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7800, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x7804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x780c, 0x0000007f, 0x00000040), ++ DECL_RFK_WM(0x780c, 0x00007f00, 0x00000040), ++ DECL_RFK_WM(0x780c, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x780c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x0000fc00, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x00010000, 0x00000001), ++ DECL_RFK_WM(0x7810, 0x00fe0000, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x7810, 0x06000000, 0x00000000), ++ DECL_RFK_WM(0x7810, 0x38000000, 0x00000003), ++ DECL_RFK_WM(0x7810, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x7810, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00000c00, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00002000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x7814, 0x003c0000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x01c00000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0xe0000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x0001ff00, 0x00000018), ++ DECL_RFK_WM(0x7818, 0x03fe0000, 0x00000016), ++ DECL_RFK_WM(0x7818, 0xfc000000, 0x00000000), ++ DECL_RFK_WM(0x781c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x781c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x781c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x781c, 0x01e00000, 0x00000008), ++ DECL_RFK_WM(0x781c, 0x01e00000, 0x0000000e), ++ DECL_RFK_WM(0x781c, 0x1e000000, 0x00000008), ++ DECL_RFK_WM(0x781c, 0x1e000000, 0x0000000e), ++ DECL_RFK_WM(0x781c, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x7820, 0x0000f000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0x001f0000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0xffe00000, 0x00000000), ++ DECL_RFK_WM(0x7824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x782c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x782c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x783c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x783c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x784c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x784c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x785c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x785c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7828, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x7fc00000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x7864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x7864, 0x03f00000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x7898, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x789c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x78a0, 0x000000ff, 0x000000fd), ++ DECL_RFK_WM(0x78a0, 0x0000ff00, 0x000000e5), ++ DECL_RFK_WM(0x78a0, 0x00ff0000, 0x000000cd), ++ DECL_RFK_WM(0x78a0, 0xff000000, 0x000000b5), ++ DECL_RFK_WM(0x78a4, 0x000000ff, 0x00000016), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78b0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x0000001f, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x00000020, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x000001c0, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x0000f000, 0x00000002), ++ DECL_RFK_WM(0x78b4, 0x00ff0000, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x78b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x78b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x78b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x78b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x78bc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x78bc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x78bc, 0x00030000, 0x00000003), ++ DECL_RFK_WM(0x78bc, 0x000c0000, 0x00000001), ++ DECL_RFK_WM(0x78bc, 0x00300000, 0x00000002), ++ DECL_RFK_WM(0x78bc, 0x00c00000, 0x00000002), ++ DECL_RFK_WM(0x78bc, 0x07000000, 0x00000007), ++ DECL_RFK_WM(0x78c0, 0x00fe0000, 0x0000003f), ++ DECL_RFK_WM(0x78c0, 0xff000000, 0x00000000), ++ DECL_RFK_WM(0x78c4, 0x0003ffff, 0x0003ffff), ++ DECL_RFK_WM(0x78c4, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x78c4, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0x00ffffff, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0xf0000000, 0x00000000), ++ DECL_RFK_WM(0x78cc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x78d0, 0x00001fff, 0x00000101), ++ DECL_RFK_WM(0x78d0, 0x0001e000, 0x00000004), ++ DECL_RFK_WM(0x78d0, 0x03fe0000, 0x00000100), ++ DECL_RFK_WM(0x78d0, 0x04000000, 0x00000000), ++ DECL_RFK_WM(0x78d4, 0x000000ff, 0x00000000), ++ DECL_RFK_WM(0x78d4, 0x0003fe00, 0x000000ff), ++ DECL_RFK_WM(0x78d4, 0x07fc0000, 0x00000100), ++ DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000016c), ++ DECL_RFK_WM(0x78d8, 0x0003fe00, 0x0000005c), ++ DECL_RFK_WM(0x78d8, 0x000c0000, 0x00000002), ++ DECL_RFK_WM(0x78d8, 0xfff00000, 0x00000800), ++ DECL_RFK_WM(0x78dc, 0x000000ff, 0x0000007f), ++ DECL_RFK_WM(0x78dc, 0x0000ff00, 0x00000080), ++ DECL_RFK_WM(0x78dc, 0x00010000, 0x00000000), ++ DECL_RFK_WM(0x78dc, 0x3ff00000, 0x00000000), ++ DECL_RFK_WM(0x78dc, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x78f0, 0x000001ff, 0x000001ff), ++ DECL_RFK_WM(0x78f0, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_2g[] = { ++ DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000013c), ++ DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000013c), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_5g[] = { ++ DECL_RFK_WM(0x58d8, 0x000001ff, 0x0000016c), ++ DECL_RFK_WM(0x78d8, 0x000001ff, 0x0000016c), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_5g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a[] = { ++ DECL_RFK_WM(0x58a0, 0xffffffff, 0x000000fc), ++ DECL_RFK_WM(0x58e4, 0x0000007f, 0x00000020), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b[] = { ++ DECL_RFK_WM(0x78a0, 0xffffffff, 0x000000fc), ++ DECL_RFK_WM(0x78e4, 0x0000007f, 0x00000020), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_a[] = { ++ DECL_RFK_WM(0x580c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00002000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x5814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x5814, 0x003c0000, 0x00000003), ++ DECL_RFK_WM(0x5814, 0x18000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_b[] = { ++ DECL_RFK_WM(0x780c, 0x0fff0000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00002000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x7814, 0x00038000, 0x00000005), ++ DECL_RFK_WM(0x7814, 0x003c0000, 0x00000003), ++ DECL_RFK_WM(0x7814, 0x18000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_a[] = { ++ DECL_RFK_WM(0x58b0, 0x00000fff, 0x00000000), ++ DECL_RFK_WM(0x58b0, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x5a00, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a04, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a08, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a0c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a10, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a14, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a18, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a1c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a20, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a24, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a28, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a2c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a30, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a34, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a38, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a3c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a40, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a44, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a48, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a4c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a50, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a54, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a58, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a5c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a60, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a64, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a68, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a6c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a70, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a74, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a78, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a7c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a80, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a84, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a88, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a8c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a90, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a94, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a98, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5a9c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aa0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aa4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aa8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5aac, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ab0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ab4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ab8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5abc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x5ac0, 0xffffffff, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_b[] = { ++ DECL_RFK_WM(0x78b0, 0x00000fff, 0x00000000), ++ DECL_RFK_WM(0x78b0, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x7a00, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a04, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a08, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a0c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a10, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a14, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a18, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a1c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a20, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a24, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a28, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a2c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a30, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a34, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a38, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a3c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a40, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a44, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a48, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a4c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a50, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a54, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a58, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a5c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a60, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a64, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a68, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a6c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a70, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a74, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a78, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a7c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a80, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a84, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a88, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a8c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a90, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a94, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a98, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7a9c, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aa0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aa4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aa8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7aac, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ab0, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ab4, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ab8, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7abc, 0xffffffff, 0x00000000), ++ DECL_RFK_WM(0x7ac0, 0xffffffff, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_a[] = { ++ DECL_RFK_WM(0x581c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x58cc, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x58cc, 0x00000007, 0x00000000), ++ DECL_RFK_WM(0x58cc, 0x00000038, 0x00000001), ++ DECL_RFK_WM(0x58cc, 0x000001c0, 0x00000002), ++ DECL_RFK_WM(0x58cc, 0x00000e00, 0x00000003), ++ DECL_RFK_WM(0x5828, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x5830, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x5838, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x5840, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x5898, 0xff000000, 0x00000040), ++ DECL_RFK_WM(0x5848, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x5850, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x5858, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x5860, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x589c, 0xff000000, 0x00000040), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_b[] = { ++ DECL_RFK_WM(0x781c, 0x00100000, 0x00000000), ++ DECL_RFK_WM(0x78cc, 0x00001000, 0x00000001), ++ DECL_RFK_WM(0x78cc, 0x00000007, 0x00000000), ++ DECL_RFK_WM(0x78cc, 0x00000038, 0x00000001), ++ DECL_RFK_WM(0x78cc, 0x000001c0, 0x00000002), ++ DECL_RFK_WM(0x78cc, 0x00000e00, 0x00000003), ++ DECL_RFK_WM(0x7828, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x7830, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x7838, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x7840, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x7898, 0xff000000, 0x00000040), ++ DECL_RFK_WM(0x7848, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0x000000ff, 0x00000040), ++ DECL_RFK_WM(0x7850, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0x0000ff00, 0x00000040), ++ DECL_RFK_WM(0x7878, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0x00ff0000, 0x00000040), ++ DECL_RFK_WM(0x7860, 0x7fc00000, 0x00000040), ++ DECL_RFK_WM(0x789c, 0xff000000, 0x00000040), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_a[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_b[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_a[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x581c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x5820, 0x0000f000, 0x00000001), ++ DECL_RFK_WM(0x581c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x581c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x58b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x58b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x58b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x58b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x58b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x5810, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x580c, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x580c, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x5838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x582c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x582c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x583c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x583c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x5844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x584c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x584c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x585c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x585c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x5828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x5860, 0x003ff000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_b[] = { ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00000800, 0x00000001), ++ DECL_RFK_WM(0x781c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x7820, 0x0000f000, 0x00000001), ++ DECL_RFK_WM(0x781c, 0x000003ff, 0x00000280), ++ DECL_RFK_WM(0x781c, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x78b8, 0x007f0000, 0x00000000), ++ DECL_RFK_WM(0x78b8, 0x7f000000, 0x00000000), ++ DECL_RFK_WM(0x78b4, 0x7f000000, 0x0000000a), ++ DECL_RFK_WM(0x78b8, 0x0000007f, 0x00000028), ++ DECL_RFK_WM(0x78b8, 0x00007f00, 0x00000076), ++ DECL_RFK_WM(0x7810, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x780c, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x780c, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x7838, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7834, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7834, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7838, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7854, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7854, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7858, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7824, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7824, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7828, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x782c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x782c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x783c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x783c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7844, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x7844, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x784c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x784c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x785c, 0x0003ffff, 0x000115f2), ++ DECL_RFK_WM(0x785c, 0x3ffc0000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x00000fff, 0x00000121), ++ DECL_RFK_WM(0x7828, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7830, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7840, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7848, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7850, 0x003ff000, 0x00000000), ++ DECL_RFK_WM(0x7860, 0x003ff000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_a[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x5814, 0x00000800, 0x00000000), ++ DECL_RFK_WM(0x581c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x5864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x5864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x5820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x5814, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_b[] = { ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x00000000), ++ DECL_RFK_WM(0x7814, 0x00000800, 0x00000000), ++ DECL_RFK_WM(0x781c, 0x20000000, 0x00000001), ++ DECL_RFK_WM(0x7864, 0x000003ff, 0x000001ff), ++ DECL_RFK_WM(0x7864, 0x000ffc00, 0x00000200), ++ DECL_RFK_WM(0x7820, 0x00000fff, 0x00000080), ++ DECL_RFK_WM(0x7814, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_a[] = { ++ DECL_RFK_WM(0x58e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x58e4, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x58e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x58e4, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x58e4, 0x000f0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_b[] = { ++ DECL_RFK_WM(0x78e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x78e4, 0x00004000, 0x00000001), ++ DECL_RFK_WM(0x78e4, 0x00004000, 0x00000000), ++ DECL_RFK_WM(0x78e4, 0x00008000, 0x00000000), ++ DECL_RFK_WM(0x78e4, 0x000f0000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_2g[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d0), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001e8), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x0000000b), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000088), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_1[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d7), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001fb), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000005), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x0000007c), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_1); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_3[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001d8), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x000001fc), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000006), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000078), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_3); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_4[] = { ++ DECL_RFK_WM(0x5814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x58f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x58a4, 0x03fe0000, 0x000001e5), ++ DECL_RFK_WM(0x58a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58a8, 0x0003fe00, 0x0000000a), ++ DECL_RFK_WM(0x58a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x58ac, 0x0003fe00, 0x00000011), ++ DECL_RFK_WM(0x58ac, 0x07fc0000, 0x00000075), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_4); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_2g[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001cc), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x000001e2), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000005), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000089), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_2g); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_1[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001d5), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x000001fc), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x00000005), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000079), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_1); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_3[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001dc), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000002), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x0000000b), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000076), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_3); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_4[] = { ++ DECL_RFK_WM(0x7814, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f4, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000003ff, 0x00000000), ++ DECL_RFK_WM(0x78f8, 0x000ffc00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x0001ff00, 0x00000000), ++ DECL_RFK_WM(0x78a4, 0x03fe0000, 0x000001f0), ++ DECL_RFK_WM(0x78a8, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78a8, 0x0003fe00, 0x00000016), ++ DECL_RFK_WM(0x78a8, 0x07fc0000, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x000001ff, 0x00000000), ++ DECL_RFK_WM(0x78ac, 0x0003fe00, 0x0000001f), ++ DECL_RFK_WM(0x78ac, 0x07fc0000, 0x00000072), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_4); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_a[] = { ++ DECL_RFK_WRF(0x0, 0x55, 0x00080, 0x00001), ++ DECL_RFK_WM(0x5818, 0x000000ff, 0x000000c0), ++ DECL_RFK_WM(0x5818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_b[] = { ++ DECL_RFK_WRF(0x1, 0x55, 0x00080, 0x00001), ++ DECL_RFK_WM(0x7818, 0x000000ff, 0x000000c0), ++ DECL_RFK_WM(0x7818, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_disable_defs[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x00000001), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x00000000), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_disable_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_ab[] = { ++ DECL_RFK_WM(0x5820, 0x80000000, 0x0), ++ DECL_RFK_WM(0x5820, 0x80000000, 0x1), ++ DECL_RFK_WM(0x5818, 0x18000000, 0x3), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x0), ++ DECL_RFK_WM(0x7820, 0x80000000, 0x1), ++ DECL_RFK_WM(0x7818, 0x18000000, 0x3), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_ab); ++ ++static const struct rtw89_reg5_def rtw8852a_tssi_tracking_defs[] = { ++ DECL_RFK_WM(0x5800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x5804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x58f0, 0xfff00000, 0x00000400), ++ DECL_RFK_WM(0x7800, 0x10000000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x7804, 0xf8000000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0xfff00000, 0x00000400), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_tssi_tracking_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_afe_init_defs[] = { ++ DECL_RFK_WC(0x12ec, 0x00008000), ++ DECL_RFK_WS(0x12ec, 0x00008000), ++ DECL_RFK_WC(0x5e00, 0x00000001), ++ DECL_RFK_WS(0x5e00, 0x00000001), ++ DECL_RFK_WC(0x32ec, 0x00008000), ++ DECL_RFK_WS(0x32ec, 0x00008000), ++ DECL_RFK_WC(0x7e00, 0x00000001), ++ DECL_RFK_WS(0x7e00, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_afe_init_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_a[] = { ++ DECL_RFK_WS(0x5e00, 0x00000008), ++ DECL_RFK_WS(0x5e50, 0x00000008), ++ DECL_RFK_WS(0x5e10, 0x80000000), ++ DECL_RFK_WS(0x5e60, 0x80000000), ++ DECL_RFK_WC(0x5e00, 0x00000008), ++ DECL_RFK_WC(0x5e50, 0x00000008), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_b[] = { ++ DECL_RFK_WS(0x7e00, 0x00000008), ++ DECL_RFK_WS(0x7e50, 0x00000008), ++ DECL_RFK_WS(0x7e10, 0x80000000), ++ DECL_RFK_WS(0x7e60, 0x80000000), ++ DECL_RFK_WC(0x7e00, 0x00000008), ++ DECL_RFK_WC(0x7e50, 0x00000008), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_a[] = { ++ DECL_RFK_WC(0x20f4, 0x01000000), ++ DECL_RFK_WS(0x20f8, 0x80000000), ++ DECL_RFK_WM(0x20f0, 0x00ff0000, 0x00000001), ++ DECL_RFK_WM(0x20f0, 0x00000f00, 0x00000002), ++ DECL_RFK_WC(0x20f0, 0x0000000f), ++ DECL_RFK_WM(0x20f0, 0x000000c0, 0x00000002), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_b[] = { ++ DECL_RFK_WC(0x20f4, 0x01000000), ++ DECL_RFK_WS(0x20f8, 0x80000000), ++ DECL_RFK_WM(0x20f0, 0x00ff0000, 0x00000001), ++ DECL_RFK_WM(0x20f0, 0x00000f00, 0x00000002), ++ DECL_RFK_WC(0x20f0, 0x0000000f), ++ DECL_RFK_WM(0x20f0, 0x000000c0, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_a[] = { ++ DECL_RFK_WC(0x12d8, 0x00000030), ++ DECL_RFK_WC(0x32d8, 0x00000030), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x00400000), ++ DECL_RFK_WS(0x032c, 0x00400000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x12dc, 0x00000002), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_a[] = { ++ DECL_RFK_WS(0x12d8, 0x000000c0), ++ DECL_RFK_WS(0x12d8, 0x00000800), ++ DECL_RFK_WC(0x12d8, 0x00000800), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x12d8, 0x00000300, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_a[] = { ++ DECL_RFK_WC(0x12dc, 0x00000002), ++ DECL_RFK_WS(0x032c, 0x00010000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x0000000c), ++ DECL_RFK_WS(0x032c, 0x40000000), ++ DECL_RFK_WC(0x12b8, 0x40000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_b[] = { ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WC(0x032c, 0x00400000), ++ DECL_RFK_WS(0x032c, 0x00400000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x32dc, 0x00000002), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_b[] = { ++ DECL_RFK_WS(0x32d8, 0x000000c0), ++ DECL_RFK_WS(0x32d8, 0x00000800), ++ DECL_RFK_WC(0x32d8, 0x00000800), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x32d8, 0x00000300, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_b[] = { ++ DECL_RFK_WC(0x32dc, 0x00000002), ++ DECL_RFK_WS(0x032c, 0x00010000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x0000000c), ++ DECL_RFK_WS(0x032c, 0x40000000), ++ DECL_RFK_WC(0x32b8, 0x40000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_a[] = { ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x12dc, 0x00000001), ++ DECL_RFK_WS(0x12e8, 0x00000004), ++ DECL_RFK_WRF(0x0, 0x8f, 0x02000, 0x00001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_b[] = { ++ DECL_RFK_WC(0x032c, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x0f000000), ++ DECL_RFK_WM(0x030c, 0x0f000000, 0x00000003), ++ DECL_RFK_WC(0x032c, 0x00010000), ++ DECL_RFK_WS(0x32dc, 0x00000001), ++ DECL_RFK_WS(0x32e8, 0x00000004), ++ DECL_RFK_WRF(0x1, 0x8f, 0x02000, 0x00001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_a[] = { ++ DECL_RFK_WC(0x12dc, 0x00000001), ++ DECL_RFK_WC(0x12e8, 0x00000004), ++ DECL_RFK_WRF(0x0, 0x8f, 0x02000, 0x00000), ++ DECL_RFK_WM(0x032c, 0x00010000, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_b[] = { ++ DECL_RFK_WC(0x32dc, 0x00000001), ++ DECL_RFK_WC(0x32e8, 0x00000004), ++ DECL_RFK_WRF(0x1, 0x8f, 0x02000, 0x00000), ++ DECL_RFK_WM(0x032c, 0x00010000, 0x00000001), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_a[] = { ++ DECL_RFK_WS(0x5e00, 0x00000008), ++ DECL_RFK_WC(0x5e10, 0x80000000), ++ DECL_RFK_WS(0x5e50, 0x00000008), ++ DECL_RFK_WC(0x5e60, 0x80000000), ++ DECL_RFK_WS(0x12a0, 0x00008000), ++ DECL_RFK_WM(0x12a0, 0x00007000, 0x00000003), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x10000000), ++ DECL_RFK_WC(0x032c, 0x80000000), ++ DECL_RFK_WS(0x12e0, 0x00010000), ++ DECL_RFK_WS(0x12e4, 0x0c000000), ++ DECL_RFK_WM(0x5e00, 0x03ff0000, 0x00000030), ++ DECL_RFK_WM(0x5e50, 0x03ff0000, 0x00000030), ++ DECL_RFK_WC(0x5e00, 0x0c000000), ++ DECL_RFK_WC(0x5e50, 0x0c000000), ++ DECL_RFK_WC(0x5e0c, 0x00000008), ++ DECL_RFK_WC(0x5e5c, 0x00000008), ++ DECL_RFK_WS(0x5e0c, 0x00000001), ++ DECL_RFK_WS(0x5e5c, 0x00000001), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_a[] = { ++ DECL_RFK_WC(0x12e4, 0x0c000000), ++ DECL_RFK_WS(0x5e0c, 0x00000008), ++ DECL_RFK_WS(0x5e5c, 0x00000008), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_a[] = { ++ DECL_RFK_WC(0x5e0c, 0x00000001), ++ DECL_RFK_WC(0x5e5c, 0x00000001), ++ DECL_RFK_WC(0x12e0, 0x00010000), ++ DECL_RFK_WC(0x12a0, 0x00008000), ++ DECL_RFK_WS(0x12a0, 0x00007000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_b[] = { ++ DECL_RFK_WS(0x7e00, 0x00000008), ++ DECL_RFK_WC(0x7e10, 0x80000000), ++ DECL_RFK_WS(0x7e50, 0x00000008), ++ DECL_RFK_WC(0x7e60, 0x80000000), ++ DECL_RFK_WS(0x32a0, 0x00008000), ++ DECL_RFK_WM(0x32a0, 0x00007000, 0x00000003), ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WS(0x030c, 0x10000000), ++ DECL_RFK_WC(0x032c, 0x80000000), ++ DECL_RFK_WS(0x32e0, 0x00010000), ++ DECL_RFK_WS(0x32e4, 0x0c000000), ++ DECL_RFK_WM(0x7e00, 0x03ff0000, 0x00000030), ++ DECL_RFK_WM(0x7e50, 0x03ff0000, 0x00000030), ++ DECL_RFK_WC(0x7e00, 0x0c000000), ++ DECL_RFK_WC(0x7e50, 0x0c000000), ++ DECL_RFK_WC(0x7e0c, 0x00000008), ++ DECL_RFK_WC(0x7e5c, 0x00000008), ++ DECL_RFK_WS(0x7e0c, 0x00000001), ++ DECL_RFK_WS(0x7e5c, 0x00000001), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_b[] = { ++ DECL_RFK_WC(0x32e4, 0x0c000000), ++ DECL_RFK_WM(0x7e0c, 0x00000008, 0x00000001), ++ DECL_RFK_WM(0x7e5c, 0x00000008, 0x00000001), ++ DECL_RFK_DELAY(1), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_b[] = { ++ DECL_RFK_WC(0x7e0c, 0x00000001), ++ DECL_RFK_WC(0x7e5c, 0x00000001), ++ DECL_RFK_WC(0x32e0, 0x00010000), ++ DECL_RFK_WC(0x32a0, 0x00008000), ++ DECL_RFK_WS(0x32a0, 0x00007000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_a[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WS(0x12b8, 0x10000000), ++ DECL_RFK_WS(0x58c8, 0x01000000), ++ DECL_RFK_WS(0x5864, 0xc0000000), ++ DECL_RFK_WS(0x2008, 0x01ffffff), ++ DECL_RFK_WS(0x0c1c, 0x00000004), ++ DECL_RFK_WS(0x0700, 0x08000000), ++ DECL_RFK_WS(0x0c70, 0x000003ff), ++ DECL_RFK_WS(0x0c60, 0x00000003), ++ DECL_RFK_WS(0x0c6c, 0x00000001), ++ DECL_RFK_WS(0x58ac, 0x08000000), ++ DECL_RFK_WS(0x0c3c, 0x00000200), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_a[] = { ++ DECL_RFK_WS(0x4490, 0x80000000), ++ DECL_RFK_WS(0x12a0, 0x00007000), ++ DECL_RFK_WS(0x12a0, 0x00008000), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x12a0, 0x00080000), ++ DECL_RFK_WS(0x0700, 0x01000000), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00001111), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_b[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WS(0x32b8, 0x10000000), ++ DECL_RFK_WS(0x78c8, 0x01000000), ++ DECL_RFK_WS(0x7864, 0xc0000000), ++ DECL_RFK_WS(0x2008, 0x01ffffff), ++ DECL_RFK_WS(0x2c1c, 0x00000004), ++ DECL_RFK_WS(0x2700, 0x08000000), ++ DECL_RFK_WS(0x0c70, 0x000003ff), ++ DECL_RFK_WS(0x0c60, 0x00000003), ++ DECL_RFK_WS(0x0c6c, 0x00000001), ++ DECL_RFK_WS(0x78ac, 0x08000000), ++ DECL_RFK_WS(0x2c3c, 0x00000200), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_b[] = { ++ DECL_RFK_WS(0x6490, 0x80000000), ++ DECL_RFK_WS(0x32a0, 0x00007000), ++ DECL_RFK_WS(0x32a0, 0x00008000), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x32a0, 0x00080000), ++ DECL_RFK_WS(0x2700, 0x01000000), ++ DECL_RFK_WM(0x2700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00002222), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_s_defs_ab[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WS(0x12b8, 0x40000000), ++ DECL_RFK_WS(0x32b8, 0x40000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WS(0x12b8, 0x10000000), ++ DECL_RFK_WS(0x58c8, 0x01000000), ++ DECL_RFK_WS(0x78c8, 0x01000000), ++ DECL_RFK_WS(0x5864, 0xc0000000), ++ DECL_RFK_WS(0x7864, 0xc0000000), ++ DECL_RFK_WS(0x2008, 0x01ffffff), ++ DECL_RFK_WS(0x0c1c, 0x00000004), ++ DECL_RFK_WS(0x0700, 0x08000000), ++ DECL_RFK_WS(0x0c70, 0x000003ff), ++ DECL_RFK_WS(0x0c60, 0x00000003), ++ DECL_RFK_WS(0x0c6c, 0x00000001), ++ DECL_RFK_WS(0x58ac, 0x08000000), ++ DECL_RFK_WS(0x78ac, 0x08000000), ++ DECL_RFK_WS(0x0c3c, 0x00000200), ++ DECL_RFK_WS(0x2344, 0x80000000), ++ DECL_RFK_WS(0x4490, 0x80000000), ++ DECL_RFK_WS(0x12a0, 0x00007000), ++ DECL_RFK_WS(0x12a0, 0x00008000), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x12a0, 0x00080000), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WS(0x32a0, 0x00080000), ++ DECL_RFK_WS(0x0700, 0x01000000), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_s_defs_ab); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_a[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WC(0x12b8, 0x40000000), ++ DECL_RFK_WC(0x5864, 0xc0000000), ++ DECL_RFK_WC(0x2008, 0x01ffffff), ++ DECL_RFK_WC(0x0c1c, 0x00000004), ++ DECL_RFK_WC(0x0700, 0x08000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WC(0x12a0, 0x000ff000), ++ DECL_RFK_WC(0x0700, 0x07000000), ++ DECL_RFK_WC(0x5864, 0x20000000), ++ DECL_RFK_WC(0x0c3c, 0x00000200), ++ DECL_RFK_WC(0x20fc, 0xffff0000), ++ DECL_RFK_WC(0x58c8, 0x01000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_a); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_b[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WC(0x32b8, 0x40000000), ++ DECL_RFK_WC(0x7864, 0xc0000000), ++ DECL_RFK_WC(0x2008, 0x01ffffff), ++ DECL_RFK_WC(0x2c1c, 0x00000004), ++ DECL_RFK_WC(0x2700, 0x08000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WC(0x32a0, 0x000ff000), ++ DECL_RFK_WC(0x2700, 0x07000000), ++ DECL_RFK_WC(0x7864, 0x20000000), ++ DECL_RFK_WC(0x2c3c, 0x00000200), ++ DECL_RFK_WC(0x20fc, 0xffff0000), ++ DECL_RFK_WC(0x78c8, 0x01000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_b); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_ab[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WC(0x12b8, 0x40000000), ++ DECL_RFK_WC(0x32b8, 0x40000000), ++ DECL_RFK_WC(0x5864, 0xc0000000), ++ DECL_RFK_WC(0x7864, 0xc0000000), ++ DECL_RFK_WC(0x2008, 0x01ffffff), ++ DECL_RFK_WC(0x0c1c, 0x00000004), ++ DECL_RFK_WC(0x0700, 0x08000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WC(0x12a0, 0x000ff000), ++ DECL_RFK_WC(0x32a0, 0x000ff000), ++ DECL_RFK_WC(0x0700, 0x07000000), ++ DECL_RFK_WC(0x5864, 0x20000000), ++ DECL_RFK_WC(0x7864, 0x20000000), ++ DECL_RFK_WC(0x0c3c, 0x00000200), ++ DECL_RFK_WC(0x20fc, 0xffff0000), ++ DECL_RFK_WC(0x58c8, 0x01000000), ++ DECL_RFK_WC(0x78c8, 0x01000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_ab); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_f[] = { ++ DECL_RFK_WM(0x030c, 0xff000000, 0x0000000f), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000003), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x0000a001), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x0000a041), ++ DECL_RFK_WS(0x8074, 0x80000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_f); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_r[] = { ++ DECL_RFK_WC(0x8074, 0x80000000), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x0000001f), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_DELAY(1), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000041), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_r); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_dpk_pas_read_defs[] = { ++ DECL_RFK_WM(0x80d4, 0x00ff0000, 0x00000006), ++ DECL_RFK_WC(0x80bc, 0x00004000), ++ DECL_RFK_WM(0x80c0, 0x00ff0000, 0x00000008), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_dpk_pas_read_defs); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_nondbcc_path01[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WM(0x5864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_WM(0x12b8, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), ++ DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), ++ DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x58ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x78ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000001), ++ DECL_RFK_WM(0x2344, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x4490, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00007000, 0x00000007), ++ DECL_RFK_WM(0x12a0, 0x00008000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x32a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00003333), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_nondbcc_path01); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path0[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WM(0x5864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_WM(0x12b8, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), ++ DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), ++ DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x58ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000001), ++ DECL_RFK_WM(0x2320, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x4490, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00007000, 0x00000007), ++ DECL_RFK_WM(0x12a0, 0x00008000, 0x00000001), ++ DECL_RFK_WM(0x12a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x0700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00001111), ++ DECL_RFK_WM(0x58f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path0); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path1[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WM(0x7864, 0x18000000, 0x00000003), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000001), ++ DECL_RFK_WM(0x030c, 0xff000000, 0x00000013), ++ DECL_RFK_WM(0x032c, 0xffff0000, 0x00000001), ++ DECL_RFK_WM(0x32b8, 0x10000000, 0x00000001), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000003), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x01ffffff), ++ DECL_RFK_WM(0x2c1c, 0x00000004, 0x00000001), ++ DECL_RFK_WM(0x2700, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x0c70, 0x000003ff, 0x000003ff), ++ DECL_RFK_WM(0x0c60, 0x00000003, 0x00000003), ++ DECL_RFK_WM(0x0c6c, 0x00000001, 0x00000001), ++ DECL_RFK_WM(0x78ac, 0x08000000, 0x00000001), ++ DECL_RFK_WM(0x2c3c, 0x00000200, 0x00000001), ++ DECL_RFK_WM(0x6490, 0x80000000, 0x00000001), ++ DECL_RFK_WM(0x32a0, 0x00007000, 0x00000007), ++ DECL_RFK_WM(0x32a0, 0x00008000, 0x00000001), ++ DECL_RFK_WM(0x32a0, 0x00070000, 0x00000003), ++ DECL_RFK_WM(0x32a0, 0x00080000, 0x00000001), ++ DECL_RFK_WM(0x2700, 0x01000000, 0x00000001), ++ DECL_RFK_WM(0x2700, 0x06000000, 0x00000002), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00002222), ++ DECL_RFK_WM(0x78f0, 0x00080000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path1); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_nondbcc_path01[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000303), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x32a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x07000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x2320, 0x00000001, 0x00000000), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_nondbcc_path01); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path0[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000101), ++ DECL_RFK_WM(0x12b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), ++ DECL_RFK_WM(0x0c1c, 0x00000004, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x08000000, 0x00000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WM(0x12a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x0700, 0x07000000, 0x00000000), ++ DECL_RFK_WM(0x5864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x0c3c, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), ++ DECL_RFK_WM(0x58c8, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path0); ++ ++static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path1[] = { ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000202), ++ DECL_RFK_WM(0x32b8, 0x40000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0xc0000000, 0x00000000), ++ DECL_RFK_WM(0x2008, 0x01ffffff, 0x00000000), ++ DECL_RFK_WM(0x2c1c, 0x00000004, 0x00000000), ++ DECL_RFK_WM(0x2700, 0x08000000, 0x00000000), ++ DECL_RFK_WM(0x0c70, 0x0000001f, 0x00000003), ++ DECL_RFK_WM(0x0c70, 0x000003e0, 0x00000003), ++ DECL_RFK_WM(0x32a0, 0x000ff000, 0x00000000), ++ DECL_RFK_WM(0x2700, 0x07000000, 0x00000000), ++ DECL_RFK_WM(0x7864, 0x20000000, 0x00000000), ++ DECL_RFK_WM(0x2c3c, 0x00000200, 0x00000000), ++ DECL_RFK_WM(0x20fc, 0xffff0000, 0x00000000), ++ DECL_RFK_WM(0x78c8, 0x01000000, 0x00000000), ++}; ++ ++DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path1); +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h +new file mode 100644 +index 000000000000..4a4a45d778ff +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_rfk_table.h +@@ -0,0 +1,133 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_RFK_TABLE_H__ ++#define __RTW89_8852A_RFK_TABLE_H__ ++ ++#include "core.h" ++ ++enum rtw89_rfk_flag { ++ RTW89_RFK_F_WRF = 0, ++ RTW89_RFK_F_WM = 1, ++ RTW89_RFK_F_WS = 2, ++ RTW89_RFK_F_WC = 3, ++ RTW89_RFK_F_DELAY = 4, ++ RTW89_RFK_F_NUM, ++}; ++ ++struct rtw89_rfk_tbl { ++ const struct rtw89_reg5_def *defs; ++ u32 size; ++}; ++ ++#define DECLARE_RFK_TBL(_name) \ ++const struct rtw89_rfk_tbl _name ## _tbl = { \ ++ .defs = _name, \ ++ .size = ARRAY_SIZE(_name), \ ++} ++ ++#define DECL_RFK_WRF(_path, _addr, _mask, _data) \ ++ {.flag = RTW89_RFK_F_WRF, \ ++ .path = _path, \ ++ .addr = _addr, \ ++ .mask = _mask, \ ++ .data = _data,} ++ ++#define DECL_RFK_WM(_addr, _mask, _data) \ ++ {.flag = RTW89_RFK_F_WM, \ ++ .addr = _addr, \ ++ .mask = _mask, \ ++ .data = _data,} ++ ++#define DECL_RFK_WS(_addr, _mask) \ ++ {.flag = RTW89_RFK_F_WS, \ ++ .addr = _addr, \ ++ .mask = _mask,} ++ ++#define DECL_RFK_WC(_addr, _mask) \ ++ {.flag = RTW89_RFK_F_WC, \ ++ .addr = _addr, \ ++ .mask = _mask,} ++ ++#define DECL_RFK_DELAY(_data) \ ++ {.flag = RTW89_RFK_F_DELAY, \ ++ .data = _data,} ++ ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_sys_defs_5g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_defs_5g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dck_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dck_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dac_gain_tbl_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_dac_gain_tbl_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_cal_org_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_cal_org_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_rf_gap_tbl_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_rf_gap_tbl_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_slope_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_track_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_track_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txagc_ofst_mv_avg_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_txagc_ofst_mv_avg_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_1_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_3_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_a_5g_4_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_2g_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_1_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_3_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_pak_defs_b_5g_4_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_enable_defs_ab_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_disable_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_tssi_tracking_defs_tbl; ++ ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_afe_init_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_reload_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_reload_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_addc_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_addc_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_reset_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_trigger_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_restore_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_reset_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_trigger_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_addck_restore_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_f_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_f_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_r_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_check_dadc_defs_r_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_f_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_m_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_r_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_f_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_m_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dack_defs_r_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sf_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sr_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sf_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_sr_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_s_defs_ab_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_a_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_b_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_bb_afe_r_defs_ab_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_lbk_rxiqk_defs_f_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_lbk_rxiqk_defs_r_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_dpk_pas_read_defs_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_nondbcc_path01_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_dbcc_path0_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_set_defs_dbcc_path1_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_nondbcc_path01_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_dbcc_path0_tbl; ++extern const struct rtw89_rfk_tbl rtw8852a_rfk_iqk_restore_defs_dbcc_path1_tbl; ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +new file mode 100644 +index 000000000000..3a4fe7207420 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -0,0 +1,48725 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "phy.h" ++#include "reg.h" ++#include "rtw8852a_table.h" ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_bb_regs[] = { ++ {0xF0FF0001, 0x00000000}, ++ {0xF03300FF, 0x00000001}, ++ {0xF03500FF, 0x00000002}, ++ {0xF03200FF, 0x00000003}, ++ {0xF03400FF, 0x00000004}, ++ {0xF03600FF, 0x00000005}, ++ {0x704, 0x601E0100}, ++ {0x714, 0x00000000}, ++ {0x718, 0x13332333}, ++ {0x714, 0x00010000}, ++ {0x720, 0x20000000}, ++ {0x980, 0x10002250}, ++ {0x994, 0x00000010}, ++ {0x644, 0x2314283C}, ++ {0x644, 0x3426283C}, ++ {0x994, 0x00000010}, ++ {0xC3C, 0x2840E1BF}, ++ {0xC40, 0x00000000}, ++ {0xC44, 0x00000007}, ++ {0xC48, 0x410E4000}, ++ {0xC54, 0x1001436E}, ++ {0xC58, 0x41000000}, ++ {0x730, 0x00000002}, ++ {0xC60, 0x017FFFF2}, ++ {0xC64, 0x0010A130}, ++ {0xC64, 0x0010A130}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x10000068}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x10000068}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0xC68, 0x90000068}, ++ {0xA0000000, 0x00000000}, ++ {0xC68, 0x10000068}, ++ {0xB0000000, 0x00000000}, ++ {0xC64, 0x0010A130}, ++ {0xC54, 0x1EE1436E}, ++ {0xC6C, 0x00000020}, ++ {0x708, 0x00000000}, ++ {0xC6C, 0x00000020}, ++ {0x804, 0x0043F01D}, ++ {0x12D0, 0x00000000}, ++ {0x12EC, 0x888CA72B}, ++ {0x32D0, 0x00000000}, ++ {0x32EC, 0x888CA72B}, ++ {0xD40, 0xF64FA0F7}, ++ {0xD44, 0x0400063F}, ++ {0xD48, 0x0003FF7F}, ++ {0xD4C, 0x00000000}, ++ {0xD50, 0xF64FA0F7}, ++ {0xD54, 0x04100437}, ++ {0xD58, 0x0000FF7F}, ++ {0xD5C, 0x00000000}, ++ {0xD60, 0x00000000}, ++ {0xD64, 0x00000000}, ++ {0xD70, 0x0000001D}, ++ {0xD90, 0x000003FF}, ++ {0xD94, 0x00000000}, ++ {0xD98, 0x0000003F}, ++ {0xD9C, 0x00000000}, ++ {0xDA0, 0x000003FF}, ++ {0xDA4, 0x00000000}, ++ {0xDA8, 0x0000003F}, ++ {0xDAC, 0x00000000}, ++ {0xD00, 0x77777777}, ++ {0xD04, 0xBBBBBBBB}, ++ {0xD08, 0xBBBBBBBB}, ++ {0xD0C, 0x00000070}, ++ {0xD10, 0x20110900}, ++ {0xD10, 0x20110FFF}, ++ {0xD7C, 0x001D050C}, ++ {0xD84, 0x00006207}, ++ {0xD18, 0x50209900}, ++ {0xD80, 0x00804100}, ++ {0x714, 0x00010000}, ++ {0x704, 0x601E00FD}, ++ {0x710, 0xF3810000}, ++ {0x000, 0x0580801F}, ++ {0x000, 0x8580801F}, ++ {0x334, 0xFFFFFFFF}, ++ {0x33C, 0x55000000}, ++ {0x340, 0x00005555}, ++ {0x724, 0x00111200}, ++ {0x5868, 0xA9550000}, ++ {0x5870, 0x33221100}, ++ {0x5874, 0x77665544}, ++ {0x5878, 0xBBAA9988}, ++ {0x587C, 0xFFEEDDCC}, ++ {0x5880, 0x76543210}, ++ {0x5884, 0xFEDCBA98}, ++ {0x5888, 0x00000000}, ++ {0x588C, 0x00000000}, ++ {0x5894, 0x00000008}, ++ {0x7868, 0xA9550000}, ++ {0x7870, 0x33221100}, ++ {0x7874, 0x77665544}, ++ {0x7878, 0xBBAA9988}, ++ {0x787C, 0xFFEEDDCC}, ++ {0x7880, 0x76543210}, ++ {0x7884, 0xFEDCBA98}, ++ {0x7888, 0x00000000}, ++ {0x788C, 0x00000000}, ++ {0x7894, 0x00000008}, ++ {0x240C, 0x00000000}, ++ {0xC70, 0x00000400}, ++ {0x700, 0x00000030}, ++ {0x704, 0x601E00FF}, ++ {0x704, 0x601E00FD}, ++ {0x704, 0x601E00FF}, ++ {0x586C, 0x000000F0}, ++ {0x586C, 0x000000E0}, ++ {0x586C, 0x000000D0}, ++ {0x586C, 0x000000C0}, ++ {0x586C, 0x000000B0}, ++ {0x586C, 0x000000A0}, ++ {0x586C, 0x00000090}, ++ {0x586C, 0x00000080}, ++ {0x586C, 0x00000070}, ++ {0x586C, 0x00000060}, ++ {0x586C, 0x00000050}, ++ {0x586C, 0x00000040}, ++ {0x586C, 0x00000030}, ++ {0x586C, 0x00000020}, ++ {0x586C, 0x00000010}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x00000000}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x00000000}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x586C, 0x03E00000}, ++ {0xA0000000, 0x00000000}, ++ {0x586C, 0x00000000}, ++ {0xB0000000, 0x00000000}, ++ {0x786C, 0x000000F0}, ++ {0x786C, 0x000000E0}, ++ {0x786C, 0x000000D0}, ++ {0x786C, 0x000000C0}, ++ {0x786C, 0x000000B0}, ++ {0x786C, 0x000000A0}, ++ {0x786C, 0x00000090}, ++ {0x786C, 0x00000080}, ++ {0x786C, 0x00000070}, ++ {0x786C, 0x00000060}, ++ {0x786C, 0x00000050}, ++ {0x786C, 0x00000040}, ++ {0x786C, 0x00000030}, ++ {0x786C, 0x00000020}, ++ {0x786C, 0x00000010}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x00000000}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x00000000}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x786C, 0x03E00000}, ++ {0xA0000000, 0x00000000}, ++ {0x786C, 0x00000000}, ++ {0xB0000000, 0x00000000}, ++ {0x5864, 0x080801FF}, ++ {0x7864, 0x080801FF}, ++ {0xC60, 0x017FFFF3}, ++ {0xC6C, 0x00000021}, ++ {0x58AC, 0x08000000}, ++ {0x78AC, 0x08000000}, ++ {0x5864, 0x180801FF}, ++ {0x7864, 0x180801FF}, ++ {0xC60, 0x017FFFF3}, ++ {0xC60, 0x017FFFF3}, ++ {0x2C60, 0x013FFF0A}, ++ {0xC70, 0x00000600}, ++ {0xC70, 0x00000660}, ++ {0xC6C, 0x10001021}, ++ {0x58AC, 0x08000000}, ++ {0x78AC, 0x08000000}, ++ {0x5864, 0x100801FF}, ++ {0x7864, 0x100801FF}, ++ {0x5864, 0x180801FF}, ++ {0x7864, 0x180801FF}, ++ {0x704, 0x601C01FF}, ++ {0x58D4, 0x0401FE00}, ++ {0x78D4, 0x0401FE00}, ++ {0x58F0, 0x000401FF}, ++ {0x78F0, 0x000401FF}, ++ {0x58F0, 0x400401FF}, ++ {0x78F0, 0x400401FF}, ++ {0x12A8, 0x333378A5}, ++ {0x32A8, 0x333378A5}, ++ {0x2300, 0x02748790}, ++ {0x2304, 0x00558670}, ++ {0x2308, 0x002883F0}, ++ {0x230C, 0x00090120}, ++ {0x2310, 0x00000000}, ++ {0x2314, 0x06000000}, ++ {0x2318, 0x00000000}, ++ {0x231C, 0x00000000}, ++ {0x2320, 0x03020100}, ++ {0x2324, 0x07060504}, ++ {0x2328, 0x0B0A0908}, ++ {0x232C, 0x0F0E0D0C}, ++ {0x2330, 0x13121110}, ++ {0x2334, 0x17161514}, ++ {0x2338, 0x0C700022}, ++ {0x233C, 0x0A05298F}, ++ {0x2340, 0x0005298E}, ++ {0x2344, 0x0006318A}, ++ {0x2348, 0xB7E6318A}, ++ {0x234C, 0x80039CE7}, ++ {0x2350, 0x80039CE7}, ++ {0x2354, 0x0005298F}, ++ {0x2358, 0x0015296E}, ++ {0x235C, 0x0C07FC31}, ++ {0x2360, 0x0219A6AE}, ++ {0x2364, 0xE4F624C3}, ++ {0x2368, 0x53626F15}, ++ {0x236C, 0x48000000}, ++ {0x2370, 0x48000000}, ++ {0x2374, 0x074C0000}, ++ {0x2378, 0x202401B5}, ++ {0x237C, 0x00F7000E}, ++ {0x2380, 0x0F0A1111}, ++ {0x2384, 0x30D9000F}, ++ {0x2388, 0x0400EA02}, ++ {0x238C, 0x003CB061}, ++ {0x2390, 0x69C00000}, ++ {0x2394, 0x00000000}, ++ {0x2398, 0x000000F0}, ++ {0x239C, 0x0001FFFF}, ++ {0x23A0, 0x00C80064}, ++ {0x23A4, 0x0190012C}, ++ {0x23A8, 0x001917BE}, ++ {0x23AC, 0x0B308800}, ++ {0x23B0, 0x0001D5B0}, ++ {0x23B4, 0x000285D2}, ++ {0x23B8, 0x00000000}, ++ {0x23BC, 0x00000000}, ++ {0x23C0, 0x00000000}, ++ {0x23C4, 0x00000000}, ++ {0x23C8, 0x00000000}, ++ {0x23CC, 0x00000000}, ++ {0x23D0, 0x00000000}, ++ {0x23D4, 0x00000000}, ++ {0x23D8, 0x00000000}, ++ {0x23DC, 0x00000000}, ++ {0x23E0, 0x00000000}, ++ {0x23E4, 0x00000000}, ++ {0x23E8, 0x00000000}, ++ {0x23EC, 0x00000000}, ++ {0x23F0, 0x00000000}, ++ {0x23F4, 0x00000000}, ++ {0x23F8, 0x00000000}, ++ {0x23FC, 0x00000000}, ++ {0x804, 0x0043F01D}, ++ {0x300, 0xF30CE31C}, ++ {0x304, 0x13EF1F19}, ++ {0x308, 0x0C0CF3F3}, ++ {0x30C, 0x0C0C0C0C}, ++ {0x310, 0x80416000}, ++ {0x314, 0x0041E000}, ++ {0x318, 0x20022042}, ++ {0x31C, 0x20448001}, ++ {0x320, 0x00410040}, ++ {0x324, 0xE000E000}, ++ {0x328, 0xE000E000}, ++ {0x32C, 0xE000E000}, ++ {0x12BC, 0x10104041}, ++ {0x12C0, 0x14411111}, ++ {0x32BC, 0x10104041}, ++ {0x32C0, 0x14411111}, ++ {0x010, 0x0005FFFF}, ++ {0x604, 0x1E1E1E28}, ++ {0x650, 0x00200888}, ++ {0x620, 0x00141230}, ++ {0x35C, 0x000004C4}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04237040}, ++ {0x7804, 0x04237040}, ++ {0x5808, 0x04237040}, ++ {0x7808, 0x04237040}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04237040}, ++ {0x7804, 0x04237040}, ++ {0x5808, 0x04237040}, ++ {0x7808, 0x04237040}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5804, 0x04231040}, ++ {0x7804, 0x04231040}, ++ {0x5808, 0x04231040}, ++ {0x7808, 0x04231040}, ++ {0xA0000000, 0x00000000}, ++ {0x5804, 0x04237040}, ++ {0x7804, 0x04237040}, ++ {0x5808, 0x04237040}, ++ {0x7808, 0x04237040}, ++ {0xB0000000, 0x00000000}, ++ {0x12A0, 0x24903156}, ++ {0x32A0, 0x24903156}, ++ {0x640, 0x1414141E}, ++ {0x12B8, 0x30020000}, ++ {0x12AC, 0x02333121}, ++ {0x9A4, 0x0000001C}, ++ {0x624, 0x01010301}, ++ {0x628, 0x00010101}, ++ {0x5800, 0x03FF807F}, ++ {0x7800, 0x03FF807F}, ++ {0x4000, 0x00000000}, ++ {0x4004, 0xCA014000}, ++ {0x4008, 0xC751D4F0}, ++ {0x400C, 0x44511475}, ++ {0x4010, 0x00000000}, ++ {0x4014, 0x00000000}, ++ {0x4018, 0x4F4C084B}, ++ {0x401C, 0x084A4E52}, ++ {0x4020, 0x4D504E4B}, ++ {0x4024, 0x4F4C0849}, ++ {0x4028, 0x08484C50}, ++ {0x402C, 0x4C50504C}, ++ {0x4030, 0x5454084A}, ++ {0x4034, 0x084B5654}, ++ {0x4038, 0x6A6C605A}, ++ {0x403C, 0x4C4C084C}, ++ {0x4040, 0x084B4E4D}, ++ {0x4044, 0x4E4C4B4B}, ++ {0x4048, 0x4B4B084A}, ++ {0x404C, 0x084A4E4C}, ++ {0x4050, 0x514F4C4A}, ++ {0x4054, 0x524E084A}, ++ {0x4058, 0x084A5154}, ++ {0x405C, 0x53555554}, ++ {0x4060, 0x45450845}, ++ {0x4064, 0x08454144}, ++ {0x4068, 0x40434445}, ++ {0x406C, 0x44450845}, ++ {0x4070, 0x08444043}, ++ {0x4074, 0x42434444}, ++ {0x4078, 0x46450844}, ++ {0x407C, 0x08444843}, ++ {0x4080, 0x4B4E4A47}, ++ {0x4084, 0x4F4C084B}, ++ {0x4088, 0x084A4E52}, ++ {0x408C, 0x4D504E4B}, ++ {0x4090, 0x4F4C0849}, ++ {0x4094, 0x08484C50}, ++ {0x4098, 0x4C50504C}, ++ {0x409C, 0x5454084A}, ++ {0x40A0, 0x084B5654}, ++ {0x40A4, 0x6A6C605A}, ++ {0x40A8, 0x4C4C084C}, ++ {0x40AC, 0x084B4E4D}, ++ {0x40B0, 0x4E4C4B4B}, ++ {0x40B4, 0x4B4B084A}, ++ {0x40B8, 0x084A4E4C}, ++ {0x40BC, 0x514F4C4A}, ++ {0x40C0, 0x524E084A}, ++ {0x40C4, 0x084A5154}, ++ {0x40C8, 0x53555554}, ++ {0x40CC, 0x45450845}, ++ {0x40D0, 0x08454144}, ++ {0x40D4, 0x40434445}, ++ {0x40D8, 0x44450845}, ++ {0x40DC, 0x08444043}, ++ {0x40E0, 0x42434444}, ++ {0x40E4, 0x46450844}, ++ {0x40E8, 0x08444843}, ++ {0x40EC, 0x4B4E4A47}, ++ {0x40F0, 0x00000000}, ++ {0x40F4, 0x00000006}, ++ {0x40F8, 0x00000001}, ++ {0x40FC, 0x8C30C30C}, ++ {0x4100, 0x4C30C30C}, ++ {0x4104, 0x0C30C30C}, ++ {0x4108, 0x0C30C30C}, ++ {0x410C, 0x0C30C30C}, ++ {0x4110, 0x0C30C30C}, ++ {0x4114, 0x28A28A28}, ++ {0x4118, 0x28A28A28}, ++ {0x411C, 0x28A28A28}, ++ {0x4120, 0x28A28A28}, ++ {0x4124, 0x28A28A28}, ++ {0x4128, 0x28A28A28}, ++ {0x412C, 0x06666666}, ++ {0x4130, 0x33333333}, ++ {0x4134, 0x33333333}, ++ {0x4138, 0x33333333}, ++ {0x413C, 0x00000031}, ++ {0x4140, 0x5100600A}, ++ {0x4144, 0x18363113}, ++ {0x4148, 0x1D976DDC}, ++ {0x414C, 0x1C072DD7}, ++ {0x4150, 0x1127CDF4}, ++ {0x4154, 0x1E37BDF1}, ++ {0x4158, 0x1FB7F1D6}, ++ {0x415C, 0x1EA7DDF9}, ++ {0x4160, 0x1FE445DD}, ++ {0x4164, 0x1F97F1FE}, ++ {0x4168, 0x1FF781ED}, ++ {0x416C, 0x1FA7F5FE}, ++ {0x4170, 0x1E07B913}, ++ {0x4174, 0x1FD7FDFF}, ++ {0x4178, 0x1E17B9FA}, ++ {0x417C, 0x19A66914}, ++ {0x4180, 0x10F65598}, ++ {0x4184, 0x14A5A111}, ++ {0x4188, 0x1D3765DB}, ++ {0x418C, 0x17C685CA}, ++ {0x4190, 0x1107C5F3}, ++ {0x4194, 0x1B5785EB}, ++ {0x4198, 0x1F97ED8F}, ++ {0x419C, 0x1BC7A5F3}, ++ {0x41A0, 0x1FE43595}, ++ {0x41A4, 0x1EB7D9FC}, ++ {0x41A8, 0x1FE65DBE}, ++ {0x41AC, 0x1EC7D9FC}, ++ {0x41B0, 0x1976FCFF}, ++ {0x41B4, 0x1F77F5FF}, ++ {0x41B8, 0x1976FDEC}, ++ {0x41BC, 0x198664EF}, ++ {0x41C0, 0x11062D93}, ++ {0x41C4, 0x10C4E910}, ++ {0x41C8, 0x1CA759DB}, ++ {0x41CC, 0x1335A9B5}, ++ {0x41D0, 0x1097B9F3}, ++ {0x41D4, 0x17B72DE1}, ++ {0x41D8, 0x1F67ED42}, ++ {0x41DC, 0x18074DE9}, ++ {0x41E0, 0x1FD40547}, ++ {0x41E4, 0x1D57ADF9}, ++ {0x41E8, 0x1FE52182}, ++ {0x41EC, 0x1D67B1F9}, ++ {0x41F0, 0x14860CE1}, ++ {0x41F4, 0x1EC7E9FE}, ++ {0x41F8, 0x14860DD6}, ++ {0x41FC, 0x195664C7}, ++ {0x4200, 0x0005E58A}, ++ {0x4204, 0x00000000}, ++ {0x4208, 0x00000000}, ++ {0x420C, 0x7A000000}, ++ {0x4210, 0x0F9F3D7A}, ++ {0x4214, 0x0040817C}, ++ {0x4218, 0x00E10204}, ++ {0x421C, 0x227D94CD}, ++ {0x4220, 0x080238E3}, ++ {0x4224, 0x00000210}, ++ {0x4228, 0x04688000}, ++ {0x422C, 0x0060B002}, ++ {0x4230, 0x9A8249A8}, ++ {0x4234, 0x26A1469E}, ++ {0x4238, 0x2099A824}, ++ {0x423C, 0x2359461C}, ++ {0x4240, 0x1631A675}, ++ {0x4244, 0x2C6B1D63}, ++ {0x4248, 0x0000000E}, ++ {0x424C, 0x00000001}, ++ {0x4250, 0x00000001}, ++ {0x4254, 0x00000000}, ++ {0x4258, 0x00000000}, ++ {0x425C, 0x00000000}, ++ {0x4260, 0x0020000C}, ++ {0x4264, 0x00000000}, ++ {0x4268, 0x00000000}, ++ {0x426C, 0x0418317C}, ++ {0x4270, 0x00D6135C}, ++ {0x4274, 0x00000000}, ++ {0x4278, 0x00000000}, ++ {0x427C, 0x00000000}, ++ {0x4280, 0x00000000}, ++ {0x4284, 0x00000000}, ++ {0x4288, 0x00000000}, ++ {0x428C, 0x00000000}, ++ {0x4290, 0x00000000}, ++ {0x4294, 0x00000000}, ++ {0x4298, 0x84026000}, ++ {0x429C, 0x0051AC20}, ++ {0x42A0, 0x02024008}, ++ {0x42A4, 0x00000000}, ++ {0x42A8, 0x00000000}, ++ {0x42AC, 0x22CE803C}, ++ {0x42B0, 0x80000000}, ++ {0x42B4, 0x00E7D03D}, ++ {0x42B8, 0x3D67D67D}, ++ {0x42BC, 0x7D67D65B}, ++ {0x42C0, 0x2802AF59}, ++ {0x42C4, 0x00280280}, ++ {0x42C8, 0x00000000}, ++ {0x42CC, 0x00000000}, ++ {0x42D0, 0x00000003}, ++ {0x42D4, 0x00000001}, ++ {0x42D8, 0x61861800}, ++ {0x42DC, 0x830C30C3}, ++ {0x42E0, 0xC30C30C3}, ++ {0x42E4, 0x830C30C3}, ++ {0x42E8, 0x451450C3}, ++ {0x42EC, 0x05145145}, ++ {0x42F0, 0x05145145}, ++ {0x42F4, 0x05145145}, ++ {0x42F8, 0x0F0C3145}, ++ {0x42FC, 0x030C30CF}, ++ {0x4300, 0x030C30C3}, ++ {0x4304, 0x030CF3C3}, ++ {0x4308, 0x030C30C3}, ++ {0x430C, 0x0F3CF3C3}, ++ {0x4310, 0x0F3CF3CF}, ++ {0x4314, 0x0F3CF3CF}, ++ {0x4318, 0x0F3CF3CF}, ++ {0x431C, 0x0F3CF3CF}, ++ {0x4320, 0x030C10C3}, ++ {0x4324, 0x051430C3}, ++ {0x4328, 0x051490CB}, ++ {0x432C, 0x030CD151}, ++ {0x4330, 0x050C50C7}, ++ {0x4334, 0x051492CB}, ++ {0x4338, 0x05145145}, ++ {0x433C, 0x05145145}, ++ {0x4340, 0x05145145}, ++ {0x4344, 0x05145145}, ++ {0x4348, 0x090CD3CF}, ++ {0x434C, 0x071491C5}, ++ {0x4350, 0x073CF143}, ++ {0x4354, 0x071431C3}, ++ {0x4358, 0x0F3CF1C5}, ++ {0x435C, 0x0F3CF3CF}, ++ {0x4360, 0x0F3CF3CF}, ++ {0x4364, 0x0F3CF3CF}, ++ {0x4368, 0x0F3CF3CF}, ++ {0x436C, 0x090C91CF}, ++ {0x4370, 0x11243143}, ++ {0x4374, 0x9777A777}, ++ {0x4378, 0xBB7BAC95}, ++ {0x437C, 0xB667B889}, ++ {0x4380, 0x7B9B8899}, ++ {0x4384, 0x7A5567C8}, ++ {0x4388, 0x2278CCCC}, ++ {0x438C, 0x7C222222}, ++ {0x4390, 0x0000069B}, ++ {0x4394, 0x001CCCCC}, ++ {0x4398, 0x00000000}, ++ {0x439C, 0x00000008}, ++ {0x49A4, 0x00000000}, ++ {0x43A0, 0x00000000}, ++ {0x43A4, 0x00000000}, ++ {0x43A8, 0x00000000}, ++ {0x43AC, 0x10000800}, ++ {0x43B0, 0x00401802}, ++ {0x43B4, 0x00061004}, ++ {0x43B8, 0x000024D8}, ++ {0x43BC, 0x00000000}, ++ {0x43C0, 0x10000020}, ++ {0x43C4, 0x20000200}, ++ {0x43C8, 0x00000000}, ++ {0x43CC, 0x04000000}, ++ {0x43D0, 0x44000100}, ++ {0x43D4, 0x60804060}, ++ {0x43D8, 0x44204210}, ++ {0x43DC, 0x82108082}, ++ {0x43E0, 0x82108402}, ++ {0x43E4, 0xC8082108}, ++ {0x43E8, 0xC8202084}, ++ {0x43EC, 0x44208208}, ++ {0x43F0, 0x84108204}, ++ {0x43F4, 0xD0108104}, ++ {0x43F8, 0xF8210108}, ++ {0x43FC, 0x6431E930}, ++ {0x4400, 0x02109468}, ++ {0x4404, 0x10C61C22}, ++ {0x4408, 0x02109469}, ++ {0x440C, 0x10C61C22}, ++ {0x4410, 0x00041049}, ++ {0x4414, 0x00000000}, ++ {0x4418, 0x00000000}, ++ {0x441C, 0x6C000000}, ++ {0x4420, 0xB0200020}, ++ {0x4424, 0x00001FF0}, ++ {0x4428, 0x00000000}, ++ {0x442C, 0x00000000}, ++ {0x4430, 0x00000000}, ++ {0x4434, 0x00000000}, ++ {0x4438, 0x65F962F8}, ++ {0x443C, 0x280668A0}, ++ {0x4440, 0x64100820}, ++ {0x4444, 0x4A146304}, ++ {0x4448, 0x0C59008F}, ++ {0x444C, 0x6E30498A}, ++ {0x4450, 0x656E371B}, ++ {0x4454, 0x00000F52}, ++ {0x4458, 0x00000000}, ++ {0x445C, 0x4801442E}, ++ {0x4460, 0x0041A0B8}, ++ {0x4464, 0x00000000}, ++ {0x4468, 0x00000000}, ++ {0x446C, 0x00000000}, ++ {0x4470, 0x00000000}, ++ {0x4474, 0x00000000}, ++ {0x4478, 0x00000000}, ++ {0x447C, 0x00000000}, ++ {0x4480, 0x2A0A6040}, ++ {0x4484, 0x0A0A6829}, ++ {0x4488, 0x00000004}, ++ {0x448C, 0x00000000}, ++ {0x4490, 0x80000000}, ++ {0x4494, 0x10000000}, ++ {0x4498, 0xA0000000}, ++ {0x449C, 0x0000001E}, ++ {0x44A0, 0x02B29397}, ++ {0x44A4, 0x00000400}, ++ {0x44A8, 0x00000001}, ++ {0x44AC, 0x00000000}, ++ {0x44B0, 0x00000000}, ++ {0x44B4, 0x00000000}, ++ {0x44B8, 0x00000000}, ++ {0x44BC, 0x00000000}, ++ {0x44C0, 0x00000000}, ++ {0x44C4, 0x00000000}, ++ {0x44C8, 0x00000000}, ++ {0x44CC, 0x00000000}, ++ {0x44D0, 0x00000000}, ++ {0x44D4, 0x00000000}, ++ {0x44D8, 0x00000000}, ++ {0x44DC, 0x00000000}, ++ {0x44E0, 0x00000000}, ++ {0x44E4, 0x00000000}, ++ {0x44E8, 0x00000000}, ++ {0x44EC, 0x00000000}, ++ {0x44F0, 0x00000000}, ++ {0x44F4, 0x00000000}, ++ {0x44F8, 0x00000000}, ++ {0x44FC, 0x00000000}, ++ {0x4500, 0x00000000}, ++ {0x4504, 0x00000000}, ++ {0x4508, 0x00000000}, ++ {0x450C, 0x00000000}, ++ {0x4510, 0x00000000}, ++ {0x4514, 0x00000000}, ++ {0x4518, 0x00000000}, ++ {0x451C, 0x00000000}, ++ {0x4520, 0x00000000}, ++ {0x4524, 0x00000000}, ++ {0x4528, 0x00000000}, ++ {0x452C, 0x00000000}, ++ {0x4530, 0x4EA20631}, ++ {0x4534, 0x000005C8}, ++ {0x4538, 0x000000FF}, ++ {0x453C, 0x00000000}, ++ {0x4540, 0x00000000}, ++ {0x4544, 0x00000000}, ++ {0x4548, 0x00000000}, ++ {0x454C, 0x00000000}, ++ {0x4550, 0x00000000}, ++ {0x4554, 0x00000000}, ++ {0x4558, 0x00000000}, ++ {0x455C, 0x00000000}, ++ {0x4560, 0x4060001A}, ++ {0x4564, 0x40000000}, ++ {0x4568, 0x00000000}, ++ {0x456C, 0x20000000}, ++ {0x4570, 0x04800406}, ++ {0x4574, 0x00022270}, ++ {0x4578, 0x0002024B}, ++ {0x457C, 0x00200000}, ++ {0x4580, 0x00009B40}, ++ {0x4584, 0x00000000}, ++ {0x4588, 0x00000063}, ++ {0x458C, 0x30000000}, ++ {0x4590, 0x00000000}, ++ {0x4594, 0x05000000}, ++ {0x4598, 0x00000001}, ++ {0x459C, 0x0003FE00}, ++ {0x45A0, 0x00000000}, ++ {0x45A4, 0x00000000}, ++ {0x45A8, 0xC00001C0}, ++ {0x45AC, 0x78028000}, ++ {0x45B0, 0x80000048}, ++ {0x45B4, 0x01C90800}, ++ {0x45B8, 0x00000002}, ++ {0x45BC, 0x06748790}, ++ {0x45C0, 0x80000000}, ++ {0x45C4, 0x00000000}, ++ {0x45C8, 0x00000000}, ++ {0x45CC, 0x00558670}, ++ {0x45D0, 0x002883F0}, ++ {0x45D4, 0x00090120}, ++ {0x45D8, 0x00000000}, ++ {0x45DC, 0xA3A6D3C4}, ++ {0x49A8, 0xAB27B126}, ++ {0x49AC, 0x00006778}, ++ {0x49FC, 0x000001B5}, ++ {0x49B0, 0x11110F0A}, ++ {0x49B4, 0x00000007}, ++ {0x49B8, 0x0000000A}, ++ {0x49BC, 0x0058BC3F}, ++ {0x49C0, 0x00000003}, ++ {0x49C4, 0x000003D9}, ++ {0x49C8, 0x002B1CB0}, ++ {0x4A00, 0x00000000}, ++ {0x49CC, 0x00000001}, ++ {0x49D0, 0x00000010}, ++ {0x49D4, 0x00000001}, ++ {0x49D8, 0x85298FBF}, ++ {0x49DC, 0x18A5296E}, ++ {0x49E0, 0x18C6298C}, ++ {0x49E4, 0x0A739CA7}, ++ {0x49E8, 0x001A50E7}, ++ {0x49EC, 0x00000001}, ++ {0x49F0, 0x00005924}, ++ {0x49F4, 0x0003AAA6}, ++ {0x49F8, 0x0000C4C3}, ++ {0x45E0, 0x00000000}, ++ {0x45E4, 0x00000000}, ++ {0x45E8, 0x00E2E100}, ++ {0x45EC, 0xCB00B6B6}, ++ {0x45F0, 0x59100FCA}, ++ {0x45F4, 0x08882550}, ++ {0x45F8, 0x08CC2660}, ++ {0x45FC, 0x09102660}, ++ {0x4600, 0x00000154}, ++ {0x4604, 0x00000800}, ++ {0x4608, 0x31BF0400}, ++ {0x460C, 0x00E0C0A0}, ++ {0x4610, 0x30604020}, ++ {0x4614, 0x2F346D50}, ++ {0x4618, 0x2E36B6E2}, ++ {0x461C, 0x3E7EF86B}, ++ {0x4620, 0x001FC004}, ++ {0x4624, 0xA8068010}, ++ {0x4628, 0x4602CA80}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76067E8C}, ++ {0x4630, 0x8EA350E8}, ++ {0x4634, 0xB3B8D8F5}, ++ {0x4638, 0x6FFF0C06}, ++ {0x463C, 0xB8FA4435}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76067E8C}, ++ {0x4630, 0x8EA350E8}, ++ {0x4634, 0xB3B8D8F5}, ++ {0x4638, 0x6FFF0C06}, ++ {0x463C, 0xB8FA4435}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x462C, 0x76078E8C}, ++ {0x4630, 0x8EDB50F6}, ++ {0x4634, 0xB5B8DD75}, ++ {0x4638, 0x6FFF4C06}, ++ {0x463C, 0xB8FA4434}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0xA0000000, 0x00000000}, ++ {0x462C, 0x76067E8C}, ++ {0x4630, 0x8EA350E8}, ++ {0x4634, 0xB3B8D8F5}, ++ {0x4638, 0x6FFF0C06}, ++ {0x463C, 0xB8FA4435}, ++ {0x4640, 0xB7C4FEF8}, ++ {0x4644, 0x2A72AD07}, ++ {0xB0000000, 0x00000000}, ++ {0x4648, 0x64204FB2}, ++ {0x464C, 0x4C823404}, ++ {0x4650, 0x9084C800}, ++ {0x4654, 0x9889314F}, ++ {0x4658, 0x5ECC3FF4}, ++ {0x465C, 0xFEECAECE}, ++ {0x4660, 0x47806638}, ++ {0x4664, 0x0F5AF843}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x56452994}, ++ {0x466C, 0x54D89ADB}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x56452994}, ++ {0x466C, 0x54D89ADB}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4668, 0x55452994}, ++ {0x466C, 0x56D89ADB}, ++ {0xA0000000, 0x00000000}, ++ {0x4668, 0x56452994}, ++ {0x466C, 0x54D89ADB}, ++ {0xB0000000, 0x00000000}, ++ {0x4670, 0xE8DF38D8}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x002ACC30}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x002ACC30}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4674, 0x0028CC30}, ++ {0xA0000000, 0x00000000}, ++ {0x4674, 0x002ACC30}, ++ {0xB0000000, 0x00000000}, ++ {0x4678, 0x00000000}, ++ {0x467C, 0x00000000}, ++ {0x4680, 0x00000219}, ++ {0x4684, 0x00000000}, ++ {0x4688, 0x00000000}, ++ {0x468C, 0x00000001}, ++ {0x4690, 0x00000001}, ++ {0x4694, 0x00000000}, ++ {0x4698, 0x00000000}, ++ {0x469C, 0x00000151}, ++ {0x46A0, 0x00000498}, ++ {0x46A4, 0x00000498}, ++ {0x46A8, 0x00000000}, ++ {0x46AC, 0x00000000}, ++ {0x46B0, 0x00001146}, ++ {0x46B4, 0x00000000}, ++ {0x46B8, 0x00000000}, ++ {0x46BC, 0x00E2E100}, ++ {0x46C0, 0xCB00B6B6}, ++ {0x46C4, 0x59100FCA}, ++ {0x46C8, 0x08882550}, ++ {0x46CC, 0x08CC2660}, ++ {0x46D0, 0x09102660}, ++ {0x46D4, 0x00000154}, ++ {0x46D8, 0x00000800}, ++ {0x46DC, 0x31BF0400}, ++ {0x46E0, 0x00E0C0A0}, ++ {0x46E4, 0x30604020}, ++ {0x46E8, 0x4F346D50}, ++ {0x46EC, 0x2E36B6E2}, ++ {0x46F0, 0x3E7EF86B}, ++ {0x46F4, 0x001FC004}, ++ {0x46F8, 0xA8068010}, ++ {0x46FC, 0x4602CA80}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x7806FECC}, ++ {0x4704, 0x8EC360F1}, ++ {0x4708, 0xB4C4DA7A}, ++ {0x470C, 0x72FF2CC6}, ++ {0x4710, 0xB8FA4439}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x7806FECC}, ++ {0x4704, 0x8EC360F1}, ++ {0x4708, 0xB4C4DA7A}, ++ {0x470C, 0x72FF2CC6}, ++ {0x4710, 0xB8FA4439}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4700, 0x78078ECC}, ++ {0x4704, 0x8EDB60F6}, ++ {0x4708, 0xB5C4DD7A}, ++ {0x470C, 0x72FF4CC6}, ++ {0x4710, 0xB8FA4434}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0xA0000000, 0x00000000}, ++ {0x4700, 0x7806FECC}, ++ {0x4704, 0x8EC360F1}, ++ {0x4708, 0xB4C4DA7A}, ++ {0x470C, 0x72FF2CC6}, ++ {0x4710, 0xB8FA4439}, ++ {0x4714, 0xB7C4FEF8}, ++ {0x4718, 0x2A72AD09}, ++ {0xB0000000, 0x00000000}, ++ {0x471C, 0x64204FB2}, ++ {0x4720, 0x4C823404}, ++ {0x4724, 0x9084C800}, ++ {0x4728, 0x9889314F}, ++ {0x472C, 0x5ECC3FF4}, ++ {0x4730, 0xFEECAECE}, ++ {0x4734, 0x47806638}, ++ {0x4738, 0x0F4A7843}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x56452994}, ++ {0x4740, 0x54D89ADB}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x56452994}, ++ {0x4740, 0x54D89ADB}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x473C, 0x55452994}, ++ {0x4740, 0x56D89ADB}, ++ {0xA0000000, 0x00000000}, ++ {0x473C, 0x56452994}, ++ {0x4740, 0x54D89ADB}, ++ {0xB0000000, 0x00000000}, ++ {0x4744, 0xE8DF38D8}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x002ACC30}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x002ACC30}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x4748, 0x0028CC30}, ++ {0xA0000000, 0x00000000}, ++ {0x4748, 0x002ACC30}, ++ {0xB0000000, 0x00000000}, ++ {0x474C, 0x00000000}, ++ {0x4750, 0x00000000}, ++ {0x4754, 0x00000219}, ++ {0x4758, 0x00000000}, ++ {0x475C, 0x00000000}, ++ {0x4760, 0x00000001}, ++ {0x4764, 0x00000001}, ++ {0x4768, 0x00000000}, ++ {0x476C, 0x00000000}, ++ {0x4770, 0x00000151}, ++ {0x4774, 0x00000498}, ++ {0x4778, 0x00000498}, ++ {0x477C, 0x00000000}, ++ {0x4780, 0x00000000}, ++ {0x4784, 0x00001147}, ++ {0x4788, 0x00000000}, ++ {0x478C, 0xA32103FE}, ++ {0x4790, 0x320A7B28}, ++ {0x4794, 0xC6A7B14F}, ++ {0x4798, 0x000006D7}, ++ {0x479C, 0x009B902A}, ++ {0x47A0, 0x009B902A}, ++ {0x47A4, 0x98682C18}, ++ {0x47A8, 0x6308C4C1}, ++ {0x47AC, 0x6248C631}, ++ {0x47B0, 0x922A8253}, ++ {0x47B4, 0x00000005}, ++ {0x47B8, 0x00001759}, ++ {0x47BC, 0x4B802000}, ++ {0x47C0, 0x831408BE}, ++ {0x47C4, 0x9ABBCACB}, ++ {0x47C8, 0x56767578}, ++ {0x47CC, 0xBBCCBBB3}, ++ {0x47D0, 0x57889989}, ++ {0x47D4, 0x00000F45}, ++ {0x47D8, 0x27039CE9}, ++ {0x47DC, 0x31413432}, ++ {0x47E0, 0x26058342}, ++ {0x47E4, 0x00000006}, ++ {0x47E8, 0x00000005}, ++ {0x47EC, 0x00000005}, ++ {0x47F0, 0xC7013016}, ++ {0x47F4, 0x84413016}, ++ {0x47F8, 0x84413016}, ++ {0x47FC, 0x8C413016}, ++ {0x4800, 0x8C40B028}, ++ {0x4804, 0x3140B028}, ++ {0x4808, 0x2940B028}, ++ {0x480C, 0x8440B028}, ++ {0x4810, 0x2318C610}, ++ {0x4814, 0x45334753}, ++ {0x4818, 0x236A6A88}, ++ {0x481C, 0x576DF814}, ++ {0x4820, 0xA08877AC}, ++ {0x4824, 0x0000087A}, ++ {0x4828, 0xBCEB4A14}, ++ {0x482C, 0x000A3A4A}, ++ {0x4830, 0xBCEB4A14}, ++ {0x4834, 0x000A3A4A}, ++ {0x4838, 0xBCBDBD85}, ++ {0x483C, 0x0CABB99A}, ++ {0x4840, 0x38384242}, ++ {0x4844, 0x8086102E}, ++ {0x4848, 0xCA24C82A}, ++ {0x484C, 0x00008A62}, ++ {0x4850, 0x00000008}, ++ {0x4854, 0x009B902A}, ++ {0x4858, 0x009B902A}, ++ {0x485C, 0x98682C18}, ++ {0x4860, 0x6308C4C1}, ++ {0x4864, 0x6248C631}, ++ {0x4868, 0x922A8253}, ++ {0x486C, 0x00000005}, ++ {0x4870, 0x00001759}, ++ {0x4874, 0x4B802000}, ++ {0x4878, 0x831408BE}, ++ {0x487C, 0x9898A8BB}, ++ {0x4880, 0x54535368}, ++ {0x4884, 0x999999B3}, ++ {0x4888, 0x35555589}, ++ {0x488C, 0x00000745}, ++ {0x4890, 0x27039CE9}, ++ {0x4894, 0x31413432}, ++ {0x4898, 0x26058342}, ++ {0x489C, 0x00000006}, ++ {0x48A0, 0x00000005}, ++ {0x48A4, 0x00000005}, ++ {0x48A8, 0xC7013016}, ++ {0x48AC, 0x84413016}, ++ {0x48B0, 0x84413016}, ++ {0x48B4, 0x8C413016}, ++ {0x48B8, 0x8C40B028}, ++ {0x48BC, 0x3140B028}, ++ {0x48C0, 0x2940B028}, ++ {0x48C4, 0x8440B028}, ++ {0x48C8, 0x2318C610}, ++ {0x48CC, 0x45334753}, ++ {0x48D0, 0x236A6A88}, ++ {0x48D4, 0x576DF814}, ++ {0x48D8, 0xA08877AC}, ++ {0x48DC, 0x0000007A}, ++ {0x48E0, 0xBCEB4A14}, ++ {0x48E4, 0x000A3A4A}, ++ {0x48E8, 0xBCEB4A14}, ++ {0x48EC, 0x000A3A4A}, ++ {0x48F0, 0x9A8A8A85}, ++ {0x48F4, 0x0CA3B99A}, ++ {0x48F8, 0x38384242}, ++ {0x48FC, 0x8086102E}, ++ {0x4900, 0xCA24C82A}, ++ {0x4904, 0x00008A62}, ++ {0x4908, 0x00000008}, ++ {0x490C, 0x80040000}, ++ {0x4910, 0x80040000}, ++ {0x4914, 0xFE800000}, ++ {0x4918, 0x834C0000}, ++ {0x491C, 0x00000000}, ++ {0x4920, 0x00000000}, ++ {0x4924, 0x00000000}, ++ {0x4928, 0x00000000}, ++ {0x492C, 0x00000000}, ++ {0x4930, 0x00000000}, ++ {0x4934, 0x40000000}, ++ {0x4938, 0x00000000}, ++ {0x493C, 0x00000000}, ++ {0x4940, 0x00000000}, ++ {0x4944, 0x00000000}, ++ {0x4948, 0x04065800}, ++ {0x494C, 0x32004080}, ++ {0x4950, 0x0E1E3E05}, ++ {0x4954, 0x0A163068}, ++ {0x4958, 0x00206040}, ++ {0x495C, 0x02020202}, ++ {0x4960, 0x00A16020}, ++ {0x4964, 0x031F4284}, ++ {0x4968, 0x00A10285}, ++ {0x496C, 0x00000005}, ++ {0x4970, 0x00000000}, ++ {0x4974, 0x800CD62D}, ++ {0x4978, 0x00000103}, ++ {0x497C, 0x00000000}, ++ {0x4980, 0x00000000}, ++ {0x4984, 0x00000000}, ++ {0x4988, 0x00000000}, ++ {0x498C, 0x00000000}, ++ {0x4990, 0x00000000}, ++ {0x4994, 0x00000000}, ++ {0x4998, 0x00000000}, ++ {0x499C, 0x00000000}, ++ {0x49A0, 0x00000000}, ++ {0x2404, 0x00000001}, ++ {0xC7C, 0x0000BFE0}, ++ {0x020, 0x0000F381}, ++ {0x024, 0x0000F381}, ++ {0x028, 0x0000F381}, ++ {0x02C, 0x0000F381}, ++ {0xD78, 0x00000005}, ++ {0x12CC, 0x00000CC1}, ++ {0x12D0, 0x00000000}, ++ {0x12D4, 0x00000000}, ++ {0x12D8, 0x00000040}, ++ {0x12DC, 0x4486888C}, ++ {0x12E0, 0xC43A10E1}, ++ {0x12E4, 0x30D52C68}, ++ {0x12E8, 0x02024128}, ++ {0x12EC, 0x888C272B}, ++ {0x12EC, 0x888CA72B}, ++ {0x32CC, 0x00000CC1}, ++ {0x32D0, 0x00000000}, ++ {0x32D4, 0x00000000}, ++ {0x32D8, 0x00000040}, ++ {0x32DC, 0x4486888C}, ++ {0x32E0, 0xC43A10E1}, ++ {0x32E4, 0x30D52C68}, ++ {0x32E8, 0x02024128}, ++ {0x32EC, 0x888C272B}, ++ {0x32EC, 0x888CA72B}, ++ {0x12AC, 0x12333121}, ++ {0x32AC, 0x12333121}, ++ {0x738, 0x004100CC}, ++ {0x80ff0001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0x903300ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0xC0001080}, ++ {0x7820, 0xC0001080}, ++ {0x903500ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0xC0001080}, ++ {0x7820, 0xC0001080}, ++ {0x903200ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0x903400ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0x903600ff, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0xA0000000, 0x00000000}, ++ {0x5820, 0x80001080}, ++ {0x7820, 0x80001080}, ++ {0xB0000000, 0x00000000}, ++ {0x2000, 0x18BBBF84}, ++ {0x0F0, 0x00000002}, ++ {0x0F4, 0x00000016}, ++ {0x0F8, 0x20201013}, ++}; ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_radioa_regs[] = { ++ {0xF0010000, 0x00000000}, ++ {0xF0010001, 0x00000001}, ++ {0xF0020001, 0x00000002}, ++ {0xF0030001, 0x00000003}, ++ {0xF0250001, 0x00000004}, ++ {0xF0260001, 0x00000005}, ++ {0xF0320001, 0x00000006}, ++ {0xF0330001, 0x00000007}, ++ {0xF0340001, 0x00000008}, ++ {0xF0350001, 0x00000009}, ++ {0xF0360001, 0x0000000A}, ++ {0xF0010002, 0x0000000B}, ++ {0xF0020002, 0x0000000C}, ++ {0xF0030002, 0x0000000D}, ++ {0xF0250002, 0x0000000E}, ++ {0xF0260002, 0x0000000F}, ++ {0xF0320002, 0x00000010}, ++ {0xF0330002, 0x00000011}, ++ {0xF0340002, 0x00000012}, ++ {0xF0350002, 0x00000013}, ++ {0xF0360002, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x000, 0x00030000}, ++ {0x018, 0x00011124}, ++ {0x000, 0x00033C00}, ++ {0x01A, 0x00040004}, ++ {0x0FE, 0x00000000}, ++ {0x055, 0x00080000}, ++ {0x056, 0x0008FFF0}, ++ {0x057, 0x0000C485}, ++ {0x058, 0x000A4164}, ++ {0x059, 0x00010000}, ++ {0x05A, 0x00060000}, ++ {0x05B, 0x0000A000}, ++ {0x05C, 0x00000000}, ++ {0x05D, 0x0001C013}, ++ {0x05E, 0x00000000}, ++ {0x05F, 0x00001FF0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0xA0000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0xB0000000, 0x00000000}, ++ {0x061, 0x0009F338}, ++ {0x062, 0x0009233A}, ++ {0x063, 0x000D6002}, ++ {0x064, 0x000A0CB0}, ++ {0x065, 0x00030EFE}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0xA0000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0xB0000000, 0x00000000}, ++ {0x068, 0x00000000}, ++ {0x069, 0x00030F0A}, ++ {0x06A, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0009BC24}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0xA0000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0009BC24}, ++ {0xB0000000, 0x00000000}, ++ {0x0D3, 0x00000143}, ++ {0x043, 0x00005000}, ++ {0x0DD, 0x000003A0}, ++ {0x0B0, 0x000E6700}, ++ {0x0AF, 0x0001F82E}, ++ {0x0B2, 0x000210A7}, ++ {0x0B1, 0x00065FFF}, ++ {0x0BB, 0x000F7A00}, ++ {0x0B3, 0x00013F7A}, ++ {0x0D4, 0x0000000E}, ++ {0x0B7, 0x00001E0C}, ++ {0x0A0, 0x0000004F}, ++ {0x0B4, 0x0007C03E}, ++ {0x0B5, 0x0007E301}, ++ {0x0B6, 0x00080800}, ++ {0x0CA, 0x00002000}, ++ {0x0DD, 0x000003A0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0xA0000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0xB0000000, 0x00000000}, ++ {0x0A1, 0x0006F300}, ++ {0x0A2, 0x00080500}, ++ {0x0A3, 0x0008050B}, ++ {0x0A4, 0x0006DB12}, ++ {0x0A5, 0x00000000}, ++ {0x0A6, 0x00000000}, ++ {0x0A7, 0x00000000}, ++ {0x0A8, 0x00000000}, ++ {0x0A9, 0x00000000}, ++ {0x0AA, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E1333}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E7333}, ++ {0x033, 0x00000002}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000FA000}, ++ {0x033, 0x00000003}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000FA400}, ++ {0x033, 0x00000004}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000F5000}, ++ {0x033, 0x00000005}, ++ {0x03E, 0x00004001}, ++ {0x03F, 0x00029400}, ++ {0x033, 0x00000006}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00041999}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00034444}, ++ {0x033, 0x00000008}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x0004D555}, ++ {0x033, 0x00000009}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000A}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000B}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x0008C555}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00081EB8}, ++ {0x033, 0x0000000D}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00071EB8}, ++ {0x033, 0x0000000E}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00090000}, ++ {0x033, 0x0000000F}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000010}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000011}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x000DB999}, ++ {0x0ED, 0x00000000}, ++ {0x0ED, 0x00002000}, ++ {0x033, 0x00000002}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x033, 0x00000006}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x0ED, 0x00000000}, ++ {0x018, 0x00001001}, ++ {0x002, 0x0000000D}, ++ {0x0EE, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0xA0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x08F, 0x000D0F7A}, ++ {0x08C, 0x00084584}, ++ {0x0EF, 0x00004000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00001000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000015}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000017}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00008000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x0000007C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000100}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x00003338}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000040}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000004BA}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000010}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000080}, ++ {0x033, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00023458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00023858}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x03E, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00023758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002E758}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002E658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00027758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C758}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000E}, ++ {0x03F, 0x0002F658}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EE, 0x00002000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000042}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000047}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000053}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000054}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000059}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000065}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000066}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000077}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000078}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x0EE, 0x00004000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003BEF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00003BE9}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00003BE3}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00003BDD}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003BD7}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x00003BD1}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000035}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000036}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000037}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000038}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000039}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x0000003A}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x0000003B}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000042}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000047}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000053}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000054}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000059}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000065}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000066}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000006B}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000077}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000078}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000007D}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000088}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000089}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000008A}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000008B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008C}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000008D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008E}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000008F}, ++ {0x03F, 0x00000807}, ++ {0x0EE, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00020F3C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x000305BC}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x03C, 0x00000020}, ++ {0x03D, 0x00000078}, ++ {0x03E, 0x00080000}, ++ {0x03F, 0x00001999}, ++ {0x0EC, 0x00000000}, ++ {0x02F, 0x0002260D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000002}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000002}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000002}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000400}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000200}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000018}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x06D, 0x00000C31}, ++ {0x0EF, 0x00020000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000005FF}, ++ {0x0EF, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00022020}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0xA0000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0xB0000000, 0x00000000}, ++ {0x002, 0x00000000}, ++ {0x067, 0x00000052}, ++ ++}; ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_radiob_regs[] = { ++ {0xF0010000, 0x00000000}, ++ {0xF0010001, 0x00000001}, ++ {0xF0020001, 0x00000002}, ++ {0xF0030001, 0x00000003}, ++ {0xF0250001, 0x00000004}, ++ {0xF0260001, 0x00000005}, ++ {0xF0320001, 0x00000006}, ++ {0xF0330001, 0x00000007}, ++ {0xF0340001, 0x00000008}, ++ {0xF0350001, 0x00000009}, ++ {0xF0360001, 0x0000000A}, ++ {0xF0010002, 0x0000000B}, ++ {0xF0020002, 0x0000000C}, ++ {0xF0030002, 0x0000000D}, ++ {0xF0250002, 0x0000000E}, ++ {0xF0260002, 0x0000000F}, ++ {0xF0320002, 0x00000010}, ++ {0xF0330002, 0x00000011}, ++ {0xF0340002, 0x00000012}, ++ {0xF0350002, 0x00000013}, ++ {0xF0360002, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x005, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x005, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x000, 0x00030000}, ++ {0x018, 0x00011124}, ++ {0x000, 0x00033C00}, ++ {0x01A, 0x00040004}, ++ {0x0FE, 0x00000000}, ++ {0x055, 0x00080000}, ++ {0x056, 0x0008FFF0}, ++ {0x057, 0x0000C485}, ++ {0x058, 0x000A4164}, ++ {0x059, 0x00010000}, ++ {0x05A, 0x00060000}, ++ {0x05B, 0x0000A000}, ++ {0x05C, 0x00000000}, ++ {0x05D, 0x0001C013}, ++ {0x05E, 0x00000000}, ++ {0x05F, 0x00001FF0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x060, 0x00011008}, ++ {0xA0000000, 0x00000000}, ++ {0x060, 0x00011000}, ++ {0xB0000000, 0x00000000}, ++ {0x061, 0x0009F338}, ++ {0x062, 0x0009233A}, ++ {0x063, 0x000D6002}, ++ {0x064, 0x000A0CB0}, ++ {0x065, 0x00030EFE}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x066, 0x00020000}, ++ {0xA0000000, 0x00000000}, ++ {0x066, 0x00010000}, ++ {0xB0000000, 0x00000000}, ++ {0x068, 0x00000000}, ++ {0x069, 0x00030F0A}, ++ {0x06A, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0007BC24}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x051, 0x000BD267}, ++ {0x052, 0x00091345}, ++ {0x053, 0x000B0081}, ++ {0x054, 0x0007BCA4}, ++ {0xA0000000, 0x00000000}, ++ {0x051, 0x000AD6A4}, ++ {0x052, 0x00091345}, ++ {0x053, 0x00080081}, ++ {0x054, 0x0007BC24}, ++ {0xB0000000, 0x00000000}, ++ {0x0D3, 0x00000143}, ++ {0x043, 0x00005000}, ++ {0x0DD, 0x000003A0}, ++ {0x0B0, 0x000E6700}, ++ {0x0AF, 0x0001F82E}, ++ {0x0B2, 0x000210A7}, ++ {0x0B1, 0x00065FFF}, ++ {0x0BB, 0x000F7A00}, ++ {0x0B3, 0x00013F7A}, ++ {0x0D4, 0x0000000E}, ++ {0x0B7, 0x00001E0C}, ++ {0x0A0, 0x0000004F}, ++ {0x0B4, 0x0007C03E}, ++ {0x0B5, 0x0007E301}, ++ {0x0B6, 0x00080800}, ++ {0x0CA, 0x00002000}, ++ {0x0DD, 0x000003A0}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0CC, 0x000E0000}, ++ {0xA0000000, 0x00000000}, ++ {0x0CC, 0x00080000}, ++ {0xB0000000, 0x00000000}, ++ {0x0A1, 0x0006F300}, ++ {0x0A2, 0x00080500}, ++ {0x0A3, 0x0008050B}, ++ {0x0A4, 0x0006DB12}, ++ {0x0A5, 0x00000000}, ++ {0x0A6, 0x00000000}, ++ {0x0A7, 0x00000000}, ++ {0x0A8, 0x00000000}, ++ {0x0A9, 0x00000000}, ++ {0x0AA, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0A5, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0A5, 0x000B0000}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0ED, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0ED, 0x00008000}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E1333}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000E7333}, ++ {0x033, 0x00000002}, ++ {0x03E, 0x00008000}, ++ {0x03F, 0x000FA000}, ++ {0x033, 0x00000003}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000FA400}, ++ {0x033, 0x00000004}, ++ {0x03E, 0x00004000}, ++ {0x03F, 0x000F5000}, ++ {0x033, 0x00000005}, ++ {0x03E, 0x00004001}, ++ {0x03F, 0x00029400}, ++ {0x033, 0x00000006}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00041999}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x00034444}, ++ {0x033, 0x00000008}, ++ {0x03E, 0x0000AAA1}, ++ {0x03F, 0x0004D555}, ++ {0x033, 0x00000009}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000A}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x00046AAA}, ++ {0x033, 0x0000000B}, ++ {0x03E, 0x00005551}, ++ {0x03F, 0x0008C555}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00081EB8}, ++ {0x033, 0x0000000D}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00071EB8}, ++ {0x033, 0x0000000E}, ++ {0x03E, 0x0000CCC1}, ++ {0x03F, 0x00090000}, ++ {0x033, 0x0000000F}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000010}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x00088000}, ++ {0x033, 0x00000011}, ++ {0x03E, 0x00006661}, ++ {0x03F, 0x000DB999}, ++ {0x0ED, 0x00000000}, ++ {0x0ED, 0x00002000}, ++ {0x033, 0x00000002}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x033, 0x00000006}, ++ {0x03D, 0x0004A883}, ++ {0x03E, 0x00000000}, ++ {0x03F, 0x00000001}, ++ {0x0ED, 0x00000000}, ++ {0x018, 0x00001001}, ++ {0x002, 0x0000000D}, ++ {0x0EE, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000A}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000011}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000018}, ++ {0xA0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0000000B}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000012}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000019}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x08F, 0x000D0F7A}, ++ {0x08C, 0x00084584}, ++ {0x0EF, 0x00004000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004700}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000700}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000B0600}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00094600}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000500}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4500}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000400}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00038B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000D4400}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00008B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00014B00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000B00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004A00}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001A00}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00004900}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00002900}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00001000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000015}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000017}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00000015}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00000017}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00008000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000FECFC}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000BECFC}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x0003E4FC}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x0001D0FC}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x0001C3FC}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000103FC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x0000007C}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x0000007C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000100}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00003317}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003336}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003338}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003337}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00003356}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002A}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002C}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002E}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x00003338}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x00003338}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000040}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000004BA}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000004BA}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000010}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000730}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000430}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x00000CB0}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x00000870}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x00000430}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000080}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F258}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F258}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00036458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0003C458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026658}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00026458}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00028558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C358}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0002C558}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002F358}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F258}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023758}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00023558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00025558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x00024558}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000C}, ++ {0x03F, 0x0002C558}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xA0000000, 0x00000000}, ++ {0x03E, 0x0000000B}, ++ {0x03F, 0x0006F458}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EE, 0x00002000}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000166}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000163}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000068}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A5}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000053}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000070}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000067}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000064}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000061}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000058}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E5}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000055}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000E2}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000052}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000DF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000065}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000062}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000049}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000046}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000042}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000043}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000059}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000040}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000056}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000047}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000053}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000054}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000059}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000065}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000066}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000077}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000078}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000078}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000075}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000072}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F6}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001EA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001F0}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001E4}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001ED}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AC}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001AA}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000E0}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001A4}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000006C}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000069}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000066}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000063}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004E}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000057}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000060}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000004B}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000054}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005D}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000048}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000051}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000005A}, ++ {0xB0000000, 0x00000000}, ++ {0x0EE, 0x00000000}, ++ {0x0EE, 0x00004000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00003BEF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00003BE9}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x00003BE3}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x00003BDD}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x00003BD7}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x00003BD1}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00003BCB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00001BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00001BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BD1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000BD3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000BCD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000857}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000859}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000851}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000084D}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000817}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000819}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000811}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x00000028}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x00000029}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000030}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000035}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000036}, ++ {0x03F, 0x000039EE}, ++ {0x033, 0x00000037}, ++ {0x03F, 0x000039E8}, ++ {0x033, 0x00000038}, ++ {0x03F, 0x000039E2}, ++ {0x033, 0x00000039}, ++ {0x03F, 0x000039DC}, ++ {0x033, 0x0000003A}, ++ {0x03F, 0x000039D6}, ++ {0x033, 0x0000003B}, ++ {0x03F, 0x000039D0}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x03F, 0x000019D2}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D8}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x03F, 0x000009D2}, ++ {0x033, 0x00000040}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CC}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000008D9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000041}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000042}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000043}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000044}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000045}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000046}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000047}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x00000048}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000049}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000004F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000050}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000051}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000052}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000053}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000054}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000055}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000056}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000057}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000058}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x00000059}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000005A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000005F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000060}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000061}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000062}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000063}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000064}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000065}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000066}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000067}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000068}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x00000069}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006A}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000006B}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000006C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000006F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000070}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000071}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000072}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000073}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000074}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000075}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000076}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000077}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x00000078}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x00000079}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007A}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000007B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007C}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000007D}, ++ {0x03F, 0x00000807}, ++ {0x033, 0x0000007E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EE}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039EF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000007F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E8}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E9}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000080}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039E3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000081}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039DD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000082}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D6}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D7}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000083}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D0}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039D1}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000084}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CA}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000039CB}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000085}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000086}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CC}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000019CD}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000087}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D2}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000009D3}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000088}, ++ {0x03F, 0x000009CD}, ++ {0x033, 0x00000089}, ++ {0x03F, 0x000008D3}, ++ {0x033, 0x0000008A}, ++ {0x03F, 0x000008CD}, ++ {0x033, 0x0000008B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000008C7}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000853}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008C}, ++ {0x03F, 0x0000084D}, ++ {0x033, 0x0000008D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000847}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x00000813}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000008E}, ++ {0x03F, 0x0000080D}, ++ {0x033, 0x0000008F}, ++ {0x03F, 0x00000807}, ++ {0x0EE, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000007}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00020F3C}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x0000000C}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x000305BC}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0EC, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0EC, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x03C, 0x00000020}, ++ {0x03D, 0x00000078}, ++ {0x03E, 0x00080000}, ++ {0x03F, 0x00001999}, ++ {0x0EC, 0x00000000}, ++ {0x02F, 0x0002260D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x0DE, 0x00000000}, ++ {0xA0000000, 0x00000000}, ++ {0x0DE, 0x00000001}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000002}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x00000002}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x00000002}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000400}, ++ {0x033, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000001}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000002}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000003}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000004}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000005}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000006}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000007}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000008}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000009}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000000F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000010}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000011}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000012}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000013}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000014}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000015}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000016}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000017}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000018}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000019}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000001F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000020}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000021}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000022}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000023}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000024}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000025}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000026}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000027}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000017F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000013F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FB}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FA}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x0EF, 0x00000200}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000001}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000002}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000003}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000004}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000005}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000006}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000007}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000008}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000009}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000000F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000010}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000011}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000012}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000013}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000014}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000015}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000016}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000017}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000018}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000019}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001A}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001B}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001C}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001D}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001E}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x0000001F}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000020}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000021}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000022}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000023}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000024}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000025}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000026}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000027}, ++ {0x03F, 0x000001FF}, ++ {0x033, 0x00000028}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000029}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x000001FF}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x000000FF}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000002F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000030}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000031}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000032}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000033}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000034}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000035}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000036}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000037}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000038}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x00000039}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003A}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003B}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003C}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003D}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003E}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x033, 0x0000003F}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003B}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xA0000000, 0x00000000}, ++ {0x03F, 0x0000003F}, ++ {0xB0000000, 0x00000000}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06E, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06E, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x06F, 0x00067A7C}, ++ {0xA0000000, 0x00000000}, ++ {0x06F, 0x00077A7C}, ++ {0xB0000000, 0x00000000}, ++ {0x06D, 0x00000C31}, ++ {0x0EF, 0x00020000}, ++ {0x033, 0x00000000}, ++ {0x03F, 0x000005FF}, ++ {0x0EF, 0x00000000}, ++ {0x0A0, 0x00000043}, ++ {0x005, 0x00000001}, ++ {0x0EF, 0x00080000}, ++ {0x033, 0x00000001}, ++ {0x03E, 0x00000001}, ++ {0x03F, 0x00022020}, ++ {0x0EF, 0x00000000}, ++ {0x80010000, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90010001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360001, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90010002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90020002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90030002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90250002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90260002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0x90320002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90330002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90340002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90350002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0x90360002, 0x00000000}, {0x40000000, 0x00000000}, ++ {0x087, 0x0000042F}, ++ {0xA0000000, 0x00000000}, ++ {0x087, 0x00000427}, ++ {0xB0000000, 0x00000000}, ++ {0x002, 0x00000000}, ++ {0x067, 0x00000052}, ++ ++}; ++ ++static const struct rtw89_reg2_def rtw89_8852a_phy_nctl_regs[] = { ++ {0x8000, 0x00000008}, ++ {0x8008, 0x00000000}, ++ {0x8004, 0xf0862966}, ++ {0x800c, 0x78000000}, ++ {0x8010, 0x88015000}, ++ {0x8014, 0x80010100}, ++ {0x8018, 0x10010100}, ++ {0x801c, 0xa210bc00}, ++ {0x8020, 0x000403e0}, ++ {0x8024, 0x00072160}, ++ {0x8028, 0x00180e00}, ++ {0x8030, 0x400000c0}, ++ {0x8034, 0x56000800}, ++ {0x8038, 0x00000009}, ++ {0x803c, 0x00000008}, ++ {0x8040, 0x00000046}, ++ {0x8044, 0x0010001f}, ++ {0x8048, 0xf0000003}, ++ {0x804c, 0x62ac6162}, ++ {0x8050, 0xf2acf162}, ++ {0x8054, 0x62ac6162}, ++ {0x8058, 0xf2acf162}, ++ {0x805c, 0x150c0b02}, ++ {0x8060, 0x150c0b02}, ++ {0x8064, 0x2aa00047}, ++ {0x8074, 0x80000000}, ++ {0x807c, 0x000000ee}, ++ {0x8088, 0x80000000}, ++ {0x8098, 0x0000ff00}, ++ {0x809c, 0x0000001f}, ++ {0x80a0, 0x00010300}, ++ {0x80b0, 0x00000000}, ++ {0x80d0, 0x00000000}, ++ {0x8114, 0x00000000}, ++ {0x8120, 0x10010000}, ++ {0x8124, 0x00000000}, ++ {0x812c, 0x0000c000}, ++ {0x8138, 0x40000002}, ++ {0x813c, 0x40000002}, ++ {0x8140, 0x00000000}, ++ {0x8144, 0x0b040b03}, ++ {0x8148, 0x0b040b04}, ++ {0x814c, 0x0b040b03}, ++ {0x8150, 0x00000000}, ++ {0x8158, 0xffffffff}, ++ {0x815c, 0xffffffff}, ++ {0x8160, 0xffffffff}, ++ {0x8164, 0xffffffff}, ++ {0x8168, 0xffffffff}, ++ {0x816c, 0x1fffffff}, ++ {0x81ac, 0x003f1a00}, ++ {0x81b0, 0x003f1a00}, ++ {0x81bc, 0x005b5b5b}, ++ {0x81c0, 0x005b5b5b}, ++ {0x81b4, 0x00600060}, ++ {0x81b8, 0x00600060}, ++ {0x81cc, 0x00000000}, ++ {0x81dc, 0x00000002}, ++ {0x8214, 0x00000000}, ++ {0x8220, 0x10010000}, ++ {0x8224, 0x00000000}, ++ {0x822c, 0x0000d000}, ++ {0x8238, 0x40000002}, ++ {0x823c, 0x40000002}, ++ {0x8240, 0x00000000}, ++ {0x8244, 0x0b040b03}, ++ {0x8248, 0x0b040b03}, ++ {0x824c, 0x0b030b03}, ++ {0x8250, 0x00000000}, ++ {0x8258, 0xffffffff}, ++ {0x825c, 0xffffffff}, ++ {0x8260, 0xffffffff}, ++ {0x8264, 0xffffffff}, ++ {0x8268, 0xffffffff}, ++ {0x826c, 0x1fffffff}, ++ {0x82ac, 0x003f1a00}, ++ {0x82b0, 0x003f1a00}, ++ {0x82bc, 0x005b5b5b}, ++ {0x82c0, 0x005b5b5b}, ++ {0x82b4, 0x00600060}, ++ {0x82b8, 0x00600060}, ++ {0x82cc, 0x00000000}, ++ {0x82dc, 0x00000002}, ++ {0x81d8, 0x00000001}, ++ {0x82d8, 0x00000001}, ++ {0x8d00, 0x00000000}, ++ {0x8d04, 0x00000000}, ++ {0x8d08, 0x00000000}, ++ {0x8d0c, 0x00000000}, ++ {0x8d10, 0x00000000}, ++ {0x8d14, 0x00000000}, ++ {0x8d18, 0x00000000}, ++ {0x8d1c, 0x00000000}, ++ {0x8d20, 0x00000000}, ++ {0x8d24, 0x00000000}, ++ {0x8d28, 0x00000000}, ++ {0x8d2c, 0x00000000}, ++ {0x8d30, 0x00000000}, ++ {0x8d34, 0x00000000}, ++ {0x8d38, 0x00000000}, ++ {0x8d3c, 0x00000000}, ++ {0x8d40, 0x00000000}, ++ {0x8d44, 0x00000000}, ++ {0x8d48, 0x00000000}, ++ {0x8d4c, 0x00000000}, ++ {0x8d50, 0x00000000}, ++ {0x8d54, 0x00000000}, ++ {0x8d58, 0x00000000}, ++ {0x8d5c, 0x00000000}, ++ {0x8d60, 0x00000000}, ++ {0x8d64, 0x00000000}, ++ {0x8d68, 0x00000000}, ++ {0x8d6c, 0x00000000}, ++ {0x8d70, 0x00000000}, ++ {0x8d74, 0x00000000}, ++ {0x8d78, 0x00000000}, ++ {0x8d7c, 0x00000000}, ++ {0x8d80, 0x00000000}, ++ {0x8d84, 0x00000000}, ++ {0x8d88, 0x00000000}, ++ {0x8d8c, 0x00000000}, ++ {0x8d90, 0x00000000}, ++ {0x8d94, 0x00000000}, ++ {0x8d98, 0x00000000}, ++ {0x8d9c, 0x00000000}, ++ {0x8da0, 0x00000000}, ++ {0x8da4, 0x00000000}, ++ {0x8da8, 0x00000000}, ++ {0x8dac, 0x00000000}, ++ {0x8db0, 0x00000000}, ++ {0x8db4, 0x00000000}, ++ {0x8db8, 0x00000000}, ++ {0x8dbc, 0x00000000}, ++ {0x8dc0, 0x00000000}, ++ {0x8dc4, 0x00000000}, ++ {0x8dc8, 0x00000000}, ++ {0x8dcc, 0x00000000}, ++ {0x8dd0, 0x00000000}, ++ {0x8dd4, 0x00000000}, ++ {0x8dd8, 0x00000000}, ++ {0x8ddc, 0x00000000}, ++ {0x8de0, 0x00000000}, ++ {0x8de4, 0x00000000}, ++ {0x8de8, 0x00000000}, ++ {0x8dec, 0x00000000}, ++ {0x8df0, 0x00000000}, ++ {0x8df4, 0x00000000}, ++ {0x8df8, 0x00000000}, ++ {0x8dfc, 0x00000000}, ++ {0x8e00, 0x00000000}, ++ {0x8e04, 0x00000000}, ++ {0x8e08, 0x00000000}, ++ {0x8e0c, 0x00000000}, ++ {0x8e10, 0x00000000}, ++ {0x8e14, 0x00000000}, ++ {0x8e18, 0x00000000}, ++ {0x8e1c, 0x00000000}, ++ {0x8e20, 0x00000000}, ++ {0x8e24, 0x00000000}, ++ {0x8e28, 0x00000000}, ++ {0x8e2c, 0x00000000}, ++ {0x8e30, 0x00000000}, ++ {0x8e34, 0x00000000}, ++ {0x8e38, 0x00000000}, ++ {0x8e3c, 0x00000000}, ++ {0x8e40, 0x00000000}, ++ {0x8e44, 0x00000000}, ++ {0x8e48, 0x00000000}, ++ {0x8e4c, 0x00000000}, ++ {0x8e50, 0x00000000}, ++ {0x8e54, 0x00000000}, ++ {0x8e58, 0x00000000}, ++ {0x8e5c, 0x00000000}, ++ {0x8e60, 0x00000000}, ++ {0x8e64, 0x00000000}, ++ {0x8e68, 0x00000000}, ++ {0x8e6c, 0x00000000}, ++ {0x8e70, 0x00000000}, ++ {0x8e74, 0x00000000}, ++ {0x8e78, 0x00000000}, ++ {0x8e7c, 0x00000000}, ++ {0x8e80, 0x00000000}, ++ {0x8e84, 0x00000000}, ++ {0x8e88, 0x00000000}, ++ {0x8e8c, 0x00000000}, ++ {0x8e90, 0x00000000}, ++ {0x8e94, 0x00000000}, ++ {0x8e98, 0x00000000}, ++ {0x8e9c, 0x00000000}, ++ {0x8ea0, 0x00000000}, ++ {0x8ea4, 0x00000000}, ++ {0x8ea8, 0x00000000}, ++ {0x8eac, 0x00000000}, ++ {0x8eb0, 0x00000000}, ++ {0x8eb4, 0x00000000}, ++ {0x8eb8, 0x00000000}, ++ {0x8ebc, 0x00000000}, ++ {0x8ec0, 0x00000000}, ++ {0x8ec4, 0x00000000}, ++ {0x8ec8, 0x00000000}, ++ {0x8ecc, 0x00000000}, ++ {0x8ed0, 0x00000000}, ++ {0x8ed4, 0x00000000}, ++ {0x8ed8, 0x00000000}, ++ {0x8edc, 0x00000000}, ++ {0x8ee0, 0x00000000}, ++ {0x8ee4, 0x00000000}, ++ {0x8ee8, 0x00000000}, ++ {0x8eec, 0x00000000}, ++ {0x8ef0, 0x00000000}, ++ {0x8ef4, 0x00000000}, ++ {0x8ef8, 0x00000000}, ++ {0x8efc, 0x00000000}, ++ {0x8f00, 0x00000000}, ++ {0x8f04, 0x00000000}, ++ {0x8f08, 0x00000000}, ++ {0x8f0c, 0x00000000}, ++ {0x8f10, 0x00000000}, ++ {0x8f14, 0x00000000}, ++ {0x8f18, 0x00000000}, ++ {0x8f1c, 0x00000000}, ++ {0x8f20, 0x00000000}, ++ {0x8f24, 0x00000000}, ++ {0x8f28, 0x00000000}, ++ {0x8f2c, 0x00000000}, ++ {0x8f30, 0x00000000}, ++ {0x8f34, 0x00000000}, ++ {0x8f38, 0x00000000}, ++ {0x8f3c, 0x00000000}, ++ {0x8f40, 0x00000000}, ++ {0x8f44, 0x00000000}, ++ {0x8f48, 0x00000000}, ++ {0x8f4c, 0x00000000}, ++ {0x8f50, 0x00000000}, ++ {0x8f54, 0x00000000}, ++ {0x8f58, 0x00000000}, ++ {0x8f5c, 0x00000000}, ++ {0x8f60, 0x00000000}, ++ {0x8f64, 0x00000000}, ++ {0x8f68, 0x00000000}, ++ {0x8f6c, 0x00000000}, ++ {0x8f70, 0x00000000}, ++ {0x8f74, 0x00000000}, ++ {0x8f78, 0x00000000}, ++ {0x8f7c, 0x00000000}, ++ {0x8f80, 0x00000000}, ++ {0x8f84, 0x00000000}, ++ {0x8f88, 0x00000000}, ++ {0x8f8c, 0x00000000}, ++ {0x8f90, 0x00000000}, ++ {0x8f94, 0x00000000}, ++ {0x8f98, 0x00000000}, ++ {0x8f9c, 0x00000000}, ++ {0x8fa0, 0x00000000}, ++ {0x8fa4, 0x00000000}, ++ {0x8fa8, 0x00000000}, ++ {0x8fac, 0x00000000}, ++ {0x8fb0, 0x00000000}, ++ {0x8fb4, 0x00000000}, ++ {0x8fb8, 0x00000000}, ++ {0x8fbc, 0x00000000}, ++ {0x8fc0, 0x00000000}, ++ {0x8fc4, 0x00000000}, ++ {0x8fc8, 0x00000000}, ++ {0x8fcc, 0x00000000}, ++ {0x8fd0, 0x00000000}, ++ {0x8fd4, 0x00000000}, ++ {0x8fd8, 0x00000000}, ++ {0x8fdc, 0x00000000}, ++ {0x8fe0, 0x00000000}, ++ {0x8fe4, 0x00000000}, ++ {0x8fe8, 0x00000000}, ++ {0x8fec, 0x00000000}, ++ {0x8ff0, 0x00000000}, ++ {0x8ff4, 0x00000000}, ++ {0x8ff8, 0x00000000}, ++ {0x8ffc, 0x00000000}, ++ {0x9000, 0x00000000}, ++ {0x9004, 0x00000000}, ++ {0x9008, 0x00000000}, ++ {0x900c, 0x00000000}, ++ {0x9010, 0x00000000}, ++ {0x9014, 0x00000000}, ++ {0x9018, 0x00000000}, ++ {0x901c, 0x00000000}, ++ {0x9020, 0x00000000}, ++ {0x9024, 0x00000000}, ++ {0x9028, 0x00000000}, ++ {0x902c, 0x00000000}, ++ {0x9030, 0x00000000}, ++ {0x9034, 0x00000000}, ++ {0x9038, 0x00000000}, ++ {0x903c, 0x00000000}, ++ {0x9040, 0x00000000}, ++ {0x9044, 0x00000000}, ++ {0x9048, 0x00000000}, ++ {0x904c, 0x00000000}, ++ {0x9050, 0x00000000}, ++ {0x9054, 0x00000000}, ++ {0x9058, 0x00000000}, ++ {0x905c, 0x00000000}, ++ {0x9060, 0x00000000}, ++ {0x9064, 0x00000000}, ++ {0x9068, 0x00000000}, ++ {0x906c, 0x00000000}, ++ {0x9070, 0x00000000}, ++ {0x9074, 0x00000000}, ++ {0x9078, 0x00000000}, ++ {0x907c, 0x00000000}, ++ {0x9080, 0x00000000}, ++ {0x9084, 0x00000000}, ++ {0x9088, 0x00000000}, ++ {0x908c, 0x00000000}, ++ {0x9090, 0x00000000}, ++ {0x9094, 0x00000000}, ++ {0x9098, 0x00000000}, ++ {0x909c, 0x00000000}, ++ {0x90a0, 0x00000000}, ++ {0x90a4, 0x00000000}, ++ {0x90a8, 0x00000000}, ++ {0x90ac, 0x00000000}, ++ {0x90b0, 0x00000000}, ++ {0x90b4, 0x00000000}, ++ {0x90b8, 0x00000000}, ++ {0x90bc, 0x00000000}, ++ {0x9100, 0x00000000}, ++ {0x9104, 0x00000000}, ++ {0x9108, 0x00000000}, ++ {0x910c, 0x00000000}, ++ {0x9110, 0x00000000}, ++ {0x9114, 0x00000000}, ++ {0x9118, 0x00000000}, ++ {0x911c, 0x00000000}, ++ {0x9120, 0x00000000}, ++ {0x9124, 0x00000000}, ++ {0x9128, 0x00000000}, ++ {0x912c, 0x00000000}, ++ {0x9130, 0x00000000}, ++ {0x9134, 0x00000000}, ++ {0x9138, 0x00000000}, ++ {0x913c, 0x00000000}, ++ {0x9140, 0x00000000}, ++ {0x9144, 0x00000000}, ++ {0x9148, 0x00000000}, ++ {0x914c, 0x00000000}, ++ {0x9150, 0x00000000}, ++ {0x9154, 0x00000000}, ++ {0x9158, 0x00000000}, ++ {0x915c, 0x00000000}, ++ {0x9160, 0x00000000}, ++ {0x9164, 0x00000000}, ++ {0x9168, 0x00000000}, ++ {0x916c, 0x00000000}, ++ {0x9170, 0x00000000}, ++ {0x9174, 0x00000000}, ++ {0x9178, 0x00000000}, ++ {0x917c, 0x00000000}, ++ {0x9180, 0x00000000}, ++ {0x9184, 0x00000000}, ++ {0x9188, 0x00000000}, ++ {0x918c, 0x00000000}, ++ {0x9190, 0x00000000}, ++ {0x9194, 0x00000000}, ++ {0x9198, 0x00000000}, ++ {0x919c, 0x00000000}, ++ {0x91a0, 0x00000000}, ++ {0x91a4, 0x00000000}, ++ {0x91a8, 0x00000000}, ++ {0x91ac, 0x00000000}, ++ {0x91b0, 0x00000000}, ++ {0x91b4, 0x00000000}, ++ {0x91b8, 0x00000000}, ++ {0x91bc, 0x00000000}, ++ {0x91c0, 0x00000000}, ++ {0x91c4, 0x00000000}, ++ {0x91c8, 0x00000000}, ++ {0x91cc, 0x00000000}, ++ {0x91d0, 0x00000000}, ++ {0x91d4, 0x00000000}, ++ {0x91d8, 0x00000000}, ++ {0x91dc, 0x00000000}, ++ {0x91e0, 0x00000000}, ++ {0x91e4, 0x00000000}, ++ {0x91e8, 0x00000000}, ++ {0x91ec, 0x00000000}, ++ {0x91f0, 0x00000000}, ++ {0x91f4, 0x00000000}, ++ {0x91f8, 0x00000000}, ++ {0x91fc, 0x00000000}, ++ {0x9200, 0x00000000}, ++ {0x9204, 0x00000000}, ++ {0x9208, 0x00000000}, ++ {0x920c, 0x00000000}, ++ {0x9210, 0x00000000}, ++ {0x9214, 0x00000000}, ++ {0x9218, 0x00000000}, ++ {0x921c, 0x00000000}, ++ {0x9220, 0x00000000}, ++ {0x9224, 0x00000000}, ++ {0x9228, 0x00000000}, ++ {0x922c, 0x00000000}, ++ {0x9230, 0x00000000}, ++ {0x9234, 0x00000000}, ++ {0x9238, 0x00000000}, ++ {0x923c, 0x00000000}, ++ {0x9240, 0x00000000}, ++ {0x9244, 0x00000000}, ++ {0x9248, 0x00000000}, ++ {0x924c, 0x00000000}, ++ {0x9250, 0x00000000}, ++ {0x9254, 0x00000000}, ++ {0x9258, 0x00000000}, ++ {0x925c, 0x00000000}, ++ {0x9260, 0x00000000}, ++ {0x9264, 0x00000000}, ++ {0x9268, 0x00000000}, ++ {0x926c, 0x00000000}, ++ {0x9270, 0x00000000}, ++ {0x9274, 0x00000000}, ++ {0x9278, 0x00000000}, ++ {0x927c, 0x00000000}, ++ {0x9280, 0x00000000}, ++ {0x9284, 0x00000000}, ++ {0x9288, 0x00000000}, ++ {0x928c, 0x00000000}, ++ {0x9290, 0x00000000}, ++ {0x9294, 0x00000000}, ++ {0x9298, 0x00000000}, ++ {0x929c, 0x00000000}, ++ {0x92a0, 0x00000000}, ++ {0x92a4, 0x00000000}, ++ {0x92a8, 0x00000000}, ++ {0x92ac, 0x00000000}, ++ {0x92b0, 0x00000000}, ++ {0x92b4, 0x00000000}, ++ {0x92b8, 0x00000000}, ++ {0x92bc, 0x00000000}, ++ {0x92c0, 0x00000000}, ++ {0x92c4, 0x00000000}, ++ {0x92c8, 0x00000000}, ++ {0x92cc, 0x00000000}, ++ {0x92d0, 0x00000000}, ++ {0x92d4, 0x00000000}, ++ {0x92d8, 0x00000000}, ++ {0x92dc, 0x00000000}, ++ {0x92e0, 0x00000000}, ++ {0x92e4, 0x00000000}, ++ {0x92e8, 0x00000000}, ++ {0x92ec, 0x00000000}, ++ {0x92f0, 0x00000000}, ++ {0x92f4, 0x00000000}, ++ {0x92f8, 0x00000000}, ++ {0x92fc, 0x00000000}, ++ {0x9300, 0x00000000}, ++ {0x9304, 0x00000000}, ++ {0x9308, 0x00000000}, ++ {0x930c, 0x00000000}, ++ {0x9310, 0x00000000}, ++ {0x9314, 0x00000000}, ++ {0x9318, 0x00000000}, ++ {0x931c, 0x00000000}, ++ {0x9320, 0x00000000}, ++ {0x9324, 0x00000000}, ++ {0x9328, 0x00000000}, ++ {0x932c, 0x00000000}, ++ {0x9330, 0x00000000}, ++ {0x9334, 0x00000000}, ++ {0x9338, 0x00000000}, ++ {0x933c, 0x00000000}, ++ {0x9340, 0x00000000}, ++ {0x9344, 0x00000000}, ++ {0x9348, 0x00000000}, ++ {0x934c, 0x00000000}, ++ {0x9350, 0x00000000}, ++ {0x9354, 0x00000000}, ++ {0x9358, 0x00000000}, ++ {0x935c, 0x00000000}, ++ {0x9360, 0x00000000}, ++ {0x9364, 0x00000000}, ++ {0x9368, 0x00000000}, ++ {0x936c, 0x00000000}, ++ {0x9370, 0x00000000}, ++ {0x9374, 0x00000000}, ++ {0x9378, 0x00000000}, ++ {0x937c, 0x00000000}, ++ {0x9380, 0x00000000}, ++ {0x9384, 0x00000000}, ++ {0x9388, 0x00000000}, ++ {0x938c, 0x00000000}, ++ {0x9390, 0x00000000}, ++ {0x9394, 0x00000000}, ++ {0x9398, 0x00000000}, ++ {0x939c, 0x00000000}, ++ {0x93a0, 0x00000000}, ++ {0x93a4, 0x00000000}, ++ {0x93a8, 0x00000000}, ++ {0x93ac, 0x00000000}, ++ {0x93b0, 0x00000000}, ++ {0x93b4, 0x00000000}, ++ {0x93b8, 0x00000000}, ++ {0x93bc, 0x00000000}, ++ {0x93c0, 0x00000000}, ++ {0x93c4, 0x00000000}, ++ {0x93c8, 0x00000000}, ++ {0x93cc, 0x00000000}, ++ {0x93d0, 0x00000000}, ++ {0x93d4, 0x00000000}, ++ {0x93d8, 0x00000000}, ++ {0x93dc, 0x00000000}, ++ {0x93e0, 0x00000000}, ++ {0x93e4, 0x00000000}, ++ {0x93e8, 0x00000000}, ++ {0x93ec, 0x00000000}, ++ {0x93f0, 0x00000000}, ++ {0x93f4, 0x00000000}, ++ {0x93f8, 0x00000000}, ++ {0x93fc, 0x00000000}, ++ {0x9400, 0x00000000}, ++ {0x9404, 0x00000000}, ++ {0x9408, 0x00000000}, ++ {0x940c, 0x00000000}, ++ {0x9410, 0x00000000}, ++ {0x9414, 0x00000000}, ++ {0x9418, 0x00000000}, ++ {0x941c, 0x00000000}, ++ {0x9420, 0x00000000}, ++ {0x9424, 0x00000000}, ++ {0x9428, 0x00000000}, ++ {0x942c, 0x00000000}, ++ {0x9430, 0x00000000}, ++ {0x9434, 0x00000000}, ++ {0x9438, 0x00000000}, ++ {0x943c, 0x00000000}, ++ {0x9440, 0x00000000}, ++ {0x9444, 0x00000000}, ++ {0x9448, 0x00000000}, ++ {0x944c, 0x00000000}, ++ {0x9450, 0x00000000}, ++ {0x9454, 0x00000000}, ++ {0x9458, 0x00000000}, ++ {0x945c, 0x00000000}, ++ {0x9460, 0x00000000}, ++ {0x9464, 0x00000000}, ++ {0x9468, 0x00000000}, ++ {0x946c, 0x00000000}, ++ {0x9470, 0x00000000}, ++ {0x9474, 0x00000000}, ++ {0x9478, 0x00000000}, ++ {0x947c, 0x00000000}, ++ {0x9480, 0x00000000}, ++ {0x9484, 0x00000000}, ++ {0x9488, 0x00000000}, ++ {0x948c, 0x00000000}, ++ {0x9490, 0x00000000}, ++ {0x9494, 0x00000000}, ++ {0x9498, 0x00000000}, ++ {0x949c, 0x00000000}, ++ {0x94a0, 0x00000000}, ++ {0x94a4, 0x00000000}, ++ {0x94a8, 0x00000000}, ++ {0x94ac, 0x00000000}, ++ {0x94b0, 0x00000000}, ++ {0x94b4, 0x00000000}, ++ {0x94b8, 0x00000000}, ++ {0x94bc, 0x00000000}, ++ {0x81d8, 0x00000000}, ++ {0x82d8, 0x00000000}, ++ {0x9f04, 0x2b251f19}, ++ {0x9f08, 0x433d3731}, ++ {0x9f0c, 0x5b554f49}, ++ {0x9f10, 0x736d6761}, ++ {0x9f14, 0x7f7f7f79}, ++ {0x9f18, 0x120f7f7f}, ++ {0x9f1c, 0x1e1b1815}, ++ {0x9f20, 0x2a272421}, ++ {0x9f24, 0x3633302d}, ++ {0x9f28, 0x3f3f3c39}, ++ {0x9f2c, 0x3f3f3f3f}, ++ {0x8088, 0x00000110}, ++ {0x8000, 0x00000008}, ++ {0x8080, 0x00000005}, ++ {0x8500, 0x00060009}, ++ {0x8504, 0x000418b0}, ++ {0x8508, 0x00089c00}, ++ {0x850c, 0x43000004}, ++ {0x8510, 0x4b044a00}, ++ {0x8514, 0x40098603}, ++ {0x8518, 0x4b05e01f}, ++ {0x851c, 0x400b8703}, ++ {0x8520, 0x4b00e01f}, ++ {0x8524, 0x43800004}, ++ {0x8528, 0x4c000007}, ++ {0x852c, 0x43000004}, ++ {0x8530, 0x57007430}, ++ {0x8534, 0x73000006}, ++ {0x8538, 0x50550004}, ++ {0x853c, 0xb4163000}, ++ {0x8540, 0xe37ea510}, ++ {0x8544, 0xf117f017}, ++ {0x8548, 0xf317f217}, ++ {0x854c, 0xf517f417}, ++ {0x8550, 0xf717f617}, ++ {0x8554, 0xf917f817}, ++ {0x8558, 0xfb17fa17}, ++ {0x855c, 0xfd17fc17}, ++ {0x8560, 0xf117f017}, ++ {0x8564, 0xf317f217}, ++ {0x8568, 0xa503f417}, ++ {0x856c, 0xf116f016}, ++ {0x8570, 0x304e0001}, ++ {0x8574, 0x30873053}, ++ {0x8578, 0x30ab30a8}, ++ {0x857c, 0x30b330ae}, ++ {0x8580, 0x30ba30b6}, ++ {0x8584, 0x30d430c7}, ++ {0x8588, 0x310d3100}, ++ {0x858c, 0x31ed3112}, ++ {0x8590, 0x320a31f1}, ++ {0x8594, 0x3243320b}, ++ {0x8598, 0x31e631b1}, ++ {0x859c, 0x5b00e283}, ++ {0x85a0, 0xe2d15500}, ++ {0x85a4, 0xe2830001}, ++ {0x85a8, 0x5b10e2e3}, ++ {0x85ac, 0x20987410}, ++ {0x85b0, 0xe3750200}, ++ {0x85b4, 0x00002080}, ++ {0x85b8, 0x23f0e375}, ++ {0x85bc, 0xe3750001}, ++ {0x85c0, 0x000023f0}, ++ {0x85c4, 0x5507e375}, ++ {0x85c8, 0xe2d5e2d5}, ++ {0x85cc, 0x20887410}, ++ {0x85d0, 0xe3750200}, ++ {0x85d4, 0x000123f0}, ++ {0x85d8, 0x23f0e375}, ++ {0x85dc, 0xe3750000}, ++ {0x85e0, 0xe2d55517}, ++ {0x85e4, 0x4e004f02}, ++ {0x85e8, 0x52015302}, ++ {0x85ec, 0x7508e2d9}, ++ {0x85f0, 0x74207900}, ++ {0x85f4, 0x57005710}, ++ {0x85f8, 0x75fbe375}, ++ {0x85fc, 0x23f07410}, ++ {0x8600, 0xe3750001}, ++ {0x8604, 0x000023f0}, ++ {0x8608, 0x7430e375}, ++ {0x860c, 0x5b100001}, ++ {0x8610, 0x20907410}, ++ {0x8614, 0xe3750000}, ++ {0x8618, 0x000123f0}, ++ {0x861c, 0x23f0e375}, ++ {0x8620, 0xe3750000}, ++ {0x8624, 0xe2d55507}, ++ {0x8628, 0x7410e2d5}, ++ {0x862c, 0x02002098}, ++ {0x8630, 0x23f0e375}, ++ {0x8634, 0xe3750001}, ++ {0x8638, 0x000023f0}, ++ {0x863c, 0x5517e375}, ++ {0x8640, 0x4f02e2d5}, ++ {0x8644, 0x53024e00}, ++ {0x8648, 0xe2d95201}, ++ {0x864c, 0x30787509}, ++ {0x8650, 0xe2e3e283}, ++ {0x8654, 0xe27b0001}, ++ {0x8658, 0x0001e2e3}, ++ {0x865c, 0x5b30e28f}, ++ {0x8660, 0xe2d15500}, ++ {0x8664, 0xe28f0001}, ++ {0x8668, 0x0001e312}, ++ {0x866c, 0x4380e287}, ++ {0x8670, 0x0001e312}, ++ {0x8674, 0x30e2e283}, ++ {0x8678, 0xe3600023}, ++ {0x867c, 0x54ed0002}, ++ {0x8680, 0x00230baa}, ++ {0x8684, 0x0002e360}, ++ {0x8688, 0xe27be330}, ++ {0x868c, 0xe2830001}, ++ {0x8690, 0x002230dd}, ++ {0x8694, 0x0002e360}, ++ {0x8698, 0x0baa54ec}, ++ {0x869c, 0xe3600022}, ++ {0x86a0, 0xe3300002}, ++ {0x86a4, 0x0001e27b}, ++ {0x86a8, 0x0baae283}, ++ {0x86ac, 0x6d0f6c67}, ++ {0x86b0, 0xe360e2e3}, ++ {0x86b4, 0xe2e36c8b}, ++ {0x86b8, 0x0bace360}, ++ {0x86bc, 0x6d0f6cb3}, ++ {0x86c0, 0xe360e2e3}, ++ {0x86c4, 0x6cdb0bad}, ++ {0x86c8, 0xe2e36d0f}, ++ {0x86cc, 0x6cf7e360}, ++ {0x86d0, 0xe2e36d0f}, ++ {0x86d4, 0x6c09e360}, ++ {0x86d8, 0xe2e36d00}, ++ {0x86dc, 0x6c25e360}, ++ {0x86e0, 0xe360e2e3}, ++ {0x86e4, 0x6c4df8ca}, ++ {0x86e8, 0xe360e2e3}, ++ {0x86ec, 0x6c75f9d3}, ++ {0x86f0, 0xe360e2e3}, ++ {0x86f4, 0xe2e36c99}, ++ {0x86f8, 0xe330e360}, ++ {0x86fc, 0x0001e27b}, ++ {0x8700, 0x314de28f}, ++ {0x8704, 0xe3650022}, ++ {0x8708, 0x54ec0002}, ++ {0x870c, 0x00220baa}, ++ {0x8710, 0x0002e365}, ++ {0x8714, 0xe287e330}, ++ {0x8718, 0xe28f0001}, ++ {0x871c, 0xe3303139}, ++ {0x8720, 0x0001e287}, ++ {0x8724, 0x0ba6e28f}, ++ {0x8728, 0x21e07410}, ++ {0x872c, 0x21e80009}, ++ {0x8730, 0x6e670009}, ++ {0x8734, 0xe32b6f0f}, ++ {0x8738, 0xe365e312}, ++ {0x873c, 0x21e07410}, ++ {0x8740, 0x21e8000a}, ++ {0x8744, 0x6e77000a}, ++ {0x8748, 0xe312e32b}, ++ {0x874c, 0x7410e365}, ++ {0x8750, 0x000b21e0}, ++ {0x8754, 0x000b21e8}, ++ {0x8758, 0xe32b6e8b}, ++ {0x875c, 0xe365e312}, ++ {0x8760, 0x21e07410}, ++ {0x8764, 0x21e8000c}, ++ {0x8768, 0x6e9f000c}, ++ {0x876c, 0xe312e32b}, ++ {0x8770, 0x0baae365}, ++ {0x8774, 0x21e07410}, ++ {0x8778, 0x21e8000d}, ++ {0x877c, 0x6eb3000d}, ++ {0x8780, 0xe32b6f0f}, ++ {0x8784, 0xe365e312}, ++ {0x8788, 0x21e07410}, ++ {0x878c, 0x21e8000e}, ++ {0x8790, 0x6ec7000e}, ++ {0x8794, 0xe312e32b}, ++ {0x8798, 0x0bace365}, ++ {0x879c, 0x21e07410}, ++ {0x87a0, 0x21e8000f}, ++ {0x87a4, 0x6edb000f}, ++ {0x87a8, 0xe32b6f0f}, ++ {0x87ac, 0xe365e312}, ++ {0x87b0, 0x21e07410}, ++ {0x87b4, 0x21e80010}, ++ {0x87b8, 0x6eef0010}, ++ {0x87bc, 0xe312e32b}, ++ {0x87c0, 0xe365e365}, ++ {0x87c4, 0x21e07410}, ++ {0x87c8, 0x21e80013}, ++ {0x87cc, 0x6e110013}, ++ {0x87d0, 0xe32b6f00}, ++ {0x87d4, 0xe365e312}, ++ {0x87d8, 0x7410e365}, ++ {0x87dc, 0x001421e0}, ++ {0x87e0, 0x001421e8}, ++ {0x87e4, 0xe32b6e25}, ++ {0x87e8, 0xe365e312}, ++ {0x87ec, 0x7410fb8c}, ++ {0x87f0, 0x001521e0}, ++ {0x87f4, 0x001521e8}, ++ {0x87f8, 0xe32b6e39}, ++ {0x87fc, 0xe365e312}, ++ {0x8800, 0x21e07410}, ++ {0x8804, 0x21e80016}, ++ {0x8808, 0x6e4d0016}, ++ {0x880c, 0xe312e32b}, ++ {0x8810, 0xfc86e365}, ++ {0x8814, 0x21e07410}, ++ {0x8818, 0x21e80017}, ++ {0x881c, 0x6e610017}, ++ {0x8820, 0xe312e32b}, ++ {0x8824, 0x7410e365}, ++ {0x8828, 0x001821e0}, ++ {0x882c, 0x001821e8}, ++ {0x8830, 0xe32b6e75}, ++ {0x8834, 0xe365e312}, ++ {0x8838, 0x21e07410}, ++ {0x883c, 0x21e80019}, ++ {0x8840, 0x6e890019}, ++ {0x8844, 0xe312e32b}, ++ {0x8848, 0x7410e365}, ++ {0x884c, 0x001a21e0}, ++ {0x8850, 0x001a21e8}, ++ {0x8854, 0xe32b6e99}, ++ {0x8858, 0xe365e312}, ++ {0x885c, 0xe287e330}, ++ {0x8860, 0x00040001}, ++ {0x8864, 0x0007775c}, ++ {0x8868, 0x62006220}, ++ {0x886c, 0x55010004}, ++ {0x8870, 0xe2d15b00}, ++ {0x8874, 0x66055b40}, ++ {0x8878, 0x62000007}, ++ {0x887c, 0xe3506300}, ++ {0x8880, 0xe2d10004}, ++ {0x8884, 0x0a010900}, ++ {0x8888, 0x0d000b40}, ++ {0x888c, 0x00320e01}, ++ {0x8890, 0x95060004}, ++ {0x8894, 0x00074380}, ++ {0x8898, 0x00044d01}, ++ {0x889c, 0x00074300}, ++ {0x88a0, 0x05a30562}, ++ {0x88a4, 0xe3509617}, ++ {0x88a8, 0xe2d10004}, ++ {0x88ac, 0x06a20007}, ++ {0x88b0, 0xe35007a3}, ++ {0x88b4, 0xe2d10004}, ++ {0x88b8, 0x0002e340}, ++ {0x88bc, 0x4380e348}, ++ {0x88c0, 0x4d000007}, ++ {0x88c4, 0x43000004}, ++ {0x88c8, 0x00017900}, ++ {0x88cc, 0x775e0004}, ++ {0x88d0, 0x000731b3}, ++ {0x88d4, 0x07a306a2}, ++ {0x88d8, 0xe29331dd}, ++ {0x88dc, 0x73000005}, ++ {0x88e0, 0xe2930001}, ++ {0x88e4, 0x5d000006}, ++ {0x88e8, 0x42f70004}, ++ {0x88ec, 0x6c000005}, ++ {0x88f0, 0x42000004}, ++ {0x88f4, 0x0004e2ab}, ++ {0x88f8, 0x00074380}, ++ {0x88fc, 0x4a004e00}, ++ {0x8900, 0x00064c00}, ++ {0x8904, 0x60007f00}, ++ {0x8908, 0x00046f00}, ++ {0x890c, 0x00054300}, ++ {0x8910, 0x00017300}, ++ {0x8914, 0xe2930001}, ++ {0x8918, 0x5d010006}, ++ {0x891c, 0x61006002}, ++ {0x8920, 0x00055601}, ++ {0x8924, 0xe2ab7710}, ++ {0x8928, 0x73000005}, ++ {0x892c, 0x43800004}, ++ {0x8930, 0x5e010007}, ++ {0x8934, 0x4d205e00}, ++ {0x8938, 0x4a084e20}, ++ {0x893c, 0x4c3f4960}, ++ {0x8940, 0x00064301}, ++ {0x8944, 0x63807f01}, ++ {0x8948, 0x00046010}, ++ {0x894c, 0x00064300}, ++ {0x8950, 0x00077402}, ++ {0x8954, 0x40004001}, ++ {0x8958, 0x0006ab00}, ++ {0x895c, 0x00077404}, ++ {0x8960, 0x40004001}, ++ {0x8964, 0x0004ab00}, ++ {0x8968, 0x00074380}, ++ {0x896c, 0x4e004d00}, ++ {0x8970, 0x4c004a00}, ++ {0x8974, 0x00064300}, ++ {0x8978, 0x63007f00}, ++ {0x897c, 0x6f006000}, ++ {0x8980, 0x43000004}, ++ {0x8984, 0x00040001}, ++ {0x8988, 0x42bf4380}, ++ {0x898c, 0x48400007}, ++ {0x8990, 0x42ef0004}, ++ {0x8994, 0x4d100007}, ++ {0x8998, 0x42000004}, ++ {0x899c, 0x5f800006}, ++ {0x89a0, 0x5a010007}, ++ {0x89a4, 0x00044a08}, ++ {0x89a8, 0x00054300}, ++ {0x89ac, 0x73807381}, ++ {0x89b0, 0x003f9300}, ++ {0x89b4, 0x00000000}, ++ {0x89b8, 0x00000000}, ++ {0x89bc, 0x00020000}, ++ {0x89c0, 0x5f800006}, ++ {0x89c4, 0x99005f00}, ++ {0x89c8, 0x43800004}, ++ {0x89cc, 0x00074280}, ++ {0x89d0, 0x00044800}, ++ {0x89d4, 0x000742ef}, ++ {0x89d8, 0x00044d00}, ++ {0x89dc, 0x00064200}, ++ {0x89e0, 0x60005f00}, ++ {0x89e4, 0x5a000007}, ++ {0x89e8, 0x48004a00}, ++ {0x89ec, 0x43000004}, ++ {0x89f0, 0x73000005}, ++ {0x89f4, 0x43800001}, ++ {0x89f8, 0x78006505}, ++ {0x89fc, 0x7a007900}, ++ {0x8a00, 0x43007b00}, ++ {0x8a04, 0x43800001}, ++ {0x8a08, 0x43006500}, ++ {0x8a0c, 0x43800001}, ++ {0x8a10, 0x7c006405}, ++ {0x8a14, 0x7e007d00}, ++ {0x8a18, 0x43007f00}, ++ {0x8a1c, 0x43800001}, ++ {0x8a20, 0x43006400}, ++ {0x8a24, 0x00060001}, ++ {0x8a28, 0x55025601}, ++ {0x8a2c, 0x00055400}, ++ {0x8a30, 0x7e127f00}, ++ {0x8a34, 0x76007710}, ++ {0x8a38, 0x74007500}, ++ {0x8a3c, 0x42700004}, ++ {0x8a40, 0x73810005}, ++ {0x8a44, 0x00047380}, ++ {0x8a48, 0x93004200}, ++ {0x8a4c, 0x77000005}, ++ {0x8a50, 0x56000006}, ++ {0x8a54, 0x00060001}, ++ {0x8a58, 0x5f005f80}, ++ {0x8a5c, 0x00059900}, ++ {0x8a60, 0x00067300}, ++ {0x8a64, 0x63006380}, ++ {0x8a68, 0x00019800}, ++ {0x8a6c, 0x7b484380}, ++ {0x8a70, 0x79007a90}, ++ {0x8a74, 0x43007802}, ++ {0x8a78, 0x32cd5503}, ++ {0x8a7c, 0x7b384380}, ++ {0x8a80, 0x79007a80}, ++ {0x8a84, 0x43007802}, ++ {0x8a88, 0x32cd5513}, ++ {0x8a8c, 0x7b404380}, ++ {0x8a90, 0x79007a00}, ++ {0x8a94, 0x43007802}, ++ {0x8a98, 0x74315523}, ++ {0x8a9c, 0x8e007430}, ++ {0x8aa0, 0x74010001}, ++ {0x8aa4, 0x8e007400}, ++ {0x8aa8, 0x74310001}, ++ {0x8aac, 0x8e007430}, ++ {0x8ab0, 0x57020001}, ++ {0x8ab4, 0x97005700}, ++ {0x8ab8, 0x42ef0001}, ++ {0x8abc, 0x56005610}, ++ {0x8ac0, 0x8c004200}, ++ {0x8ac4, 0x4f780001}, ++ {0x8ac8, 0x53884e00}, ++ {0x8acc, 0x5b205201}, ++ {0x8ad0, 0x5480e2f2}, ++ {0x8ad4, 0x54815400}, ++ {0x8ad8, 0x54825400}, ++ {0x8adc, 0xe2fd5400}, ++ {0x8ae0, 0x3012bf1d}, ++ {0x8ae4, 0xe2bee2b6}, ++ {0x8ae8, 0xe2d9e2c6}, ++ {0x8aec, 0x5523e359}, ++ {0x8af0, 0x5525e2cd}, ++ {0x8af4, 0xe359e2d9}, ++ {0x8af8, 0x54bf0001}, ++ {0x8afc, 0x54a354c0}, ++ {0x8b00, 0x54a454c1}, ++ {0x8b04, 0xbf074c18}, ++ {0x8b08, 0x54a454c2}, ++ {0x8b0c, 0x54c1bf04}, ++ {0x8b10, 0xbf0154a3}, ++ {0x8b14, 0x54dfe36a}, ++ {0x8b18, 0x54bf0001}, ++ {0x8b1c, 0x050a54e5}, ++ {0x8b20, 0x000154df}, ++ {0x8b24, 0x43807b80}, ++ {0x8b28, 0x7e007f40}, ++ {0x8b2c, 0x7c027d00}, ++ {0x8b30, 0x5b404300}, ++ {0x8b34, 0x5c015501}, ++ {0x8b38, 0x5480e2dd}, ++ {0x8b3c, 0x54815400}, ++ {0x8b40, 0x54825400}, ++ {0x8b44, 0x7b005400}, ++ {0x8b48, 0xbfe8e2fd}, ++ {0x8b4c, 0x56103012}, ++ {0x8b50, 0x8c005600}, ++ {0x8b54, 0xe36d0001}, ++ {0x8b58, 0xe36de36d}, ++ {0x8b5c, 0x0001e36d}, ++ {0x8b60, 0x57005704}, ++ {0x8b64, 0x57089700}, ++ {0x8b68, 0x97005700}, ++ {0x8b6c, 0x57805781}, ++ {0x8b70, 0x43809700}, ++ {0x8b74, 0x5c010007}, ++ {0x8b78, 0x00045c00}, ++ {0x8b7c, 0x00014300}, ++ {0x8b80, 0x0007427f}, ++ {0x8b84, 0x62006280}, ++ {0x8b88, 0x00049200}, ++ {0x8b8c, 0x00014200}, ++ {0x8b90, 0x0007427f}, ++ {0x8b94, 0x63146394}, ++ {0x8b98, 0x00049100}, ++ {0x8b9c, 0x00014200}, ++ {0x8ba0, 0x79010004}, ++ {0x8ba4, 0xe3757420}, ++ {0x8ba8, 0x57005710}, ++ {0x8bac, 0xe375e375}, ++ {0x8bb0, 0x549f0001}, ++ {0x8bb4, 0x5c015400}, ++ {0x8bb8, 0x540054df}, ++ {0x8bbc, 0x00015c02}, ++ {0x8bc0, 0x07145c01}, ++ {0x8bc4, 0x5c025400}, ++ {0x8bc8, 0x5c020001}, ++ {0x8bcc, 0x54000714}, ++ {0x8bd0, 0x00015c01}, ++ {0x8bd4, 0x4c184c98}, ++ {0x8bd8, 0x003f0001}, ++ {0x8bdc, 0x00000000}, ++ {0x8be0, 0x00000000}, ++ {0x8be4, 0x00020000}, ++ {0x8be8, 0x00000001}, ++ {0x8bec, 0x00000000}, ++ {0x8bf0, 0x00000000}, ++ {0x8bf4, 0x00000000}, ++ {0x8bf8, 0x00010000}, ++ {0x8bfc, 0x5c020004}, ++ {0x8c00, 0x66076204}, ++ {0x8c04, 0x743070c0}, ++ {0x8c08, 0x0c010901}, ++ {0x8c0c, 0x00010ba6}, ++ {0x8080, 0x00000004}, ++ {0x8080, 0x00000000}, ++ {0x8088, 0x00000000}, ++}; ++ ++static const struct rtw89_txpwr_byrate_cfg rtw89_8852a_txpwr_byrate[] = { ++ { 0, 0, 0, 0, 4, 0x50505050, }, ++ { 0, 0, 1, 0, 4, 0x50505050, }, ++ { 0, 0, 1, 4, 4, 0x484c5050, }, ++ { 0, 0, 2, 0, 4, 0x50505050, }, ++ { 0, 0, 2, 4, 4, 0x44484c50, }, ++ { 0, 0, 2, 8, 4, 0x34383c40, }, ++ { 0, 0, 3, 0, 4, 0x50505050, }, ++ { 0, 1, 2, 0, 4, 0x50505050, }, ++ { 0, 1, 2, 4, 4, 0x44484c50, }, ++ { 0, 1, 2, 8, 4, 0x34383c40, }, ++ { 0, 1, 3, 0, 4, 0x50505050, }, ++ { 0, 0, 4, 1, 4, 0x00000000, }, ++ { 0, 0, 4, 0, 1, 0x00000000, }, ++ { 1, 0, 1, 0, 4, 0x50505050, }, ++ { 1, 0, 1, 4, 4, 0x484c5050, }, ++ { 1, 0, 2, 0, 4, 0x50505050, }, ++ { 1, 0, 2, 4, 4, 0x44484c50, }, ++ { 1, 0, 2, 8, 4, 0x34383c40, }, ++ { 1, 0, 3, 0, 4, 0x50505050, }, ++ { 1, 1, 2, 0, 4, 0x50505050, }, ++ { 1, 1, 2, 4, 4, 0x44484c50, }, ++ { 1, 1, 2, 8, 4, 0x34383c40, }, ++ { 1, 1, 3, 0, 4, 0x50505050, }, ++ { 1, 0, 4, 0, 4, 0x00000000, }, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5gb_n[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, ++ 7, 7, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5gb_p[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, ++ 6, 7, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5ga_n[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, ++ 7, 7, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_5ga_p[][DELTA_SWINGIDX_SIZE] = { ++ {0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, ++ 6, 7, 7, 7, 8, 8, 8, 9, 9, 10, 10, 10, 11, 11}, ++ {0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 4, ++ 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8}, ++ {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, ++ 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9}, ++}; ++ ++static const u8 _txpwr_track_delta_swingidx_2gb_n[] = { ++ 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, ++ 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7}; ++ ++static const u8 _txpwr_track_delta_swingidx_2gb_p[] = { ++ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, ++ 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3}; ++ ++static const u8 _txpwr_track_delta_swingidx_2ga_n[] = { ++ 0, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, ++ 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5}; ++ ++static const u8 _txpwr_track_delta_swingidx_2ga_p[] = { ++ 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, ++ 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_b_n[] = { ++ 0, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 4, ++ 4, 4, 4, 5, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_b_p[] = { ++ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, ++ 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_a_n[] = { ++ 0, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 3, 3, ++ 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5}; ++ ++static const u8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = { ++ 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, ++ 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10}; ++ ++const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = { ++ [0][0][0][0][0][0] = 56, ++ [0][0][0][0][0][1] = 56, ++ [0][0][0][0][0][2] = 56, ++ [0][0][0][0][0][3] = 56, ++ [0][0][0][0][0][4] = 56, ++ [0][0][0][0][0][5] = 56, ++ [0][0][0][0][0][6] = 56, ++ [0][0][0][0][0][7] = 56, ++ [0][0][0][0][0][8] = 56, ++ [0][0][0][0][0][9] = 56, ++ [0][0][0][0][0][10] = 56, ++ [0][0][0][0][0][11] = 56, ++ [0][0][0][0][0][12] = 48, ++ [0][0][0][0][0][13] = 76, ++ [0][1][0][0][0][0] = 44, ++ [0][1][0][0][0][1] = 44, ++ [0][1][0][0][0][2] = 44, ++ [0][1][0][0][0][3] = 44, ++ [0][1][0][0][0][4] = 44, ++ [0][1][0][0][0][5] = 44, ++ [0][1][0][0][0][6] = 44, ++ [0][1][0][0][0][7] = 44, ++ [0][1][0][0][0][8] = 44, ++ [0][1][0][0][0][9] = 44, ++ [0][1][0][0][0][10] = 44, ++ [0][1][0][0][0][11] = 44, ++ [0][1][0][0][0][12] = 38, ++ [0][1][0][0][0][13] = 64, ++ [1][0][0][0][0][0] = 0, ++ [1][0][0][0][0][1] = 0, ++ [1][0][0][0][0][2] = 58, ++ [1][0][0][0][0][3] = 58, ++ [1][0][0][0][0][4] = 58, ++ [1][0][0][0][0][5] = 58, ++ [1][0][0][0][0][6] = 46, ++ [1][0][0][0][0][7] = 46, ++ [1][0][0][0][0][8] = 46, ++ [1][0][0][0][0][9] = 32, ++ [1][0][0][0][0][10] = 32, ++ [1][0][0][0][0][11] = 0, ++ [1][0][0][0][0][12] = 0, ++ [1][0][0][0][0][13] = 0, ++ [1][1][0][0][0][0] = 0, ++ [1][1][0][0][0][1] = 0, ++ [1][1][0][0][0][2] = 46, ++ [1][1][0][0][0][3] = 46, ++ [1][1][0][0][0][4] = 46, ++ [1][1][0][0][0][5] = 46, ++ [1][1][0][0][0][6] = 46, ++ [1][1][0][0][0][7] = 46, ++ [1][1][0][0][0][8] = 46, ++ [1][1][0][0][0][9] = 24, ++ [1][1][0][0][0][10] = 24, ++ [1][1][0][0][0][11] = 0, ++ [1][1][0][0][0][12] = 0, ++ [1][1][0][0][0][13] = 0, ++ [0][0][1][0][0][0] = 58, ++ [0][0][1][0][0][1] = 58, ++ [0][0][1][0][0][2] = 58, ++ [0][0][1][0][0][3] = 58, ++ [0][0][1][0][0][4] = 58, ++ [0][0][1][0][0][5] = 58, ++ [0][0][1][0][0][6] = 58, ++ [0][0][1][0][0][7] = 58, ++ [0][0][1][0][0][8] = 58, ++ [0][0][1][0][0][9] = 58, ++ [0][0][1][0][0][10] = 58, ++ [0][0][1][0][0][11] = 56, ++ [0][0][1][0][0][12] = 52, ++ [0][0][1][0][0][13] = 0, ++ [0][1][1][0][0][0] = 46, ++ [0][1][1][0][0][1] = 46, ++ [0][1][1][0][0][2] = 46, ++ [0][1][1][0][0][3] = 46, ++ [0][1][1][0][0][4] = 46, ++ [0][1][1][0][0][5] = 46, ++ [0][1][1][0][0][6] = 46, ++ [0][1][1][0][0][7] = 46, ++ [0][1][1][0][0][8] = 46, ++ [0][1][1][0][0][9] = 46, ++ [0][1][1][0][0][10] = 46, ++ [0][1][1][0][0][11] = 42, ++ [0][1][1][0][0][12] = 40, ++ [0][1][1][0][0][13] = 0, ++ [0][0][2][0][0][0] = 58, ++ [0][0][2][0][0][1] = 58, ++ [0][0][2][0][0][2] = 58, ++ [0][0][2][0][0][3] = 58, ++ [0][0][2][0][0][4] = 58, ++ [0][0][2][0][0][5] = 58, ++ [0][0][2][0][0][6] = 58, ++ [0][0][2][0][0][7] = 58, ++ [0][0][2][0][0][8] = 58, ++ [0][0][2][0][0][9] = 58, ++ [0][0][2][0][0][10] = 58, ++ [0][0][2][0][0][11] = 54, ++ [0][0][2][0][0][12] = 50, ++ [0][0][2][0][0][13] = 0, ++ [0][1][2][0][0][0] = 46, ++ [0][1][2][0][0][1] = 46, ++ [0][1][2][0][0][2] = 46, ++ [0][1][2][0][0][3] = 46, ++ [0][1][2][0][0][4] = 46, ++ [0][1][2][0][0][5] = 46, ++ [0][1][2][0][0][6] = 46, ++ [0][1][2][0][0][7] = 46, ++ [0][1][2][0][0][8] = 46, ++ [0][1][2][0][0][9] = 46, ++ [0][1][2][0][0][10] = 46, ++ [0][1][2][0][0][11] = 42, ++ [0][1][2][0][0][12] = 40, ++ [0][1][2][0][0][13] = 0, ++ [0][1][2][1][0][0] = 34, ++ [0][1][2][1][0][1] = 34, ++ [0][1][2][1][0][2] = 34, ++ [0][1][2][1][0][3] = 34, ++ [0][1][2][1][0][4] = 34, ++ [0][1][2][1][0][5] = 34, ++ [0][1][2][1][0][6] = 34, ++ [0][1][2][1][0][7] = 34, ++ [0][1][2][1][0][8] = 34, ++ [0][1][2][1][0][9] = 34, ++ [0][1][2][1][0][10] = 34, ++ [0][1][2][1][0][11] = 34, ++ [0][1][2][1][0][12] = 34, ++ [0][1][2][1][0][13] = 0, ++ [1][0][2][0][0][0] = 0, ++ [1][0][2][0][0][1] = 0, ++ [1][0][2][0][0][2] = 56, ++ [1][0][2][0][0][3] = 56, ++ [1][0][2][0][0][4] = 58, ++ [1][0][2][0][0][5] = 58, ++ [1][0][2][0][0][6] = 54, ++ [1][0][2][0][0][7] = 50, ++ [1][0][2][0][0][8] = 50, ++ [1][0][2][0][0][9] = 42, ++ [1][0][2][0][0][10] = 40, ++ [1][0][2][0][0][11] = 0, ++ [1][0][2][0][0][12] = 0, ++ [1][0][2][0][0][13] = 0, ++ [1][1][2][0][0][0] = 0, ++ [1][1][2][0][0][1] = 0, ++ [1][1][2][0][0][2] = 46, ++ [1][1][2][0][0][3] = 46, ++ [1][1][2][0][0][4] = 46, ++ [1][1][2][0][0][5] = 46, ++ [1][1][2][0][0][6] = 46, ++ [1][1][2][0][0][7] = 46, ++ [1][1][2][0][0][8] = 46, ++ [1][1][2][0][0][9] = 38, ++ [1][1][2][0][0][10] = 36, ++ [1][1][2][0][0][11] = 0, ++ [1][1][2][0][0][12] = 0, ++ [1][1][2][0][0][13] = 0, ++ [1][1][2][1][0][0] = 0, ++ [1][1][2][1][0][1] = 0, ++ [1][1][2][1][0][2] = 34, ++ [1][1][2][1][0][3] = 34, ++ [1][1][2][1][0][4] = 34, ++ [1][1][2][1][0][5] = 34, ++ [1][1][2][1][0][6] = 34, ++ [1][1][2][1][0][7] = 34, ++ [1][1][2][1][0][8] = 34, ++ [1][1][2][1][0][9] = 34, ++ [1][1][2][1][0][10] = 34, ++ [1][1][2][1][0][11] = 0, ++ [1][1][2][1][0][12] = 0, ++ [1][1][2][1][0][13] = 0, ++ [0][0][0][0][2][0] = 76, ++ [0][0][0][0][1][0] = 56, ++ [0][0][0][0][3][0] = 68, ++ [0][0][0][0][5][0] = 76, ++ [0][0][0][0][6][0] = 56, ++ [0][0][0][0][9][0] = 56, ++ [0][0][0][0][8][0] = 60, ++ [0][0][0][0][11][0] = 56, ++ [0][0][0][0][2][1] = 76, ++ [0][0][0][0][1][1] = 56, ++ [0][0][0][0][3][1] = 68, ++ [0][0][0][0][5][1] = 76, ++ [0][0][0][0][6][1] = 56, ++ [0][0][0][0][9][1] = 56, ++ [0][0][0][0][8][1] = 60, ++ [0][0][0][0][11][1] = 56, ++ [0][0][0][0][2][2] = 76, ++ [0][0][0][0][1][2] = 56, ++ [0][0][0][0][3][2] = 68, ++ [0][0][0][0][5][2] = 76, ++ [0][0][0][0][6][2] = 56, ++ [0][0][0][0][9][2] = 56, ++ [0][0][0][0][8][2] = 60, ++ [0][0][0][0][11][2] = 56, ++ [0][0][0][0][2][3] = 76, ++ [0][0][0][0][1][3] = 56, ++ [0][0][0][0][3][3] = 68, ++ [0][0][0][0][5][3] = 76, ++ [0][0][0][0][6][3] = 56, ++ [0][0][0][0][9][3] = 56, ++ [0][0][0][0][8][3] = 60, ++ [0][0][0][0][11][3] = 56, ++ [0][0][0][0][2][4] = 76, ++ [0][0][0][0][1][4] = 56, ++ [0][0][0][0][3][4] = 68, ++ [0][0][0][0][5][4] = 76, ++ [0][0][0][0][6][4] = 56, ++ [0][0][0][0][9][4] = 56, ++ [0][0][0][0][8][4] = 60, ++ [0][0][0][0][11][4] = 56, ++ [0][0][0][0][2][5] = 76, ++ [0][0][0][0][1][5] = 56, ++ [0][0][0][0][3][5] = 68, ++ [0][0][0][0][5][5] = 76, ++ [0][0][0][0][6][5] = 56, ++ [0][0][0][0][9][5] = 56, ++ [0][0][0][0][8][5] = 60, ++ [0][0][0][0][11][5] = 56, ++ [0][0][0][0][2][6] = 76, ++ [0][0][0][0][1][6] = 56, ++ [0][0][0][0][3][6] = 68, ++ [0][0][0][0][5][6] = 76, ++ [0][0][0][0][6][6] = 56, ++ [0][0][0][0][9][6] = 56, ++ [0][0][0][0][8][6] = 60, ++ [0][0][0][0][11][6] = 56, ++ [0][0][0][0][2][7] = 76, ++ [0][0][0][0][1][7] = 56, ++ [0][0][0][0][3][7] = 68, ++ [0][0][0][0][5][7] = 76, ++ [0][0][0][0][6][7] = 56, ++ [0][0][0][0][9][7] = 56, ++ [0][0][0][0][8][7] = 60, ++ [0][0][0][0][11][7] = 56, ++ [0][0][0][0][2][8] = 76, ++ [0][0][0][0][1][8] = 56, ++ [0][0][0][0][3][8] = 68, ++ [0][0][0][0][5][8] = 76, ++ [0][0][0][0][6][8] = 56, ++ [0][0][0][0][9][8] = 56, ++ [0][0][0][0][8][8] = 60, ++ [0][0][0][0][11][8] = 56, ++ [0][0][0][0][2][9] = 76, ++ [0][0][0][0][1][9] = 56, ++ [0][0][0][0][3][9] = 68, ++ [0][0][0][0][5][9] = 76, ++ [0][0][0][0][6][9] = 56, ++ [0][0][0][0][9][9] = 56, ++ [0][0][0][0][8][9] = 60, ++ [0][0][0][0][11][9] = 56, ++ [0][0][0][0][2][10] = 76, ++ [0][0][0][0][1][10] = 56, ++ [0][0][0][0][3][10] = 68, ++ [0][0][0][0][5][10] = 76, ++ [0][0][0][0][6][10] = 56, ++ [0][0][0][0][9][10] = 56, ++ [0][0][0][0][8][10] = 60, ++ [0][0][0][0][11][10] = 56, ++ [0][0][0][0][2][11] = 68, ++ [0][0][0][0][1][11] = 56, ++ [0][0][0][0][3][11] = 68, ++ [0][0][0][0][5][11] = 68, ++ [0][0][0][0][6][11] = 56, ++ [0][0][0][0][9][11] = 56, ++ [0][0][0][0][8][11] = 60, ++ [0][0][0][0][11][11] = 56, ++ [0][0][0][0][2][12] = 48, ++ [0][0][0][0][1][12] = 56, ++ [0][0][0][0][3][12] = 68, ++ [0][0][0][0][5][12] = 48, ++ [0][0][0][0][6][12] = 56, ++ [0][0][0][0][9][12] = 56, ++ [0][0][0][0][8][12] = 60, ++ [0][0][0][0][11][12] = 56, ++ [0][0][0][0][2][13] = 127, ++ [0][0][0][0][1][13] = 127, ++ [0][0][0][0][3][13] = 76, ++ [0][0][0][0][5][13] = 127, ++ [0][0][0][0][6][13] = 127, ++ [0][0][0][0][9][13] = 127, ++ [0][0][0][0][8][13] = 127, ++ [0][0][0][0][11][13] = 127, ++ [0][1][0][0][2][0] = 74, ++ [0][1][0][0][1][0] = 44, ++ [0][1][0][0][3][0] = 56, ++ [0][1][0][0][5][0] = 74, ++ [0][1][0][0][6][0] = 44, ++ [0][1][0][0][9][0] = 44, ++ [0][1][0][0][8][0] = 48, ++ [0][1][0][0][11][0] = 44, ++ [0][1][0][0][2][1] = 76, ++ [0][1][0][0][1][1] = 44, ++ [0][1][0][0][3][1] = 56, ++ [0][1][0][0][5][1] = 76, ++ [0][1][0][0][6][1] = 44, ++ [0][1][0][0][9][1] = 44, ++ [0][1][0][0][8][1] = 48, ++ [0][1][0][0][11][1] = 44, ++ [0][1][0][0][2][2] = 76, ++ [0][1][0][0][1][2] = 44, ++ [0][1][0][0][3][2] = 56, ++ [0][1][0][0][5][2] = 76, ++ [0][1][0][0][6][2] = 44, ++ [0][1][0][0][9][2] = 44, ++ [0][1][0][0][8][2] = 48, ++ [0][1][0][0][11][2] = 44, ++ [0][1][0][0][2][3] = 76, ++ [0][1][0][0][1][3] = 44, ++ [0][1][0][0][3][3] = 56, ++ [0][1][0][0][5][3] = 76, ++ [0][1][0][0][6][3] = 44, ++ [0][1][0][0][9][3] = 44, ++ [0][1][0][0][8][3] = 48, ++ [0][1][0][0][11][3] = 44, ++ [0][1][0][0][2][4] = 76, ++ [0][1][0][0][1][4] = 44, ++ [0][1][0][0][3][4] = 56, ++ [0][1][0][0][5][4] = 76, ++ [0][1][0][0][6][4] = 44, ++ [0][1][0][0][9][4] = 44, ++ [0][1][0][0][8][4] = 48, ++ [0][1][0][0][11][4] = 44, ++ [0][1][0][0][2][5] = 76, ++ [0][1][0][0][1][5] = 44, ++ [0][1][0][0][3][5] = 56, ++ [0][1][0][0][5][5] = 76, ++ [0][1][0][0][6][5] = 44, ++ [0][1][0][0][9][5] = 44, ++ [0][1][0][0][8][5] = 48, ++ [0][1][0][0][11][5] = 44, ++ [0][1][0][0][2][6] = 76, ++ [0][1][0][0][1][6] = 44, ++ [0][1][0][0][3][6] = 56, ++ [0][1][0][0][5][6] = 76, ++ [0][1][0][0][6][6] = 44, ++ [0][1][0][0][9][6] = 44, ++ [0][1][0][0][8][6] = 48, ++ [0][1][0][0][11][6] = 44, ++ [0][1][0][0][2][7] = 76, ++ [0][1][0][0][1][7] = 44, ++ [0][1][0][0][3][7] = 56, ++ [0][1][0][0][5][7] = 76, ++ [0][1][0][0][6][7] = 44, ++ [0][1][0][0][9][7] = 44, ++ [0][1][0][0][8][7] = 48, ++ [0][1][0][0][11][7] = 44, ++ [0][1][0][0][2][8] = 76, ++ [0][1][0][0][1][8] = 44, ++ [0][1][0][0][3][8] = 56, ++ [0][1][0][0][5][8] = 76, ++ [0][1][0][0][6][8] = 44, ++ [0][1][0][0][9][8] = 44, ++ [0][1][0][0][8][8] = 48, ++ [0][1][0][0][11][8] = 44, ++ [0][1][0][0][2][9] = 76, ++ [0][1][0][0][1][9] = 44, ++ [0][1][0][0][3][9] = 56, ++ [0][1][0][0][5][9] = 76, ++ [0][1][0][0][6][9] = 44, ++ [0][1][0][0][9][9] = 44, ++ [0][1][0][0][8][9] = 48, ++ [0][1][0][0][11][9] = 44, ++ [0][1][0][0][2][10] = 62, ++ [0][1][0][0][1][10] = 44, ++ [0][1][0][0][3][10] = 56, ++ [0][1][0][0][5][10] = 62, ++ [0][1][0][0][6][10] = 44, ++ [0][1][0][0][9][10] = 44, ++ [0][1][0][0][8][10] = 48, ++ [0][1][0][0][11][10] = 44, ++ [0][1][0][0][2][11] = 52, ++ [0][1][0][0][1][11] = 44, ++ [0][1][0][0][3][11] = 56, ++ [0][1][0][0][5][11] = 52, ++ [0][1][0][0][6][11] = 44, ++ [0][1][0][0][9][11] = 44, ++ [0][1][0][0][8][11] = 48, ++ [0][1][0][0][11][11] = 44, ++ [0][1][0][0][2][12] = 38, ++ [0][1][0][0][1][12] = 44, ++ [0][1][0][0][3][12] = 56, ++ [0][1][0][0][5][12] = 38, ++ [0][1][0][0][6][12] = 44, ++ [0][1][0][0][9][12] = 44, ++ [0][1][0][0][8][12] = 48, ++ [0][1][0][0][11][12] = 44, ++ [0][1][0][0][2][13] = 127, ++ [0][1][0][0][1][13] = 127, ++ [0][1][0][0][3][13] = 64, ++ [0][1][0][0][5][13] = 127, ++ [0][1][0][0][6][13] = 127, ++ [0][1][0][0][9][13] = 127, ++ [0][1][0][0][8][13] = 127, ++ [0][1][0][0][11][13] = 127, ++ [1][0][0][0][2][0] = 127, ++ [1][0][0][0][1][0] = 127, ++ [1][0][0][0][3][0] = 127, ++ [1][0][0][0][5][0] = 127, ++ [1][0][0][0][6][0] = 127, ++ [1][0][0][0][9][0] = 127, ++ [1][0][0][0][8][0] = 127, ++ [1][0][0][0][11][0] = 127, ++ [1][0][0][0][2][1] = 127, ++ [1][0][0][0][1][1] = 127, ++ [1][0][0][0][3][1] = 127, ++ [1][0][0][0][5][1] = 127, ++ [1][0][0][0][6][1] = 127, ++ [1][0][0][0][9][1] = 127, ++ [1][0][0][0][8][1] = 127, ++ [1][0][0][0][11][1] = 127, ++ [1][0][0][0][2][2] = 60, ++ [1][0][0][0][1][2] = 58, ++ [1][0][0][0][3][2] = 68, ++ [1][0][0][0][5][2] = 60, ++ [1][0][0][0][6][2] = 58, ++ [1][0][0][0][9][2] = 58, ++ [1][0][0][0][8][2] = 60, ++ [1][0][0][0][11][2] = 58, ++ [1][0][0][0][2][3] = 60, ++ [1][0][0][0][1][3] = 58, ++ [1][0][0][0][3][3] = 68, ++ [1][0][0][0][5][3] = 60, ++ [1][0][0][0][6][3] = 58, ++ [1][0][0][0][9][3] = 58, ++ [1][0][0][0][8][3] = 60, ++ [1][0][0][0][11][3] = 58, ++ [1][0][0][0][2][4] = 60, ++ [1][0][0][0][1][4] = 58, ++ [1][0][0][0][3][4] = 68, ++ [1][0][0][0][5][4] = 60, ++ [1][0][0][0][6][4] = 58, ++ [1][0][0][0][9][4] = 58, ++ [1][0][0][0][8][4] = 60, ++ [1][0][0][0][11][4] = 58, ++ [1][0][0][0][2][5] = 60, ++ [1][0][0][0][1][5] = 58, ++ [1][0][0][0][3][5] = 68, ++ [1][0][0][0][5][5] = 60, ++ [1][0][0][0][6][5] = 58, ++ [1][0][0][0][9][5] = 58, ++ [1][0][0][0][8][5] = 60, ++ [1][0][0][0][11][5] = 58, ++ [1][0][0][0][2][6] = 46, ++ [1][0][0][0][1][6] = 58, ++ [1][0][0][0][3][6] = 68, ++ [1][0][0][0][5][6] = 46, ++ [1][0][0][0][6][6] = 58, ++ [1][0][0][0][9][6] = 58, ++ [1][0][0][0][8][6] = 60, ++ [1][0][0][0][11][6] = 58, ++ [1][0][0][0][2][7] = 46, ++ [1][0][0][0][1][7] = 58, ++ [1][0][0][0][3][7] = 68, ++ [1][0][0][0][5][7] = 46, ++ [1][0][0][0][6][7] = 58, ++ [1][0][0][0][9][7] = 58, ++ [1][0][0][0][8][7] = 60, ++ [1][0][0][0][11][7] = 58, ++ [1][0][0][0][2][8] = 46, ++ [1][0][0][0][1][8] = 58, ++ [1][0][0][0][3][8] = 68, ++ [1][0][0][0][5][8] = 46, ++ [1][0][0][0][6][8] = 58, ++ [1][0][0][0][9][8] = 58, ++ [1][0][0][0][8][8] = 60, ++ [1][0][0][0][11][8] = 58, ++ [1][0][0][0][2][9] = 32, ++ [1][0][0][0][1][9] = 58, ++ [1][0][0][0][3][9] = 68, ++ [1][0][0][0][5][9] = 32, ++ [1][0][0][0][6][9] = 58, ++ [1][0][0][0][9][9] = 58, ++ [1][0][0][0][8][9] = 60, ++ [1][0][0][0][11][9] = 58, ++ [1][0][0][0][2][10] = 32, ++ [1][0][0][0][1][10] = 58, ++ [1][0][0][0][3][10] = 68, ++ [1][0][0][0][5][10] = 32, ++ [1][0][0][0][6][10] = 58, ++ [1][0][0][0][9][10] = 58, ++ [1][0][0][0][8][10] = 60, ++ [1][0][0][0][11][10] = 58, ++ [1][0][0][0][2][11] = 127, ++ [1][0][0][0][1][11] = 127, ++ [1][0][0][0][3][11] = 127, ++ [1][0][0][0][5][11] = 127, ++ [1][0][0][0][6][11] = 127, ++ [1][0][0][0][9][11] = 127, ++ [1][0][0][0][8][11] = 127, ++ [1][0][0][0][11][11] = 127, ++ [1][0][0][0][2][12] = 127, ++ [1][0][0][0][1][12] = 127, ++ [1][0][0][0][3][12] = 127, ++ [1][0][0][0][5][12] = 127, ++ [1][0][0][0][6][12] = 127, ++ [1][0][0][0][9][12] = 127, ++ [1][0][0][0][8][12] = 127, ++ [1][0][0][0][11][12] = 127, ++ [1][0][0][0][2][13] = 127, ++ [1][0][0][0][1][13] = 127, ++ [1][0][0][0][3][13] = 127, ++ [1][0][0][0][5][13] = 127, ++ [1][0][0][0][6][13] = 127, ++ [1][0][0][0][9][13] = 127, ++ [1][0][0][0][8][13] = 127, ++ [1][0][0][0][11][13] = 127, ++ [1][1][0][0][2][0] = 127, ++ [1][1][0][0][1][0] = 127, ++ [1][1][0][0][3][0] = 127, ++ [1][1][0][0][5][0] = 127, ++ [1][1][0][0][6][0] = 127, ++ [1][1][0][0][9][0] = 127, ++ [1][1][0][0][8][0] = 127, ++ [1][1][0][0][11][0] = 127, ++ [1][1][0][0][2][1] = 127, ++ [1][1][0][0][1][1] = 127, ++ [1][1][0][0][3][1] = 127, ++ [1][1][0][0][5][1] = 127, ++ [1][1][0][0][6][1] = 127, ++ [1][1][0][0][9][1] = 127, ++ [1][1][0][0][8][1] = 127, ++ [1][1][0][0][11][1] = 127, ++ [1][1][0][0][2][2] = 48, ++ [1][1][0][0][1][2] = 46, ++ [1][1][0][0][3][2] = 56, ++ [1][1][0][0][5][2] = 48, ++ [1][1][0][0][6][2] = 46, ++ [1][1][0][0][9][2] = 46, ++ [1][1][0][0][8][2] = 48, ++ [1][1][0][0][11][2] = 46, ++ [1][1][0][0][2][3] = 48, ++ [1][1][0][0][1][3] = 46, ++ [1][1][0][0][3][3] = 56, ++ [1][1][0][0][5][3] = 48, ++ [1][1][0][0][6][3] = 46, ++ [1][1][0][0][9][3] = 46, ++ [1][1][0][0][8][3] = 48, ++ [1][1][0][0][11][3] = 46, ++ [1][1][0][0][2][4] = 48, ++ [1][1][0][0][1][4] = 46, ++ [1][1][0][0][3][4] = 56, ++ [1][1][0][0][5][4] = 48, ++ [1][1][0][0][6][4] = 46, ++ [1][1][0][0][9][4] = 46, ++ [1][1][0][0][8][4] = 48, ++ [1][1][0][0][11][4] = 46, ++ [1][1][0][0][2][5] = 58, ++ [1][1][0][0][1][5] = 46, ++ [1][1][0][0][3][5] = 56, ++ [1][1][0][0][5][5] = 58, ++ [1][1][0][0][6][5] = 46, ++ [1][1][0][0][9][5] = 46, ++ [1][1][0][0][8][5] = 48, ++ [1][1][0][0][11][5] = 46, ++ [1][1][0][0][2][6] = 46, ++ [1][1][0][0][1][6] = 46, ++ [1][1][0][0][3][6] = 56, ++ [1][1][0][0][5][6] = 46, ++ [1][1][0][0][6][6] = 46, ++ [1][1][0][0][9][6] = 46, ++ [1][1][0][0][8][6] = 48, ++ [1][1][0][0][11][6] = 46, ++ [1][1][0][0][2][7] = 46, ++ [1][1][0][0][1][7] = 46, ++ [1][1][0][0][3][7] = 56, ++ [1][1][0][0][5][7] = 46, ++ [1][1][0][0][6][7] = 46, ++ [1][1][0][0][9][7] = 46, ++ [1][1][0][0][8][7] = 48, ++ [1][1][0][0][11][7] = 46, ++ [1][1][0][0][2][8] = 46, ++ [1][1][0][0][1][8] = 46, ++ [1][1][0][0][3][8] = 56, ++ [1][1][0][0][5][8] = 46, ++ [1][1][0][0][6][8] = 46, ++ [1][1][0][0][9][8] = 46, ++ [1][1][0][0][8][8] = 48, ++ [1][1][0][0][11][8] = 46, ++ [1][1][0][0][2][9] = 24, ++ [1][1][0][0][1][9] = 46, ++ [1][1][0][0][3][9] = 56, ++ [1][1][0][0][5][9] = 24, ++ [1][1][0][0][6][9] = 46, ++ [1][1][0][0][9][9] = 46, ++ [1][1][0][0][8][9] = 48, ++ [1][1][0][0][11][9] = 46, ++ [1][1][0][0][2][10] = 24, ++ [1][1][0][0][1][10] = 46, ++ [1][1][0][0][3][10] = 56, ++ [1][1][0][0][5][10] = 24, ++ [1][1][0][0][6][10] = 46, ++ [1][1][0][0][9][10] = 46, ++ [1][1][0][0][8][10] = 48, ++ [1][1][0][0][11][10] = 46, ++ [1][1][0][0][2][11] = 127, ++ [1][1][0][0][1][11] = 127, ++ [1][1][0][0][3][11] = 127, ++ [1][1][0][0][5][11] = 127, ++ [1][1][0][0][6][11] = 127, ++ [1][1][0][0][9][11] = 127, ++ [1][1][0][0][8][11] = 127, ++ [1][1][0][0][11][11] = 127, ++ [1][1][0][0][2][12] = 127, ++ [1][1][0][0][1][12] = 127, ++ [1][1][0][0][3][12] = 127, ++ [1][1][0][0][5][12] = 127, ++ [1][1][0][0][6][12] = 127, ++ [1][1][0][0][9][12] = 127, ++ [1][1][0][0][8][12] = 127, ++ [1][1][0][0][11][12] = 127, ++ [1][1][0][0][2][13] = 127, ++ [1][1][0][0][1][13] = 127, ++ [1][1][0][0][3][13] = 127, ++ [1][1][0][0][5][13] = 127, ++ [1][1][0][0][6][13] = 127, ++ [1][1][0][0][9][13] = 127, ++ [1][1][0][0][8][13] = 127, ++ [1][1][0][0][11][13] = 127, ++ [0][0][1][0][2][0] = 66, ++ [0][0][1][0][1][0] = 58, ++ [0][0][1][0][3][0] = 76, ++ [0][0][1][0][5][0] = 66, ++ [0][0][1][0][6][0] = 58, ++ [0][0][1][0][9][0] = 58, ++ [0][0][1][0][8][0] = 60, ++ [0][0][1][0][11][0] = 58, ++ [0][0][1][0][2][1] = 66, ++ [0][0][1][0][1][1] = 58, ++ [0][0][1][0][3][1] = 76, ++ [0][0][1][0][5][1] = 66, ++ [0][0][1][0][6][1] = 58, ++ [0][0][1][0][9][1] = 58, ++ [0][0][1][0][8][1] = 60, ++ [0][0][1][0][11][1] = 58, ++ [0][0][1][0][2][2] = 70, ++ [0][0][1][0][1][2] = 58, ++ [0][0][1][0][3][2] = 76, ++ [0][0][1][0][5][2] = 70, ++ [0][0][1][0][6][2] = 58, ++ [0][0][1][0][9][2] = 58, ++ [0][0][1][0][8][2] = 60, ++ [0][0][1][0][11][2] = 58, ++ [0][0][1][0][2][3] = 74, ++ [0][0][1][0][1][3] = 58, ++ [0][0][1][0][3][3] = 76, ++ [0][0][1][0][5][3] = 74, ++ [0][0][1][0][6][3] = 58, ++ [0][0][1][0][9][3] = 58, ++ [0][0][1][0][8][3] = 60, ++ [0][0][1][0][11][3] = 58, ++ [0][0][1][0][2][4] = 78, ++ [0][0][1][0][1][4] = 58, ++ [0][0][1][0][3][4] = 76, ++ [0][0][1][0][5][4] = 78, ++ [0][0][1][0][6][4] = 58, ++ [0][0][1][0][9][4] = 58, ++ [0][0][1][0][8][4] = 60, ++ [0][0][1][0][11][4] = 58, ++ [0][0][1][0][2][5] = 78, ++ [0][0][1][0][1][5] = 58, ++ [0][0][1][0][3][5] = 76, ++ [0][0][1][0][5][5] = 78, ++ [0][0][1][0][6][5] = 58, ++ [0][0][1][0][9][5] = 58, ++ [0][0][1][0][8][5] = 60, ++ [0][0][1][0][11][5] = 58, ++ [0][0][1][0][2][6] = 78, ++ [0][0][1][0][1][6] = 58, ++ [0][0][1][0][3][6] = 76, ++ [0][0][1][0][5][6] = 78, ++ [0][0][1][0][6][6] = 58, ++ [0][0][1][0][9][6] = 58, ++ [0][0][1][0][8][6] = 60, ++ [0][0][1][0][11][6] = 58, ++ [0][0][1][0][2][7] = 74, ++ [0][0][1][0][1][7] = 58, ++ [0][0][1][0][3][7] = 76, ++ [0][0][1][0][5][7] = 74, ++ [0][0][1][0][6][7] = 58, ++ [0][0][1][0][9][7] = 58, ++ [0][0][1][0][8][7] = 60, ++ [0][0][1][0][11][7] = 58, ++ [0][0][1][0][2][8] = 70, ++ [0][0][1][0][1][8] = 58, ++ [0][0][1][0][3][8] = 76, ++ [0][0][1][0][5][8] = 70, ++ [0][0][1][0][6][8] = 58, ++ [0][0][1][0][9][8] = 58, ++ [0][0][1][0][8][8] = 60, ++ [0][0][1][0][11][8] = 58, ++ [0][0][1][0][2][9] = 66, ++ [0][0][1][0][1][9] = 58, ++ [0][0][1][0][3][9] = 76, ++ [0][0][1][0][5][9] = 66, ++ [0][0][1][0][6][9] = 58, ++ [0][0][1][0][9][9] = 58, ++ [0][0][1][0][8][9] = 60, ++ [0][0][1][0][11][9] = 58, ++ [0][0][1][0][2][10] = 66, ++ [0][0][1][0][1][10] = 58, ++ [0][0][1][0][3][10] = 76, ++ [0][0][1][0][5][10] = 66, ++ [0][0][1][0][6][10] = 58, ++ [0][0][1][0][9][10] = 58, ++ [0][0][1][0][8][10] = 60, ++ [0][0][1][0][11][10] = 58, ++ [0][0][1][0][2][11] = 56, ++ [0][0][1][0][1][11] = 58, ++ [0][0][1][0][3][11] = 76, ++ [0][0][1][0][5][11] = 56, ++ [0][0][1][0][6][11] = 58, ++ [0][0][1][0][9][11] = 58, ++ [0][0][1][0][8][11] = 60, ++ [0][0][1][0][11][11] = 58, ++ [0][0][1][0][2][12] = 52, ++ [0][0][1][0][1][12] = 58, ++ [0][0][1][0][3][12] = 76, ++ [0][0][1][0][5][12] = 52, ++ [0][0][1][0][6][12] = 58, ++ [0][0][1][0][9][12] = 58, ++ [0][0][1][0][8][12] = 60, ++ [0][0][1][0][11][12] = 58, ++ [0][0][1][0][2][13] = 127, ++ [0][0][1][0][1][13] = 127, ++ [0][0][1][0][3][13] = 127, ++ [0][0][1][0][5][13] = 127, ++ [0][0][1][0][6][13] = 127, ++ [0][0][1][0][9][13] = 127, ++ [0][0][1][0][8][13] = 127, ++ [0][0][1][0][11][13] = 127, ++ [0][1][1][0][2][0] = 62, ++ [0][1][1][0][1][0] = 46, ++ [0][1][1][0][3][0] = 64, ++ [0][1][1][0][5][0] = 62, ++ [0][1][1][0][6][0] = 46, ++ [0][1][1][0][9][0] = 46, ++ [0][1][1][0][8][0] = 48, ++ [0][1][1][0][11][0] = 46, ++ [0][1][1][0][2][1] = 62, ++ [0][1][1][0][1][1] = 46, ++ [0][1][1][0][3][1] = 64, ++ [0][1][1][0][5][1] = 62, ++ [0][1][1][0][6][1] = 46, ++ [0][1][1][0][9][1] = 46, ++ [0][1][1][0][8][1] = 48, ++ [0][1][1][0][11][1] = 46, ++ [0][1][1][0][2][2] = 66, ++ [0][1][1][0][1][2] = 46, ++ [0][1][1][0][3][2] = 64, ++ [0][1][1][0][5][2] = 66, ++ [0][1][1][0][6][2] = 46, ++ [0][1][1][0][9][2] = 46, ++ [0][1][1][0][8][2] = 48, ++ [0][1][1][0][11][2] = 46, ++ [0][1][1][0][2][3] = 70, ++ [0][1][1][0][1][3] = 46, ++ [0][1][1][0][3][3] = 64, ++ [0][1][1][0][5][3] = 70, ++ [0][1][1][0][6][3] = 46, ++ [0][1][1][0][9][3] = 46, ++ [0][1][1][0][8][3] = 48, ++ [0][1][1][0][11][3] = 46, ++ [0][1][1][0][2][4] = 78, ++ [0][1][1][0][1][4] = 46, ++ [0][1][1][0][3][4] = 64, ++ [0][1][1][0][5][4] = 78, ++ [0][1][1][0][6][4] = 46, ++ [0][1][1][0][9][4] = 46, ++ [0][1][1][0][8][4] = 48, ++ [0][1][1][0][11][4] = 46, ++ [0][1][1][0][2][5] = 78, ++ [0][1][1][0][1][5] = 46, ++ [0][1][1][0][3][5] = 64, ++ [0][1][1][0][5][5] = 78, ++ [0][1][1][0][6][5] = 46, ++ [0][1][1][0][9][5] = 46, ++ [0][1][1][0][8][5] = 48, ++ [0][1][1][0][11][5] = 46, ++ [0][1][1][0][2][6] = 78, ++ [0][1][1][0][1][6] = 46, ++ [0][1][1][0][3][6] = 64, ++ [0][1][1][0][5][6] = 78, ++ [0][1][1][0][6][6] = 46, ++ [0][1][1][0][9][6] = 46, ++ [0][1][1][0][8][6] = 48, ++ [0][1][1][0][11][6] = 46, ++ [0][1][1][0][2][7] = 70, ++ [0][1][1][0][1][7] = 46, ++ [0][1][1][0][3][7] = 64, ++ [0][1][1][0][5][7] = 70, ++ [0][1][1][0][6][7] = 46, ++ [0][1][1][0][9][7] = 46, ++ [0][1][1][0][8][7] = 48, ++ [0][1][1][0][11][7] = 46, ++ [0][1][1][0][2][8] = 66, ++ [0][1][1][0][1][8] = 46, ++ [0][1][1][0][3][8] = 64, ++ [0][1][1][0][5][8] = 66, ++ [0][1][1][0][6][8] = 46, ++ [0][1][1][0][9][8] = 46, ++ [0][1][1][0][8][8] = 48, ++ [0][1][1][0][11][8] = 46, ++ [0][1][1][0][2][9] = 62, ++ [0][1][1][0][1][9] = 46, ++ [0][1][1][0][3][9] = 64, ++ [0][1][1][0][5][9] = 62, ++ [0][1][1][0][6][9] = 46, ++ [0][1][1][0][9][9] = 46, ++ [0][1][1][0][8][9] = 48, ++ [0][1][1][0][11][9] = 46, ++ [0][1][1][0][2][10] = 62, ++ [0][1][1][0][1][10] = 46, ++ [0][1][1][0][3][10] = 64, ++ [0][1][1][0][5][10] = 62, ++ [0][1][1][0][6][10] = 46, ++ [0][1][1][0][9][10] = 46, ++ [0][1][1][0][8][10] = 48, ++ [0][1][1][0][11][10] = 46, ++ [0][1][1][0][2][11] = 42, ++ [0][1][1][0][1][11] = 46, ++ [0][1][1][0][3][11] = 64, ++ [0][1][1][0][5][11] = 42, ++ [0][1][1][0][6][11] = 46, ++ [0][1][1][0][9][11] = 46, ++ [0][1][1][0][8][11] = 48, ++ [0][1][1][0][11][11] = 46, ++ [0][1][1][0][2][12] = 40, ++ [0][1][1][0][1][12] = 46, ++ [0][1][1][0][3][12] = 64, ++ [0][1][1][0][5][12] = 40, ++ [0][1][1][0][6][12] = 46, ++ [0][1][1][0][9][12] = 46, ++ [0][1][1][0][8][12] = 48, ++ [0][1][1][0][11][12] = 46, ++ [0][1][1][0][2][13] = 127, ++ [0][1][1][0][1][13] = 127, ++ [0][1][1][0][3][13] = 127, ++ [0][1][1][0][5][13] = 127, ++ [0][1][1][0][6][13] = 127, ++ [0][1][1][0][9][13] = 127, ++ [0][1][1][0][8][13] = 127, ++ [0][1][1][0][11][13] = 127, ++ [0][0][2][0][2][0] = 66, ++ [0][0][2][0][1][0] = 58, ++ [0][0][2][0][3][0] = 76, ++ [0][0][2][0][5][0] = 66, ++ [0][0][2][0][6][0] = 58, ++ [0][0][2][0][9][0] = 58, ++ [0][0][2][0][8][0] = 60, ++ [0][0][2][0][11][0] = 58, ++ [0][0][2][0][2][1] = 66, ++ [0][0][2][0][1][1] = 58, ++ [0][0][2][0][3][1] = 76, ++ [0][0][2][0][5][1] = 66, ++ [0][0][2][0][6][1] = 58, ++ [0][0][2][0][9][1] = 58, ++ [0][0][2][0][8][1] = 60, ++ [0][0][2][0][11][1] = 58, ++ [0][0][2][0][2][2] = 70, ++ [0][0][2][0][1][2] = 58, ++ [0][0][2][0][3][2] = 76, ++ [0][0][2][0][5][2] = 70, ++ [0][0][2][0][6][2] = 58, ++ [0][0][2][0][9][2] = 58, ++ [0][0][2][0][8][2] = 60, ++ [0][0][2][0][11][2] = 58, ++ [0][0][2][0][2][3] = 74, ++ [0][0][2][0][1][3] = 58, ++ [0][0][2][0][3][3] = 76, ++ [0][0][2][0][5][3] = 74, ++ [0][0][2][0][6][3] = 58, ++ [0][0][2][0][9][3] = 58, ++ [0][0][2][0][8][3] = 60, ++ [0][0][2][0][11][3] = 58, ++ [0][0][2][0][2][4] = 76, ++ [0][0][2][0][1][4] = 58, ++ [0][0][2][0][3][4] = 76, ++ [0][0][2][0][5][4] = 76, ++ [0][0][2][0][6][4] = 58, ++ [0][0][2][0][9][4] = 58, ++ [0][0][2][0][8][4] = 60, ++ [0][0][2][0][11][4] = 58, ++ [0][0][2][0][2][5] = 76, ++ [0][0][2][0][1][5] = 58, ++ [0][0][2][0][3][5] = 76, ++ [0][0][2][0][5][5] = 76, ++ [0][0][2][0][6][5] = 58, ++ [0][0][2][0][9][5] = 58, ++ [0][0][2][0][8][5] = 60, ++ [0][0][2][0][11][5] = 58, ++ [0][0][2][0][2][6] = 76, ++ [0][0][2][0][1][6] = 58, ++ [0][0][2][0][3][6] = 76, ++ [0][0][2][0][5][6] = 76, ++ [0][0][2][0][6][6] = 58, ++ [0][0][2][0][9][6] = 58, ++ [0][0][2][0][8][6] = 60, ++ [0][0][2][0][11][6] = 58, ++ [0][0][2][0][2][7] = 74, ++ [0][0][2][0][1][7] = 58, ++ [0][0][2][0][3][7] = 76, ++ [0][0][2][0][5][7] = 74, ++ [0][0][2][0][6][7] = 58, ++ [0][0][2][0][9][7] = 58, ++ [0][0][2][0][8][7] = 60, ++ [0][0][2][0][11][7] = 58, ++ [0][0][2][0][2][8] = 70, ++ [0][0][2][0][1][8] = 58, ++ [0][0][2][0][3][8] = 76, ++ [0][0][2][0][5][8] = 70, ++ [0][0][2][0][6][8] = 58, ++ [0][0][2][0][9][8] = 58, ++ [0][0][2][0][8][8] = 60, ++ [0][0][2][0][11][8] = 58, ++ [0][0][2][0][2][9] = 66, ++ [0][0][2][0][1][9] = 58, ++ [0][0][2][0][3][9] = 76, ++ [0][0][2][0][5][9] = 66, ++ [0][0][2][0][6][9] = 58, ++ [0][0][2][0][9][9] = 58, ++ [0][0][2][0][8][9] = 60, ++ [0][0][2][0][11][9] = 58, ++ [0][0][2][0][2][10] = 66, ++ [0][0][2][0][1][10] = 58, ++ [0][0][2][0][3][10] = 76, ++ [0][0][2][0][5][10] = 66, ++ [0][0][2][0][6][10] = 58, ++ [0][0][2][0][9][10] = 58, ++ [0][0][2][0][8][10] = 60, ++ [0][0][2][0][11][10] = 58, ++ [0][0][2][0][2][11] = 54, ++ [0][0][2][0][1][11] = 58, ++ [0][0][2][0][3][11] = 76, ++ [0][0][2][0][5][11] = 54, ++ [0][0][2][0][6][11] = 58, ++ [0][0][2][0][9][11] = 58, ++ [0][0][2][0][8][11] = 60, ++ [0][0][2][0][11][11] = 58, ++ [0][0][2][0][2][12] = 50, ++ [0][0][2][0][1][12] = 58, ++ [0][0][2][0][3][12] = 76, ++ [0][0][2][0][5][12] = 50, ++ [0][0][2][0][6][12] = 58, ++ [0][0][2][0][9][12] = 58, ++ [0][0][2][0][8][12] = 60, ++ [0][0][2][0][11][12] = 58, ++ [0][0][2][0][2][13] = 127, ++ [0][0][2][0][1][13] = 127, ++ [0][0][2][0][3][13] = 127, ++ [0][0][2][0][5][13] = 127, ++ [0][0][2][0][6][13] = 127, ++ [0][0][2][0][9][13] = 127, ++ [0][0][2][0][8][13] = 127, ++ [0][0][2][0][11][13] = 127, ++ [0][1][2][0][2][0] = 62, ++ [0][1][2][0][1][0] = 46, ++ [0][1][2][0][3][0] = 64, ++ [0][1][2][0][5][0] = 62, ++ [0][1][2][0][6][0] = 46, ++ [0][1][2][0][9][0] = 46, ++ [0][1][2][0][8][0] = 48, ++ [0][1][2][0][11][0] = 46, ++ [0][1][2][0][2][1] = 62, ++ [0][1][2][0][1][1] = 46, ++ [0][1][2][0][3][1] = 64, ++ [0][1][2][0][5][1] = 62, ++ [0][1][2][0][6][1] = 46, ++ [0][1][2][0][9][1] = 46, ++ [0][1][2][0][8][1] = 48, ++ [0][1][2][0][11][1] = 46, ++ [0][1][2][0][2][2] = 66, ++ [0][1][2][0][1][2] = 46, ++ [0][1][2][0][3][2] = 64, ++ [0][1][2][0][5][2] = 66, ++ [0][1][2][0][6][2] = 46, ++ [0][1][2][0][9][2] = 46, ++ [0][1][2][0][8][2] = 48, ++ [0][1][2][0][11][2] = 46, ++ [0][1][2][0][2][3] = 70, ++ [0][1][2][0][1][3] = 46, ++ [0][1][2][0][3][3] = 64, ++ [0][1][2][0][5][3] = 70, ++ [0][1][2][0][6][3] = 46, ++ [0][1][2][0][9][3] = 46, ++ [0][1][2][0][8][3] = 48, ++ [0][1][2][0][11][3] = 46, ++ [0][1][2][0][2][4] = 76, ++ [0][1][2][0][1][4] = 46, ++ [0][1][2][0][3][4] = 64, ++ [0][1][2][0][5][4] = 76, ++ [0][1][2][0][6][4] = 46, ++ [0][1][2][0][9][4] = 46, ++ [0][1][2][0][8][4] = 48, ++ [0][1][2][0][11][4] = 46, ++ [0][1][2][0][2][5] = 76, ++ [0][1][2][0][1][5] = 46, ++ [0][1][2][0][3][5] = 64, ++ [0][1][2][0][5][5] = 76, ++ [0][1][2][0][6][5] = 46, ++ [0][1][2][0][9][5] = 46, ++ [0][1][2][0][8][5] = 48, ++ [0][1][2][0][11][5] = 46, ++ [0][1][2][0][2][6] = 76, ++ [0][1][2][0][1][6] = 46, ++ [0][1][2][0][3][6] = 64, ++ [0][1][2][0][5][6] = 76, ++ [0][1][2][0][6][6] = 46, ++ [0][1][2][0][9][6] = 46, ++ [0][1][2][0][8][6] = 48, ++ [0][1][2][0][11][6] = 46, ++ [0][1][2][0][2][7] = 68, ++ [0][1][2][0][1][7] = 46, ++ [0][1][2][0][3][7] = 64, ++ [0][1][2][0][5][7] = 68, ++ [0][1][2][0][6][7] = 46, ++ [0][1][2][0][9][7] = 46, ++ [0][1][2][0][8][7] = 48, ++ [0][1][2][0][11][7] = 46, ++ [0][1][2][0][2][8] = 64, ++ [0][1][2][0][1][8] = 46, ++ [0][1][2][0][3][8] = 64, ++ [0][1][2][0][5][8] = 64, ++ [0][1][2][0][6][8] = 46, ++ [0][1][2][0][9][8] = 46, ++ [0][1][2][0][8][8] = 48, ++ [0][1][2][0][11][8] = 46, ++ [0][1][2][0][2][9] = 60, ++ [0][1][2][0][1][9] = 46, ++ [0][1][2][0][3][9] = 64, ++ [0][1][2][0][5][9] = 60, ++ [0][1][2][0][6][9] = 46, ++ [0][1][2][0][9][9] = 46, ++ [0][1][2][0][8][9] = 48, ++ [0][1][2][0][11][9] = 46, ++ [0][1][2][0][2][10] = 60, ++ [0][1][2][0][1][10] = 46, ++ [0][1][2][0][3][10] = 64, ++ [0][1][2][0][5][10] = 60, ++ [0][1][2][0][6][10] = 46, ++ [0][1][2][0][9][10] = 46, ++ [0][1][2][0][8][10] = 48, ++ [0][1][2][0][11][10] = 46, ++ [0][1][2][0][2][11] = 42, ++ [0][1][2][0][1][11] = 46, ++ [0][1][2][0][3][11] = 64, ++ [0][1][2][0][5][11] = 42, ++ [0][1][2][0][6][11] = 46, ++ [0][1][2][0][9][11] = 46, ++ [0][1][2][0][8][11] = 48, ++ [0][1][2][0][11][11] = 46, ++ [0][1][2][0][2][12] = 40, ++ [0][1][2][0][1][12] = 46, ++ [0][1][2][0][3][12] = 64, ++ [0][1][2][0][5][12] = 40, ++ [0][1][2][0][6][12] = 46, ++ [0][1][2][0][9][12] = 46, ++ [0][1][2][0][8][12] = 48, ++ [0][1][2][0][11][12] = 46, ++ [0][1][2][0][2][13] = 127, ++ [0][1][2][0][1][13] = 127, ++ [0][1][2][0][3][13] = 127, ++ [0][1][2][0][5][13] = 127, ++ [0][1][2][0][6][13] = 127, ++ [0][1][2][0][9][13] = 127, ++ [0][1][2][0][8][13] = 127, ++ [0][1][2][0][11][13] = 127, ++ [0][1][2][1][2][0] = 62, ++ [0][1][2][1][1][0] = 34, ++ [0][1][2][1][3][0] = 64, ++ [0][1][2][1][5][0] = 62, ++ [0][1][2][1][6][0] = 34, ++ [0][1][2][1][9][0] = 34, ++ [0][1][2][1][8][0] = 36, ++ [0][1][2][1][11][0] = 34, ++ [0][1][2][1][2][1] = 62, ++ [0][1][2][1][1][1] = 34, ++ [0][1][2][1][3][1] = 64, ++ [0][1][2][1][5][1] = 62, ++ [0][1][2][1][6][1] = 34, ++ [0][1][2][1][9][1] = 34, ++ [0][1][2][1][8][1] = 36, ++ [0][1][2][1][11][1] = 34, ++ [0][1][2][1][2][2] = 66, ++ [0][1][2][1][1][2] = 34, ++ [0][1][2][1][3][2] = 64, ++ [0][1][2][1][5][2] = 66, ++ [0][1][2][1][6][2] = 34, ++ [0][1][2][1][9][2] = 34, ++ [0][1][2][1][8][2] = 36, ++ [0][1][2][1][11][2] = 34, ++ [0][1][2][1][2][3] = 70, ++ [0][1][2][1][1][3] = 34, ++ [0][1][2][1][3][3] = 64, ++ [0][1][2][1][5][3] = 70, ++ [0][1][2][1][6][3] = 34, ++ [0][1][2][1][9][3] = 34, ++ [0][1][2][1][8][3] = 36, ++ [0][1][2][1][11][3] = 34, ++ [0][1][2][1][2][4] = 76, ++ [0][1][2][1][1][4] = 34, ++ [0][1][2][1][3][4] = 64, ++ [0][1][2][1][5][4] = 76, ++ [0][1][2][1][6][4] = 34, ++ [0][1][2][1][9][4] = 34, ++ [0][1][2][1][8][4] = 36, ++ [0][1][2][1][11][4] = 34, ++ [0][1][2][1][2][5] = 76, ++ [0][1][2][1][1][5] = 34, ++ [0][1][2][1][3][5] = 64, ++ [0][1][2][1][5][5] = 76, ++ [0][1][2][1][6][5] = 34, ++ [0][1][2][1][9][5] = 34, ++ [0][1][2][1][8][5] = 36, ++ [0][1][2][1][11][5] = 34, ++ [0][1][2][1][2][6] = 76, ++ [0][1][2][1][1][6] = 34, ++ [0][1][2][1][3][6] = 64, ++ [0][1][2][1][5][6] = 76, ++ [0][1][2][1][6][6] = 34, ++ [0][1][2][1][9][6] = 34, ++ [0][1][2][1][8][6] = 36, ++ [0][1][2][1][11][6] = 34, ++ [0][1][2][1][2][7] = 68, ++ [0][1][2][1][1][7] = 34, ++ [0][1][2][1][3][7] = 64, ++ [0][1][2][1][5][7] = 68, ++ [0][1][2][1][6][7] = 34, ++ [0][1][2][1][9][7] = 34, ++ [0][1][2][1][8][7] = 36, ++ [0][1][2][1][11][7] = 34, ++ [0][1][2][1][2][8] = 64, ++ [0][1][2][1][1][8] = 34, ++ [0][1][2][1][3][8] = 64, ++ [0][1][2][1][5][8] = 64, ++ [0][1][2][1][6][8] = 34, ++ [0][1][2][1][9][8] = 34, ++ [0][1][2][1][8][8] = 36, ++ [0][1][2][1][11][8] = 34, ++ [0][1][2][1][2][9] = 60, ++ [0][1][2][1][1][9] = 34, ++ [0][1][2][1][3][9] = 64, ++ [0][1][2][1][5][9] = 60, ++ [0][1][2][1][6][9] = 34, ++ [0][1][2][1][9][9] = 34, ++ [0][1][2][1][8][9] = 36, ++ [0][1][2][1][11][9] = 34, ++ [0][1][2][1][2][10] = 60, ++ [0][1][2][1][1][10] = 34, ++ [0][1][2][1][3][10] = 64, ++ [0][1][2][1][5][10] = 60, ++ [0][1][2][1][6][10] = 34, ++ [0][1][2][1][9][10] = 34, ++ [0][1][2][1][8][10] = 36, ++ [0][1][2][1][11][10] = 34, ++ [0][1][2][1][2][11] = 42, ++ [0][1][2][1][1][11] = 34, ++ [0][1][2][1][3][11] = 64, ++ [0][1][2][1][5][11] = 42, ++ [0][1][2][1][6][11] = 34, ++ [0][1][2][1][9][11] = 34, ++ [0][1][2][1][8][11] = 36, ++ [0][1][2][1][11][11] = 34, ++ [0][1][2][1][2][12] = 40, ++ [0][1][2][1][1][12] = 34, ++ [0][1][2][1][3][12] = 64, ++ [0][1][2][1][5][12] = 40, ++ [0][1][2][1][6][12] = 34, ++ [0][1][2][1][9][12] = 34, ++ [0][1][2][1][8][12] = 36, ++ [0][1][2][1][11][12] = 34, ++ [0][1][2][1][2][13] = 127, ++ [0][1][2][1][1][13] = 127, ++ [0][1][2][1][3][13] = 127, ++ [0][1][2][1][5][13] = 127, ++ [0][1][2][1][6][13] = 127, ++ [0][1][2][1][9][13] = 127, ++ [0][1][2][1][8][13] = 127, ++ [0][1][2][1][11][13] = 127, ++ [1][0][2][0][2][0] = 127, ++ [1][0][2][0][1][0] = 127, ++ [1][0][2][0][3][0] = 127, ++ [1][0][2][0][5][0] = 127, ++ [1][0][2][0][6][0] = 127, ++ [1][0][2][0][9][0] = 127, ++ [1][0][2][0][8][0] = 127, ++ [1][0][2][0][11][0] = 127, ++ [1][0][2][0][2][1] = 127, ++ [1][0][2][0][1][1] = 127, ++ [1][0][2][0][3][1] = 127, ++ [1][0][2][0][5][1] = 127, ++ [1][0][2][0][6][1] = 127, ++ [1][0][2][0][9][1] = 127, ++ [1][0][2][0][8][1] = 127, ++ [1][0][2][0][11][1] = 127, ++ [1][0][2][0][2][2] = 56, ++ [1][0][2][0][1][2] = 58, ++ [1][0][2][0][3][2] = 76, ++ [1][0][2][0][5][2] = 56, ++ [1][0][2][0][6][2] = 58, ++ [1][0][2][0][9][2] = 58, ++ [1][0][2][0][8][2] = 60, ++ [1][0][2][0][11][2] = 58, ++ [1][0][2][0][2][3] = 56, ++ [1][0][2][0][1][3] = 58, ++ [1][0][2][0][3][3] = 76, ++ [1][0][2][0][5][3] = 56, ++ [1][0][2][0][6][3] = 58, ++ [1][0][2][0][9][3] = 58, ++ [1][0][2][0][8][3] = 60, ++ [1][0][2][0][11][3] = 58, ++ [1][0][2][0][2][4] = 60, ++ [1][0][2][0][1][4] = 58, ++ [1][0][2][0][3][4] = 76, ++ [1][0][2][0][5][4] = 60, ++ [1][0][2][0][6][4] = 58, ++ [1][0][2][0][9][4] = 58, ++ [1][0][2][0][8][4] = 60, ++ [1][0][2][0][11][4] = 58, ++ [1][0][2][0][2][5] = 64, ++ [1][0][2][0][1][5] = 58, ++ [1][0][2][0][3][5] = 76, ++ [1][0][2][0][5][5] = 64, ++ [1][0][2][0][6][5] = 58, ++ [1][0][2][0][9][5] = 58, ++ [1][0][2][0][8][5] = 60, ++ [1][0][2][0][11][5] = 58, ++ [1][0][2][0][2][6] = 54, ++ [1][0][2][0][1][6] = 58, ++ [1][0][2][0][3][6] = 76, ++ [1][0][2][0][5][6] = 54, ++ [1][0][2][0][6][6] = 58, ++ [1][0][2][0][9][6] = 58, ++ [1][0][2][0][8][6] = 60, ++ [1][0][2][0][11][6] = 58, ++ [1][0][2][0][2][7] = 50, ++ [1][0][2][0][1][7] = 58, ++ [1][0][2][0][3][7] = 76, ++ [1][0][2][0][5][7] = 50, ++ [1][0][2][0][6][7] = 58, ++ [1][0][2][0][9][7] = 58, ++ [1][0][2][0][8][7] = 60, ++ [1][0][2][0][11][7] = 58, ++ [1][0][2][0][2][8] = 50, ++ [1][0][2][0][1][8] = 58, ++ [1][0][2][0][3][8] = 76, ++ [1][0][2][0][5][8] = 50, ++ [1][0][2][0][6][8] = 58, ++ [1][0][2][0][9][8] = 58, ++ [1][0][2][0][8][8] = 60, ++ [1][0][2][0][11][8] = 58, ++ [1][0][2][0][2][9] = 42, ++ [1][0][2][0][1][9] = 58, ++ [1][0][2][0][3][9] = 76, ++ [1][0][2][0][5][9] = 42, ++ [1][0][2][0][6][9] = 58, ++ [1][0][2][0][9][9] = 58, ++ [1][0][2][0][8][9] = 60, ++ [1][0][2][0][11][9] = 58, ++ [1][0][2][0][2][10] = 40, ++ [1][0][2][0][1][10] = 58, ++ [1][0][2][0][3][10] = 76, ++ [1][0][2][0][5][10] = 40, ++ [1][0][2][0][6][10] = 58, ++ [1][0][2][0][9][10] = 58, ++ [1][0][2][0][8][10] = 60, ++ [1][0][2][0][11][10] = 58, ++ [1][0][2][0][2][11] = 127, ++ [1][0][2][0][1][11] = 127, ++ [1][0][2][0][3][11] = 127, ++ [1][0][2][0][5][11] = 127, ++ [1][0][2][0][6][11] = 127, ++ [1][0][2][0][9][11] = 127, ++ [1][0][2][0][8][11] = 127, ++ [1][0][2][0][11][11] = 127, ++ [1][0][2][0][2][12] = 127, ++ [1][0][2][0][1][12] = 127, ++ [1][0][2][0][3][12] = 127, ++ [1][0][2][0][5][12] = 127, ++ [1][0][2][0][6][12] = 127, ++ [1][0][2][0][9][12] = 127, ++ [1][0][2][0][8][12] = 127, ++ [1][0][2][0][11][12] = 127, ++ [1][0][2][0][2][13] = 127, ++ [1][0][2][0][1][13] = 127, ++ [1][0][2][0][3][13] = 127, ++ [1][0][2][0][5][13] = 127, ++ [1][0][2][0][6][13] = 127, ++ [1][0][2][0][9][13] = 127, ++ [1][0][2][0][8][13] = 127, ++ [1][0][2][0][11][13] = 127, ++ [1][1][2][0][2][0] = 127, ++ [1][1][2][0][1][0] = 127, ++ [1][1][2][0][3][0] = 127, ++ [1][1][2][0][5][0] = 127, ++ [1][1][2][0][6][0] = 127, ++ [1][1][2][0][9][0] = 127, ++ [1][1][2][0][8][0] = 127, ++ [1][1][2][0][11][0] = 127, ++ [1][1][2][0][2][1] = 127, ++ [1][1][2][0][1][1] = 127, ++ [1][1][2][0][3][1] = 127, ++ [1][1][2][0][5][1] = 127, ++ [1][1][2][0][6][1] = 127, ++ [1][1][2][0][9][1] = 127, ++ [1][1][2][0][8][1] = 127, ++ [1][1][2][0][11][1] = 127, ++ [1][1][2][0][2][2] = 52, ++ [1][1][2][0][1][2] = 46, ++ [1][1][2][0][3][2] = 64, ++ [1][1][2][0][5][2] = 52, ++ [1][1][2][0][6][2] = 46, ++ [1][1][2][0][9][2] = 46, ++ [1][1][2][0][8][2] = 48, ++ [1][1][2][0][11][2] = 46, ++ [1][1][2][0][2][3] = 52, ++ [1][1][2][0][1][3] = 46, ++ [1][1][2][0][3][3] = 64, ++ [1][1][2][0][5][3] = 52, ++ [1][1][2][0][6][3] = 46, ++ [1][1][2][0][9][3] = 46, ++ [1][1][2][0][8][3] = 48, ++ [1][1][2][0][11][3] = 46, ++ [1][1][2][0][2][4] = 56, ++ [1][1][2][0][1][4] = 46, ++ [1][1][2][0][3][4] = 64, ++ [1][1][2][0][5][4] = 56, ++ [1][1][2][0][6][4] = 46, ++ [1][1][2][0][9][4] = 46, ++ [1][1][2][0][8][4] = 48, ++ [1][1][2][0][11][4] = 46, ++ [1][1][2][0][2][5] = 60, ++ [1][1][2][0][1][5] = 46, ++ [1][1][2][0][3][5] = 64, ++ [1][1][2][0][5][5] = 60, ++ [1][1][2][0][6][5] = 46, ++ [1][1][2][0][9][5] = 46, ++ [1][1][2][0][8][5] = 48, ++ [1][1][2][0][11][5] = 46, ++ [1][1][2][0][2][6] = 54, ++ [1][1][2][0][1][6] = 46, ++ [1][1][2][0][3][6] = 64, ++ [1][1][2][0][5][6] = 52, ++ [1][1][2][0][6][6] = 46, ++ [1][1][2][0][9][6] = 46, ++ [1][1][2][0][8][6] = 48, ++ [1][1][2][0][11][6] = 46, ++ [1][1][2][0][2][7] = 50, ++ [1][1][2][0][1][7] = 46, ++ [1][1][2][0][3][7] = 64, ++ [1][1][2][0][5][7] = 48, ++ [1][1][2][0][6][7] = 46, ++ [1][1][2][0][9][7] = 46, ++ [1][1][2][0][8][7] = 48, ++ [1][1][2][0][11][7] = 46, ++ [1][1][2][0][2][8] = 50, ++ [1][1][2][0][1][8] = 46, ++ [1][1][2][0][3][8] = 64, ++ [1][1][2][0][5][8] = 48, ++ [1][1][2][0][6][8] = 46, ++ [1][1][2][0][9][8] = 46, ++ [1][1][2][0][8][8] = 48, ++ [1][1][2][0][11][8] = 46, ++ [1][1][2][0][2][9] = 38, ++ [1][1][2][0][1][9] = 46, ++ [1][1][2][0][3][9] = 64, ++ [1][1][2][0][5][9] = 38, ++ [1][1][2][0][6][9] = 46, ++ [1][1][2][0][9][9] = 46, ++ [1][1][2][0][8][9] = 48, ++ [1][1][2][0][11][9] = 46, ++ [1][1][2][0][2][10] = 36, ++ [1][1][2][0][1][10] = 46, ++ [1][1][2][0][3][10] = 64, ++ [1][1][2][0][5][10] = 36, ++ [1][1][2][0][6][10] = 46, ++ [1][1][2][0][9][10] = 46, ++ [1][1][2][0][8][10] = 48, ++ [1][1][2][0][11][10] = 46, ++ [1][1][2][0][2][11] = 127, ++ [1][1][2][0][1][11] = 127, ++ [1][1][2][0][3][11] = 127, ++ [1][1][2][0][5][11] = 127, ++ [1][1][2][0][6][11] = 127, ++ [1][1][2][0][9][11] = 127, ++ [1][1][2][0][8][11] = 127, ++ [1][1][2][0][11][11] = 127, ++ [1][1][2][0][2][12] = 127, ++ [1][1][2][0][1][12] = 127, ++ [1][1][2][0][3][12] = 127, ++ [1][1][2][0][5][12] = 127, ++ [1][1][2][0][6][12] = 127, ++ [1][1][2][0][9][12] = 127, ++ [1][1][2][0][8][12] = 127, ++ [1][1][2][0][11][12] = 127, ++ [1][1][2][0][2][13] = 127, ++ [1][1][2][0][1][13] = 127, ++ [1][1][2][0][3][13] = 127, ++ [1][1][2][0][5][13] = 127, ++ [1][1][2][0][6][13] = 127, ++ [1][1][2][0][9][13] = 127, ++ [1][1][2][0][8][13] = 127, ++ [1][1][2][0][11][13] = 127, ++ [1][1][2][1][2][0] = 127, ++ [1][1][2][1][1][0] = 127, ++ [1][1][2][1][3][0] = 127, ++ [1][1][2][1][5][0] = 127, ++ [1][1][2][1][6][0] = 127, ++ [1][1][2][1][9][0] = 127, ++ [1][1][2][1][8][0] = 127, ++ [1][1][2][1][11][0] = 127, ++ [1][1][2][1][2][1] = 127, ++ [1][1][2][1][1][1] = 127, ++ [1][1][2][1][3][1] = 127, ++ [1][1][2][1][5][1] = 127, ++ [1][1][2][1][6][1] = 127, ++ [1][1][2][1][9][1] = 127, ++ [1][1][2][1][8][1] = 127, ++ [1][1][2][1][11][1] = 127, ++ [1][1][2][1][2][2] = 52, ++ [1][1][2][1][1][2] = 34, ++ [1][1][2][1][3][2] = 64, ++ [1][1][2][1][5][2] = 52, ++ [1][1][2][1][6][2] = 34, ++ [1][1][2][1][9][2] = 34, ++ [1][1][2][1][8][2] = 36, ++ [1][1][2][1][11][2] = 34, ++ [1][1][2][1][2][3] = 52, ++ [1][1][2][1][1][3] = 34, ++ [1][1][2][1][3][3] = 64, ++ [1][1][2][1][5][3] = 52, ++ [1][1][2][1][6][3] = 34, ++ [1][1][2][1][9][3] = 34, ++ [1][1][2][1][8][3] = 36, ++ [1][1][2][1][11][3] = 34, ++ [1][1][2][1][2][4] = 56, ++ [1][1][2][1][1][4] = 34, ++ [1][1][2][1][3][4] = 64, ++ [1][1][2][1][5][4] = 56, ++ [1][1][2][1][6][4] = 34, ++ [1][1][2][1][9][4] = 34, ++ [1][1][2][1][8][4] = 36, ++ [1][1][2][1][11][4] = 34, ++ [1][1][2][1][2][5] = 60, ++ [1][1][2][1][1][5] = 34, ++ [1][1][2][1][3][5] = 64, ++ [1][1][2][1][5][5] = 60, ++ [1][1][2][1][6][5] = 34, ++ [1][1][2][1][9][5] = 34, ++ [1][1][2][1][8][5] = 36, ++ [1][1][2][1][11][5] = 34, ++ [1][1][2][1][2][6] = 54, ++ [1][1][2][1][1][6] = 34, ++ [1][1][2][1][3][6] = 64, ++ [1][1][2][1][5][6] = 52, ++ [1][1][2][1][6][6] = 34, ++ [1][1][2][1][9][6] = 34, ++ [1][1][2][1][8][6] = 36, ++ [1][1][2][1][11][6] = 34, ++ [1][1][2][1][2][7] = 50, ++ [1][1][2][1][1][7] = 34, ++ [1][1][2][1][3][7] = 64, ++ [1][1][2][1][5][7] = 48, ++ [1][1][2][1][6][7] = 34, ++ [1][1][2][1][9][7] = 34, ++ [1][1][2][1][8][7] = 36, ++ [1][1][2][1][11][7] = 34, ++ [1][1][2][1][2][8] = 50, ++ [1][1][2][1][1][8] = 34, ++ [1][1][2][1][3][8] = 64, ++ [1][1][2][1][5][8] = 48, ++ [1][1][2][1][6][8] = 34, ++ [1][1][2][1][9][8] = 34, ++ [1][1][2][1][8][8] = 36, ++ [1][1][2][1][11][8] = 34, ++ [1][1][2][1][2][9] = 38, ++ [1][1][2][1][1][9] = 34, ++ [1][1][2][1][3][9] = 64, ++ [1][1][2][1][5][9] = 38, ++ [1][1][2][1][6][9] = 34, ++ [1][1][2][1][9][9] = 34, ++ [1][1][2][1][8][9] = 36, ++ [1][1][2][1][11][9] = 34, ++ [1][1][2][1][2][10] = 36, ++ [1][1][2][1][1][10] = 34, ++ [1][1][2][1][3][10] = 64, ++ [1][1][2][1][5][10] = 36, ++ [1][1][2][1][6][10] = 34, ++ [1][1][2][1][9][10] = 34, ++ [1][1][2][1][8][10] = 36, ++ [1][1][2][1][11][10] = 34, ++ [1][1][2][1][2][11] = 127, ++ [1][1][2][1][1][11] = 127, ++ [1][1][2][1][3][11] = 127, ++ [1][1][2][1][5][11] = 127, ++ [1][1][2][1][6][11] = 127, ++ [1][1][2][1][9][11] = 127, ++ [1][1][2][1][8][11] = 127, ++ [1][1][2][1][11][11] = 127, ++ [1][1][2][1][2][12] = 127, ++ [1][1][2][1][1][12] = 127, ++ [1][1][2][1][3][12] = 127, ++ [1][1][2][1][5][12] = 127, ++ [1][1][2][1][6][12] = 127, ++ [1][1][2][1][9][12] = 127, ++ [1][1][2][1][8][12] = 127, ++ [1][1][2][1][11][12] = 127, ++ [1][1][2][1][2][13] = 127, ++ [1][1][2][1][1][13] = 127, ++ [1][1][2][1][3][13] = 127, ++ [1][1][2][1][5][13] = 127, ++ [1][1][2][1][6][13] = 127, ++ [1][1][2][1][9][13] = 127, ++ [1][1][2][1][8][13] = 127, ++ [1][1][2][1][11][13] = 127, ++}; ++ ++const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = { ++ [0][0][1][0][0][0] = 30, ++ [0][0][1][0][0][2] = 30, ++ [0][0][1][0][0][4] = 30, ++ [0][0][1][0][0][6] = 30, ++ [0][0][1][0][0][8] = 52, ++ [0][0][1][0][0][10] = 52, ++ [0][0][1][0][0][12] = 52, ++ [0][0][1][0][0][14] = 52, ++ [0][0][1][0][0][15] = 52, ++ [0][0][1][0][0][17] = 52, ++ [0][0][1][0][0][19] = 52, ++ [0][0][1][0][0][21] = 52, ++ [0][0][1][0][0][23] = 52, ++ [0][0][1][0][0][25] = 52, ++ [0][0][1][0][0][27] = 52, ++ [0][0][1][0][0][29] = 52, ++ [0][0][1][0][0][31] = 52, ++ [0][0][1][0][0][33] = 52, ++ [0][0][1][0][0][35] = 52, ++ [0][0][1][0][0][37] = 54, ++ [0][0][1][0][0][38] = 28, ++ [0][0][1][0][0][40] = 28, ++ [0][0][1][0][0][42] = 28, ++ [0][0][1][0][0][44] = 28, ++ [0][0][1][0][0][46] = 28, ++ [0][1][1][0][0][0] = 18, ++ [0][1][1][0][0][2] = 18, ++ [0][1][1][0][0][4] = 18, ++ [0][1][1][0][0][6] = 18, ++ [0][1][1][0][0][8] = 40, ++ [0][1][1][0][0][10] = 40, ++ [0][1][1][0][0][12] = 40, ++ [0][1][1][0][0][14] = 40, ++ [0][1][1][0][0][15] = 40, ++ [0][1][1][0][0][17] = 40, ++ [0][1][1][0][0][19] = 40, ++ [0][1][1][0][0][21] = 40, ++ [0][1][1][0][0][23] = 40, ++ [0][1][1][0][0][25] = 40, ++ [0][1][1][0][0][27] = 40, ++ [0][1][1][0][0][29] = 40, ++ [0][1][1][0][0][31] = 40, ++ [0][1][1][0][0][33] = 40, ++ [0][1][1][0][0][35] = 40, ++ [0][1][1][0][0][37] = 42, ++ [0][1][1][0][0][38] = 16, ++ [0][1][1][0][0][40] = 16, ++ [0][1][1][0][0][42] = 16, ++ [0][1][1][0][0][44] = 16, ++ [0][1][1][0][0][46] = 16, ++ [0][0][2][0][0][0] = 30, ++ [0][0][2][0][0][2] = 30, ++ [0][0][2][0][0][4] = 30, ++ [0][0][2][0][0][6] = 30, ++ [0][0][2][0][0][8] = 52, ++ [0][0][2][0][0][10] = 52, ++ [0][0][2][0][0][12] = 52, ++ [0][0][2][0][0][14] = 52, ++ [0][0][2][0][0][15] = 52, ++ [0][0][2][0][0][17] = 52, ++ [0][0][2][0][0][19] = 52, ++ [0][0][2][0][0][21] = 52, ++ [0][0][2][0][0][23] = 52, ++ [0][0][2][0][0][25] = 52, ++ [0][0][2][0][0][27] = 52, ++ [0][0][2][0][0][29] = 52, ++ [0][0][2][0][0][31] = 52, ++ [0][0][2][0][0][33] = 52, ++ [0][0][2][0][0][35] = 52, ++ [0][0][2][0][0][37] = 54, ++ [0][0][2][0][0][38] = 28, ++ [0][0][2][0][0][40] = 28, ++ [0][0][2][0][0][42] = 28, ++ [0][0][2][0][0][44] = 28, ++ [0][0][2][0][0][46] = 28, ++ [0][1][2][0][0][0] = 18, ++ [0][1][2][0][0][2] = 18, ++ [0][1][2][0][0][4] = 18, ++ [0][1][2][0][0][6] = 18, ++ [0][1][2][0][0][8] = 40, ++ [0][1][2][0][0][10] = 40, ++ [0][1][2][0][0][12] = 40, ++ [0][1][2][0][0][14] = 40, ++ [0][1][2][0][0][15] = 40, ++ [0][1][2][0][0][17] = 40, ++ [0][1][2][0][0][19] = 40, ++ [0][1][2][0][0][21] = 40, ++ [0][1][2][0][0][23] = 40, ++ [0][1][2][0][0][25] = 40, ++ [0][1][2][0][0][27] = 40, ++ [0][1][2][0][0][29] = 40, ++ [0][1][2][0][0][31] = 40, ++ [0][1][2][0][0][33] = 40, ++ [0][1][2][0][0][35] = 40, ++ [0][1][2][0][0][37] = 42, ++ [0][1][2][0][0][38] = 16, ++ [0][1][2][0][0][40] = 16, ++ [0][1][2][0][0][42] = 16, ++ [0][1][2][0][0][44] = 16, ++ [0][1][2][0][0][46] = 16, ++ [0][1][2][1][0][0] = 6, ++ [0][1][2][1][0][2] = 6, ++ [0][1][2][1][0][4] = 6, ++ [0][1][2][1][0][6] = 6, ++ [0][1][2][1][0][8] = 28, ++ [0][1][2][1][0][10] = 28, ++ [0][1][2][1][0][12] = 28, ++ [0][1][2][1][0][14] = 28, ++ [0][1][2][1][0][15] = 28, ++ [0][1][2][1][0][17] = 28, ++ [0][1][2][1][0][19] = 28, ++ [0][1][2][1][0][21] = 28, ++ [0][1][2][1][0][23] = 28, ++ [0][1][2][1][0][25] = 28, ++ [0][1][2][1][0][27] = 28, ++ [0][1][2][1][0][29] = 28, ++ [0][1][2][1][0][31] = 28, ++ [0][1][2][1][0][33] = 28, ++ [0][1][2][1][0][35] = 28, ++ [0][1][2][1][0][37] = 30, ++ [0][1][2][1][0][38] = 4, ++ [0][1][2][1][0][40] = 4, ++ [0][1][2][1][0][42] = 4, ++ [0][1][2][1][0][44] = 4, ++ [0][1][2][1][0][46] = 4, ++ [1][0][2][0][0][1] = 30, ++ [1][0][2][0][0][5] = 30, ++ [1][0][2][0][0][9] = 52, ++ [1][0][2][0][0][13] = 52, ++ [1][0][2][0][0][16] = 52, ++ [1][0][2][0][0][20] = 52, ++ [1][0][2][0][0][24] = 52, ++ [1][0][2][0][0][28] = 52, ++ [1][0][2][0][0][32] = 52, ++ [1][0][2][0][0][36] = 54, ++ [1][0][2][0][0][39] = 28, ++ [1][0][2][0][0][43] = 28, ++ [1][1][2][0][0][1] = 18, ++ [1][1][2][0][0][5] = 18, ++ [1][1][2][0][0][9] = 40, ++ [1][1][2][0][0][13] = 40, ++ [1][1][2][0][0][16] = 40, ++ [1][1][2][0][0][20] = 40, ++ [1][1][2][0][0][24] = 40, ++ [1][1][2][0][0][28] = 40, ++ [1][1][2][0][0][32] = 40, ++ [1][1][2][0][0][36] = 42, ++ [1][1][2][0][0][39] = 16, ++ [1][1][2][0][0][43] = 16, ++ [1][1][2][1][0][1] = 6, ++ [1][1][2][1][0][5] = 6, ++ [1][1][2][1][0][9] = 28, ++ [1][1][2][1][0][13] = 28, ++ [1][1][2][1][0][16] = 28, ++ [1][1][2][1][0][20] = 28, ++ [1][1][2][1][0][24] = 28, ++ [1][1][2][1][0][28] = 28, ++ [1][1][2][1][0][32] = 28, ++ [1][1][2][1][0][36] = 30, ++ [1][1][2][1][0][39] = 4, ++ [1][1][2][1][0][43] = 4, ++ [2][0][2][0][0][3] = 30, ++ [2][0][2][0][0][11] = 52, ++ [2][0][2][0][0][18] = 52, ++ [2][0][2][0][0][26] = 52, ++ [2][0][2][0][0][34] = 54, ++ [2][0][2][0][0][41] = 28, ++ [2][1][2][0][0][3] = 18, ++ [2][1][2][0][0][11] = 40, ++ [2][1][2][0][0][18] = 40, ++ [2][1][2][0][0][26] = 40, ++ [2][1][2][0][0][34] = 42, ++ [2][1][2][0][0][41] = 16, ++ [2][1][2][1][0][3] = 6, ++ [2][1][2][1][0][11] = 28, ++ [2][1][2][1][0][18] = 28, ++ [2][1][2][1][0][26] = 28, ++ [2][1][2][1][0][34] = 30, ++ [2][1][2][1][0][41] = 4, ++ [0][0][1][0][2][0] = 76, ++ [0][0][1][0][1][0] = 58, ++ [0][0][1][0][3][0] = 62, ++ [0][0][1][0][5][0] = 62, ++ [0][0][1][0][6][0] = 58, ++ [0][0][1][0][9][0] = 58, ++ [0][0][1][0][8][0] = 30, ++ [0][0][1][0][11][0] = 52, ++ [0][0][1][0][2][2] = 76, ++ [0][0][1][0][1][2] = 58, ++ [0][0][1][0][3][2] = 62, ++ [0][0][1][0][5][2] = 62, ++ [0][0][1][0][6][2] = 58, ++ [0][0][1][0][9][2] = 58, ++ [0][0][1][0][8][2] = 30, ++ [0][0][1][0][11][2] = 52, ++ [0][0][1][0][2][4] = 76, ++ [0][0][1][0][1][4] = 58, ++ [0][0][1][0][3][4] = 62, ++ [0][0][1][0][5][4] = 62, ++ [0][0][1][0][6][4] = 58, ++ [0][0][1][0][9][4] = 58, ++ [0][0][1][0][8][4] = 30, ++ [0][0][1][0][11][4] = 52, ++ [0][0][1][0][2][6] = 76, ++ [0][0][1][0][1][6] = 58, ++ [0][0][1][0][3][6] = 62, ++ [0][0][1][0][5][6] = 62, ++ [0][0][1][0][6][6] = 54, ++ [0][0][1][0][9][6] = 58, ++ [0][0][1][0][8][6] = 30, ++ [0][0][1][0][11][6] = 52, ++ [0][0][1][0][2][8] = 76, ++ [0][0][1][0][1][8] = 58, ++ [0][0][1][0][3][8] = 62, ++ [0][0][1][0][5][8] = 64, ++ [0][0][1][0][6][8] = 58, ++ [0][0][1][0][9][8] = 58, ++ [0][0][1][0][8][8] = 54, ++ [0][0][1][0][11][8] = 52, ++ [0][0][1][0][2][10] = 76, ++ [0][0][1][0][1][10] = 58, ++ [0][0][1][0][3][10] = 62, ++ [0][0][1][0][5][10] = 64, ++ [0][0][1][0][6][10] = 58, ++ [0][0][1][0][9][10] = 58, ++ [0][0][1][0][8][10] = 54, ++ [0][0][1][0][11][10] = 52, ++ [0][0][1][0][2][12] = 76, ++ [0][0][1][0][1][12] = 58, ++ [0][0][1][0][3][12] = 62, ++ [0][0][1][0][5][12] = 64, ++ [0][0][1][0][6][12] = 58, ++ [0][0][1][0][9][12] = 58, ++ [0][0][1][0][8][12] = 54, ++ [0][0][1][0][11][12] = 52, ++ [0][0][1][0][2][14] = 76, ++ [0][0][1][0][1][14] = 58, ++ [0][0][1][0][3][14] = 62, ++ [0][0][1][0][5][14] = 64, ++ [0][0][1][0][6][14] = 58, ++ [0][0][1][0][9][14] = 58, ++ [0][0][1][0][8][14] = 54, ++ [0][0][1][0][11][14] = 52, ++ [0][0][1][0][2][15] = 76, ++ [0][0][1][0][1][15] = 58, ++ [0][0][1][0][3][15] = 76, ++ [0][0][1][0][5][15] = 76, ++ [0][0][1][0][6][15] = 58, ++ [0][0][1][0][9][15] = 58, ++ [0][0][1][0][8][15] = 54, ++ [0][0][1][0][11][15] = 52, ++ [0][0][1][0][2][17] = 76, ++ [0][0][1][0][1][17] = 58, ++ [0][0][1][0][3][17] = 76, ++ [0][0][1][0][5][17] = 76, ++ [0][0][1][0][6][17] = 58, ++ [0][0][1][0][9][17] = 58, ++ [0][0][1][0][8][17] = 54, ++ [0][0][1][0][11][17] = 52, ++ [0][0][1][0][2][19] = 76, ++ [0][0][1][0][1][19] = 58, ++ [0][0][1][0][3][19] = 76, ++ [0][0][1][0][5][19] = 76, ++ [0][0][1][0][6][19] = 58, ++ [0][0][1][0][9][19] = 58, ++ [0][0][1][0][8][19] = 54, ++ [0][0][1][0][11][19] = 52, ++ [0][0][1][0][2][21] = 76, ++ [0][0][1][0][1][21] = 58, ++ [0][0][1][0][3][21] = 76, ++ [0][0][1][0][5][21] = 76, ++ [0][0][1][0][6][21] = 58, ++ [0][0][1][0][9][21] = 58, ++ [0][0][1][0][8][21] = 54, ++ [0][0][1][0][11][21] = 52, ++ [0][0][1][0][2][23] = 76, ++ [0][0][1][0][1][23] = 58, ++ [0][0][1][0][3][23] = 76, ++ [0][0][1][0][5][23] = 76, ++ [0][0][1][0][6][23] = 58, ++ [0][0][1][0][9][23] = 58, ++ [0][0][1][0][8][23] = 54, ++ [0][0][1][0][11][23] = 52, ++ [0][0][1][0][2][25] = 76, ++ [0][0][1][0][1][25] = 58, ++ [0][0][1][0][3][25] = 76, ++ [0][0][1][0][5][25] = 127, ++ [0][0][1][0][6][25] = 58, ++ [0][0][1][0][9][25] = 127, ++ [0][0][1][0][8][25] = 54, ++ [0][0][1][0][11][25] = 52, ++ [0][0][1][0][2][27] = 76, ++ [0][0][1][0][1][27] = 58, ++ [0][0][1][0][3][27] = 76, ++ [0][0][1][0][5][27] = 127, ++ [0][0][1][0][6][27] = 58, ++ [0][0][1][0][9][27] = 127, ++ [0][0][1][0][8][27] = 54, ++ [0][0][1][0][11][27] = 52, ++ [0][0][1][0][2][29] = 76, ++ [0][0][1][0][1][29] = 58, ++ [0][0][1][0][3][29] = 76, ++ [0][0][1][0][5][29] = 127, ++ [0][0][1][0][6][29] = 58, ++ [0][0][1][0][9][29] = 127, ++ [0][0][1][0][8][29] = 54, ++ [0][0][1][0][11][29] = 52, ++ [0][0][1][0][2][31] = 76, ++ [0][0][1][0][1][31] = 58, ++ [0][0][1][0][3][31] = 76, ++ [0][0][1][0][5][31] = 76, ++ [0][0][1][0][6][31] = 58, ++ [0][0][1][0][9][31] = 58, ++ [0][0][1][0][8][31] = 54, ++ [0][0][1][0][11][31] = 52, ++ [0][0][1][0][2][33] = 76, ++ [0][0][1][0][1][33] = 58, ++ [0][0][1][0][3][33] = 76, ++ [0][0][1][0][5][33] = 76, ++ [0][0][1][0][6][33] = 58, ++ [0][0][1][0][9][33] = 58, ++ [0][0][1][0][8][33] = 54, ++ [0][0][1][0][11][33] = 52, ++ [0][0][1][0][2][35] = 74, ++ [0][0][1][0][1][35] = 58, ++ [0][0][1][0][3][35] = 76, ++ [0][0][1][0][5][35] = 74, ++ [0][0][1][0][6][35] = 58, ++ [0][0][1][0][9][35] = 58, ++ [0][0][1][0][8][35] = 54, ++ [0][0][1][0][11][35] = 52, ++ [0][0][1][0][2][37] = 76, ++ [0][0][1][0][1][37] = 127, ++ [0][0][1][0][3][37] = 76, ++ [0][0][1][0][5][37] = 76, ++ [0][0][1][0][6][37] = 58, ++ [0][0][1][0][9][37] = 76, ++ [0][0][1][0][8][37] = 54, ++ [0][0][1][0][11][37] = 127, ++ [0][0][1][0][2][38] = 76, ++ [0][0][1][0][1][38] = 28, ++ [0][0][1][0][3][38] = 127, ++ [0][0][1][0][5][38] = 76, ++ [0][0][1][0][6][38] = 28, ++ [0][0][1][0][9][38] = 76, ++ [0][0][1][0][8][38] = 54, ++ [0][0][1][0][11][38] = 52, ++ [0][0][1][0][2][40] = 76, ++ [0][0][1][0][1][40] = 28, ++ [0][0][1][0][3][40] = 127, ++ [0][0][1][0][5][40] = 76, ++ [0][0][1][0][6][40] = 28, ++ [0][0][1][0][9][40] = 76, ++ [0][0][1][0][8][40] = 54, ++ [0][0][1][0][11][40] = 52, ++ [0][0][1][0][2][42] = 76, ++ [0][0][1][0][1][42] = 28, ++ [0][0][1][0][3][42] = 127, ++ [0][0][1][0][5][42] = 76, ++ [0][0][1][0][6][42] = 28, ++ [0][0][1][0][9][42] = 76, ++ [0][0][1][0][8][42] = 54, ++ [0][0][1][0][11][42] = 52, ++ [0][0][1][0][2][44] = 76, ++ [0][0][1][0][1][44] = 28, ++ [0][0][1][0][3][44] = 127, ++ [0][0][1][0][5][44] = 76, ++ [0][0][1][0][6][44] = 28, ++ [0][0][1][0][9][44] = 76, ++ [0][0][1][0][8][44] = 54, ++ [0][0][1][0][11][44] = 52, ++ [0][0][1][0][2][46] = 76, ++ [0][0][1][0][1][46] = 28, ++ [0][0][1][0][3][46] = 127, ++ [0][0][1][0][5][46] = 76, ++ [0][0][1][0][6][46] = 28, ++ [0][0][1][0][9][46] = 76, ++ [0][0][1][0][8][46] = 54, ++ [0][0][1][0][11][46] = 52, ++ [0][1][1][0][2][0] = 68, ++ [0][1][1][0][1][0] = 46, ++ [0][1][1][0][3][0] = 50, ++ [0][1][1][0][5][0] = 40, ++ [0][1][1][0][6][0] = 46, ++ [0][1][1][0][9][0] = 46, ++ [0][1][1][0][8][0] = 18, ++ [0][1][1][0][11][0] = 40, ++ [0][1][1][0][2][2] = 68, ++ [0][1][1][0][1][2] = 46, ++ [0][1][1][0][3][2] = 50, ++ [0][1][1][0][5][2] = 40, ++ [0][1][1][0][6][2] = 46, ++ [0][1][1][0][9][2] = 46, ++ [0][1][1][0][8][2] = 18, ++ [0][1][1][0][11][2] = 40, ++ [0][1][1][0][2][4] = 68, ++ [0][1][1][0][1][4] = 46, ++ [0][1][1][0][3][4] = 50, ++ [0][1][1][0][5][4] = 40, ++ [0][1][1][0][6][4] = 46, ++ [0][1][1][0][9][4] = 46, ++ [0][1][1][0][8][4] = 18, ++ [0][1][1][0][11][4] = 40, ++ [0][1][1][0][2][6] = 68, ++ [0][1][1][0][1][6] = 46, ++ [0][1][1][0][3][6] = 50, ++ [0][1][1][0][5][6] = 40, ++ [0][1][1][0][6][6] = 36, ++ [0][1][1][0][9][6] = 46, ++ [0][1][1][0][8][6] = 18, ++ [0][1][1][0][11][6] = 40, ++ [0][1][1][0][2][8] = 68, ++ [0][1][1][0][1][8] = 46, ++ [0][1][1][0][3][8] = 50, ++ [0][1][1][0][5][8] = 52, ++ [0][1][1][0][6][8] = 46, ++ [0][1][1][0][9][8] = 46, ++ [0][1][1][0][8][8] = 42, ++ [0][1][1][0][11][8] = 40, ++ [0][1][1][0][2][10] = 68, ++ [0][1][1][0][1][10] = 46, ++ [0][1][1][0][3][10] = 50, ++ [0][1][1][0][5][10] = 52, ++ [0][1][1][0][6][10] = 46, ++ [0][1][1][0][9][10] = 46, ++ [0][1][1][0][8][10] = 42, ++ [0][1][1][0][11][10] = 40, ++ [0][1][1][0][2][12] = 68, ++ [0][1][1][0][1][12] = 46, ++ [0][1][1][0][3][12] = 50, ++ [0][1][1][0][5][12] = 52, ++ [0][1][1][0][6][12] = 46, ++ [0][1][1][0][9][12] = 46, ++ [0][1][1][0][8][12] = 42, ++ [0][1][1][0][11][12] = 40, ++ [0][1][1][0][2][14] = 68, ++ [0][1][1][0][1][14] = 46, ++ [0][1][1][0][3][14] = 50, ++ [0][1][1][0][5][14] = 52, ++ [0][1][1][0][6][14] = 46, ++ [0][1][1][0][9][14] = 46, ++ [0][1][1][0][8][14] = 42, ++ [0][1][1][0][11][14] = 40, ++ [0][1][1][0][2][15] = 68, ++ [0][1][1][0][1][15] = 46, ++ [0][1][1][0][3][15] = 70, ++ [0][1][1][0][5][15] = 68, ++ [0][1][1][0][6][15] = 46, ++ [0][1][1][0][9][15] = 46, ++ [0][1][1][0][8][15] = 42, ++ [0][1][1][0][11][15] = 40, ++ [0][1][1][0][2][17] = 68, ++ [0][1][1][0][1][17] = 46, ++ [0][1][1][0][3][17] = 70, ++ [0][1][1][0][5][17] = 68, ++ [0][1][1][0][6][17] = 46, ++ [0][1][1][0][9][17] = 46, ++ [0][1][1][0][8][17] = 42, ++ [0][1][1][0][11][17] = 40, ++ [0][1][1][0][2][19] = 68, ++ [0][1][1][0][1][19] = 46, ++ [0][1][1][0][3][19] = 70, ++ [0][1][1][0][5][19] = 68, ++ [0][1][1][0][6][19] = 46, ++ [0][1][1][0][9][19] = 46, ++ [0][1][1][0][8][19] = 42, ++ [0][1][1][0][11][19] = 40, ++ [0][1][1][0][2][21] = 68, ++ [0][1][1][0][1][21] = 46, ++ [0][1][1][0][3][21] = 70, ++ [0][1][1][0][5][21] = 68, ++ [0][1][1][0][6][21] = 46, ++ [0][1][1][0][9][21] = 46, ++ [0][1][1][0][8][21] = 42, ++ [0][1][1][0][11][21] = 40, ++ [0][1][1][0][2][23] = 68, ++ [0][1][1][0][1][23] = 46, ++ [0][1][1][0][3][23] = 70, ++ [0][1][1][0][5][23] = 68, ++ [0][1][1][0][6][23] = 46, ++ [0][1][1][0][9][23] = 46, ++ [0][1][1][0][8][23] = 42, ++ [0][1][1][0][11][23] = 40, ++ [0][1][1][0][2][25] = 68, ++ [0][1][1][0][1][25] = 46, ++ [0][1][1][0][3][25] = 70, ++ [0][1][1][0][5][25] = 127, ++ [0][1][1][0][6][25] = 46, ++ [0][1][1][0][9][25] = 127, ++ [0][1][1][0][8][25] = 42, ++ [0][1][1][0][11][25] = 40, ++ [0][1][1][0][2][27] = 68, ++ [0][1][1][0][1][27] = 46, ++ [0][1][1][0][3][27] = 70, ++ [0][1][1][0][5][27] = 127, ++ [0][1][1][0][6][27] = 46, ++ [0][1][1][0][9][27] = 127, ++ [0][1][1][0][8][27] = 42, ++ [0][1][1][0][11][27] = 40, ++ [0][1][1][0][2][29] = 68, ++ [0][1][1][0][1][29] = 46, ++ [0][1][1][0][3][29] = 70, ++ [0][1][1][0][5][29] = 127, ++ [0][1][1][0][6][29] = 46, ++ [0][1][1][0][9][29] = 127, ++ [0][1][1][0][8][29] = 42, ++ [0][1][1][0][11][29] = 40, ++ [0][1][1][0][2][31] = 68, ++ [0][1][1][0][1][31] = 46, ++ [0][1][1][0][3][31] = 70, ++ [0][1][1][0][5][31] = 68, ++ [0][1][1][0][6][31] = 46, ++ [0][1][1][0][9][31] = 46, ++ [0][1][1][0][8][31] = 42, ++ [0][1][1][0][11][31] = 40, ++ [0][1][1][0][2][33] = 68, ++ [0][1][1][0][1][33] = 46, ++ [0][1][1][0][3][33] = 70, ++ [0][1][1][0][5][33] = 68, ++ [0][1][1][0][6][33] = 46, ++ [0][1][1][0][9][33] = 46, ++ [0][1][1][0][8][33] = 42, ++ [0][1][1][0][11][33] = 40, ++ [0][1][1][0][2][35] = 66, ++ [0][1][1][0][1][35] = 46, ++ [0][1][1][0][3][35] = 70, ++ [0][1][1][0][5][35] = 66, ++ [0][1][1][0][6][35] = 46, ++ [0][1][1][0][9][35] = 46, ++ [0][1][1][0][8][35] = 42, ++ [0][1][1][0][11][35] = 40, ++ [0][1][1][0][2][37] = 68, ++ [0][1][1][0][1][37] = 127, ++ [0][1][1][0][3][37] = 70, ++ [0][1][1][0][5][37] = 68, ++ [0][1][1][0][6][37] = 46, ++ [0][1][1][0][9][37] = 68, ++ [0][1][1][0][8][37] = 42, ++ [0][1][1][0][11][37] = 127, ++ [0][1][1][0][2][38] = 76, ++ [0][1][1][0][1][38] = 16, ++ [0][1][1][0][3][38] = 127, ++ [0][1][1][0][5][38] = 76, ++ [0][1][1][0][6][38] = 16, ++ [0][1][1][0][9][38] = 76, ++ [0][1][1][0][8][38] = 42, ++ [0][1][1][0][11][38] = 40, ++ [0][1][1][0][2][40] = 76, ++ [0][1][1][0][1][40] = 16, ++ [0][1][1][0][3][40] = 127, ++ [0][1][1][0][5][40] = 76, ++ [0][1][1][0][6][40] = 16, ++ [0][1][1][0][9][40] = 76, ++ [0][1][1][0][8][40] = 42, ++ [0][1][1][0][11][40] = 40, ++ [0][1][1][0][2][42] = 76, ++ [0][1][1][0][1][42] = 16, ++ [0][1][1][0][3][42] = 127, ++ [0][1][1][0][5][42] = 76, ++ [0][1][1][0][6][42] = 16, ++ [0][1][1][0][9][42] = 76, ++ [0][1][1][0][8][42] = 42, ++ [0][1][1][0][11][42] = 40, ++ [0][1][1][0][2][44] = 76, ++ [0][1][1][0][1][44] = 16, ++ [0][1][1][0][3][44] = 127, ++ [0][1][1][0][5][44] = 76, ++ [0][1][1][0][6][44] = 16, ++ [0][1][1][0][9][44] = 76, ++ [0][1][1][0][8][44] = 42, ++ [0][1][1][0][11][44] = 40, ++ [0][1][1][0][2][46] = 76, ++ [0][1][1][0][1][46] = 16, ++ [0][1][1][0][3][46] = 127, ++ [0][1][1][0][5][46] = 76, ++ [0][1][1][0][6][46] = 16, ++ [0][1][1][0][9][46] = 76, ++ [0][1][1][0][8][46] = 42, ++ [0][1][1][0][11][46] = 40, ++ [0][0][2][0][2][0] = 76, ++ [0][0][2][0][1][0] = 58, ++ [0][0][2][0][3][0] = 62, ++ [0][0][2][0][5][0] = 62, ++ [0][0][2][0][6][0] = 58, ++ [0][0][2][0][9][0] = 58, ++ [0][0][2][0][8][0] = 30, ++ [0][0][2][0][11][0] = 52, ++ [0][0][2][0][2][2] = 76, ++ [0][0][2][0][1][2] = 58, ++ [0][0][2][0][3][2] = 62, ++ [0][0][2][0][5][2] = 62, ++ [0][0][2][0][6][2] = 58, ++ [0][0][2][0][9][2] = 58, ++ [0][0][2][0][8][2] = 30, ++ [0][0][2][0][11][2] = 52, ++ [0][0][2][0][2][4] = 76, ++ [0][0][2][0][1][4] = 58, ++ [0][0][2][0][3][4] = 62, ++ [0][0][2][0][5][4] = 62, ++ [0][0][2][0][6][4] = 58, ++ [0][0][2][0][9][4] = 58, ++ [0][0][2][0][8][4] = 30, ++ [0][0][2][0][11][4] = 52, ++ [0][0][2][0][2][6] = 76, ++ [0][0][2][0][1][6] = 58, ++ [0][0][2][0][3][6] = 62, ++ [0][0][2][0][5][6] = 62, ++ [0][0][2][0][6][6] = 54, ++ [0][0][2][0][9][6] = 58, ++ [0][0][2][0][8][6] = 30, ++ [0][0][2][0][11][6] = 52, ++ [0][0][2][0][2][8] = 76, ++ [0][0][2][0][1][8] = 58, ++ [0][0][2][0][3][8] = 62, ++ [0][0][2][0][5][8] = 64, ++ [0][0][2][0][6][8] = 58, ++ [0][0][2][0][9][8] = 58, ++ [0][0][2][0][8][8] = 54, ++ [0][0][2][0][11][8] = 52, ++ [0][0][2][0][2][10] = 76, ++ [0][0][2][0][1][10] = 58, ++ [0][0][2][0][3][10] = 62, ++ [0][0][2][0][5][10] = 64, ++ [0][0][2][0][6][10] = 58, ++ [0][0][2][0][9][10] = 58, ++ [0][0][2][0][8][10] = 54, ++ [0][0][2][0][11][10] = 52, ++ [0][0][2][0][2][12] = 76, ++ [0][0][2][0][1][12] = 58, ++ [0][0][2][0][3][12] = 62, ++ [0][0][2][0][5][12] = 64, ++ [0][0][2][0][6][12] = 58, ++ [0][0][2][0][9][12] = 58, ++ [0][0][2][0][8][12] = 54, ++ [0][0][2][0][11][12] = 52, ++ [0][0][2][0][2][14] = 76, ++ [0][0][2][0][1][14] = 58, ++ [0][0][2][0][3][14] = 62, ++ [0][0][2][0][5][14] = 64, ++ [0][0][2][0][6][14] = 58, ++ [0][0][2][0][9][14] = 58, ++ [0][0][2][0][8][14] = 54, ++ [0][0][2][0][11][14] = 52, ++ [0][0][2][0][2][15] = 74, ++ [0][0][2][0][1][15] = 58, ++ [0][0][2][0][3][15] = 76, ++ [0][0][2][0][5][15] = 74, ++ [0][0][2][0][6][15] = 58, ++ [0][0][2][0][9][15] = 58, ++ [0][0][2][0][8][15] = 54, ++ [0][0][2][0][11][15] = 52, ++ [0][0][2][0][2][17] = 76, ++ [0][0][2][0][1][17] = 58, ++ [0][0][2][0][3][17] = 76, ++ [0][0][2][0][5][17] = 76, ++ [0][0][2][0][6][17] = 58, ++ [0][0][2][0][9][17] = 58, ++ [0][0][2][0][8][17] = 54, ++ [0][0][2][0][11][17] = 52, ++ [0][0][2][0][2][19] = 76, ++ [0][0][2][0][1][19] = 58, ++ [0][0][2][0][3][19] = 76, ++ [0][0][2][0][5][19] = 76, ++ [0][0][2][0][6][19] = 58, ++ [0][0][2][0][9][19] = 58, ++ [0][0][2][0][8][19] = 54, ++ [0][0][2][0][11][19] = 52, ++ [0][0][2][0][2][21] = 76, ++ [0][0][2][0][1][21] = 58, ++ [0][0][2][0][3][21] = 76, ++ [0][0][2][0][5][21] = 76, ++ [0][0][2][0][6][21] = 58, ++ [0][0][2][0][9][21] = 58, ++ [0][0][2][0][8][21] = 54, ++ [0][0][2][0][11][21] = 52, ++ [0][0][2][0][2][23] = 76, ++ [0][0][2][0][1][23] = 58, ++ [0][0][2][0][3][23] = 76, ++ [0][0][2][0][5][23] = 76, ++ [0][0][2][0][6][23] = 58, ++ [0][0][2][0][9][23] = 58, ++ [0][0][2][0][8][23] = 54, ++ [0][0][2][0][11][23] = 52, ++ [0][0][2][0][2][25] = 76, ++ [0][0][2][0][1][25] = 58, ++ [0][0][2][0][3][25] = 76, ++ [0][0][2][0][5][25] = 127, ++ [0][0][2][0][6][25] = 58, ++ [0][0][2][0][9][25] = 127, ++ [0][0][2][0][8][25] = 54, ++ [0][0][2][0][11][25] = 52, ++ [0][0][2][0][2][27] = 76, ++ [0][0][2][0][1][27] = 58, ++ [0][0][2][0][3][27] = 76, ++ [0][0][2][0][5][27] = 127, ++ [0][0][2][0][6][27] = 58, ++ [0][0][2][0][9][27] = 127, ++ [0][0][2][0][8][27] = 54, ++ [0][0][2][0][11][27] = 52, ++ [0][0][2][0][2][29] = 76, ++ [0][0][2][0][1][29] = 58, ++ [0][0][2][0][3][29] = 76, ++ [0][0][2][0][5][29] = 127, ++ [0][0][2][0][6][29] = 58, ++ [0][0][2][0][9][29] = 127, ++ [0][0][2][0][8][29] = 54, ++ [0][0][2][0][11][29] = 52, ++ [0][0][2][0][2][31] = 76, ++ [0][0][2][0][1][31] = 58, ++ [0][0][2][0][3][31] = 76, ++ [0][0][2][0][5][31] = 76, ++ [0][0][2][0][6][31] = 58, ++ [0][0][2][0][9][31] = 58, ++ [0][0][2][0][8][31] = 54, ++ [0][0][2][0][11][31] = 52, ++ [0][0][2][0][2][33] = 76, ++ [0][0][2][0][1][33] = 58, ++ [0][0][2][0][3][33] = 76, ++ [0][0][2][0][5][33] = 76, ++ [0][0][2][0][6][33] = 58, ++ [0][0][2][0][9][33] = 58, ++ [0][0][2][0][8][33] = 54, ++ [0][0][2][0][11][33] = 52, ++ [0][0][2][0][2][35] = 70, ++ [0][0][2][0][1][35] = 58, ++ [0][0][2][0][3][35] = 76, ++ [0][0][2][0][5][35] = 70, ++ [0][0][2][0][6][35] = 58, ++ [0][0][2][0][9][35] = 58, ++ [0][0][2][0][8][35] = 54, ++ [0][0][2][0][11][35] = 52, ++ [0][0][2][0][2][37] = 76, ++ [0][0][2][0][1][37] = 127, ++ [0][0][2][0][3][37] = 76, ++ [0][0][2][0][5][37] = 76, ++ [0][0][2][0][6][37] = 58, ++ [0][0][2][0][9][37] = 76, ++ [0][0][2][0][8][37] = 54, ++ [0][0][2][0][11][37] = 127, ++ [0][0][2][0][2][38] = 76, ++ [0][0][2][0][1][38] = 28, ++ [0][0][2][0][3][38] = 127, ++ [0][0][2][0][5][38] = 76, ++ [0][0][2][0][6][38] = 28, ++ [0][0][2][0][9][38] = 76, ++ [0][0][2][0][8][38] = 54, ++ [0][0][2][0][11][38] = 52, ++ [0][0][2][0][2][40] = 76, ++ [0][0][2][0][1][40] = 28, ++ [0][0][2][0][3][40] = 127, ++ [0][0][2][0][5][40] = 76, ++ [0][0][2][0][6][40] = 28, ++ [0][0][2][0][9][40] = 76, ++ [0][0][2][0][8][40] = 54, ++ [0][0][2][0][11][40] = 52, ++ [0][0][2][0][2][42] = 76, ++ [0][0][2][0][1][42] = 28, ++ [0][0][2][0][3][42] = 127, ++ [0][0][2][0][5][42] = 76, ++ [0][0][2][0][6][42] = 28, ++ [0][0][2][0][9][42] = 76, ++ [0][0][2][0][8][42] = 54, ++ [0][0][2][0][11][42] = 52, ++ [0][0][2][0][2][44] = 76, ++ [0][0][2][0][1][44] = 28, ++ [0][0][2][0][3][44] = 127, ++ [0][0][2][0][5][44] = 76, ++ [0][0][2][0][6][44] = 28, ++ [0][0][2][0][9][44] = 76, ++ [0][0][2][0][8][44] = 54, ++ [0][0][2][0][11][44] = 52, ++ [0][0][2][0][2][46] = 76, ++ [0][0][2][0][1][46] = 28, ++ [0][0][2][0][3][46] = 127, ++ [0][0][2][0][5][46] = 76, ++ [0][0][2][0][6][46] = 28, ++ [0][0][2][0][9][46] = 76, ++ [0][0][2][0][8][46] = 54, ++ [0][0][2][0][11][46] = 52, ++ [0][1][2][0][2][0] = 68, ++ [0][1][2][0][1][0] = 46, ++ [0][1][2][0][3][0] = 50, ++ [0][1][2][0][5][0] = 40, ++ [0][1][2][0][6][0] = 46, ++ [0][1][2][0][9][0] = 46, ++ [0][1][2][0][8][0] = 18, ++ [0][1][2][0][11][0] = 40, ++ [0][1][2][0][2][2] = 68, ++ [0][1][2][0][1][2] = 46, ++ [0][1][2][0][3][2] = 50, ++ [0][1][2][0][5][2] = 40, ++ [0][1][2][0][6][2] = 46, ++ [0][1][2][0][9][2] = 46, ++ [0][1][2][0][8][2] = 18, ++ [0][1][2][0][11][2] = 40, ++ [0][1][2][0][2][4] = 68, ++ [0][1][2][0][1][4] = 46, ++ [0][1][2][0][3][4] = 50, ++ [0][1][2][0][5][4] = 40, ++ [0][1][2][0][6][4] = 46, ++ [0][1][2][0][9][4] = 46, ++ [0][1][2][0][8][4] = 18, ++ [0][1][2][0][11][4] = 40, ++ [0][1][2][0][2][6] = 68, ++ [0][1][2][0][1][6] = 46, ++ [0][1][2][0][3][6] = 50, ++ [0][1][2][0][5][6] = 40, ++ [0][1][2][0][6][6] = 36, ++ [0][1][2][0][9][6] = 46, ++ [0][1][2][0][8][6] = 18, ++ [0][1][2][0][11][6] = 40, ++ [0][1][2][0][2][8] = 68, ++ [0][1][2][0][1][8] = 46, ++ [0][1][2][0][3][8] = 50, ++ [0][1][2][0][5][8] = 52, ++ [0][1][2][0][6][8] = 46, ++ [0][1][2][0][9][8] = 46, ++ [0][1][2][0][8][8] = 42, ++ [0][1][2][0][11][8] = 40, ++ [0][1][2][0][2][10] = 68, ++ [0][1][2][0][1][10] = 46, ++ [0][1][2][0][3][10] = 50, ++ [0][1][2][0][5][10] = 52, ++ [0][1][2][0][6][10] = 46, ++ [0][1][2][0][9][10] = 46, ++ [0][1][2][0][8][10] = 42, ++ [0][1][2][0][11][10] = 40, ++ [0][1][2][0][2][12] = 68, ++ [0][1][2][0][1][12] = 46, ++ [0][1][2][0][3][12] = 50, ++ [0][1][2][0][5][12] = 52, ++ [0][1][2][0][6][12] = 46, ++ [0][1][2][0][9][12] = 46, ++ [0][1][2][0][8][12] = 42, ++ [0][1][2][0][11][12] = 40, ++ [0][1][2][0][2][14] = 68, ++ [0][1][2][0][1][14] = 46, ++ [0][1][2][0][3][14] = 50, ++ [0][1][2][0][5][14] = 52, ++ [0][1][2][0][6][14] = 46, ++ [0][1][2][0][9][14] = 46, ++ [0][1][2][0][8][14] = 42, ++ [0][1][2][0][11][14] = 40, ++ [0][1][2][0][2][15] = 68, ++ [0][1][2][0][1][15] = 46, ++ [0][1][2][0][3][15] = 70, ++ [0][1][2][0][5][15] = 68, ++ [0][1][2][0][6][15] = 46, ++ [0][1][2][0][9][15] = 46, ++ [0][1][2][0][8][15] = 42, ++ [0][1][2][0][11][15] = 40, ++ [0][1][2][0][2][17] = 68, ++ [0][1][2][0][1][17] = 46, ++ [0][1][2][0][3][17] = 70, ++ [0][1][2][0][5][17] = 68, ++ [0][1][2][0][6][17] = 46, ++ [0][1][2][0][9][17] = 46, ++ [0][1][2][0][8][17] = 42, ++ [0][1][2][0][11][17] = 40, ++ [0][1][2][0][2][19] = 68, ++ [0][1][2][0][1][19] = 46, ++ [0][1][2][0][3][19] = 70, ++ [0][1][2][0][5][19] = 68, ++ [0][1][2][0][6][19] = 46, ++ [0][1][2][0][9][19] = 46, ++ [0][1][2][0][8][19] = 42, ++ [0][1][2][0][11][19] = 40, ++ [0][1][2][0][2][21] = 68, ++ [0][1][2][0][1][21] = 46, ++ [0][1][2][0][3][21] = 70, ++ [0][1][2][0][5][21] = 68, ++ [0][1][2][0][6][21] = 46, ++ [0][1][2][0][9][21] = 46, ++ [0][1][2][0][8][21] = 42, ++ [0][1][2][0][11][21] = 40, ++ [0][1][2][0][2][23] = 68, ++ [0][1][2][0][1][23] = 46, ++ [0][1][2][0][3][23] = 70, ++ [0][1][2][0][5][23] = 68, ++ [0][1][2][0][6][23] = 46, ++ [0][1][2][0][9][23] = 46, ++ [0][1][2][0][8][23] = 42, ++ [0][1][2][0][11][23] = 40, ++ [0][1][2][0][2][25] = 68, ++ [0][1][2][0][1][25] = 46, ++ [0][1][2][0][3][25] = 70, ++ [0][1][2][0][5][25] = 127, ++ [0][1][2][0][6][25] = 46, ++ [0][1][2][0][9][25] = 127, ++ [0][1][2][0][8][25] = 42, ++ [0][1][2][0][11][25] = 40, ++ [0][1][2][0][2][27] = 68, ++ [0][1][2][0][1][27] = 46, ++ [0][1][2][0][3][27] = 70, ++ [0][1][2][0][5][27] = 127, ++ [0][1][2][0][6][27] = 46, ++ [0][1][2][0][9][27] = 127, ++ [0][1][2][0][8][27] = 42, ++ [0][1][2][0][11][27] = 40, ++ [0][1][2][0][2][29] = 68, ++ [0][1][2][0][1][29] = 46, ++ [0][1][2][0][3][29] = 70, ++ [0][1][2][0][5][29] = 127, ++ [0][1][2][0][6][29] = 46, ++ [0][1][2][0][9][29] = 127, ++ [0][1][2][0][8][29] = 42, ++ [0][1][2][0][11][29] = 40, ++ [0][1][2][0][2][31] = 68, ++ [0][1][2][0][1][31] = 46, ++ [0][1][2][0][3][31] = 70, ++ [0][1][2][0][5][31] = 68, ++ [0][1][2][0][6][31] = 46, ++ [0][1][2][0][9][31] = 46, ++ [0][1][2][0][8][31] = 42, ++ [0][1][2][0][11][31] = 40, ++ [0][1][2][0][2][33] = 68, ++ [0][1][2][0][1][33] = 46, ++ [0][1][2][0][3][33] = 70, ++ [0][1][2][0][5][33] = 68, ++ [0][1][2][0][6][33] = 46, ++ [0][1][2][0][9][33] = 46, ++ [0][1][2][0][8][33] = 42, ++ [0][1][2][0][11][33] = 40, ++ [0][1][2][0][2][35] = 64, ++ [0][1][2][0][1][35] = 46, ++ [0][1][2][0][3][35] = 70, ++ [0][1][2][0][5][35] = 64, ++ [0][1][2][0][6][35] = 46, ++ [0][1][2][0][9][35] = 46, ++ [0][1][2][0][8][35] = 42, ++ [0][1][2][0][11][35] = 40, ++ [0][1][2][0][2][37] = 68, ++ [0][1][2][0][1][37] = 127, ++ [0][1][2][0][3][37] = 70, ++ [0][1][2][0][5][37] = 68, ++ [0][1][2][0][6][37] = 46, ++ [0][1][2][0][9][37] = 68, ++ [0][1][2][0][8][37] = 42, ++ [0][1][2][0][11][37] = 127, ++ [0][1][2][0][2][38] = 76, ++ [0][1][2][0][1][38] = 16, ++ [0][1][2][0][3][38] = 127, ++ [0][1][2][0][5][38] = 76, ++ [0][1][2][0][6][38] = 16, ++ [0][1][2][0][9][38] = 76, ++ [0][1][2][0][8][38] = 42, ++ [0][1][2][0][11][38] = 40, ++ [0][1][2][0][2][40] = 76, ++ [0][1][2][0][1][40] = 16, ++ [0][1][2][0][3][40] = 127, ++ [0][1][2][0][5][40] = 76, ++ [0][1][2][0][6][40] = 16, ++ [0][1][2][0][9][40] = 76, ++ [0][1][2][0][8][40] = 42, ++ [0][1][2][0][11][40] = 40, ++ [0][1][2][0][2][42] = 76, ++ [0][1][2][0][1][42] = 16, ++ [0][1][2][0][3][42] = 127, ++ [0][1][2][0][5][42] = 76, ++ [0][1][2][0][6][42] = 16, ++ [0][1][2][0][9][42] = 76, ++ [0][1][2][0][8][42] = 42, ++ [0][1][2][0][11][42] = 40, ++ [0][1][2][0][2][44] = 76, ++ [0][1][2][0][1][44] = 16, ++ [0][1][2][0][3][44] = 127, ++ [0][1][2][0][5][44] = 76, ++ [0][1][2][0][6][44] = 16, ++ [0][1][2][0][9][44] = 76, ++ [0][1][2][0][8][44] = 42, ++ [0][1][2][0][11][44] = 40, ++ [0][1][2][0][2][46] = 76, ++ [0][1][2][0][1][46] = 16, ++ [0][1][2][0][3][46] = 127, ++ [0][1][2][0][5][46] = 76, ++ [0][1][2][0][6][46] = 16, ++ [0][1][2][0][9][46] = 76, ++ [0][1][2][0][8][46] = 42, ++ [0][1][2][0][11][46] = 40, ++ [0][1][2][1][2][0] = 68, ++ [0][1][2][1][1][0] = 34, ++ [0][1][2][1][3][0] = 50, ++ [0][1][2][1][5][0] = 38, ++ [0][1][2][1][6][0] = 34, ++ [0][1][2][1][9][0] = 34, ++ [0][1][2][1][8][0] = 6, ++ [0][1][2][1][11][0] = 28, ++ [0][1][2][1][2][2] = 68, ++ [0][1][2][1][1][2] = 34, ++ [0][1][2][1][3][2] = 50, ++ [0][1][2][1][5][2] = 38, ++ [0][1][2][1][6][2] = 34, ++ [0][1][2][1][9][2] = 34, ++ [0][1][2][1][8][2] = 6, ++ [0][1][2][1][11][2] = 28, ++ [0][1][2][1][2][4] = 68, ++ [0][1][2][1][1][4] = 34, ++ [0][1][2][1][3][4] = 50, ++ [0][1][2][1][5][4] = 38, ++ [0][1][2][1][6][4] = 34, ++ [0][1][2][1][9][4] = 34, ++ [0][1][2][1][8][4] = 6, ++ [0][1][2][1][11][4] = 28, ++ [0][1][2][1][2][6] = 68, ++ [0][1][2][1][1][6] = 34, ++ [0][1][2][1][3][6] = 50, ++ [0][1][2][1][5][6] = 38, ++ [0][1][2][1][6][6] = 34, ++ [0][1][2][1][9][6] = 34, ++ [0][1][2][1][8][6] = 6, ++ [0][1][2][1][11][6] = 28, ++ [0][1][2][1][2][8] = 68, ++ [0][1][2][1][1][8] = 34, ++ [0][1][2][1][3][8] = 50, ++ [0][1][2][1][5][8] = 38, ++ [0][1][2][1][6][8] = 34, ++ [0][1][2][1][9][8] = 34, ++ [0][1][2][1][8][8] = 30, ++ [0][1][2][1][11][8] = 28, ++ [0][1][2][1][2][10] = 68, ++ [0][1][2][1][1][10] = 34, ++ [0][1][2][1][3][10] = 50, ++ [0][1][2][1][5][10] = 38, ++ [0][1][2][1][6][10] = 34, ++ [0][1][2][1][9][10] = 34, ++ [0][1][2][1][8][10] = 30, ++ [0][1][2][1][11][10] = 28, ++ [0][1][2][1][2][12] = 68, ++ [0][1][2][1][1][12] = 34, ++ [0][1][2][1][3][12] = 50, ++ [0][1][2][1][5][12] = 38, ++ [0][1][2][1][6][12] = 34, ++ [0][1][2][1][9][12] = 34, ++ [0][1][2][1][8][12] = 30, ++ [0][1][2][1][11][12] = 28, ++ [0][1][2][1][2][14] = 68, ++ [0][1][2][1][1][14] = 34, ++ [0][1][2][1][3][14] = 50, ++ [0][1][2][1][5][14] = 38, ++ [0][1][2][1][6][14] = 34, ++ [0][1][2][1][9][14] = 34, ++ [0][1][2][1][8][14] = 30, ++ [0][1][2][1][11][14] = 28, ++ [0][1][2][1][2][15] = 68, ++ [0][1][2][1][1][15] = 34, ++ [0][1][2][1][3][15] = 70, ++ [0][1][2][1][5][15] = 62, ++ [0][1][2][1][6][15] = 34, ++ [0][1][2][1][9][15] = 34, ++ [0][1][2][1][8][15] = 30, ++ [0][1][2][1][11][15] = 28, ++ [0][1][2][1][2][17] = 68, ++ [0][1][2][1][1][17] = 34, ++ [0][1][2][1][3][17] = 70, ++ [0][1][2][1][5][17] = 62, ++ [0][1][2][1][6][17] = 34, ++ [0][1][2][1][9][17] = 34, ++ [0][1][2][1][8][17] = 30, ++ [0][1][2][1][11][17] = 28, ++ [0][1][2][1][2][19] = 68, ++ [0][1][2][1][1][19] = 34, ++ [0][1][2][1][3][19] = 70, ++ [0][1][2][1][5][19] = 62, ++ [0][1][2][1][6][19] = 34, ++ [0][1][2][1][9][19] = 34, ++ [0][1][2][1][8][19] = 30, ++ [0][1][2][1][11][19] = 28, ++ [0][1][2][1][2][21] = 68, ++ [0][1][2][1][1][21] = 34, ++ [0][1][2][1][3][21] = 70, ++ [0][1][2][1][5][21] = 62, ++ [0][1][2][1][6][21] = 34, ++ [0][1][2][1][9][21] = 34, ++ [0][1][2][1][8][21] = 30, ++ [0][1][2][1][11][21] = 28, ++ [0][1][2][1][2][23] = 68, ++ [0][1][2][1][1][23] = 34, ++ [0][1][2][1][3][23] = 70, ++ [0][1][2][1][5][23] = 62, ++ [0][1][2][1][6][23] = 34, ++ [0][1][2][1][9][23] = 34, ++ [0][1][2][1][8][23] = 30, ++ [0][1][2][1][11][23] = 28, ++ [0][1][2][1][2][25] = 68, ++ [0][1][2][1][1][25] = 34, ++ [0][1][2][1][3][25] = 70, ++ [0][1][2][1][5][25] = 127, ++ [0][1][2][1][6][25] = 34, ++ [0][1][2][1][9][25] = 127, ++ [0][1][2][1][8][25] = 30, ++ [0][1][2][1][11][25] = 28, ++ [0][1][2][1][2][27] = 68, ++ [0][1][2][1][1][27] = 34, ++ [0][1][2][1][3][27] = 70, ++ [0][1][2][1][5][27] = 127, ++ [0][1][2][1][6][27] = 34, ++ [0][1][2][1][9][27] = 127, ++ [0][1][2][1][8][27] = 30, ++ [0][1][2][1][11][27] = 28, ++ [0][1][2][1][2][29] = 68, ++ [0][1][2][1][1][29] = 34, ++ [0][1][2][1][3][29] = 70, ++ [0][1][2][1][5][29] = 127, ++ [0][1][2][1][6][29] = 34, ++ [0][1][2][1][9][29] = 127, ++ [0][1][2][1][8][29] = 30, ++ [0][1][2][1][11][29] = 28, ++ [0][1][2][1][2][31] = 68, ++ [0][1][2][1][1][31] = 34, ++ [0][1][2][1][3][31] = 70, ++ [0][1][2][1][5][31] = 62, ++ [0][1][2][1][6][31] = 34, ++ [0][1][2][1][9][31] = 34, ++ [0][1][2][1][8][31] = 30, ++ [0][1][2][1][11][31] = 28, ++ [0][1][2][1][2][33] = 68, ++ [0][1][2][1][1][33] = 34, ++ [0][1][2][1][3][33] = 70, ++ [0][1][2][1][5][33] = 62, ++ [0][1][2][1][6][33] = 34, ++ [0][1][2][1][9][33] = 34, ++ [0][1][2][1][8][33] = 30, ++ [0][1][2][1][11][33] = 28, ++ [0][1][2][1][2][35] = 64, ++ [0][1][2][1][1][35] = 34, ++ [0][1][2][1][3][35] = 70, ++ [0][1][2][1][5][35] = 62, ++ [0][1][2][1][6][35] = 34, ++ [0][1][2][1][9][35] = 34, ++ [0][1][2][1][8][35] = 30, ++ [0][1][2][1][11][35] = 28, ++ [0][1][2][1][2][37] = 68, ++ [0][1][2][1][1][37] = 127, ++ [0][1][2][1][3][37] = 70, ++ [0][1][2][1][5][37] = 62, ++ [0][1][2][1][6][37] = 34, ++ [0][1][2][1][9][37] = 68, ++ [0][1][2][1][8][37] = 30, ++ [0][1][2][1][11][37] = 127, ++ [0][1][2][1][2][38] = 76, ++ [0][1][2][1][1][38] = 4, ++ [0][1][2][1][3][38] = 127, ++ [0][1][2][1][5][38] = 76, ++ [0][1][2][1][6][38] = 4, ++ [0][1][2][1][9][38] = 76, ++ [0][1][2][1][8][38] = 30, ++ [0][1][2][1][11][38] = 28, ++ [0][1][2][1][2][40] = 76, ++ [0][1][2][1][1][40] = 4, ++ [0][1][2][1][3][40] = 127, ++ [0][1][2][1][5][40] = 76, ++ [0][1][2][1][6][40] = 4, ++ [0][1][2][1][9][40] = 76, ++ [0][1][2][1][8][40] = 30, ++ [0][1][2][1][11][40] = 28, ++ [0][1][2][1][2][42] = 76, ++ [0][1][2][1][1][42] = 4, ++ [0][1][2][1][3][42] = 127, ++ [0][1][2][1][5][42] = 76, ++ [0][1][2][1][6][42] = 4, ++ [0][1][2][1][9][42] = 76, ++ [0][1][2][1][8][42] = 30, ++ [0][1][2][1][11][42] = 28, ++ [0][1][2][1][2][44] = 76, ++ [0][1][2][1][1][44] = 4, ++ [0][1][2][1][3][44] = 127, ++ [0][1][2][1][5][44] = 76, ++ [0][1][2][1][6][44] = 4, ++ [0][1][2][1][9][44] = 76, ++ [0][1][2][1][8][44] = 30, ++ [0][1][2][1][11][44] = 28, ++ [0][1][2][1][2][46] = 76, ++ [0][1][2][1][1][46] = 4, ++ [0][1][2][1][3][46] = 127, ++ [0][1][2][1][5][46] = 76, ++ [0][1][2][1][6][46] = 4, ++ [0][1][2][1][9][46] = 76, ++ [0][1][2][1][8][46] = 30, ++ [0][1][2][1][11][46] = 28, ++ [1][0][2][0][2][1] = 68, ++ [1][0][2][0][1][1] = 64, ++ [1][0][2][0][3][1] = 62, ++ [1][0][2][0][5][1] = 64, ++ [1][0][2][0][6][1] = 64, ++ [1][0][2][0][9][1] = 64, ++ [1][0][2][0][8][1] = 30, ++ [1][0][2][0][11][1] = 52, ++ [1][0][2][0][2][5] = 72, ++ [1][0][2][0][1][5] = 64, ++ [1][0][2][0][3][5] = 62, ++ [1][0][2][0][5][5] = 64, ++ [1][0][2][0][6][5] = 60, ++ [1][0][2][0][9][5] = 64, ++ [1][0][2][0][8][5] = 30, ++ [1][0][2][0][11][5] = 52, ++ [1][0][2][0][2][9] = 72, ++ [1][0][2][0][1][9] = 64, ++ [1][0][2][0][3][9] = 62, ++ [1][0][2][0][5][9] = 64, ++ [1][0][2][0][6][9] = 64, ++ [1][0][2][0][9][9] = 64, ++ [1][0][2][0][8][9] = 54, ++ [1][0][2][0][11][9] = 52, ++ [1][0][2][0][2][13] = 66, ++ [1][0][2][0][1][13] = 64, ++ [1][0][2][0][3][13] = 62, ++ [1][0][2][0][5][13] = 64, ++ [1][0][2][0][6][13] = 64, ++ [1][0][2][0][9][13] = 64, ++ [1][0][2][0][8][13] = 54, ++ [1][0][2][0][11][13] = 52, ++ [1][0][2][0][2][16] = 62, ++ [1][0][2][0][1][16] = 64, ++ [1][0][2][0][3][16] = 72, ++ [1][0][2][0][5][16] = 62, ++ [1][0][2][0][6][16] = 64, ++ [1][0][2][0][9][16] = 64, ++ [1][0][2][0][8][16] = 54, ++ [1][0][2][0][11][16] = 52, ++ [1][0][2][0][2][20] = 72, ++ [1][0][2][0][1][20] = 64, ++ [1][0][2][0][3][20] = 72, ++ [1][0][2][0][5][20] = 72, ++ [1][0][2][0][6][20] = 64, ++ [1][0][2][0][9][20] = 64, ++ [1][0][2][0][8][20] = 54, ++ [1][0][2][0][11][20] = 52, ++ [1][0][2][0][2][24] = 72, ++ [1][0][2][0][1][24] = 64, ++ [1][0][2][0][3][24] = 72, ++ [1][0][2][0][5][24] = 127, ++ [1][0][2][0][6][24] = 64, ++ [1][0][2][0][9][24] = 127, ++ [1][0][2][0][8][24] = 54, ++ [1][0][2][0][11][24] = 52, ++ [1][0][2][0][2][28] = 72, ++ [1][0][2][0][1][28] = 64, ++ [1][0][2][0][3][28] = 72, ++ [1][0][2][0][5][28] = 127, ++ [1][0][2][0][6][28] = 64, ++ [1][0][2][0][9][28] = 127, ++ [1][0][2][0][8][28] = 54, ++ [1][0][2][0][11][28] = 52, ++ [1][0][2][0][2][32] = 72, ++ [1][0][2][0][1][32] = 64, ++ [1][0][2][0][3][32] = 72, ++ [1][0][2][0][5][32] = 72, ++ [1][0][2][0][6][32] = 64, ++ [1][0][2][0][9][32] = 64, ++ [1][0][2][0][8][32] = 54, ++ [1][0][2][0][11][32] = 52, ++ [1][0][2][0][2][36] = 72, ++ [1][0][2][0][1][36] = 127, ++ [1][0][2][0][3][36] = 72, ++ [1][0][2][0][5][36] = 72, ++ [1][0][2][0][6][36] = 64, ++ [1][0][2][0][9][36] = 72, ++ [1][0][2][0][8][36] = 54, ++ [1][0][2][0][11][36] = 127, ++ [1][0][2][0][2][39] = 72, ++ [1][0][2][0][1][39] = 28, ++ [1][0][2][0][3][39] = 127, ++ [1][0][2][0][5][39] = 72, ++ [1][0][2][0][6][39] = 28, ++ [1][0][2][0][9][39] = 72, ++ [1][0][2][0][8][39] = 54, ++ [1][0][2][0][11][39] = 52, ++ [1][0][2][0][2][43] = 72, ++ [1][0][2][0][1][43] = 28, ++ [1][0][2][0][3][43] = 127, ++ [1][0][2][0][5][43] = 72, ++ [1][0][2][0][6][43] = 28, ++ [1][0][2][0][9][43] = 72, ++ [1][0][2][0][8][43] = 54, ++ [1][0][2][0][11][43] = 52, ++ [1][1][2][0][2][1] = 58, ++ [1][1][2][0][1][1] = 52, ++ [1][1][2][0][3][1] = 50, ++ [1][1][2][0][5][1] = 52, ++ [1][1][2][0][6][1] = 52, ++ [1][1][2][0][9][1] = 52, ++ [1][1][2][0][8][1] = 18, ++ [1][1][2][0][11][1] = 40, ++ [1][1][2][0][2][5] = 72, ++ [1][1][2][0][1][5] = 52, ++ [1][1][2][0][3][5] = 50, ++ [1][1][2][0][5][5] = 52, ++ [1][1][2][0][6][5] = 46, ++ [1][1][2][0][9][5] = 52, ++ [1][1][2][0][8][5] = 18, ++ [1][1][2][0][11][5] = 40, ++ [1][1][2][0][2][9] = 72, ++ [1][1][2][0][1][9] = 52, ++ [1][1][2][0][3][9] = 50, ++ [1][1][2][0][5][9] = 52, ++ [1][1][2][0][6][9] = 52, ++ [1][1][2][0][9][9] = 52, ++ [1][1][2][0][8][9] = 42, ++ [1][1][2][0][11][9] = 40, ++ [1][1][2][0][2][13] = 58, ++ [1][1][2][0][1][13] = 52, ++ [1][1][2][0][3][13] = 50, ++ [1][1][2][0][5][13] = 52, ++ [1][1][2][0][6][13] = 52, ++ [1][1][2][0][9][13] = 52, ++ [1][1][2][0][8][13] = 42, ++ [1][1][2][0][11][13] = 40, ++ [1][1][2][0][2][16] = 56, ++ [1][1][2][0][1][16] = 52, ++ [1][1][2][0][3][16] = 72, ++ [1][1][2][0][5][16] = 56, ++ [1][1][2][0][6][16] = 52, ++ [1][1][2][0][9][16] = 52, ++ [1][1][2][0][8][16] = 42, ++ [1][1][2][0][11][16] = 40, ++ [1][1][2][0][2][20] = 72, ++ [1][1][2][0][1][20] = 52, ++ [1][1][2][0][3][20] = 72, ++ [1][1][2][0][5][20] = 72, ++ [1][1][2][0][6][20] = 52, ++ [1][1][2][0][9][20] = 52, ++ [1][1][2][0][8][20] = 42, ++ [1][1][2][0][11][20] = 40, ++ [1][1][2][0][2][24] = 72, ++ [1][1][2][0][1][24] = 52, ++ [1][1][2][0][3][24] = 72, ++ [1][1][2][0][5][24] = 127, ++ [1][1][2][0][6][24] = 52, ++ [1][1][2][0][9][24] = 127, ++ [1][1][2][0][8][24] = 42, ++ [1][1][2][0][11][24] = 40, ++ [1][1][2][0][2][28] = 72, ++ [1][1][2][0][1][28] = 52, ++ [1][1][2][0][3][28] = 72, ++ [1][1][2][0][5][28] = 127, ++ [1][1][2][0][6][28] = 52, ++ [1][1][2][0][9][28] = 127, ++ [1][1][2][0][8][28] = 42, ++ [1][1][2][0][11][28] = 40, ++ [1][1][2][0][2][32] = 68, ++ [1][1][2][0][1][32] = 52, ++ [1][1][2][0][3][32] = 72, ++ [1][1][2][0][5][32] = 68, ++ [1][1][2][0][6][32] = 52, ++ [1][1][2][0][9][32] = 52, ++ [1][1][2][0][8][32] = 42, ++ [1][1][2][0][11][32] = 40, ++ [1][1][2][0][2][36] = 72, ++ [1][1][2][0][1][36] = 127, ++ [1][1][2][0][3][36] = 72, ++ [1][1][2][0][5][36] = 72, ++ [1][1][2][0][6][36] = 52, ++ [1][1][2][0][9][36] = 72, ++ [1][1][2][0][8][36] = 42, ++ [1][1][2][0][11][36] = 127, ++ [1][1][2][0][2][39] = 72, ++ [1][1][2][0][1][39] = 16, ++ [1][1][2][0][3][39] = 127, ++ [1][1][2][0][5][39] = 72, ++ [1][1][2][0][6][39] = 16, ++ [1][1][2][0][9][39] = 72, ++ [1][1][2][0][8][39] = 42, ++ [1][1][2][0][11][39] = 40, ++ [1][1][2][0][2][43] = 72, ++ [1][1][2][0][1][43] = 16, ++ [1][1][2][0][3][43] = 127, ++ [1][1][2][0][5][43] = 72, ++ [1][1][2][0][6][43] = 16, ++ [1][1][2][0][9][43] = 72, ++ [1][1][2][0][8][43] = 42, ++ [1][1][2][0][11][43] = 40, ++ [1][1][2][1][2][1] = 58, ++ [1][1][2][1][1][1] = 40, ++ [1][1][2][1][3][1] = 50, ++ [1][1][2][1][5][1] = 40, ++ [1][1][2][1][6][1] = 40, ++ [1][1][2][1][9][1] = 40, ++ [1][1][2][1][8][1] = 6, ++ [1][1][2][1][11][1] = 28, ++ [1][1][2][1][2][5] = 68, ++ [1][1][2][1][1][5] = 40, ++ [1][1][2][1][3][5] = 50, ++ [1][1][2][1][5][5] = 40, ++ [1][1][2][1][6][5] = 40, ++ [1][1][2][1][9][5] = 40, ++ [1][1][2][1][8][5] = 6, ++ [1][1][2][1][11][5] = 28, ++ [1][1][2][1][2][9] = 68, ++ [1][1][2][1][1][9] = 40, ++ [1][1][2][1][3][9] = 50, ++ [1][1][2][1][5][9] = 40, ++ [1][1][2][1][6][9] = 40, ++ [1][1][2][1][9][9] = 40, ++ [1][1][2][1][8][9] = 30, ++ [1][1][2][1][11][9] = 28, ++ [1][1][2][1][2][13] = 58, ++ [1][1][2][1][1][13] = 40, ++ [1][1][2][1][3][13] = 50, ++ [1][1][2][1][5][13] = 40, ++ [1][1][2][1][6][13] = 40, ++ [1][1][2][1][9][13] = 40, ++ [1][1][2][1][8][13] = 30, ++ [1][1][2][1][11][13] = 28, ++ [1][1][2][1][2][16] = 56, ++ [1][1][2][1][1][16] = 40, ++ [1][1][2][1][3][16] = 72, ++ [1][1][2][1][5][16] = 56, ++ [1][1][2][1][6][16] = 40, ++ [1][1][2][1][9][16] = 40, ++ [1][1][2][1][8][16] = 30, ++ [1][1][2][1][11][16] = 28, ++ [1][1][2][1][2][20] = 68, ++ [1][1][2][1][1][20] = 40, ++ [1][1][2][1][3][20] = 72, ++ [1][1][2][1][5][20] = 68, ++ [1][1][2][1][6][20] = 40, ++ [1][1][2][1][9][20] = 40, ++ [1][1][2][1][8][20] = 30, ++ [1][1][2][1][11][20] = 28, ++ [1][1][2][1][2][24] = 68, ++ [1][1][2][1][1][24] = 40, ++ [1][1][2][1][3][24] = 72, ++ [1][1][2][1][5][24] = 127, ++ [1][1][2][1][6][24] = 40, ++ [1][1][2][1][9][24] = 127, ++ [1][1][2][1][8][24] = 30, ++ [1][1][2][1][11][24] = 28, ++ [1][1][2][1][2][28] = 68, ++ [1][1][2][1][1][28] = 40, ++ [1][1][2][1][3][28] = 72, ++ [1][1][2][1][5][28] = 127, ++ [1][1][2][1][6][28] = 40, ++ [1][1][2][1][9][28] = 127, ++ [1][1][2][1][8][28] = 30, ++ [1][1][2][1][11][28] = 28, ++ [1][1][2][1][2][32] = 68, ++ [1][1][2][1][1][32] = 40, ++ [1][1][2][1][3][32] = 72, ++ [1][1][2][1][5][32] = 68, ++ [1][1][2][1][6][32] = 40, ++ [1][1][2][1][9][32] = 40, ++ [1][1][2][1][8][32] = 30, ++ [1][1][2][1][11][32] = 28, ++ [1][1][2][1][2][36] = 68, ++ [1][1][2][1][1][36] = 127, ++ [1][1][2][1][3][36] = 72, ++ [1][1][2][1][5][36] = 68, ++ [1][1][2][1][6][36] = 40, ++ [1][1][2][1][9][36] = 68, ++ [1][1][2][1][8][36] = 30, ++ [1][1][2][1][11][36] = 127, ++ [1][1][2][1][2][39] = 72, ++ [1][1][2][1][1][39] = 4, ++ [1][1][2][1][3][39] = 127, ++ [1][1][2][1][5][39] = 72, ++ [1][1][2][1][6][39] = 4, ++ [1][1][2][1][9][39] = 72, ++ [1][1][2][1][8][39] = 30, ++ [1][1][2][1][11][39] = 28, ++ [1][1][2][1][2][43] = 72, ++ [1][1][2][1][1][43] = 4, ++ [1][1][2][1][3][43] = 127, ++ [1][1][2][1][5][43] = 72, ++ [1][1][2][1][6][43] = 4, ++ [1][1][2][1][9][43] = 72, ++ [1][1][2][1][8][43] = 30, ++ [1][1][2][1][11][43] = 28, ++ [2][0][2][0][2][3] = 64, ++ [2][0][2][0][1][3] = 64, ++ [2][0][2][0][3][3] = 64, ++ [2][0][2][0][5][3] = 62, ++ [2][0][2][0][6][3] = 64, ++ [2][0][2][0][9][3] = 64, ++ [2][0][2][0][8][3] = 30, ++ [2][0][2][0][11][3] = 52, ++ [2][0][2][0][2][11] = 64, ++ [2][0][2][0][1][11] = 64, ++ [2][0][2][0][3][11] = 64, ++ [2][0][2][0][5][11] = 62, ++ [2][0][2][0][6][11] = 64, ++ [2][0][2][0][9][11] = 64, ++ [2][0][2][0][8][11] = 54, ++ [2][0][2][0][11][11] = 52, ++ [2][0][2][0][2][18] = 62, ++ [2][0][2][0][1][18] = 64, ++ [2][0][2][0][3][18] = 72, ++ [2][0][2][0][5][18] = 66, ++ [2][0][2][0][6][18] = 64, ++ [2][0][2][0][9][18] = 64, ++ [2][0][2][0][8][18] = 54, ++ [2][0][2][0][11][18] = 52, ++ [2][0][2][0][2][26] = 72, ++ [2][0][2][0][1][26] = 64, ++ [2][0][2][0][3][26] = 72, ++ [2][0][2][0][5][26] = 127, ++ [2][0][2][0][6][26] = 64, ++ [2][0][2][0][9][26] = 127, ++ [2][0][2][0][8][26] = 54, ++ [2][0][2][0][11][26] = 52, ++ [2][0][2][0][2][34] = 72, ++ [2][0][2][0][1][34] = 127, ++ [2][0][2][0][3][34] = 72, ++ [2][0][2][0][5][34] = 72, ++ [2][0][2][0][6][34] = 64, ++ [2][0][2][0][9][34] = 72, ++ [2][0][2][0][8][34] = 54, ++ [2][0][2][0][11][34] = 127, ++ [2][0][2][0][2][41] = 72, ++ [2][0][2][0][1][41] = 28, ++ [2][0][2][0][3][41] = 127, ++ [2][0][2][0][5][41] = 72, ++ [2][0][2][0][6][41] = 28, ++ [2][0][2][0][9][41] = 72, ++ [2][0][2][0][8][41] = 54, ++ [2][0][2][0][11][41] = 52, ++ [2][1][2][0][2][3] = 56, ++ [2][1][2][0][1][3] = 52, ++ [2][1][2][0][3][3] = 52, ++ [2][1][2][0][5][3] = 52, ++ [2][1][2][0][6][3] = 52, ++ [2][1][2][0][9][3] = 52, ++ [2][1][2][0][8][3] = 18, ++ [2][1][2][0][11][3] = 40, ++ [2][1][2][0][2][11] = 56, ++ [2][1][2][0][1][11] = 52, ++ [2][1][2][0][3][11] = 52, ++ [2][1][2][0][5][11] = 52, ++ [2][1][2][0][6][11] = 52, ++ [2][1][2][0][9][11] = 52, ++ [2][1][2][0][8][11] = 42, ++ [2][1][2][0][11][11] = 40, ++ [2][1][2][0][2][18] = 56, ++ [2][1][2][0][1][18] = 52, ++ [2][1][2][0][3][18] = 72, ++ [2][1][2][0][5][18] = 56, ++ [2][1][2][0][6][18] = 52, ++ [2][1][2][0][9][18] = 52, ++ [2][1][2][0][8][18] = 42, ++ [2][1][2][0][11][18] = 40, ++ [2][1][2][0][2][26] = 72, ++ [2][1][2][0][1][26] = 52, ++ [2][1][2][0][3][26] = 72, ++ [2][1][2][0][5][26] = 127, ++ [2][1][2][0][6][26] = 52, ++ [2][1][2][0][9][26] = 127, ++ [2][1][2][0][8][26] = 42, ++ [2][1][2][0][11][26] = 40, ++ [2][1][2][0][2][34] = 72, ++ [2][1][2][0][1][34] = 127, ++ [2][1][2][0][3][34] = 72, ++ [2][1][2][0][5][34] = 72, ++ [2][1][2][0][6][34] = 52, ++ [2][1][2][0][9][34] = 72, ++ [2][1][2][0][8][34] = 42, ++ [2][1][2][0][11][34] = 127, ++ [2][1][2][0][2][41] = 72, ++ [2][1][2][0][1][41] = 16, ++ [2][1][2][0][3][41] = 127, ++ [2][1][2][0][5][41] = 72, ++ [2][1][2][0][6][41] = 16, ++ [2][1][2][0][9][41] = 72, ++ [2][1][2][0][8][41] = 42, ++ [2][1][2][0][11][41] = 40, ++ [2][1][2][1][2][3] = 56, ++ [2][1][2][1][1][3] = 40, ++ [2][1][2][1][3][3] = 52, ++ [2][1][2][1][5][3] = 40, ++ [2][1][2][1][6][3] = 40, ++ [2][1][2][1][9][3] = 40, ++ [2][1][2][1][8][3] = 6, ++ [2][1][2][1][11][3] = 28, ++ [2][1][2][1][2][11] = 56, ++ [2][1][2][1][1][11] = 40, ++ [2][1][2][1][3][11] = 52, ++ [2][1][2][1][5][11] = 40, ++ [2][1][2][1][6][11] = 40, ++ [2][1][2][1][9][11] = 40, ++ [2][1][2][1][8][11] = 30, ++ [2][1][2][1][11][11] = 28, ++ [2][1][2][1][2][18] = 56, ++ [2][1][2][1][1][18] = 40, ++ [2][1][2][1][3][18] = 72, ++ [2][1][2][1][5][18] = 56, ++ [2][1][2][1][6][18] = 40, ++ [2][1][2][1][9][18] = 40, ++ [2][1][2][1][8][18] = 30, ++ [2][1][2][1][11][18] = 28, ++ [2][1][2][1][2][26] = 68, ++ [2][1][2][1][1][26] = 40, ++ [2][1][2][1][3][26] = 72, ++ [2][1][2][1][5][26] = 127, ++ [2][1][2][1][6][26] = 40, ++ [2][1][2][1][9][26] = 127, ++ [2][1][2][1][8][26] = 30, ++ [2][1][2][1][11][26] = 28, ++ [2][1][2][1][2][34] = 68, ++ [2][1][2][1][1][34] = 127, ++ [2][1][2][1][3][34] = 72, ++ [2][1][2][1][5][34] = 68, ++ [2][1][2][1][6][34] = 40, ++ [2][1][2][1][9][34] = 68, ++ [2][1][2][1][8][34] = 30, ++ [2][1][2][1][11][34] = 127, ++ [2][1][2][1][2][41] = 72, ++ [2][1][2][1][1][41] = 4, ++ [2][1][2][1][3][41] = 127, ++ [2][1][2][1][5][41] = 72, ++ [2][1][2][1][6][41] = 4, ++ [2][1][2][1][9][41] = 72, ++ [2][1][2][1][8][41] = 30, ++ [2][1][2][1][11][41] = 28, ++}; ++ ++const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = { ++ [0][0][0][0] = 32, ++ [0][0][0][1] = 32, ++ [0][0][0][2] = 32, ++ [0][0][0][3] = 32, ++ [0][0][0][4] = 32, ++ [0][0][0][5] = 32, ++ [0][0][0][6] = 32, ++ [0][0][0][7] = 32, ++ [0][0][0][8] = 32, ++ [0][0][0][9] = 32, ++ [0][0][0][10] = 32, ++ [0][0][0][11] = 32, ++ [0][0][0][12] = 32, ++ [0][0][0][13] = 0, ++ [0][1][0][0] = 20, ++ [0][1][0][1] = 20, ++ [0][1][0][2] = 20, ++ [0][1][0][3] = 20, ++ [0][1][0][4] = 20, ++ [0][1][0][5] = 20, ++ [0][1][0][6] = 20, ++ [0][1][0][7] = 20, ++ [0][1][0][8] = 20, ++ [0][1][0][9] = 20, ++ [0][1][0][10] = 20, ++ [0][1][0][11] = 20, ++ [0][1][0][12] = 20, ++ [0][1][0][13] = 0, ++ [1][0][0][0] = 42, ++ [1][0][0][1] = 42, ++ [1][0][0][2] = 42, ++ [1][0][0][3] = 42, ++ [1][0][0][4] = 42, ++ [1][0][0][5] = 42, ++ [1][0][0][6] = 42, ++ [1][0][0][7] = 42, ++ [1][0][0][8] = 42, ++ [1][0][0][9] = 42, ++ [1][0][0][10] = 42, ++ [1][0][0][11] = 42, ++ [1][0][0][12] = 36, ++ [1][0][0][13] = 0, ++ [1][1][0][0] = 30, ++ [1][1][0][1] = 30, ++ [1][1][0][2] = 30, ++ [1][1][0][3] = 30, ++ [1][1][0][4] = 30, ++ [1][1][0][5] = 30, ++ [1][1][0][6] = 30, ++ [1][1][0][7] = 30, ++ [1][1][0][8] = 30, ++ [1][1][0][9] = 30, ++ [1][1][0][10] = 30, ++ [1][1][0][11] = 30, ++ [1][1][0][12] = 30, ++ [1][1][0][13] = 0, ++ [2][0][0][0] = 52, ++ [2][0][0][1] = 52, ++ [2][0][0][2] = 52, ++ [2][0][0][3] = 52, ++ [2][0][0][4] = 52, ++ [2][0][0][5] = 52, ++ [2][0][0][6] = 52, ++ [2][0][0][7] = 52, ++ [2][0][0][8] = 52, ++ [2][0][0][9] = 52, ++ [2][0][0][10] = 52, ++ [2][0][0][11] = 52, ++ [2][0][0][12] = 40, ++ [2][0][0][13] = 0, ++ [2][1][0][0] = 40, ++ [2][1][0][1] = 40, ++ [2][1][0][2] = 40, ++ [2][1][0][3] = 40, ++ [2][1][0][4] = 40, ++ [2][1][0][5] = 40, ++ [2][1][0][6] = 40, ++ [2][1][0][7] = 40, ++ [2][1][0][8] = 40, ++ [2][1][0][9] = 40, ++ [2][1][0][10] = 40, ++ [2][1][0][11] = 40, ++ [2][1][0][12] = 26, ++ [2][1][0][13] = 0, ++ [0][0][2][0] = 70, ++ [0][0][1][0] = 32, ++ [0][0][3][0] = 40, ++ [0][0][5][0] = 70, ++ [0][0][6][0] = 32, ++ [0][0][9][0] = 32, ++ [0][0][8][0] = 60, ++ [0][0][11][0] = 32, ++ [0][0][2][1] = 70, ++ [0][0][1][1] = 32, ++ [0][0][3][1] = 40, ++ [0][0][5][1] = 70, ++ [0][0][6][1] = 32, ++ [0][0][9][1] = 32, ++ [0][0][8][1] = 60, ++ [0][0][11][1] = 32, ++ [0][0][2][2] = 74, ++ [0][0][1][2] = 32, ++ [0][0][3][2] = 40, ++ [0][0][5][2] = 74, ++ [0][0][6][2] = 32, ++ [0][0][9][2] = 32, ++ [0][0][8][2] = 60, ++ [0][0][11][2] = 32, ++ [0][0][2][3] = 78, ++ [0][0][1][3] = 32, ++ [0][0][3][3] = 40, ++ [0][0][5][3] = 78, ++ [0][0][6][3] = 32, ++ [0][0][9][3] = 32, ++ [0][0][8][3] = 60, ++ [0][0][11][3] = 32, ++ [0][0][2][4] = 78, ++ [0][0][1][4] = 32, ++ [0][0][3][4] = 40, ++ [0][0][5][4] = 78, ++ [0][0][6][4] = 32, ++ [0][0][9][4] = 32, ++ [0][0][8][4] = 60, ++ [0][0][11][4] = 32, ++ [0][0][2][5] = 78, ++ [0][0][1][5] = 32, ++ [0][0][3][5] = 40, ++ [0][0][5][5] = 78, ++ [0][0][6][5] = 32, ++ [0][0][9][5] = 32, ++ [0][0][8][5] = 60, ++ [0][0][11][5] = 32, ++ [0][0][2][6] = 78, ++ [0][0][1][6] = 32, ++ [0][0][3][6] = 40, ++ [0][0][5][6] = 78, ++ [0][0][6][6] = 32, ++ [0][0][9][6] = 32, ++ [0][0][8][6] = 60, ++ [0][0][11][6] = 32, ++ [0][0][2][7] = 78, ++ [0][0][1][7] = 32, ++ [0][0][3][7] = 40, ++ [0][0][5][7] = 78, ++ [0][0][6][7] = 32, ++ [0][0][9][7] = 32, ++ [0][0][8][7] = 60, ++ [0][0][11][7] = 32, ++ [0][0][2][8] = 74, ++ [0][0][1][8] = 32, ++ [0][0][3][8] = 40, ++ [0][0][5][8] = 74, ++ [0][0][6][8] = 32, ++ [0][0][9][8] = 32, ++ [0][0][8][8] = 60, ++ [0][0][11][8] = 32, ++ [0][0][2][9] = 70, ++ [0][0][1][9] = 32, ++ [0][0][3][9] = 40, ++ [0][0][5][9] = 70, ++ [0][0][6][9] = 32, ++ [0][0][9][9] = 32, ++ [0][0][8][9] = 60, ++ [0][0][11][9] = 32, ++ [0][0][2][10] = 70, ++ [0][0][1][10] = 32, ++ [0][0][3][10] = 40, ++ [0][0][5][10] = 70, ++ [0][0][6][10] = 32, ++ [0][0][9][10] = 32, ++ [0][0][8][10] = 60, ++ [0][0][11][10] = 32, ++ [0][0][2][11] = 58, ++ [0][0][1][11] = 32, ++ [0][0][3][11] = 40, ++ [0][0][5][11] = 58, ++ [0][0][6][11] = 32, ++ [0][0][9][11] = 32, ++ [0][0][8][11] = 60, ++ [0][0][11][11] = 32, ++ [0][0][2][12] = 34, ++ [0][0][1][12] = 32, ++ [0][0][3][12] = 40, ++ [0][0][5][12] = 34, ++ [0][0][6][12] = 32, ++ [0][0][9][12] = 32, ++ [0][0][8][12] = 60, ++ [0][0][11][12] = 32, ++ [0][0][2][13] = 127, ++ [0][0][1][13] = 127, ++ [0][0][3][13] = 127, ++ [0][0][5][13] = 127, ++ [0][0][6][13] = 127, ++ [0][0][9][13] = 127, ++ [0][0][8][13] = 127, ++ [0][0][11][13] = 127, ++ [0][1][2][0] = 64, ++ [0][1][1][0] = 20, ++ [0][1][3][0] = 28, ++ [0][1][5][0] = 64, ++ [0][1][6][0] = 20, ++ [0][1][9][0] = 20, ++ [0][1][8][0] = 48, ++ [0][1][11][0] = 20, ++ [0][1][2][1] = 64, ++ [0][1][1][1] = 20, ++ [0][1][3][1] = 28, ++ [0][1][5][1] = 64, ++ [0][1][6][1] = 20, ++ [0][1][9][1] = 20, ++ [0][1][8][1] = 48, ++ [0][1][11][1] = 20, ++ [0][1][2][2] = 68, ++ [0][1][1][2] = 20, ++ [0][1][3][2] = 28, ++ [0][1][5][2] = 68, ++ [0][1][6][2] = 20, ++ [0][1][9][2] = 20, ++ [0][1][8][2] = 48, ++ [0][1][11][2] = 20, ++ [0][1][2][3] = 72, ++ [0][1][1][3] = 20, ++ [0][1][3][3] = 28, ++ [0][1][5][3] = 72, ++ [0][1][6][3] = 20, ++ [0][1][9][3] = 20, ++ [0][1][8][3] = 48, ++ [0][1][11][3] = 20, ++ [0][1][2][4] = 76, ++ [0][1][1][4] = 20, ++ [0][1][3][4] = 28, ++ [0][1][5][4] = 76, ++ [0][1][6][4] = 20, ++ [0][1][9][4] = 20, ++ [0][1][8][4] = 48, ++ [0][1][11][4] = 20, ++ [0][1][2][5] = 78, ++ [0][1][1][5] = 20, ++ [0][1][3][5] = 28, ++ [0][1][5][5] = 78, ++ [0][1][6][5] = 20, ++ [0][1][9][5] = 20, ++ [0][1][8][5] = 48, ++ [0][1][11][5] = 20, ++ [0][1][2][6] = 76, ++ [0][1][1][6] = 20, ++ [0][1][3][6] = 28, ++ [0][1][5][6] = 76, ++ [0][1][6][6] = 20, ++ [0][1][9][6] = 20, ++ [0][1][8][6] = 48, ++ [0][1][11][6] = 20, ++ [0][1][2][7] = 72, ++ [0][1][1][7] = 20, ++ [0][1][3][7] = 28, ++ [0][1][5][7] = 72, ++ [0][1][6][7] = 20, ++ [0][1][9][7] = 20, ++ [0][1][8][7] = 48, ++ [0][1][11][7] = 20, ++ [0][1][2][8] = 68, ++ [0][1][1][8] = 20, ++ [0][1][3][8] = 28, ++ [0][1][5][8] = 68, ++ [0][1][6][8] = 20, ++ [0][1][9][8] = 20, ++ [0][1][8][8] = 48, ++ [0][1][11][8] = 20, ++ [0][1][2][9] = 64, ++ [0][1][1][9] = 20, ++ [0][1][3][9] = 28, ++ [0][1][5][9] = 64, ++ [0][1][6][9] = 20, ++ [0][1][9][9] = 20, ++ [0][1][8][9] = 48, ++ [0][1][11][9] = 20, ++ [0][1][2][10] = 64, ++ [0][1][1][10] = 20, ++ [0][1][3][10] = 28, ++ [0][1][5][10] = 64, ++ [0][1][6][10] = 20, ++ [0][1][9][10] = 20, ++ [0][1][8][10] = 48, ++ [0][1][11][10] = 20, ++ [0][1][2][11] = 54, ++ [0][1][1][11] = 20, ++ [0][1][3][11] = 28, ++ [0][1][5][11] = 54, ++ [0][1][6][11] = 20, ++ [0][1][9][11] = 20, ++ [0][1][8][11] = 48, ++ [0][1][11][11] = 20, ++ [0][1][2][12] = 32, ++ [0][1][1][12] = 20, ++ [0][1][3][12] = 28, ++ [0][1][5][12] = 32, ++ [0][1][6][12] = 20, ++ [0][1][9][12] = 20, ++ [0][1][8][12] = 48, ++ [0][1][11][12] = 20, ++ [0][1][2][13] = 127, ++ [0][1][1][13] = 127, ++ [0][1][3][13] = 127, ++ [0][1][5][13] = 127, ++ [0][1][6][13] = 127, ++ [0][1][9][13] = 127, ++ [0][1][8][13] = 127, ++ [0][1][11][13] = 127, ++ [1][0][2][0] = 72, ++ [1][0][1][0] = 42, ++ [1][0][3][0] = 50, ++ [1][0][5][0] = 72, ++ [1][0][6][0] = 42, ++ [1][0][9][0] = 42, ++ [1][0][8][0] = 60, ++ [1][0][11][0] = 42, ++ [1][0][2][1] = 72, ++ [1][0][1][1] = 42, ++ [1][0][3][1] = 50, ++ [1][0][5][1] = 72, ++ [1][0][6][1] = 42, ++ [1][0][9][1] = 42, ++ [1][0][8][1] = 60, ++ [1][0][11][1] = 42, ++ [1][0][2][2] = 76, ++ [1][0][1][2] = 42, ++ [1][0][3][2] = 50, ++ [1][0][5][2] = 76, ++ [1][0][6][2] = 42, ++ [1][0][9][2] = 42, ++ [1][0][8][2] = 60, ++ [1][0][11][2] = 42, ++ [1][0][2][3] = 78, ++ [1][0][1][3] = 42, ++ [1][0][3][3] = 50, ++ [1][0][5][3] = 78, ++ [1][0][6][3] = 42, ++ [1][0][9][3] = 42, ++ [1][0][8][3] = 60, ++ [1][0][11][3] = 42, ++ [1][0][2][4] = 78, ++ [1][0][1][4] = 42, ++ [1][0][3][4] = 50, ++ [1][0][5][4] = 78, ++ [1][0][6][4] = 42, ++ [1][0][9][4] = 42, ++ [1][0][8][4] = 60, ++ [1][0][11][4] = 42, ++ [1][0][2][5] = 78, ++ [1][0][1][5] = 42, ++ [1][0][3][5] = 50, ++ [1][0][5][5] = 78, ++ [1][0][6][5] = 42, ++ [1][0][9][5] = 42, ++ [1][0][8][5] = 60, ++ [1][0][11][5] = 42, ++ [1][0][2][6] = 78, ++ [1][0][1][6] = 42, ++ [1][0][3][6] = 50, ++ [1][0][5][6] = 78, ++ [1][0][6][6] = 42, ++ [1][0][9][6] = 42, ++ [1][0][8][6] = 60, ++ [1][0][11][6] = 42, ++ [1][0][2][7] = 78, ++ [1][0][1][7] = 42, ++ [1][0][3][7] = 50, ++ [1][0][5][7] = 78, ++ [1][0][6][7] = 42, ++ [1][0][9][7] = 42, ++ [1][0][8][7] = 60, ++ [1][0][11][7] = 42, ++ [1][0][2][8] = 78, ++ [1][0][1][8] = 42, ++ [1][0][3][8] = 50, ++ [1][0][5][8] = 78, ++ [1][0][6][8] = 42, ++ [1][0][9][8] = 42, ++ [1][0][8][8] = 60, ++ [1][0][11][8] = 42, ++ [1][0][2][9] = 74, ++ [1][0][1][9] = 42, ++ [1][0][3][9] = 50, ++ [1][0][5][9] = 74, ++ [1][0][6][9] = 42, ++ [1][0][9][9] = 42, ++ [1][0][8][9] = 60, ++ [1][0][11][9] = 42, ++ [1][0][2][10] = 74, ++ [1][0][1][10] = 42, ++ [1][0][3][10] = 50, ++ [1][0][5][10] = 74, ++ [1][0][6][10] = 42, ++ [1][0][9][10] = 42, ++ [1][0][8][10] = 60, ++ [1][0][11][10] = 42, ++ [1][0][2][11] = 64, ++ [1][0][1][11] = 42, ++ [1][0][3][11] = 50, ++ [1][0][5][11] = 64, ++ [1][0][6][11] = 42, ++ [1][0][9][11] = 42, ++ [1][0][8][11] = 60, ++ [1][0][11][11] = 42, ++ [1][0][2][12] = 36, ++ [1][0][1][12] = 42, ++ [1][0][3][12] = 50, ++ [1][0][5][12] = 36, ++ [1][0][6][12] = 42, ++ [1][0][9][12] = 42, ++ [1][0][8][12] = 60, ++ [1][0][11][12] = 42, ++ [1][0][2][13] = 127, ++ [1][0][1][13] = 127, ++ [1][0][3][13] = 127, ++ [1][0][5][13] = 127, ++ [1][0][6][13] = 127, ++ [1][0][9][13] = 127, ++ [1][0][8][13] = 127, ++ [1][0][11][13] = 127, ++ [1][1][2][0] = 66, ++ [1][1][1][0] = 30, ++ [1][1][3][0] = 38, ++ [1][1][5][0] = 66, ++ [1][1][6][0] = 30, ++ [1][1][9][0] = 30, ++ [1][1][8][0] = 48, ++ [1][1][11][0] = 30, ++ [1][1][2][1] = 66, ++ [1][1][1][1] = 30, ++ [1][1][3][1] = 38, ++ [1][1][5][1] = 66, ++ [1][1][6][1] = 30, ++ [1][1][9][1] = 30, ++ [1][1][8][1] = 48, ++ [1][1][11][1] = 30, ++ [1][1][2][2] = 70, ++ [1][1][1][2] = 30, ++ [1][1][3][2] = 38, ++ [1][1][5][2] = 70, ++ [1][1][6][2] = 30, ++ [1][1][9][2] = 30, ++ [1][1][8][2] = 48, ++ [1][1][11][2] = 30, ++ [1][1][2][3] = 74, ++ [1][1][1][3] = 30, ++ [1][1][3][3] = 38, ++ [1][1][5][3] = 74, ++ [1][1][6][3] = 30, ++ [1][1][9][3] = 30, ++ [1][1][8][3] = 48, ++ [1][1][11][3] = 30, ++ [1][1][2][4] = 78, ++ [1][1][1][4] = 30, ++ [1][1][3][4] = 38, ++ [1][1][5][4] = 78, ++ [1][1][6][4] = 30, ++ [1][1][9][4] = 30, ++ [1][1][8][4] = 48, ++ [1][1][11][4] = 30, ++ [1][1][2][5] = 78, ++ [1][1][1][5] = 30, ++ [1][1][3][5] = 38, ++ [1][1][5][5] = 78, ++ [1][1][6][5] = 30, ++ [1][1][9][5] = 30, ++ [1][1][8][5] = 48, ++ [1][1][11][5] = 30, ++ [1][1][2][6] = 78, ++ [1][1][1][6] = 30, ++ [1][1][3][6] = 38, ++ [1][1][5][6] = 78, ++ [1][1][6][6] = 30, ++ [1][1][9][6] = 30, ++ [1][1][8][6] = 48, ++ [1][1][11][6] = 30, ++ [1][1][2][7] = 74, ++ [1][1][1][7] = 30, ++ [1][1][3][7] = 38, ++ [1][1][5][7] = 74, ++ [1][1][6][7] = 30, ++ [1][1][9][7] = 30, ++ [1][1][8][7] = 48, ++ [1][1][11][7] = 30, ++ [1][1][2][8] = 70, ++ [1][1][1][8] = 30, ++ [1][1][3][8] = 38, ++ [1][1][5][8] = 70, ++ [1][1][6][8] = 30, ++ [1][1][9][8] = 30, ++ [1][1][8][8] = 48, ++ [1][1][11][8] = 30, ++ [1][1][2][9] = 66, ++ [1][1][1][9] = 30, ++ [1][1][3][9] = 38, ++ [1][1][5][9] = 66, ++ [1][1][6][9] = 30, ++ [1][1][9][9] = 30, ++ [1][1][8][9] = 48, ++ [1][1][11][9] = 30, ++ [1][1][2][10] = 66, ++ [1][1][1][10] = 30, ++ [1][1][3][10] = 38, ++ [1][1][5][10] = 66, ++ [1][1][6][10] = 30, ++ [1][1][9][10] = 30, ++ [1][1][8][10] = 48, ++ [1][1][11][10] = 30, ++ [1][1][2][11] = 60, ++ [1][1][1][11] = 30, ++ [1][1][3][11] = 38, ++ [1][1][5][11] = 60, ++ [1][1][6][11] = 30, ++ [1][1][9][11] = 30, ++ [1][1][8][11] = 48, ++ [1][1][11][11] = 30, ++ [1][1][2][12] = 32, ++ [1][1][1][12] = 30, ++ [1][1][3][12] = 38, ++ [1][1][5][12] = 32, ++ [1][1][6][12] = 30, ++ [1][1][9][12] = 30, ++ [1][1][8][12] = 48, ++ [1][1][11][12] = 30, ++ [1][1][2][13] = 127, ++ [1][1][1][13] = 127, ++ [1][1][3][13] = 127, ++ [1][1][5][13] = 127, ++ [1][1][6][13] = 127, ++ [1][1][9][13] = 127, ++ [1][1][8][13] = 127, ++ [1][1][11][13] = 127, ++ [2][0][2][0] = 76, ++ [2][0][1][0] = 52, ++ [2][0][3][0] = 64, ++ [2][0][5][0] = 76, ++ [2][0][6][0] = 52, ++ [2][0][9][0] = 52, ++ [2][0][8][0] = 60, ++ [2][0][11][0] = 52, ++ [2][0][2][1] = 76, ++ [2][0][1][1] = 52, ++ [2][0][3][1] = 64, ++ [2][0][5][1] = 76, ++ [2][0][6][1] = 52, ++ [2][0][9][1] = 52, ++ [2][0][8][1] = 60, ++ [2][0][11][1] = 52, ++ [2][0][2][2] = 78, ++ [2][0][1][2] = 52, ++ [2][0][3][2] = 64, ++ [2][0][5][2] = 78, ++ [2][0][6][2] = 52, ++ [2][0][9][2] = 52, ++ [2][0][8][2] = 60, ++ [2][0][11][2] = 52, ++ [2][0][2][3] = 78, ++ [2][0][1][3] = 52, ++ [2][0][3][3] = 64, ++ [2][0][5][3] = 78, ++ [2][0][6][3] = 52, ++ [2][0][9][3] = 52, ++ [2][0][8][3] = 60, ++ [2][0][11][3] = 52, ++ [2][0][2][4] = 78, ++ [2][0][1][4] = 52, ++ [2][0][3][4] = 64, ++ [2][0][5][4] = 78, ++ [2][0][6][4] = 52, ++ [2][0][9][4] = 52, ++ [2][0][8][4] = 60, ++ [2][0][11][4] = 52, ++ [2][0][2][5] = 78, ++ [2][0][1][5] = 52, ++ [2][0][3][5] = 64, ++ [2][0][5][5] = 78, ++ [2][0][6][5] = 52, ++ [2][0][9][5] = 52, ++ [2][0][8][5] = 60, ++ [2][0][11][5] = 52, ++ [2][0][2][6] = 78, ++ [2][0][1][6] = 52, ++ [2][0][3][6] = 64, ++ [2][0][5][6] = 78, ++ [2][0][6][6] = 52, ++ [2][0][9][6] = 52, ++ [2][0][8][6] = 60, ++ [2][0][11][6] = 52, ++ [2][0][2][7] = 78, ++ [2][0][1][7] = 52, ++ [2][0][3][7] = 64, ++ [2][0][5][7] = 78, ++ [2][0][6][7] = 52, ++ [2][0][9][7] = 52, ++ [2][0][8][7] = 60, ++ [2][0][11][7] = 52, ++ [2][0][2][8] = 78, ++ [2][0][1][8] = 52, ++ [2][0][3][8] = 64, ++ [2][0][5][8] = 78, ++ [2][0][6][8] = 52, ++ [2][0][9][8] = 52, ++ [2][0][8][8] = 60, ++ [2][0][11][8] = 52, ++ [2][0][2][9] = 76, ++ [2][0][1][9] = 52, ++ [2][0][3][9] = 64, ++ [2][0][5][9] = 76, ++ [2][0][6][9] = 52, ++ [2][0][9][9] = 52, ++ [2][0][8][9] = 60, ++ [2][0][11][9] = 52, ++ [2][0][2][10] = 76, ++ [2][0][1][10] = 52, ++ [2][0][3][10] = 64, ++ [2][0][5][10] = 76, ++ [2][0][6][10] = 52, ++ [2][0][9][10] = 52, ++ [2][0][8][10] = 60, ++ [2][0][11][10] = 52, ++ [2][0][2][11] = 68, ++ [2][0][1][11] = 52, ++ [2][0][3][11] = 64, ++ [2][0][5][11] = 68, ++ [2][0][6][11] = 52, ++ [2][0][9][11] = 52, ++ [2][0][8][11] = 60, ++ [2][0][11][11] = 52, ++ [2][0][2][12] = 40, ++ [2][0][1][12] = 52, ++ [2][0][3][12] = 64, ++ [2][0][5][12] = 40, ++ [2][0][6][12] = 52, ++ [2][0][9][12] = 52, ++ [2][0][8][12] = 60, ++ [2][0][11][12] = 52, ++ [2][0][2][13] = 127, ++ [2][0][1][13] = 127, ++ [2][0][3][13] = 127, ++ [2][0][5][13] = 127, ++ [2][0][6][13] = 127, ++ [2][0][9][13] = 127, ++ [2][0][8][13] = 127, ++ [2][0][11][13] = 127, ++ [2][1][2][0] = 68, ++ [2][1][1][0] = 40, ++ [2][1][3][0] = 52, ++ [2][1][5][0] = 68, ++ [2][1][6][0] = 40, ++ [2][1][9][0] = 40, ++ [2][1][8][0] = 48, ++ [2][1][11][0] = 40, ++ [2][1][2][1] = 68, ++ [2][1][1][1] = 40, ++ [2][1][3][1] = 52, ++ [2][1][5][1] = 68, ++ [2][1][6][1] = 40, ++ [2][1][9][1] = 40, ++ [2][1][8][1] = 48, ++ [2][1][11][1] = 40, ++ [2][1][2][2] = 72, ++ [2][1][1][2] = 40, ++ [2][1][3][2] = 52, ++ [2][1][5][2] = 72, ++ [2][1][6][2] = 40, ++ [2][1][9][2] = 40, ++ [2][1][8][2] = 48, ++ [2][1][11][2] = 40, ++ [2][1][2][3] = 76, ++ [2][1][1][3] = 40, ++ [2][1][3][3] = 52, ++ [2][1][5][3] = 76, ++ [2][1][6][3] = 40, ++ [2][1][9][3] = 40, ++ [2][1][8][3] = 48, ++ [2][1][11][3] = 40, ++ [2][1][2][4] = 78, ++ [2][1][1][4] = 40, ++ [2][1][3][4] = 52, ++ [2][1][5][4] = 78, ++ [2][1][6][4] = 40, ++ [2][1][9][4] = 40, ++ [2][1][8][4] = 48, ++ [2][1][11][4] = 40, ++ [2][1][2][5] = 78, ++ [2][1][1][5] = 40, ++ [2][1][3][5] = 52, ++ [2][1][5][5] = 78, ++ [2][1][6][5] = 40, ++ [2][1][9][5] = 40, ++ [2][1][8][5] = 48, ++ [2][1][11][5] = 40, ++ [2][1][2][6] = 78, ++ [2][1][1][6] = 40, ++ [2][1][3][6] = 52, ++ [2][1][5][6] = 78, ++ [2][1][6][6] = 40, ++ [2][1][9][6] = 40, ++ [2][1][8][6] = 48, ++ [2][1][11][6] = 40, ++ [2][1][2][7] = 78, ++ [2][1][1][7] = 40, ++ [2][1][3][7] = 52, ++ [2][1][5][7] = 78, ++ [2][1][6][7] = 40, ++ [2][1][9][7] = 40, ++ [2][1][8][7] = 48, ++ [2][1][11][7] = 40, ++ [2][1][2][8] = 74, ++ [2][1][1][8] = 40, ++ [2][1][3][8] = 52, ++ [2][1][5][8] = 74, ++ [2][1][6][8] = 40, ++ [2][1][9][8] = 40, ++ [2][1][8][8] = 48, ++ [2][1][11][8] = 40, ++ [2][1][2][9] = 70, ++ [2][1][1][9] = 40, ++ [2][1][3][9] = 52, ++ [2][1][5][9] = 70, ++ [2][1][6][9] = 40, ++ [2][1][9][9] = 40, ++ [2][1][8][9] = 48, ++ [2][1][11][9] = 40, ++ [2][1][2][10] = 70, ++ [2][1][1][10] = 40, ++ [2][1][3][10] = 52, ++ [2][1][5][10] = 70, ++ [2][1][6][10] = 40, ++ [2][1][9][10] = 40, ++ [2][1][8][10] = 48, ++ [2][1][11][10] = 40, ++ [2][1][2][11] = 48, ++ [2][1][1][11] = 40, ++ [2][1][3][11] = 52, ++ [2][1][5][11] = 48, ++ [2][1][6][11] = 40, ++ [2][1][9][11] = 40, ++ [2][1][8][11] = 48, ++ [2][1][11][11] = 40, ++ [2][1][2][12] = 26, ++ [2][1][1][12] = 40, ++ [2][1][3][12] = 52, ++ [2][1][5][12] = 26, ++ [2][1][6][12] = 40, ++ [2][1][9][12] = 40, ++ [2][1][8][12] = 48, ++ [2][1][11][12] = 40, ++ [2][1][2][13] = 127, ++ [2][1][1][13] = 127, ++ [2][1][3][13] = 127, ++ [2][1][5][13] = 127, ++ [2][1][6][13] = 127, ++ [2][1][9][13] = 127, ++ [2][1][8][13] = 127, ++ [2][1][11][13] = 127, ++}; ++ ++const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = { ++ [0][0][0][0] = 22, ++ [0][0][0][2] = 22, ++ [0][0][0][4] = 22, ++ [0][0][0][6] = 22, ++ [0][0][0][8] = 24, ++ [0][0][0][10] = 24, ++ [0][0][0][12] = 24, ++ [0][0][0][14] = 24, ++ [0][0][0][15] = 24, ++ [0][0][0][17] = 24, ++ [0][0][0][19] = 24, ++ [0][0][0][21] = 24, ++ [0][0][0][23] = 24, ++ [0][0][0][25] = 24, ++ [0][0][0][27] = 24, ++ [0][0][0][29] = 24, ++ [0][0][0][31] = 24, ++ [0][0][0][33] = 24, ++ [0][0][0][35] = 24, ++ [0][0][0][37] = 24, ++ [0][0][0][38] = 28, ++ [0][0][0][40] = 28, ++ [0][0][0][42] = 28, ++ [0][0][0][44] = 28, ++ [0][0][0][46] = 28, ++ [0][1][0][0] = 8, ++ [0][1][0][2] = 8, ++ [0][1][0][4] = 8, ++ [0][1][0][6] = 8, ++ [0][1][0][8] = 12, ++ [0][1][0][10] = 12, ++ [0][1][0][12] = 12, ++ [0][1][0][14] = 12, ++ [0][1][0][15] = 12, ++ [0][1][0][17] = 12, ++ [0][1][0][19] = 12, ++ [0][1][0][21] = 12, ++ [0][1][0][23] = 12, ++ [0][1][0][25] = 12, ++ [0][1][0][27] = 12, ++ [0][1][0][29] = 12, ++ [0][1][0][31] = 12, ++ [0][1][0][33] = 12, ++ [0][1][0][35] = 12, ++ [0][1][0][37] = 12, ++ [0][1][0][38] = 16, ++ [0][1][0][40] = 16, ++ [0][1][0][42] = 16, ++ [0][1][0][44] = 16, ++ [0][1][0][46] = 16, ++ [1][0][0][0] = 30, ++ [1][0][0][2] = 30, ++ [1][0][0][4] = 30, ++ [1][0][0][6] = 30, ++ [1][0][0][8] = 36, ++ [1][0][0][10] = 36, ++ [1][0][0][12] = 36, ++ [1][0][0][14] = 36, ++ [1][0][0][15] = 36, ++ [1][0][0][17] = 36, ++ [1][0][0][19] = 36, ++ [1][0][0][21] = 36, ++ [1][0][0][23] = 36, ++ [1][0][0][25] = 36, ++ [1][0][0][27] = 36, ++ [1][0][0][29] = 36, ++ [1][0][0][31] = 36, ++ [1][0][0][33] = 36, ++ [1][0][0][35] = 36, ++ [1][0][0][37] = 36, ++ [1][0][0][38] = 28, ++ [1][0][0][40] = 28, ++ [1][0][0][42] = 28, ++ [1][0][0][44] = 28, ++ [1][0][0][46] = 28, ++ [1][1][0][0] = 18, ++ [1][1][0][2] = 18, ++ [1][1][0][4] = 18, ++ [1][1][0][6] = 18, ++ [1][1][0][8] = 22, ++ [1][1][0][10] = 22, ++ [1][1][0][12] = 22, ++ [1][1][0][14] = 22, ++ [1][1][0][15] = 22, ++ [1][1][0][17] = 22, ++ [1][1][0][19] = 22, ++ [1][1][0][21] = 22, ++ [1][1][0][23] = 22, ++ [1][1][0][25] = 22, ++ [1][1][0][27] = 22, ++ [1][1][0][29] = 22, ++ [1][1][0][31] = 22, ++ [1][1][0][33] = 22, ++ [1][1][0][35] = 22, ++ [1][1][0][37] = 22, ++ [1][1][0][38] = 16, ++ [1][1][0][40] = 16, ++ [1][1][0][42] = 16, ++ [1][1][0][44] = 16, ++ [1][1][0][46] = 16, ++ [2][0][0][0] = 30, ++ [2][0][0][2] = 30, ++ [2][0][0][4] = 30, ++ [2][0][0][6] = 30, ++ [2][0][0][8] = 46, ++ [2][0][0][10] = 46, ++ [2][0][0][12] = 46, ++ [2][0][0][14] = 46, ++ [2][0][0][15] = 46, ++ [2][0][0][17] = 46, ++ [2][0][0][19] = 46, ++ [2][0][0][21] = 46, ++ [2][0][0][23] = 46, ++ [2][0][0][25] = 46, ++ [2][0][0][27] = 46, ++ [2][0][0][29] = 46, ++ [2][0][0][31] = 46, ++ [2][0][0][33] = 46, ++ [2][0][0][35] = 46, ++ [2][0][0][37] = 46, ++ [2][0][0][38] = 28, ++ [2][0][0][40] = 28, ++ [2][0][0][42] = 28, ++ [2][0][0][44] = 28, ++ [2][0][0][46] = 28, ++ [2][1][0][0] = 18, ++ [2][1][0][2] = 18, ++ [2][1][0][4] = 18, ++ [2][1][0][6] = 18, ++ [2][1][0][8] = 32, ++ [2][1][0][10] = 32, ++ [2][1][0][12] = 32, ++ [2][1][0][14] = 32, ++ [2][1][0][15] = 32, ++ [2][1][0][17] = 32, ++ [2][1][0][19] = 32, ++ [2][1][0][21] = 32, ++ [2][1][0][23] = 32, ++ [2][1][0][25] = 32, ++ [2][1][0][27] = 32, ++ [2][1][0][29] = 32, ++ [2][1][0][31] = 32, ++ [2][1][0][33] = 32, ++ [2][1][0][35] = 32, ++ [2][1][0][37] = 32, ++ [2][1][0][38] = 16, ++ [2][1][0][40] = 16, ++ [2][1][0][42] = 16, ++ [2][1][0][44] = 16, ++ [2][1][0][46] = 16, ++ [0][0][2][0] = 48, ++ [0][0][1][0] = 24, ++ [0][0][3][0] = 26, ++ [0][0][5][0] = 22, ++ [0][0][6][0] = 24, ++ [0][0][9][0] = 24, ++ [0][0][8][0] = 30, ++ [0][0][11][0] = 24, ++ [0][0][2][2] = 48, ++ [0][0][1][2] = 24, ++ [0][0][3][2] = 26, ++ [0][0][5][2] = 22, ++ [0][0][6][2] = 24, ++ [0][0][9][2] = 24, ++ [0][0][8][2] = 30, ++ [0][0][11][2] = 24, ++ [0][0][2][4] = 48, ++ [0][0][1][4] = 24, ++ [0][0][3][4] = 26, ++ [0][0][5][4] = 22, ++ [0][0][6][4] = 24, ++ [0][0][9][4] = 24, ++ [0][0][8][4] = 30, ++ [0][0][11][4] = 24, ++ [0][0][2][6] = 48, ++ [0][0][1][6] = 24, ++ [0][0][3][6] = 26, ++ [0][0][5][6] = 22, ++ [0][0][6][6] = 24, ++ [0][0][9][6] = 24, ++ [0][0][8][6] = 30, ++ [0][0][11][6] = 24, ++ [0][0][2][8] = 48, ++ [0][0][1][8] = 24, ++ [0][0][3][8] = 26, ++ [0][0][5][8] = 48, ++ [0][0][6][8] = 24, ++ [0][0][9][8] = 24, ++ [0][0][8][8] = 54, ++ [0][0][11][8] = 24, ++ [0][0][2][10] = 48, ++ [0][0][1][10] = 24, ++ [0][0][3][10] = 26, ++ [0][0][5][10] = 48, ++ [0][0][6][10] = 24, ++ [0][0][9][10] = 24, ++ [0][0][8][10] = 54, ++ [0][0][11][10] = 24, ++ [0][0][2][12] = 48, ++ [0][0][1][12] = 24, ++ [0][0][3][12] = 26, ++ [0][0][5][12] = 48, ++ [0][0][6][12] = 24, ++ [0][0][9][12] = 24, ++ [0][0][8][12] = 54, ++ [0][0][11][12] = 24, ++ [0][0][2][14] = 48, ++ [0][0][1][14] = 24, ++ [0][0][3][14] = 26, ++ [0][0][5][14] = 48, ++ [0][0][6][14] = 24, ++ [0][0][9][14] = 24, ++ [0][0][8][14] = 54, ++ [0][0][11][14] = 24, ++ [0][0][2][15] = 48, ++ [0][0][1][15] = 24, ++ [0][0][3][15] = 44, ++ [0][0][5][15] = 48, ++ [0][0][6][15] = 24, ++ [0][0][9][15] = 24, ++ [0][0][8][15] = 54, ++ [0][0][11][15] = 24, ++ [0][0][2][17] = 48, ++ [0][0][1][17] = 24, ++ [0][0][3][17] = 44, ++ [0][0][5][17] = 48, ++ [0][0][6][17] = 24, ++ [0][0][9][17] = 24, ++ [0][0][8][17] = 54, ++ [0][0][11][17] = 24, ++ [0][0][2][19] = 48, ++ [0][0][1][19] = 24, ++ [0][0][3][19] = 44, ++ [0][0][5][19] = 48, ++ [0][0][6][19] = 24, ++ [0][0][9][19] = 24, ++ [0][0][8][19] = 54, ++ [0][0][11][19] = 24, ++ [0][0][2][21] = 48, ++ [0][0][1][21] = 24, ++ [0][0][3][21] = 44, ++ [0][0][5][21] = 48, ++ [0][0][6][21] = 24, ++ [0][0][9][21] = 24, ++ [0][0][8][21] = 54, ++ [0][0][11][21] = 24, ++ [0][0][2][23] = 48, ++ [0][0][1][23] = 24, ++ [0][0][3][23] = 44, ++ [0][0][5][23] = 48, ++ [0][0][6][23] = 24, ++ [0][0][9][23] = 24, ++ [0][0][8][23] = 54, ++ [0][0][11][23] = 24, ++ [0][0][2][25] = 48, ++ [0][0][1][25] = 24, ++ [0][0][3][25] = 44, ++ [0][0][5][25] = 127, ++ [0][0][6][25] = 24, ++ [0][0][9][25] = 127, ++ [0][0][8][25] = 54, ++ [0][0][11][25] = 24, ++ [0][0][2][27] = 48, ++ [0][0][1][27] = 24, ++ [0][0][3][27] = 44, ++ [0][0][5][27] = 127, ++ [0][0][6][27] = 24, ++ [0][0][9][27] = 127, ++ [0][0][8][27] = 54, ++ [0][0][11][27] = 24, ++ [0][0][2][29] = 48, ++ [0][0][1][29] = 24, ++ [0][0][3][29] = 44, ++ [0][0][5][29] = 127, ++ [0][0][6][29] = 24, ++ [0][0][9][29] = 127, ++ [0][0][8][29] = 54, ++ [0][0][11][29] = 24, ++ [0][0][2][31] = 48, ++ [0][0][1][31] = 24, ++ [0][0][3][31] = 44, ++ [0][0][5][31] = 48, ++ [0][0][6][31] = 24, ++ [0][0][9][31] = 24, ++ [0][0][8][31] = 54, ++ [0][0][11][31] = 24, ++ [0][0][2][33] = 48, ++ [0][0][1][33] = 24, ++ [0][0][3][33] = 44, ++ [0][0][5][33] = 48, ++ [0][0][6][33] = 24, ++ [0][0][9][33] = 24, ++ [0][0][8][33] = 54, ++ [0][0][11][33] = 24, ++ [0][0][2][35] = 48, ++ [0][0][1][35] = 24, ++ [0][0][3][35] = 44, ++ [0][0][5][35] = 48, ++ [0][0][6][35] = 24, ++ [0][0][9][35] = 24, ++ [0][0][8][35] = 54, ++ [0][0][11][35] = 24, ++ [0][0][2][37] = 48, ++ [0][0][1][37] = 127, ++ [0][0][3][37] = 44, ++ [0][0][5][37] = 48, ++ [0][0][6][37] = 24, ++ [0][0][9][37] = 48, ++ [0][0][8][37] = 54, ++ [0][0][11][37] = 127, ++ [0][0][2][38] = 76, ++ [0][0][1][38] = 28, ++ [0][0][3][38] = 127, ++ [0][0][5][38] = 76, ++ [0][0][6][38] = 28, ++ [0][0][9][38] = 76, ++ [0][0][8][38] = 54, ++ [0][0][11][38] = 28, ++ [0][0][2][40] = 76, ++ [0][0][1][40] = 28, ++ [0][0][3][40] = 127, ++ [0][0][5][40] = 76, ++ [0][0][6][40] = 28, ++ [0][0][9][40] = 76, ++ [0][0][8][40] = 54, ++ [0][0][11][40] = 28, ++ [0][0][2][42] = 76, ++ [0][0][1][42] = 28, ++ [0][0][3][42] = 127, ++ [0][0][5][42] = 76, ++ [0][0][6][42] = 28, ++ [0][0][9][42] = 76, ++ [0][0][8][42] = 54, ++ [0][0][11][42] = 28, ++ [0][0][2][44] = 76, ++ [0][0][1][44] = 28, ++ [0][0][3][44] = 127, ++ [0][0][5][44] = 76, ++ [0][0][6][44] = 28, ++ [0][0][9][44] = 76, ++ [0][0][8][44] = 54, ++ [0][0][11][44] = 28, ++ [0][0][2][46] = 76, ++ [0][0][1][46] = 28, ++ [0][0][3][46] = 127, ++ [0][0][5][46] = 76, ++ [0][0][6][46] = 28, ++ [0][0][9][46] = 76, ++ [0][0][8][46] = 54, ++ [0][0][11][46] = 28, ++ [0][1][2][0] = 36, ++ [0][1][1][0] = 12, ++ [0][1][3][0] = 14, ++ [0][1][5][0] = 8, ++ [0][1][6][0] = 12, ++ [0][1][9][0] = 12, ++ [0][1][8][0] = 18, ++ [0][1][11][0] = 12, ++ [0][1][2][2] = 36, ++ [0][1][1][2] = 12, ++ [0][1][3][2] = 14, ++ [0][1][5][2] = 8, ++ [0][1][6][2] = 12, ++ [0][1][9][2] = 12, ++ [0][1][8][2] = 18, ++ [0][1][11][2] = 12, ++ [0][1][2][4] = 36, ++ [0][1][1][4] = 12, ++ [0][1][3][4] = 14, ++ [0][1][5][4] = 8, ++ [0][1][6][4] = 12, ++ [0][1][9][4] = 12, ++ [0][1][8][4] = 18, ++ [0][1][11][4] = 12, ++ [0][1][2][6] = 36, ++ [0][1][1][6] = 12, ++ [0][1][3][6] = 14, ++ [0][1][5][6] = 8, ++ [0][1][6][6] = 12, ++ [0][1][9][6] = 12, ++ [0][1][8][6] = 18, ++ [0][1][11][6] = 12, ++ [0][1][2][8] = 36, ++ [0][1][1][8] = 12, ++ [0][1][3][8] = 14, ++ [0][1][5][8] = 36, ++ [0][1][6][8] = 12, ++ [0][1][9][8] = 12, ++ [0][1][8][8] = 42, ++ [0][1][11][8] = 12, ++ [0][1][2][10] = 36, ++ [0][1][1][10] = 12, ++ [0][1][3][10] = 14, ++ [0][1][5][10] = 36, ++ [0][1][6][10] = 12, ++ [0][1][9][10] = 12, ++ [0][1][8][10] = 42, ++ [0][1][11][10] = 12, ++ [0][1][2][12] = 36, ++ [0][1][1][12] = 12, ++ [0][1][3][12] = 14, ++ [0][1][5][12] = 36, ++ [0][1][6][12] = 12, ++ [0][1][9][12] = 12, ++ [0][1][8][12] = 42, ++ [0][1][11][12] = 12, ++ [0][1][2][14] = 36, ++ [0][1][1][14] = 12, ++ [0][1][3][14] = 14, ++ [0][1][5][14] = 36, ++ [0][1][6][14] = 12, ++ [0][1][9][14] = 12, ++ [0][1][8][14] = 42, ++ [0][1][11][14] = 12, ++ [0][1][2][15] = 36, ++ [0][1][1][15] = 12, ++ [0][1][3][15] = 32, ++ [0][1][5][15] = 36, ++ [0][1][6][15] = 12, ++ [0][1][9][15] = 12, ++ [0][1][8][15] = 42, ++ [0][1][11][15] = 12, ++ [0][1][2][17] = 36, ++ [0][1][1][17] = 12, ++ [0][1][3][17] = 32, ++ [0][1][5][17] = 36, ++ [0][1][6][17] = 12, ++ [0][1][9][17] = 12, ++ [0][1][8][17] = 42, ++ [0][1][11][17] = 12, ++ [0][1][2][19] = 36, ++ [0][1][1][19] = 12, ++ [0][1][3][19] = 32, ++ [0][1][5][19] = 36, ++ [0][1][6][19] = 12, ++ [0][1][9][19] = 12, ++ [0][1][8][19] = 42, ++ [0][1][11][19] = 12, ++ [0][1][2][21] = 36, ++ [0][1][1][21] = 12, ++ [0][1][3][21] = 32, ++ [0][1][5][21] = 36, ++ [0][1][6][21] = 12, ++ [0][1][9][21] = 12, ++ [0][1][8][21] = 42, ++ [0][1][11][21] = 12, ++ [0][1][2][23] = 36, ++ [0][1][1][23] = 12, ++ [0][1][3][23] = 32, ++ [0][1][5][23] = 36, ++ [0][1][6][23] = 12, ++ [0][1][9][23] = 12, ++ [0][1][8][23] = 42, ++ [0][1][11][23] = 12, ++ [0][1][2][25] = 36, ++ [0][1][1][25] = 12, ++ [0][1][3][25] = 32, ++ [0][1][5][25] = 127, ++ [0][1][6][25] = 12, ++ [0][1][9][25] = 127, ++ [0][1][8][25] = 42, ++ [0][1][11][25] = 12, ++ [0][1][2][27] = 36, ++ [0][1][1][27] = 12, ++ [0][1][3][27] = 32, ++ [0][1][5][27] = 127, ++ [0][1][6][27] = 12, ++ [0][1][9][27] = 127, ++ [0][1][8][27] = 42, ++ [0][1][11][27] = 12, ++ [0][1][2][29] = 36, ++ [0][1][1][29] = 12, ++ [0][1][3][29] = 32, ++ [0][1][5][29] = 127, ++ [0][1][6][29] = 12, ++ [0][1][9][29] = 127, ++ [0][1][8][29] = 42, ++ [0][1][11][29] = 12, ++ [0][1][2][31] = 36, ++ [0][1][1][31] = 12, ++ [0][1][3][31] = 32, ++ [0][1][5][31] = 36, ++ [0][1][6][31] = 12, ++ [0][1][9][31] = 12, ++ [0][1][8][31] = 42, ++ [0][1][11][31] = 12, ++ [0][1][2][33] = 36, ++ [0][1][1][33] = 12, ++ [0][1][3][33] = 32, ++ [0][1][5][33] = 36, ++ [0][1][6][33] = 12, ++ [0][1][9][33] = 12, ++ [0][1][8][33] = 42, ++ [0][1][11][33] = 12, ++ [0][1][2][35] = 36, ++ [0][1][1][35] = 12, ++ [0][1][3][35] = 32, ++ [0][1][5][35] = 36, ++ [0][1][6][35] = 12, ++ [0][1][9][35] = 12, ++ [0][1][8][35] = 42, ++ [0][1][11][35] = 12, ++ [0][1][2][37] = 36, ++ [0][1][1][37] = 127, ++ [0][1][3][37] = 32, ++ [0][1][5][37] = 36, ++ [0][1][6][37] = 12, ++ [0][1][9][37] = 36, ++ [0][1][8][37] = 42, ++ [0][1][11][37] = 127, ++ [0][1][2][38] = 72, ++ [0][1][1][38] = 16, ++ [0][1][3][38] = 127, ++ [0][1][5][38] = 72, ++ [0][1][6][38] = 16, ++ [0][1][9][38] = 76, ++ [0][1][8][38] = 42, ++ [0][1][11][38] = 16, ++ [0][1][2][40] = 76, ++ [0][1][1][40] = 16, ++ [0][1][3][40] = 127, ++ [0][1][5][40] = 76, ++ [0][1][6][40] = 16, ++ [0][1][9][40] = 76, ++ [0][1][8][40] = 42, ++ [0][1][11][40] = 16, ++ [0][1][2][42] = 76, ++ [0][1][1][42] = 16, ++ [0][1][3][42] = 127, ++ [0][1][5][42] = 76, ++ [0][1][6][42] = 16, ++ [0][1][9][42] = 76, ++ [0][1][8][42] = 42, ++ [0][1][11][42] = 16, ++ [0][1][2][44] = 76, ++ [0][1][1][44] = 16, ++ [0][1][3][44] = 127, ++ [0][1][5][44] = 76, ++ [0][1][6][44] = 16, ++ [0][1][9][44] = 76, ++ [0][1][8][44] = 42, ++ [0][1][11][44] = 16, ++ [0][1][2][46] = 76, ++ [0][1][1][46] = 16, ++ [0][1][3][46] = 127, ++ [0][1][5][46] = 76, ++ [0][1][6][46] = 16, ++ [0][1][9][46] = 76, ++ [0][1][8][46] = 42, ++ [0][1][11][46] = 16, ++ [1][0][2][0] = 62, ++ [1][0][1][0] = 36, ++ [1][0][3][0] = 36, ++ [1][0][5][0] = 34, ++ [1][0][6][0] = 36, ++ [1][0][9][0] = 36, ++ [1][0][8][0] = 30, ++ [1][0][11][0] = 36, ++ [1][0][2][2] = 62, ++ [1][0][1][2] = 36, ++ [1][0][3][2] = 36, ++ [1][0][5][2] = 34, ++ [1][0][6][2] = 36, ++ [1][0][9][2] = 36, ++ [1][0][8][2] = 30, ++ [1][0][11][2] = 36, ++ [1][0][2][4] = 62, ++ [1][0][1][4] = 36, ++ [1][0][3][4] = 36, ++ [1][0][5][4] = 34, ++ [1][0][6][4] = 36, ++ [1][0][9][4] = 36, ++ [1][0][8][4] = 30, ++ [1][0][11][4] = 36, ++ [1][0][2][6] = 62, ++ [1][0][1][6] = 36, ++ [1][0][3][6] = 36, ++ [1][0][5][6] = 34, ++ [1][0][6][6] = 36, ++ [1][0][9][6] = 36, ++ [1][0][8][6] = 30, ++ [1][0][11][6] = 36, ++ [1][0][2][8] = 62, ++ [1][0][1][8] = 36, ++ [1][0][3][8] = 36, ++ [1][0][5][8] = 62, ++ [1][0][6][8] = 36, ++ [1][0][9][8] = 36, ++ [1][0][8][8] = 54, ++ [1][0][11][8] = 36, ++ [1][0][2][10] = 62, ++ [1][0][1][10] = 36, ++ [1][0][3][10] = 36, ++ [1][0][5][10] = 62, ++ [1][0][6][10] = 36, ++ [1][0][9][10] = 36, ++ [1][0][8][10] = 54, ++ [1][0][11][10] = 36, ++ [1][0][2][12] = 62, ++ [1][0][1][12] = 36, ++ [1][0][3][12] = 36, ++ [1][0][5][12] = 62, ++ [1][0][6][12] = 36, ++ [1][0][9][12] = 36, ++ [1][0][8][12] = 54, ++ [1][0][11][12] = 36, ++ [1][0][2][14] = 62, ++ [1][0][1][14] = 36, ++ [1][0][3][14] = 36, ++ [1][0][5][14] = 62, ++ [1][0][6][14] = 36, ++ [1][0][9][14] = 36, ++ [1][0][8][14] = 54, ++ [1][0][11][14] = 36, ++ [1][0][2][15] = 62, ++ [1][0][1][15] = 36, ++ [1][0][3][15] = 58, ++ [1][0][5][15] = 62, ++ [1][0][6][15] = 36, ++ [1][0][9][15] = 36, ++ [1][0][8][15] = 54, ++ [1][0][11][15] = 36, ++ [1][0][2][17] = 62, ++ [1][0][1][17] = 36, ++ [1][0][3][17] = 58, ++ [1][0][5][17] = 62, ++ [1][0][6][17] = 36, ++ [1][0][9][17] = 36, ++ [1][0][8][17] = 54, ++ [1][0][11][17] = 36, ++ [1][0][2][19] = 62, ++ [1][0][1][19] = 36, ++ [1][0][3][19] = 58, ++ [1][0][5][19] = 62, ++ [1][0][6][19] = 36, ++ [1][0][9][19] = 36, ++ [1][0][8][19] = 54, ++ [1][0][11][19] = 36, ++ [1][0][2][21] = 62, ++ [1][0][1][21] = 36, ++ [1][0][3][21] = 58, ++ [1][0][5][21] = 62, ++ [1][0][6][21] = 36, ++ [1][0][9][21] = 36, ++ [1][0][8][21] = 54, ++ [1][0][11][21] = 36, ++ [1][0][2][23] = 62, ++ [1][0][1][23] = 36, ++ [1][0][3][23] = 58, ++ [1][0][5][23] = 62, ++ [1][0][6][23] = 36, ++ [1][0][9][23] = 36, ++ [1][0][8][23] = 54, ++ [1][0][11][23] = 36, ++ [1][0][2][25] = 62, ++ [1][0][1][25] = 36, ++ [1][0][3][25] = 58, ++ [1][0][5][25] = 127, ++ [1][0][6][25] = 36, ++ [1][0][9][25] = 127, ++ [1][0][8][25] = 54, ++ [1][0][11][25] = 36, ++ [1][0][2][27] = 62, ++ [1][0][1][27] = 36, ++ [1][0][3][27] = 58, ++ [1][0][5][27] = 127, ++ [1][0][6][27] = 36, ++ [1][0][9][27] = 127, ++ [1][0][8][27] = 54, ++ [1][0][11][27] = 36, ++ [1][0][2][29] = 62, ++ [1][0][1][29] = 36, ++ [1][0][3][29] = 58, ++ [1][0][5][29] = 127, ++ [1][0][6][29] = 36, ++ [1][0][9][29] = 127, ++ [1][0][8][29] = 54, ++ [1][0][11][29] = 36, ++ [1][0][2][31] = 62, ++ [1][0][1][31] = 36, ++ [1][0][3][31] = 58, ++ [1][0][5][31] = 62, ++ [1][0][6][31] = 36, ++ [1][0][9][31] = 36, ++ [1][0][8][31] = 54, ++ [1][0][11][31] = 36, ++ [1][0][2][33] = 62, ++ [1][0][1][33] = 36, ++ [1][0][3][33] = 58, ++ [1][0][5][33] = 62, ++ [1][0][6][33] = 36, ++ [1][0][9][33] = 36, ++ [1][0][8][33] = 54, ++ [1][0][11][33] = 36, ++ [1][0][2][35] = 62, ++ [1][0][1][35] = 36, ++ [1][0][3][35] = 58, ++ [1][0][5][35] = 62, ++ [1][0][6][35] = 36, ++ [1][0][9][35] = 36, ++ [1][0][8][35] = 54, ++ [1][0][11][35] = 36, ++ [1][0][2][37] = 56, ++ [1][0][1][37] = 62, ++ [1][0][3][37] = 127, ++ [1][0][5][37] = 58, ++ [1][0][6][37] = 62, ++ [1][0][9][37] = 36, ++ [1][0][8][37] = 62, ++ [1][0][11][37] = 54, ++ [1][0][2][38] = 76, ++ [1][0][1][38] = 28, ++ [1][0][3][38] = 127, ++ [1][0][5][38] = 76, ++ [1][0][6][38] = 28, ++ [1][0][9][38] = 76, ++ [1][0][8][38] = 54, ++ [1][0][11][38] = 28, ++ [1][0][2][40] = 76, ++ [1][0][1][40] = 28, ++ [1][0][3][40] = 127, ++ [1][0][5][40] = 76, ++ [1][0][6][40] = 28, ++ [1][0][9][40] = 76, ++ [1][0][8][40] = 54, ++ [1][0][11][40] = 28, ++ [1][0][2][42] = 76, ++ [1][0][1][42] = 28, ++ [1][0][3][42] = 127, ++ [1][0][5][42] = 76, ++ [1][0][6][42] = 28, ++ [1][0][9][42] = 76, ++ [1][0][8][42] = 54, ++ [1][0][11][42] = 28, ++ [1][0][2][44] = 76, ++ [1][0][1][44] = 28, ++ [1][0][3][44] = 127, ++ [1][0][5][44] = 76, ++ [1][0][6][44] = 28, ++ [1][0][9][44] = 76, ++ [1][0][8][44] = 54, ++ [1][0][11][44] = 28, ++ [1][0][2][46] = 76, ++ [1][0][1][46] = 28, ++ [1][0][3][46] = 127, ++ [1][0][5][46] = 76, ++ [1][0][6][46] = 28, ++ [1][0][9][46] = 76, ++ [1][0][8][46] = 54, ++ [1][0][11][46] = 28, ++ [1][1][2][0] = 46, ++ [1][1][1][0] = 22, ++ [1][1][3][0] = 24, ++ [1][1][5][0] = 18, ++ [1][1][6][0] = 22, ++ [1][1][9][0] = 22, ++ [1][1][8][0] = 18, ++ [1][1][11][0] = 22, ++ [1][1][2][2] = 46, ++ [1][1][1][2] = 22, ++ [1][1][3][2] = 24, ++ [1][1][5][2] = 18, ++ [1][1][6][2] = 22, ++ [1][1][9][2] = 22, ++ [1][1][8][2] = 18, ++ [1][1][11][2] = 22, ++ [1][1][2][4] = 46, ++ [1][1][1][4] = 22, ++ [1][1][3][4] = 24, ++ [1][1][5][4] = 18, ++ [1][1][6][4] = 22, ++ [1][1][9][4] = 22, ++ [1][1][8][4] = 18, ++ [1][1][11][4] = 22, ++ [1][1][2][6] = 46, ++ [1][1][1][6] = 22, ++ [1][1][3][6] = 24, ++ [1][1][5][6] = 18, ++ [1][1][6][6] = 22, ++ [1][1][9][6] = 22, ++ [1][1][8][6] = 18, ++ [1][1][11][6] = 22, ++ [1][1][2][8] = 46, ++ [1][1][1][8] = 22, ++ [1][1][3][8] = 24, ++ [1][1][5][8] = 46, ++ [1][1][6][8] = 22, ++ [1][1][9][8] = 22, ++ [1][1][8][8] = 42, ++ [1][1][11][8] = 22, ++ [1][1][2][10] = 46, ++ [1][1][1][10] = 22, ++ [1][1][3][10] = 24, ++ [1][1][5][10] = 46, ++ [1][1][6][10] = 22, ++ [1][1][9][10] = 22, ++ [1][1][8][10] = 42, ++ [1][1][11][10] = 22, ++ [1][1][2][12] = 46, ++ [1][1][1][12] = 22, ++ [1][1][3][12] = 24, ++ [1][1][5][12] = 46, ++ [1][1][6][12] = 22, ++ [1][1][9][12] = 22, ++ [1][1][8][12] = 42, ++ [1][1][11][12] = 22, ++ [1][1][2][14] = 46, ++ [1][1][1][14] = 22, ++ [1][1][3][14] = 24, ++ [1][1][5][14] = 46, ++ [1][1][6][14] = 22, ++ [1][1][9][14] = 22, ++ [1][1][8][14] = 42, ++ [1][1][11][14] = 22, ++ [1][1][2][15] = 46, ++ [1][1][1][15] = 22, ++ [1][1][3][15] = 46, ++ [1][1][5][15] = 46, ++ [1][1][6][15] = 22, ++ [1][1][9][15] = 22, ++ [1][1][8][15] = 42, ++ [1][1][11][15] = 22, ++ [1][1][2][17] = 46, ++ [1][1][1][17] = 22, ++ [1][1][3][17] = 46, ++ [1][1][5][17] = 46, ++ [1][1][6][17] = 22, ++ [1][1][9][17] = 22, ++ [1][1][8][17] = 42, ++ [1][1][11][17] = 22, ++ [1][1][2][19] = 46, ++ [1][1][1][19] = 22, ++ [1][1][3][19] = 46, ++ [1][1][5][19] = 46, ++ [1][1][6][19] = 22, ++ [1][1][9][19] = 22, ++ [1][1][8][19] = 42, ++ [1][1][11][19] = 22, ++ [1][1][2][21] = 46, ++ [1][1][1][21] = 22, ++ [1][1][3][21] = 46, ++ [1][1][5][21] = 46, ++ [1][1][6][21] = 22, ++ [1][1][9][21] = 22, ++ [1][1][8][21] = 42, ++ [1][1][11][21] = 22, ++ [1][1][2][23] = 46, ++ [1][1][1][23] = 22, ++ [1][1][3][23] = 46, ++ [1][1][5][23] = 46, ++ [1][1][6][23] = 22, ++ [1][1][9][23] = 22, ++ [1][1][8][23] = 42, ++ [1][1][11][23] = 22, ++ [1][1][2][25] = 46, ++ [1][1][1][25] = 22, ++ [1][1][3][25] = 46, ++ [1][1][5][25] = 127, ++ [1][1][6][25] = 22, ++ [1][1][9][25] = 127, ++ [1][1][8][25] = 42, ++ [1][1][11][25] = 22, ++ [1][1][2][27] = 46, ++ [1][1][1][27] = 22, ++ [1][1][3][27] = 46, ++ [1][1][5][27] = 127, ++ [1][1][6][27] = 22, ++ [1][1][9][27] = 127, ++ [1][1][8][27] = 42, ++ [1][1][11][27] = 22, ++ [1][1][2][29] = 46, ++ [1][1][1][29] = 22, ++ [1][1][3][29] = 46, ++ [1][1][5][29] = 127, ++ [1][1][6][29] = 22, ++ [1][1][9][29] = 127, ++ [1][1][8][29] = 42, ++ [1][1][11][29] = 22, ++ [1][1][2][31] = 46, ++ [1][1][1][31] = 22, ++ [1][1][3][31] = 46, ++ [1][1][5][31] = 46, ++ [1][1][6][31] = 22, ++ [1][1][9][31] = 22, ++ [1][1][8][31] = 42, ++ [1][1][11][31] = 22, ++ [1][1][2][33] = 46, ++ [1][1][1][33] = 22, ++ [1][1][3][33] = 46, ++ [1][1][5][33] = 46, ++ [1][1][6][33] = 22, ++ [1][1][9][33] = 22, ++ [1][1][8][33] = 42, ++ [1][1][11][33] = 22, ++ [1][1][2][35] = 46, ++ [1][1][1][35] = 22, ++ [1][1][3][35] = 46, ++ [1][1][5][35] = 46, ++ [1][1][6][35] = 22, ++ [1][1][9][35] = 22, ++ [1][1][8][35] = 42, ++ [1][1][11][35] = 22, ++ [1][1][2][37] = 46, ++ [1][1][1][37] = 127, ++ [1][1][3][37] = 46, ++ [1][1][5][37] = 46, ++ [1][1][6][37] = 22, ++ [1][1][9][37] = 50, ++ [1][1][8][37] = 42, ++ [1][1][11][37] = 127, ++ [1][1][2][38] = 74, ++ [1][1][1][38] = 16, ++ [1][1][3][38] = 127, ++ [1][1][5][38] = 74, ++ [1][1][6][38] = 16, ++ [1][1][9][38] = 76, ++ [1][1][8][38] = 42, ++ [1][1][11][38] = 16, ++ [1][1][2][40] = 76, ++ [1][1][1][40] = 16, ++ [1][1][3][40] = 127, ++ [1][1][5][40] = 76, ++ [1][1][6][40] = 16, ++ [1][1][9][40] = 76, ++ [1][1][8][40] = 42, ++ [1][1][11][40] = 16, ++ [1][1][2][42] = 76, ++ [1][1][1][42] = 16, ++ [1][1][3][42] = 127, ++ [1][1][5][42] = 76, ++ [1][1][6][42] = 16, ++ [1][1][9][42] = 76, ++ [1][1][8][42] = 42, ++ [1][1][11][42] = 16, ++ [1][1][2][44] = 76, ++ [1][1][1][44] = 16, ++ [1][1][3][44] = 127, ++ [1][1][5][44] = 76, ++ [1][1][6][44] = 16, ++ [1][1][9][44] = 76, ++ [1][1][8][44] = 42, ++ [1][1][11][44] = 16, ++ [1][1][2][46] = 76, ++ [1][1][1][46] = 16, ++ [1][1][3][46] = 127, ++ [1][1][5][46] = 76, ++ [1][1][6][46] = 16, ++ [1][1][9][46] = 76, ++ [1][1][8][46] = 42, ++ [1][1][11][46] = 16, ++ [2][0][2][0] = 74, ++ [2][0][1][0] = 46, ++ [2][0][3][0] = 50, ++ [2][0][5][0] = 46, ++ [2][0][6][0] = 46, ++ [2][0][9][0] = 46, ++ [2][0][8][0] = 30, ++ [2][0][11][0] = 46, ++ [2][0][2][2] = 74, ++ [2][0][1][2] = 46, ++ [2][0][3][2] = 50, ++ [2][0][5][2] = 46, ++ [2][0][6][2] = 46, ++ [2][0][9][2] = 46, ++ [2][0][8][2] = 30, ++ [2][0][11][2] = 46, ++ [2][0][2][4] = 74, ++ [2][0][1][4] = 46, ++ [2][0][3][4] = 50, ++ [2][0][5][4] = 46, ++ [2][0][6][4] = 46, ++ [2][0][9][4] = 46, ++ [2][0][8][4] = 30, ++ [2][0][11][4] = 46, ++ [2][0][2][6] = 74, ++ [2][0][1][6] = 46, ++ [2][0][3][6] = 50, ++ [2][0][5][6] = 46, ++ [2][0][6][6] = 46, ++ [2][0][9][6] = 46, ++ [2][0][8][6] = 30, ++ [2][0][11][6] = 46, ++ [2][0][2][8] = 74, ++ [2][0][1][8] = 46, ++ [2][0][3][8] = 50, ++ [2][0][5][8] = 66, ++ [2][0][6][8] = 46, ++ [2][0][9][8] = 46, ++ [2][0][8][8] = 54, ++ [2][0][11][8] = 46, ++ [2][0][2][10] = 74, ++ [2][0][1][10] = 46, ++ [2][0][3][10] = 50, ++ [2][0][5][10] = 66, ++ [2][0][6][10] = 46, ++ [2][0][9][10] = 46, ++ [2][0][8][10] = 54, ++ [2][0][11][10] = 46, ++ [2][0][2][12] = 74, ++ [2][0][1][12] = 46, ++ [2][0][3][12] = 50, ++ [2][0][5][12] = 66, ++ [2][0][6][12] = 46, ++ [2][0][9][12] = 46, ++ [2][0][8][12] = 54, ++ [2][0][11][12] = 46, ++ [2][0][2][14] = 74, ++ [2][0][1][14] = 46, ++ [2][0][3][14] = 50, ++ [2][0][5][14] = 66, ++ [2][0][6][14] = 46, ++ [2][0][9][14] = 46, ++ [2][0][8][14] = 54, ++ [2][0][11][14] = 46, ++ [2][0][2][15] = 74, ++ [2][0][1][15] = 46, ++ [2][0][3][15] = 70, ++ [2][0][5][15] = 74, ++ [2][0][6][15] = 46, ++ [2][0][9][15] = 46, ++ [2][0][8][15] = 54, ++ [2][0][11][15] = 46, ++ [2][0][2][17] = 74, ++ [2][0][1][17] = 46, ++ [2][0][3][17] = 70, ++ [2][0][5][17] = 74, ++ [2][0][6][17] = 46, ++ [2][0][9][17] = 46, ++ [2][0][8][17] = 54, ++ [2][0][11][17] = 46, ++ [2][0][2][19] = 74, ++ [2][0][1][19] = 46, ++ [2][0][3][19] = 70, ++ [2][0][5][19] = 74, ++ [2][0][6][19] = 46, ++ [2][0][9][19] = 46, ++ [2][0][8][19] = 54, ++ [2][0][11][19] = 46, ++ [2][0][2][21] = 74, ++ [2][0][1][21] = 46, ++ [2][0][3][21] = 70, ++ [2][0][5][21] = 74, ++ [2][0][6][21] = 46, ++ [2][0][9][21] = 46, ++ [2][0][8][21] = 54, ++ [2][0][11][21] = 46, ++ [2][0][2][23] = 74, ++ [2][0][1][23] = 46, ++ [2][0][3][23] = 70, ++ [2][0][5][23] = 74, ++ [2][0][6][23] = 46, ++ [2][0][9][23] = 46, ++ [2][0][8][23] = 54, ++ [2][0][11][23] = 46, ++ [2][0][2][25] = 74, ++ [2][0][1][25] = 46, ++ [2][0][3][25] = 70, ++ [2][0][5][25] = 127, ++ [2][0][6][25] = 46, ++ [2][0][9][25] = 127, ++ [2][0][8][25] = 54, ++ [2][0][11][25] = 46, ++ [2][0][2][27] = 74, ++ [2][0][1][27] = 46, ++ [2][0][3][27] = 70, ++ [2][0][5][27] = 127, ++ [2][0][6][27] = 46, ++ [2][0][9][27] = 127, ++ [2][0][8][27] = 54, ++ [2][0][11][27] = 46, ++ [2][0][2][29] = 74, ++ [2][0][1][29] = 46, ++ [2][0][3][29] = 70, ++ [2][0][5][29] = 127, ++ [2][0][6][29] = 46, ++ [2][0][9][29] = 127, ++ [2][0][8][29] = 54, ++ [2][0][11][29] = 46, ++ [2][0][2][31] = 74, ++ [2][0][1][31] = 46, ++ [2][0][3][31] = 70, ++ [2][0][5][31] = 74, ++ [2][0][6][31] = 46, ++ [2][0][9][31] = 46, ++ [2][0][8][31] = 54, ++ [2][0][11][31] = 46, ++ [2][0][2][33] = 74, ++ [2][0][1][33] = 46, ++ [2][0][3][33] = 70, ++ [2][0][5][33] = 74, ++ [2][0][6][33] = 46, ++ [2][0][9][33] = 46, ++ [2][0][8][33] = 54, ++ [2][0][11][33] = 46, ++ [2][0][2][35] = 74, ++ [2][0][1][35] = 46, ++ [2][0][3][35] = 70, ++ [2][0][5][35] = 74, ++ [2][0][6][35] = 46, ++ [2][0][9][35] = 46, ++ [2][0][8][35] = 54, ++ [2][0][11][35] = 46, ++ [2][0][2][37] = 74, ++ [2][0][1][37] = 127, ++ [2][0][3][37] = 70, ++ [2][0][5][37] = 74, ++ [2][0][6][37] = 46, ++ [2][0][9][37] = 74, ++ [2][0][8][37] = 54, ++ [2][0][11][37] = 127, ++ [2][0][2][38] = 76, ++ [2][0][1][38] = 28, ++ [2][0][3][38] = 127, ++ [2][0][5][38] = 76, ++ [2][0][6][38] = 28, ++ [2][0][9][38] = 76, ++ [2][0][8][38] = 54, ++ [2][0][11][38] = 28, ++ [2][0][2][40] = 76, ++ [2][0][1][40] = 28, ++ [2][0][3][40] = 127, ++ [2][0][5][40] = 76, ++ [2][0][6][40] = 28, ++ [2][0][9][40] = 76, ++ [2][0][8][40] = 54, ++ [2][0][11][40] = 28, ++ [2][0][2][42] = 76, ++ [2][0][1][42] = 28, ++ [2][0][3][42] = 127, ++ [2][0][5][42] = 76, ++ [2][0][6][42] = 28, ++ [2][0][9][42] = 76, ++ [2][0][8][42] = 54, ++ [2][0][11][42] = 28, ++ [2][0][2][44] = 76, ++ [2][0][1][44] = 28, ++ [2][0][3][44] = 127, ++ [2][0][5][44] = 76, ++ [2][0][6][44] = 28, ++ [2][0][9][44] = 76, ++ [2][0][8][44] = 54, ++ [2][0][11][44] = 28, ++ [2][0][2][46] = 76, ++ [2][0][1][46] = 28, ++ [2][0][3][46] = 127, ++ [2][0][5][46] = 76, ++ [2][0][6][46] = 28, ++ [2][0][9][46] = 76, ++ [2][0][8][46] = 54, ++ [2][0][11][46] = 28, ++ [2][1][2][0] = 58, ++ [2][1][1][0] = 32, ++ [2][1][3][0] = 38, ++ [2][1][5][0] = 30, ++ [2][1][6][0] = 32, ++ [2][1][9][0] = 32, ++ [2][1][8][0] = 18, ++ [2][1][11][0] = 32, ++ [2][1][2][2] = 58, ++ [2][1][1][2] = 32, ++ [2][1][3][2] = 38, ++ [2][1][5][2] = 30, ++ [2][1][6][2] = 32, ++ [2][1][9][2] = 32, ++ [2][1][8][2] = 18, ++ [2][1][11][2] = 32, ++ [2][1][2][4] = 58, ++ [2][1][1][4] = 32, ++ [2][1][3][4] = 38, ++ [2][1][5][4] = 30, ++ [2][1][6][4] = 32, ++ [2][1][9][4] = 32, ++ [2][1][8][4] = 18, ++ [2][1][11][4] = 32, ++ [2][1][2][6] = 58, ++ [2][1][1][6] = 32, ++ [2][1][3][6] = 38, ++ [2][1][5][6] = 30, ++ [2][1][6][6] = 32, ++ [2][1][9][6] = 32, ++ [2][1][8][6] = 18, ++ [2][1][11][6] = 32, ++ [2][1][2][8] = 58, ++ [2][1][1][8] = 32, ++ [2][1][3][8] = 38, ++ [2][1][5][8] = 52, ++ [2][1][6][8] = 32, ++ [2][1][9][8] = 32, ++ [2][1][8][8] = 42, ++ [2][1][11][8] = 32, ++ [2][1][2][10] = 58, ++ [2][1][1][10] = 32, ++ [2][1][3][10] = 38, ++ [2][1][5][10] = 52, ++ [2][1][6][10] = 32, ++ [2][1][9][10] = 32, ++ [2][1][8][10] = 42, ++ [2][1][11][10] = 32, ++ [2][1][2][12] = 58, ++ [2][1][1][12] = 32, ++ [2][1][3][12] = 38, ++ [2][1][5][12] = 52, ++ [2][1][6][12] = 32, ++ [2][1][9][12] = 32, ++ [2][1][8][12] = 42, ++ [2][1][11][12] = 32, ++ [2][1][2][14] = 58, ++ [2][1][1][14] = 32, ++ [2][1][3][14] = 38, ++ [2][1][5][14] = 52, ++ [2][1][6][14] = 32, ++ [2][1][9][14] = 32, ++ [2][1][8][14] = 42, ++ [2][1][11][14] = 32, ++ [2][1][2][15] = 58, ++ [2][1][1][15] = 32, ++ [2][1][3][15] = 58, ++ [2][1][5][15] = 58, ++ [2][1][6][15] = 32, ++ [2][1][9][15] = 32, ++ [2][1][8][15] = 42, ++ [2][1][11][15] = 32, ++ [2][1][2][17] = 58, ++ [2][1][1][17] = 32, ++ [2][1][3][17] = 58, ++ [2][1][5][17] = 58, ++ [2][1][6][17] = 32, ++ [2][1][9][17] = 32, ++ [2][1][8][17] = 42, ++ [2][1][11][17] = 32, ++ [2][1][2][19] = 58, ++ [2][1][1][19] = 32, ++ [2][1][3][19] = 58, ++ [2][1][5][19] = 58, ++ [2][1][6][19] = 32, ++ [2][1][9][19] = 32, ++ [2][1][8][19] = 42, ++ [2][1][11][19] = 32, ++ [2][1][2][21] = 58, ++ [2][1][1][21] = 32, ++ [2][1][3][21] = 58, ++ [2][1][5][21] = 58, ++ [2][1][6][21] = 32, ++ [2][1][9][21] = 32, ++ [2][1][8][21] = 42, ++ [2][1][11][21] = 32, ++ [2][1][2][23] = 58, ++ [2][1][1][23] = 32, ++ [2][1][3][23] = 58, ++ [2][1][5][23] = 58, ++ [2][1][6][23] = 32, ++ [2][1][9][23] = 32, ++ [2][1][8][23] = 42, ++ [2][1][11][23] = 32, ++ [2][1][2][25] = 58, ++ [2][1][1][25] = 32, ++ [2][1][3][25] = 58, ++ [2][1][5][25] = 127, ++ [2][1][6][25] = 32, ++ [2][1][9][25] = 127, ++ [2][1][8][25] = 42, ++ [2][1][11][25] = 32, ++ [2][1][2][27] = 58, ++ [2][1][1][27] = 32, ++ [2][1][3][27] = 58, ++ [2][1][5][27] = 127, ++ [2][1][6][27] = 32, ++ [2][1][9][27] = 127, ++ [2][1][8][27] = 42, ++ [2][1][11][27] = 32, ++ [2][1][2][29] = 58, ++ [2][1][1][29] = 32, ++ [2][1][3][29] = 58, ++ [2][1][5][29] = 127, ++ [2][1][6][29] = 32, ++ [2][1][9][29] = 127, ++ [2][1][8][29] = 42, ++ [2][1][11][29] = 32, ++ [2][1][2][31] = 58, ++ [2][1][1][31] = 32, ++ [2][1][3][31] = 58, ++ [2][1][5][31] = 58, ++ [2][1][6][31] = 32, ++ [2][1][9][31] = 32, ++ [2][1][8][31] = 42, ++ [2][1][11][31] = 32, ++ [2][1][2][33] = 58, ++ [2][1][1][33] = 32, ++ [2][1][3][33] = 58, ++ [2][1][5][33] = 58, ++ [2][1][6][33] = 32, ++ [2][1][9][33] = 32, ++ [2][1][8][33] = 42, ++ [2][1][11][33] = 32, ++ [2][1][2][35] = 58, ++ [2][1][1][35] = 32, ++ [2][1][3][35] = 58, ++ [2][1][5][35] = 58, ++ [2][1][6][35] = 32, ++ [2][1][9][35] = 32, ++ [2][1][8][35] = 42, ++ [2][1][11][35] = 32, ++ [2][1][2][37] = 58, ++ [2][1][1][37] = 127, ++ [2][1][3][37] = 58, ++ [2][1][5][37] = 58, ++ [2][1][6][37] = 32, ++ [2][1][9][37] = 62, ++ [2][1][8][37] = 42, ++ [2][1][11][37] = 127, ++ [2][1][2][38] = 76, ++ [2][1][1][38] = 16, ++ [2][1][3][38] = 127, ++ [2][1][5][38] = 76, ++ [2][1][6][38] = 16, ++ [2][1][9][38] = 76, ++ [2][1][8][38] = 42, ++ [2][1][11][38] = 16, ++ [2][1][2][40] = 76, ++ [2][1][1][40] = 16, ++ [2][1][3][40] = 127, ++ [2][1][5][40] = 76, ++ [2][1][6][40] = 16, ++ [2][1][9][40] = 76, ++ [2][1][8][40] = 42, ++ [2][1][11][40] = 16, ++ [2][1][2][42] = 76, ++ [2][1][1][42] = 16, ++ [2][1][3][42] = 127, ++ [2][1][5][42] = 76, ++ [2][1][6][42] = 16, ++ [2][1][9][42] = 76, ++ [2][1][8][42] = 42, ++ [2][1][11][42] = 16, ++ [2][1][2][44] = 76, ++ [2][1][1][44] = 16, ++ [2][1][3][44] = 127, ++ [2][1][5][44] = 76, ++ [2][1][6][44] = 16, ++ [2][1][9][44] = 76, ++ [2][1][8][44] = 42, ++ [2][1][11][44] = 16, ++ [2][1][2][46] = 76, ++ [2][1][1][46] = 16, ++ [2][1][3][46] = 127, ++ [2][1][5][46] = 76, ++ [2][1][6][46] = 16, ++ [2][1][9][46] = 76, ++ [2][1][8][46] = 42, ++ [2][1][11][46] = 16, ++}; ++ ++#define DECLARE_DIG_TABLE(name) \ ++static const struct rtw89_phy_dig_gain_cfg name##_table = { \ ++ .table = name, \ ++ .size = ARRAY_SIZE(name) \ ++} ++ ++static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = { ++ {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_G_MSK}, ++ {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G1_G_MSK}, ++ {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_G_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_G_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_G_MSK}, ++ {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_G_MSK}, ++ {R_PATH0_LNA_ERR5, B_PATH0_LNA_ERR_G6_G_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g); ++ ++static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = { ++ {R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_G_MSK}, ++ {R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_G_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g); ++ ++static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = { ++ {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G0_A_MSK}, ++ {R_PATH0_LNA_ERR1, B_PATH0_LNA_ERR_G1_A_MSK}, ++ {R_PATH0_LNA_ERR2, B_PATH0_LNA_ERR_G2_A_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G3_A_MSK}, ++ {R_PATH0_LNA_ERR3, B_PATH0_LNA_ERR_G4_A_MSK}, ++ {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G5_A_MSK}, ++ {R_PATH0_LNA_ERR4, B_PATH0_LNA_ERR_G6_A_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a); ++ ++static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = { ++ {R_PATH0_TIA_ERR_G0, B_PATH0_TIA_ERR_G0_A_MSK}, ++ {R_PATH0_TIA_ERR_G1, B_PATH0_TIA_ERR_G1_A_MSK}, ++}; ++ ++DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a); ++ ++const struct rtw89_phy_table rtw89_8852a_phy_bb_table = { ++ .regs = rtw89_8852a_phy_bb_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_bb_regs), ++ .rf_path = 0, /* don't care */ ++}; ++ ++const struct rtw89_phy_table rtw89_8852a_phy_radioa_table = { ++ .regs = rtw89_8852a_phy_radioa_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_radioa_regs), ++ .rf_path = RF_PATH_A, ++}; ++ ++const struct rtw89_phy_table rtw89_8852a_phy_radiob_table = { ++ .regs = rtw89_8852a_phy_radiob_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_radiob_regs), ++ .rf_path = RF_PATH_B, ++}; ++ ++const struct rtw89_phy_table rtw89_8852a_phy_nctl_table = { ++ .regs = rtw89_8852a_phy_nctl_regs, ++ .n_regs = ARRAY_SIZE(rtw89_8852a_phy_nctl_regs), ++ .rf_path = 0, /* don't care */ ++}; ++ ++const struct rtw89_txpwr_table rtw89_8852a_byr_table = { ++ .data = rtw89_8852a_txpwr_byrate, ++ .size = ARRAY_SIZE(rtw89_8852a_txpwr_byrate), ++ .load = rtw89_phy_load_txpwr_byrate, ++}; ++ ++const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg = { ++ .delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n, ++ .delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p, ++ .delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n, ++ .delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p, ++ .delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n, ++ .delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p, ++ .delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n, ++ .delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p, ++ .delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n, ++ .delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p, ++ .delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n, ++ .delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p, ++}; ++ ++const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = { ++ .cfg_lna_g = &rtw89_8852a_lna_gain_g_table, ++ .cfg_tia_g = &rtw89_8852a_tia_gain_g_table, ++ .cfg_lna_a = &rtw89_8852a_lna_gain_a_table, ++ .cfg_tia_a = &rtw89_8852a_tia_gain_a_table ++}; +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.h b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.h +new file mode 100644 +index 000000000000..913796506286 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.h +@@ -0,0 +1,28 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_8852A_TABLE_H__ ++#define __RTW89_8852A_TABLE_H__ ++ ++#include "core.h" ++ ++extern const struct rtw89_phy_table rtw89_8852a_phy_bb_table; ++extern const struct rtw89_phy_table rtw89_8852a_phy_radioa_table; ++extern const struct rtw89_phy_table rtw89_8852a_phy_radiob_table; ++extern const struct rtw89_phy_table rtw89_8852a_phy_nctl_table; ++extern const struct rtw89_txpwr_table rtw89_8852a_byr_table; ++extern const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table; ++extern const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg; ++extern const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++extern const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] ++ [RTW89_RS_LMT_NUM][RTW89_BF_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++extern const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; ++extern const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] ++ [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/sar.c b/drivers/net/wireless/realtek/rtw89/sar.c +new file mode 100644 +index 000000000000..097c87899cea +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/sar.c +@@ -0,0 +1,190 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "debug.h" ++#include "sar.h" ++ ++static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, s32 *cfg) ++{ ++ struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common; ++ enum rtw89_subband subband = rtwdev->hal.current_subband; ++ ++ if (!rtwsar->set[subband]) ++ return -ENODATA; ++ ++ *cfg = rtwsar->cfg[subband]; ++ return 0; ++} ++ ++static const ++struct rtw89_sar_handler rtw89_sar_handlers[RTW89_SAR_SOURCE_NR] = { ++ [RTW89_SAR_SOURCE_COMMON] = { ++ .descr_sar_source = "RTW89_SAR_SOURCE_COMMON", ++ .txpwr_factor_sar = 2, ++ .query_sar_config = rtw89_query_sar_config_common, ++ }, ++}; ++ ++#define rtw89_sar_set_src(_dev, _src, _cfg_name, _cfg_data) \ ++ do { \ ++ typeof(_src) _s = (_src); \ ++ typeof(_dev) _d = (_dev); \ ++ BUILD_BUG_ON(!rtw89_sar_handlers[_s].descr_sar_source); \ ++ BUILD_BUG_ON(!rtw89_sar_handlers[_s].query_sar_config); \ ++ lockdep_assert_held(&_d->mutex); \ ++ _d->sar._cfg_name = *(_cfg_data); \ ++ _d->sar.src = _s; \ ++ } while (0) ++ ++static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg) ++{ ++ const u8 fct_mac = rtwdev->chip->txpwr_factor_mac; ++ s32 cfg_mac; ++ ++ cfg_mac = fct > fct_mac ? ++ cfg >> (fct - fct_mac) : cfg << (fct_mac - fct); ++ ++ return (s8)clamp_t(s32, cfg_mac, ++ RTW89_SAR_TXPWR_MAC_MIN, ++ RTW89_SAR_TXPWR_MAC_MAX); ++} ++ ++s8 rtw89_query_sar(struct rtw89_dev *rtwdev) ++{ ++ const enum rtw89_sar_sources src = rtwdev->sar.src; ++ /* its members are protected by rtw89_sar_set_src() */ ++ const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; ++ int ret; ++ s32 cfg; ++ u8 fct; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (src == RTW89_SAR_SOURCE_NONE) ++ return RTW89_SAR_TXPWR_MAC_MAX; ++ ++ ret = sar_hdl->query_sar_config(rtwdev, &cfg); ++ if (ret) ++ return RTW89_SAR_TXPWR_MAC_MAX; ++ ++ fct = sar_hdl->txpwr_factor_sar; ++ ++ return rtw89_txpwr_sar_to_mac(rtwdev, fct, cfg); ++} ++ ++void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev) ++{ ++ const enum rtw89_sar_sources src = rtwdev->sar.src; ++ /* its members are protected by rtw89_sar_set_src() */ ++ const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src]; ++ const u8 fct_mac = rtwdev->chip->txpwr_factor_mac; ++ int ret; ++ s32 cfg; ++ u8 fct; ++ ++ lockdep_assert_held(&rtwdev->mutex); ++ ++ if (src == RTW89_SAR_SOURCE_NONE) { ++ seq_puts(m, "no SAR is applied\n"); ++ return; ++ } ++ ++ seq_printf(m, "source: %d (%s)\n", src, sar_hdl->descr_sar_source); ++ ++ ret = sar_hdl->query_sar_config(rtwdev, &cfg); ++ if (ret) { ++ seq_printf(m, "config: return code: %d\n", ret); ++ seq_printf(m, "assign: max setting: %d (unit: 1/%lu dBm)\n", ++ RTW89_SAR_TXPWR_MAC_MAX, BIT(fct_mac)); ++ return; ++ } ++ ++ fct = sar_hdl->txpwr_factor_sar; ++ ++ seq_printf(m, "config: %d (unit: 1/%lu dBm)\n", cfg, BIT(fct)); ++} ++ ++static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev, ++ const struct rtw89_sar_cfg_common *sar) ++{ ++ enum rtw89_sar_sources src; ++ int ret = 0; ++ ++ mutex_lock(&rtwdev->mutex); ++ ++ src = rtwdev->sar.src; ++ if (src != RTW89_SAR_SOURCE_NONE && src != RTW89_SAR_SOURCE_COMMON) { ++ rtw89_warn(rtwdev, "SAR source: %d is in use", src); ++ ret = -EBUSY; ++ goto exit; ++ } ++ ++ rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_COMMON, cfg_common, sar); ++ rtw89_chip_set_txpwr(rtwdev); ++ ++exit: ++ mutex_unlock(&rtwdev->mutex); ++ return ret; ++} ++ ++static const u8 rtw89_common_sar_subband_map[] = { ++ RTW89_CH_2G, ++ RTW89_CH_5G_BAND_1, ++ RTW89_CH_5G_BAND_3, ++ RTW89_CH_5G_BAND_4, ++}; ++ ++static const struct cfg80211_sar_freq_ranges rtw89_common_sar_freq_ranges[] = { ++ { .start_freq = 2412, .end_freq = 2484, }, ++ { .start_freq = 5180, .end_freq = 5320, }, ++ { .start_freq = 5500, .end_freq = 5720, }, ++ { .start_freq = 5745, .end_freq = 5825, }, ++}; ++ ++static_assert(ARRAY_SIZE(rtw89_common_sar_subband_map) == ++ ARRAY_SIZE(rtw89_common_sar_freq_ranges)); ++ ++const struct cfg80211_sar_capa rtw89_sar_capa = { ++ .type = NL80211_SAR_TYPE_POWER, ++ .num_freq_ranges = ARRAY_SIZE(rtw89_common_sar_freq_ranges), ++ .freq_ranges = rtw89_common_sar_freq_ranges, ++}; ++ ++int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, ++ const struct cfg80211_sar_specs *sar) ++{ ++ struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_sar_cfg_common sar_common = {0}; ++ u8 fct; ++ u32 freq_start; ++ u32 freq_end; ++ u32 band; ++ s32 power; ++ u32 i, idx; ++ ++ if (sar->type != NL80211_SAR_TYPE_POWER) ++ return -EINVAL; ++ ++ fct = rtw89_sar_handlers[RTW89_SAR_SOURCE_COMMON].txpwr_factor_sar; ++ ++ for (i = 0; i < sar->num_sub_specs; i++) { ++ idx = sar->sub_specs[i].freq_range_index; ++ if (idx >= ARRAY_SIZE(rtw89_common_sar_freq_ranges)) ++ return -EINVAL; ++ ++ freq_start = rtw89_common_sar_freq_ranges[idx].start_freq; ++ freq_end = rtw89_common_sar_freq_ranges[idx].end_freq; ++ band = rtw89_common_sar_subband_map[idx]; ++ power = sar->sub_specs[i].power; ++ ++ rtw89_info(rtwdev, "On freq %u to %u, ", freq_start, freq_end); ++ rtw89_info(rtwdev, "set SAR power limit %d (unit: 1/%lu dBm)\n", ++ power, BIT(fct)); ++ ++ sar_common.set[band] = true; ++ sar_common.cfg[band] = power; ++ } ++ ++ return rtw89_apply_sar_common(rtwdev, &sar_common); ++} +diff --git a/drivers/net/wireless/realtek/rtw89/sar.h b/drivers/net/wireless/realtek/rtw89/sar.h +new file mode 100644 +index 000000000000..7b5484c84eb1 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/sar.h +@@ -0,0 +1,26 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_SAR_H__ ++#define __RTW89_SAR_H__ ++ ++#include "core.h" ++ ++#define RTW89_SAR_TXPWR_MAC_MAX S8_MAX ++#define RTW89_SAR_TXPWR_MAC_MIN S8_MIN ++ ++struct rtw89_sar_handler { ++ const char *descr_sar_source; ++ u8 txpwr_factor_sar; ++ int (*query_sar_config)(struct rtw89_dev *rtwdev, s32 *cfg); ++}; ++ ++extern const struct cfg80211_sar_capa rtw89_sar_capa; ++ ++s8 rtw89_query_sar(struct rtw89_dev *rtwdev); ++void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev); ++int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw, ++ const struct cfg80211_sar_specs *sar); ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/ser.c b/drivers/net/wireless/realtek/rtw89/ser.c +new file mode 100644 +index 000000000000..837cdc366a61 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ser.c +@@ -0,0 +1,491 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* Copyright(c) 2019-2020 Realtek Corporation ++ */ ++ ++#include "cam.h" ++#include "debug.h" ++#include "mac.h" ++#include "ps.h" ++#include "ser.h" ++#include "util.h" ++ ++#define SER_RECFG_TIMEOUT 1000 ++ ++enum ser_evt { ++ SER_EV_NONE, ++ SER_EV_STATE_IN, ++ SER_EV_STATE_OUT, ++ SER_EV_L1_RESET, /* M1 */ ++ SER_EV_DO_RECOVERY, /* M3 */ ++ SER_EV_MAC_RESET_DONE, /* M5 */ ++ SER_EV_L2_RESET, ++ SER_EV_L2_RECFG_DONE, ++ SER_EV_L2_RECFG_TIMEOUT, ++ SER_EV_M3_TIMEOUT, ++ SER_EV_FW_M5_TIMEOUT, ++ SER_EV_L0_RESET, ++ SER_EV_MAXX ++}; ++ ++enum ser_state { ++ SER_IDLE_ST, ++ SER_RESET_TRX_ST, ++ SER_DO_HCI_ST, ++ SER_L2_RESET_ST, ++ SER_ST_MAX_ST ++}; ++ ++struct ser_msg { ++ struct list_head list; ++ u8 event; ++}; ++ ++struct state_ent { ++ u8 state; ++ char *name; ++ void (*st_func)(struct rtw89_ser *ser, u8 event); ++}; ++ ++struct event_ent { ++ u8 event; ++ char *name; ++}; ++ ++static char *ser_ev_name(struct rtw89_ser *ser, u8 event) ++{ ++ if (event < SER_EV_MAXX) ++ return ser->ev_tbl[event].name; ++ ++ return "err_ev_name"; ++} ++ ++static char *ser_st_name(struct rtw89_ser *ser) ++{ ++ if (ser->state < SER_ST_MAX_ST) ++ return ser->st_tbl[ser->state].name; ++ ++ return "err_st_name"; ++} ++ ++static void ser_state_run(struct rtw89_ser *ser, u8 evt) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s receive %s\n", ++ ser_st_name(ser), ser_ev_name(ser, evt)); ++ ++ rtw89_leave_lps(rtwdev); ++ ser->st_tbl[ser->state].st_func(ser, evt); ++} ++ ++static void ser_state_goto(struct rtw89_ser *ser, u8 new_state) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (ser->state == new_state || new_state >= SER_ST_MAX_ST) ++ return; ++ ser_state_run(ser, SER_EV_STATE_OUT); ++ ++ rtw89_debug(rtwdev, RTW89_DBG_SER, "ser: %s goto -> %s\n", ++ ser_st_name(ser), ser->st_tbl[new_state].name); ++ ++ ser->state = new_state; ++ ser_state_run(ser, SER_EV_STATE_IN); ++} ++ ++static struct ser_msg *__rtw89_ser_dequeue_msg(struct rtw89_ser *ser) ++{ ++ struct ser_msg *msg; ++ ++ spin_lock_irq(&ser->msg_q_lock); ++ msg = list_first_entry_or_null(&ser->msg_q, struct ser_msg, list); ++ if (msg) ++ list_del(&msg->list); ++ spin_unlock_irq(&ser->msg_q_lock); ++ ++ return msg; ++} ++ ++static void rtw89_ser_hdl_work(struct work_struct *work) ++{ ++ struct ser_msg *msg; ++ struct rtw89_ser *ser = container_of(work, struct rtw89_ser, ++ ser_hdl_work); ++ ++ while ((msg = __rtw89_ser_dequeue_msg(ser))) { ++ ser_state_run(ser, msg->event); ++ kfree(msg); ++ } ++} ++ ++static int ser_send_msg(struct rtw89_ser *ser, u8 event) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ struct ser_msg *msg = NULL; ++ ++ if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) ++ return -EIO; ++ ++ msg = kmalloc(sizeof(*msg), GFP_ATOMIC); ++ if (!msg) ++ return -ENOMEM; ++ ++ msg->event = event; ++ ++ spin_lock_irq(&ser->msg_q_lock); ++ list_add(&msg->list, &ser->msg_q); ++ spin_unlock_irq(&ser->msg_q_lock); ++ ++ ieee80211_queue_work(rtwdev->hw, &ser->ser_hdl_work); ++ return 0; ++} ++ ++static void rtw89_ser_alarm_work(struct work_struct *work) ++{ ++ struct rtw89_ser *ser = container_of(work, struct rtw89_ser, ++ ser_alarm_work.work); ++ ++ ser_send_msg(ser, ser->alarm_event); ++ ser->alarm_event = SER_EV_NONE; ++} ++ ++static void ser_set_alarm(struct rtw89_ser *ser, u32 ms, u8 event) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (test_bit(RTW89_SER_DRV_STOP_RUN, ser->flags)) ++ return; ++ ++ ser->alarm_event = event; ++ ieee80211_queue_delayed_work(rtwdev->hw, &ser->ser_alarm_work, ++ msecs_to_jiffies(ms)); ++} ++ ++static void ser_del_alarm(struct rtw89_ser *ser) ++{ ++ cancel_delayed_work(&ser->ser_alarm_work); ++ ser->alarm_event = SER_EV_NONE; ++} ++ ++/* driver function */ ++static void drv_stop_tx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ ieee80211_stop_queues(rtwdev->hw); ++ set_bit(RTW89_SER_DRV_STOP_TX, ser->flags); ++} ++ ++static void drv_stop_rx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ set_bit(RTW89_SER_DRV_STOP_RX, ser->flags); ++} ++ ++static void drv_trx_reset(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_hci_reset(rtwdev); ++} ++ ++static void drv_resume_tx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (!test_bit(RTW89_SER_DRV_STOP_TX, ser->flags)) ++ return; ++ ++ ieee80211_wake_queues(rtwdev->hw); ++ clear_bit(RTW89_SER_DRV_STOP_TX, ser->flags); ++} ++ ++static void drv_resume_rx(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ if (!test_bit(RTW89_SER_DRV_STOP_RX, ser->flags)) ++ return; ++ ++ set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); ++ clear_bit(RTW89_SER_DRV_STOP_RX, ser->flags); ++} ++ ++static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++{ ++ rtw89_core_release_bit_map(rtwdev->hw_port, rtwvif->port); ++ rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; ++ rtwvif->trigger = false; ++} ++ ++static void ser_reset_mac_binding(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_vif *rtwvif; ++ ++ rtw89_cam_reset_keys(rtwdev); ++ rtw89_core_release_all_bits_map(rtwdev->mac_id_map, RTW89_MAX_MAC_ID_NUM); ++ rtw89_for_each_rtwvif(rtwdev, rtwvif) ++ ser_reset_vif(rtwdev, rtwvif); ++} ++ ++/* hal function */ ++static int hal_enable_dma(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ int ret; ++ ++ if (!test_bit(RTW89_SER_HAL_STOP_DMA, ser->flags)) ++ return 0; ++ ++ if (!rtwdev->hci.ops->mac_lv1_rcvy) ++ return -EIO; ++ ++ ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_2); ++ if (!ret) ++ clear_bit(RTW89_SER_HAL_STOP_DMA, ser->flags); ++ ++ return ret; ++} ++ ++static int hal_stop_dma(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ int ret; ++ ++ if (!rtwdev->hci.ops->mac_lv1_rcvy) ++ return -EIO; ++ ++ ret = rtwdev->hci.ops->mac_lv1_rcvy(rtwdev, RTW89_LV1_RCVY_STEP_1); ++ if (!ret) ++ set_bit(RTW89_SER_HAL_STOP_DMA, ser->flags); ++ ++ return ret; ++} ++ ++static void hal_send_m2_event(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_DISABLE_EN); ++} ++ ++static void hal_send_m4_event(struct rtw89_ser *ser) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ rtw89_mac_set_err_status(rtwdev, MAC_AX_ERR_L1_RCVY_EN); ++} ++ ++/* state handler */ ++static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ break; ++ case SER_EV_L1_RESET: ++ ser_state_goto(ser, SER_RESET_TRX_ST); ++ break; ++ case SER_EV_L2_RESET: ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ case SER_EV_STATE_OUT: ++ default: ++ break; ++ } ++} ++ ++static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ drv_stop_tx(ser); ++ ++ if (hal_stop_dma(ser)) { ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ } ++ ++ drv_stop_rx(ser); ++ drv_trx_reset(ser); ++ ++ /* wait m3 */ ++ hal_send_m2_event(ser); ++ ++ /* set alarm to prevent FW response timeout */ ++ ser_set_alarm(ser, 1000, SER_EV_M3_TIMEOUT); ++ break; ++ ++ case SER_EV_DO_RECOVERY: ++ ser_state_goto(ser, SER_DO_HCI_ST); ++ break; ++ ++ case SER_EV_M3_TIMEOUT: ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ ++ case SER_EV_STATE_OUT: ++ ser_del_alarm(ser); ++ hal_enable_dma(ser); ++ drv_resume_rx(ser); ++ drv_resume_tx(ser); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ /* wait m5 */ ++ hal_send_m4_event(ser); ++ ++ /* prevent FW response timeout */ ++ ser_set_alarm(ser, 1000, SER_EV_FW_M5_TIMEOUT); ++ break; ++ ++ case SER_EV_FW_M5_TIMEOUT: ++ ser_state_goto(ser, SER_L2_RESET_ST); ++ break; ++ ++ case SER_EV_MAC_RESET_DONE: ++ ser_state_goto(ser, SER_IDLE_ST); ++ break; ++ ++ case SER_EV_STATE_OUT: ++ ser_del_alarm(ser); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt) ++{ ++ struct rtw89_dev *rtwdev = container_of(ser, struct rtw89_dev, ser); ++ ++ switch (evt) { ++ case SER_EV_STATE_IN: ++ mutex_lock(&rtwdev->mutex); ++ ser_reset_mac_binding(rtwdev); ++ rtw89_core_stop(rtwdev); ++ mutex_unlock(&rtwdev->mutex); ++ ++ ieee80211_restart_hw(rtwdev->hw); ++ ser_set_alarm(ser, SER_RECFG_TIMEOUT, SER_EV_L2_RECFG_TIMEOUT); ++ break; ++ ++ case SER_EV_L2_RECFG_TIMEOUT: ++ rtw89_info(rtwdev, "Err: ser L2 re-config timeout\n"); ++ fallthrough; ++ case SER_EV_L2_RECFG_DONE: ++ ser_state_goto(ser, SER_IDLE_ST); ++ break; ++ ++ case SER_EV_STATE_OUT: ++ ser_del_alarm(ser); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++static struct event_ent ser_ev_tbl[] = { ++ {SER_EV_NONE, "SER_EV_NONE"}, ++ {SER_EV_STATE_IN, "SER_EV_STATE_IN"}, ++ {SER_EV_STATE_OUT, "SER_EV_STATE_OUT"}, ++ {SER_EV_L1_RESET, "SER_EV_L1_RESET"}, ++ {SER_EV_DO_RECOVERY, "SER_EV_DO_RECOVERY m3"}, ++ {SER_EV_MAC_RESET_DONE, "SER_EV_MAC_RESET_DONE m5"}, ++ {SER_EV_L2_RESET, "SER_EV_L2_RESET"}, ++ {SER_EV_L2_RECFG_DONE, "SER_EV_L2_RECFG_DONE"}, ++ {SER_EV_L2_RECFG_TIMEOUT, "SER_EV_L2_RECFG_TIMEOUT"}, ++ {SER_EV_M3_TIMEOUT, "SER_EV_M3_TIMEOUT"}, ++ {SER_EV_FW_M5_TIMEOUT, "SER_EV_FW_M5_TIMEOUT"}, ++ {SER_EV_L0_RESET, "SER_EV_L0_RESET"}, ++ {SER_EV_MAXX, "SER_EV_MAX"} ++}; ++ ++static struct state_ent ser_st_tbl[] = { ++ {SER_IDLE_ST, "SER_IDLE_ST", ser_idle_st_hdl}, ++ {SER_RESET_TRX_ST, "SER_RESET_TRX_ST", ser_reset_trx_st_hdl}, ++ {SER_DO_HCI_ST, "SER_DO_HCI_ST", ser_do_hci_st_hdl}, ++ {SER_L2_RESET_ST, "SER_L2_RESET_ST", ser_l2_reset_st_hdl} ++}; ++ ++int rtw89_ser_init(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_ser *ser = &rtwdev->ser; ++ ++ memset(ser, 0, sizeof(*ser)); ++ INIT_LIST_HEAD(&ser->msg_q); ++ ser->state = SER_IDLE_ST; ++ ser->st_tbl = ser_st_tbl; ++ ser->ev_tbl = ser_ev_tbl; ++ ++ bitmap_zero(ser->flags, RTW89_NUM_OF_SER_FLAGS); ++ spin_lock_init(&ser->msg_q_lock); ++ INIT_WORK(&ser->ser_hdl_work, rtw89_ser_hdl_work); ++ INIT_DELAYED_WORK(&ser->ser_alarm_work, rtw89_ser_alarm_work); ++ return 0; ++} ++ ++int rtw89_ser_deinit(struct rtw89_dev *rtwdev) ++{ ++ struct rtw89_ser *ser = (struct rtw89_ser *)&rtwdev->ser; ++ ++ set_bit(RTW89_SER_DRV_STOP_RUN, ser->flags); ++ cancel_delayed_work_sync(&ser->ser_alarm_work); ++ cancel_work_sync(&ser->ser_hdl_work); ++ clear_bit(RTW89_SER_DRV_STOP_RUN, ser->flags); ++ return 0; ++} ++ ++void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev) ++{ ++ ser_send_msg(&rtwdev->ser, SER_EV_L2_RECFG_DONE); ++} ++ ++int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err) ++{ ++ u8 event = SER_EV_NONE; ++ ++ rtw89_info(rtwdev, "ser event = 0x%04x\n", err); ++ ++ switch (err) { ++ case MAC_AX_ERR_L1_ERR_DMAC: ++ case MAC_AX_ERR_L0_PROMOTE_TO_L1: ++ event = SER_EV_L1_RESET; /* M1 */ ++ break; ++ case MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE: ++ event = SER_EV_DO_RECOVERY; /* M3 */ ++ break; ++ case MAC_AX_ERR_L1_RESET_RECOVERY_DONE: ++ event = SER_EV_MAC_RESET_DONE; /* M5 */ ++ break; ++ case MAC_AX_ERR_L0_ERR_CMAC0: ++ case MAC_AX_ERR_L0_ERR_CMAC1: ++ case MAC_AX_ERR_L0_RESET_DONE: ++ event = SER_EV_L0_RESET; ++ break; ++ default: ++ if (err == MAC_AX_ERR_L1_PROMOTE_TO_L2 || ++ (err >= MAC_AX_ERR_L2_ERR_AH_DMA && ++ err <= MAC_AX_GET_ERR_MAX)) ++ event = SER_EV_L2_RESET; ++ break; ++ } ++ ++ if (event == SER_EV_NONE) ++ return -EINVAL; ++ ++ ser_send_msg(&rtwdev->ser, event); ++ return 0; ++} ++EXPORT_SYMBOL(rtw89_ser_notify); +diff --git a/drivers/net/wireless/realtek/rtw89/ser.h b/drivers/net/wireless/realtek/rtw89/ser.h +new file mode 100644 +index 000000000000..6b8e62019942 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/ser.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++ * Copyright(c) 2019-2020 Realtek Corporation ++ */ ++#ifndef __SER_H__ ++#define __SER_H__ ++ ++#include "core.h" ++ ++int rtw89_ser_init(struct rtw89_dev *rtwdev); ++int rtw89_ser_deinit(struct rtw89_dev *rtwdev); ++int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err); ++void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev); ++ ++#endif /* __SER_H__*/ ++ +diff --git a/drivers/net/wireless/realtek/rtw89/txrx.h b/drivers/net/wireless/realtek/rtw89/txrx.h +new file mode 100644 +index 000000000000..f1e0fe36107d +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/txrx.h +@@ -0,0 +1,358 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* Copyright(c) 2020 Realtek Corporation ++ */ ++ ++#ifndef __RTW89_TXRX_H__ ++#define __RTW89_TXRX_H__ ++ ++#include "debug.h" ++ ++#define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) ++#define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) ++#define DATA_RATE_MODE_NON_HT 0x0 ++#define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) ++#define DATA_RATE_MODE_HT 0x1 ++#define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) ++#define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) ++#define DATA_RATE_MODE_VHT 0x2 ++#define DATA_RATE_MODE_HE 0x3 ++#define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) ++#define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) ++#define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) ++#define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) ++#define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) ++ ++/* TX WD BODY DWORD 0 */ ++#define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) ++#define RTW89_TXWD_BODY0_MORE_DATA BIT(23) ++#define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) ++#define RTW89_TXWD_BODY0_FW_DL BIT(20) ++#define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) ++#define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) ++#define RTW89_TXWD_BODY0_WD_PAGE BIT(7) ++#define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) ++ ++/* TX WD BODY DWORD 1 */ ++#define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) ++ ++/* TX WD BODY DWORD 2 */ ++#define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) ++#define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) ++#define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) ++#define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) ++ ++/* TX WD BODY DWORD 3 */ ++#define RTW89_TXWD_BODY3_BK BIT(13) ++#define RTW89_TXWD_BODY3_AGG_EN BIT(12) ++#define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) ++ ++/* TX WD BODY DWORD 4 */ ++ ++/* TX WD BODY DWORD 5 */ ++ ++/* TX WD INFO DWORD 0 */ ++#define RTW89_TXWD_INFO0_USE_RATE BIT(30) ++#define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) ++#define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) ++#define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) ++#define RTW89_TXWD_INFO0_DISDATAFB BIT(10) ++ ++/* TX WD INFO DWORD 1 */ ++#define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) ++#define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) ++#define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) ++ ++/* TX WD INFO DWORD 2 */ ++#define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) ++#define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) ++#define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) ++#define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) ++ ++/* TX WD INFO DWORD 3 */ ++ ++/* TX WD INFO DWORD 4 */ ++#define RTW89_TXWD_INFO4_RTS_EN BIT(27) ++#define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) ++ ++/* TX WD INFO DWORD 5 */ ++ ++/* RX DESC helpers */ ++/* Short Descriptor */ ++#define RTW89_GET_RXWD_LONG_RXD(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, BIT(31)) ++#define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(30, 28)) ++#define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(27, 24)) ++#define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, BIT(23)) ++#define RTW89_GET_RXWD_BB_SEL(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, BIT(22)) ++#define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(21, 16)) ++#define RTW89_GET_RXWD_SHIFT(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(15, 14)) ++#define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword0, GENMASK(13, 0)) ++#define RTW89_GET_RXWD_BW(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(31, 30)) ++#define RTW89_GET_RXWD_GI_LTF(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(27, 25)) ++#define RTW89_GET_RXWD_DATA_RATE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(24, 16)) ++#define RTW89_GET_RXWD_USER_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(15, 8)) ++#define RTW89_GET_RXWD_SR_EN(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, BIT(7)) ++#define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(6, 4)) ++#define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword1, GENMASK(3, 0)) ++#define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \ ++ le32_get_bits((rxdesc)->dword2, GENMASK(31, 0)) ++#define RTW89_GET_RXWD_ICV_ERR(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(10)) ++#define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(9)) ++#define RTW89_GET_RXWD_HW_DEC(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(2)) ++#define RTW89_GET_RXWD_SW_DEC(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(1)) ++#define RTW89_GET_RXWD_A1_MATCH(rxdesc) \ ++ le32_get_bits((rxdesc)->dword3, BIT(0)) ++ ++/* Long Descriptor */ ++#define RTW89_GET_RXWD_FRAG(rxdesc) \ ++ le32_get_bits((rxdesc)->dword4, GENMASK(31, 28)) ++#define RTW89_GET_RXWD_SEQ(rxdesc) \ ++ le32_get_bits((rxdesc)->dword4, GENMASK(27, 16)) ++#define RTW89_GET_RXWD_TYPE(rxdesc) \ ++ le32_get_bits((rxdesc)->dword4, GENMASK(1, 0)) ++#define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, BIT(28)) ++#define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(27, 24)) ++#define RTW89_GET_RXWD_MAC_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(23, 16)) ++#define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(15, 8)) ++#define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \ ++ le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) ++ ++#define RTW89_GET_RXINFO_USR_NUM(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(3, 0)) ++#define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(15, 8)) ++#define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(27, 16)) ++#define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), BIT(28)) ++#define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), BIT(29)) ++#define RTW89_GET_RXINFO_LONG_RXD(rpt) \ ++ le32_get_bits(*((__le32 *)rpt), GENMASK(31, 30)) ++#define RTW89_GET_RXINFO_SERVICE(rpt) \ ++ le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(15, 0)) ++#define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ ++ le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(23, 16)) ++#define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(0)) ++#define RTW89_GET_RXINFO_DATA(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(1)) ++#define RTW89_GET_RXINFO_CTRL(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(2)) ++#define RTW89_GET_RXINFO_MGMT(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(3)) ++#define RTW89_GET_RXINFO_BCM(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(4)) ++#define RTW89_GET_RXINFO_MACID(rpt, usr) \ ++ le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) ++ ++#define RTW89_GET_PHY_STS_RSSI_A(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(7, 0)) ++#define RTW89_GET_PHY_STS_RSSI_B(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(15, 8)) ++#define RTW89_GET_PHY_STS_RSSI_C(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(23, 16)) ++#define RTW89_GET_PHY_STS_RSSI_D(sts) \ ++ le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(31, 24)) ++#define RTW89_GET_PHY_STS_LEN(sts) \ ++ le32_get_bits(*((__le32 *)sts), GENMASK(15, 8)) ++#define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ ++ le32_get_bits(*((__le32 *)sts), GENMASK(31, 24)) ++#define RTW89_GET_PHY_STS_IE_TYPE(ie) \ ++ le32_get_bits(*((__le32 *)ie), GENMASK(4, 0)) ++#define RTW89_GET_PHY_STS_IE_LEN(ie) \ ++ le32_get_bits(*((__le32 *)ie), GENMASK(11, 5)) ++#define RTW89_GET_PHY_STS_IE0_CFO(ie) \ ++ le32_get_bits(*((__le32 *)(ie) + 1), GENMASK(31, 20)) ++ ++enum rtw89_tx_channel { ++ RTW89_TXCH_ACH0 = 0, ++ RTW89_TXCH_ACH1 = 1, ++ RTW89_TXCH_ACH2 = 2, ++ RTW89_TXCH_ACH3 = 3, ++ RTW89_TXCH_ACH4 = 4, ++ RTW89_TXCH_ACH5 = 5, ++ RTW89_TXCH_ACH6 = 6, ++ RTW89_TXCH_ACH7 = 7, ++ RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ ++ RTW89_TXCH_CH9 = 9, /* HI Band 0 */ ++ RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ ++ RTW89_TXCH_CH11 = 11, /* HI Band 1 */ ++ RTW89_TXCH_CH12 = 12, /* FW CMD */ ++ ++ /* keep last */ ++ RTW89_TXCH_NUM, ++ RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 ++}; ++ ++enum rtw89_rx_channel { ++ RTW89_RXCH_RXQ = 0, ++ RTW89_RXCH_RPQ = 1, ++ ++ /* keep last */ ++ RTW89_RXCH_NUM, ++ RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 ++}; ++ ++enum rtw89_tx_qsel { ++ RTW89_TX_QSEL_BE_0 = 0x00, ++ RTW89_TX_QSEL_BK_0 = 0x01, ++ RTW89_TX_QSEL_VI_0 = 0x02, ++ RTW89_TX_QSEL_VO_0 = 0x03, ++ RTW89_TX_QSEL_BE_1 = 0x04, ++ RTW89_TX_QSEL_BK_1 = 0x05, ++ RTW89_TX_QSEL_VI_1 = 0x06, ++ RTW89_TX_QSEL_VO_1 = 0x07, ++ RTW89_TX_QSEL_BE_2 = 0x08, ++ RTW89_TX_QSEL_BK_2 = 0x09, ++ RTW89_TX_QSEL_VI_2 = 0x0a, ++ RTW89_TX_QSEL_VO_2 = 0x0b, ++ RTW89_TX_QSEL_BE_3 = 0x0c, ++ RTW89_TX_QSEL_BK_3 = 0x0d, ++ RTW89_TX_QSEL_VI_3 = 0x0e, ++ RTW89_TX_QSEL_VO_3 = 0x0f, ++ RTW89_TX_QSEL_B0_BCN = 0x10, ++ RTW89_TX_QSEL_B0_HI = 0x11, ++ RTW89_TX_QSEL_B0_MGMT = 0x12, ++ RTW89_TX_QSEL_B0_NOPS = 0x13, ++ RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, ++ /* reserved */ ++ /* reserved */ ++ /* reserved */ ++ RTW89_TX_QSEL_B1_BCN = 0x18, ++ RTW89_TX_QSEL_B1_HI = 0x19, ++ RTW89_TX_QSEL_B1_MGMT = 0x1a, ++ RTW89_TX_QSEL_B1_NOPS = 0x1b, ++ RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, ++ /* reserved */ ++ /* reserved */ ++ /* reserved */ ++}; ++ ++enum rtw89_phy_status_ie_type { ++ RTW89_PHYSTS_IE00_CMN_CCK = 0, ++ RTW89_PHYSTS_IE01_CMN_OFDM = 1, ++ RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, ++ RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, ++ RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, ++ RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, ++ RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, ++ RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, ++ RTW89_PHYSTS_IE08_FTR_CH = 8, ++ RTW89_PHYSTS_IE09_FTR_PLCP_0 = 9, ++ RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, ++ RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, ++ RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, ++ RTW89_PHYSTS_IE13_DL_MU_DEF = 13, ++ RTW89_PHYSTS_IE14_TB_UL_CQI = 14, ++ RTW89_PHYSTS_IE15_TB_UL_DEF = 15, ++ RTW89_PHYSTS_IE16_RSVD16 = 16, ++ RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, ++ RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, ++ RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, ++ RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, ++ RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, ++ RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, ++ RTW89_PHYSTS_IE23_RSVD23 = 23, ++ RTW89_PHYSTS_IE24_DBG_OFDM_TD_PATH_A = 24, ++ RTW89_PHYSTS_IE25_DBG_OFDM_TD_PATH_B = 25, ++ RTW89_PHYSTS_IE26_DBG_OFDM_TD_PATH_C = 26, ++ RTW89_PHYSTS_IE27_DBG_OFDM_TD_PATH_D = 27, ++ RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, ++ RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, ++ RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, ++ RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, ++ ++ /* keep last */ ++ RTW89_PHYSTS_IE_NUM, ++ RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 ++}; ++ ++static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) ++{ ++ switch (tid) { ++ default: ++ rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); ++ fallthrough; ++ case 0: ++ case 3: ++ return RTW89_TX_QSEL_BE_0; ++ case 1: ++ case 2: ++ return RTW89_TX_QSEL_BK_0; ++ case 4: ++ case 5: ++ return RTW89_TX_QSEL_VI_0; ++ case 6: ++ case 7: ++ return RTW89_TX_QSEL_VO_0; ++ } ++} ++ ++static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) ++{ ++ switch (qsel) { ++ default: ++ rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); ++ fallthrough; ++ case RTW89_TX_QSEL_BE_0: ++ return RTW89_TXCH_ACH0; ++ case RTW89_TX_QSEL_BK_0: ++ return RTW89_TXCH_ACH1; ++ case RTW89_TX_QSEL_VI_0: ++ return RTW89_TXCH_ACH2; ++ case RTW89_TX_QSEL_VO_0: ++ return RTW89_TXCH_ACH3; ++ case RTW89_TX_QSEL_B0_MGMT: ++ return RTW89_TXCH_CH8; ++ case RTW89_TX_QSEL_B0_HI: ++ return RTW89_TXCH_CH9; ++ case RTW89_TX_QSEL_B1_MGMT: ++ return RTW89_TXCH_CH10; ++ case RTW89_TX_QSEL_B1_HI: ++ return RTW89_TXCH_CH11; ++ } ++} ++ ++static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) ++{ ++ switch (tid) { ++ case 3: ++ case 2: ++ case 5: ++ case 7: ++ return 1; ++ default: ++ rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); ++ fallthrough; ++ case 0: ++ case 1: ++ case 4: ++ case 6: ++ return 0; ++ } ++} ++ ++#endif +diff --git a/drivers/net/wireless/realtek/rtw89/util.h b/drivers/net/wireless/realtek/rtw89/util.h +new file mode 100644 +index 000000000000..229e81009de6 +--- /dev/null ++++ b/drivers/net/wireless/realtek/rtw89/util.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++ * Copyright(c) 2019-2020 Realtek Corporation ++ */ ++#ifndef __RTW89_UTIL_H__ ++#define __RTW89_UTIL_H__ ++ ++#include "core.h" ++ ++#define rtw89_iterate_vifs_bh(rtwdev, iterator, data) \ ++ ieee80211_iterate_active_interfaces_atomic((rtwdev)->hw, \ ++ IEEE80211_IFACE_ITER_NORMAL, iterator, data) ++ ++/* call this function with rtwdev->mutex is held */ ++#define rtw89_for_each_rtwvif(rtwdev, rtwvif) \ ++ list_for_each_entry(rtwvif, &(rtwdev)->rtwvifs_list, list) ++ ++#endif +-- +2.13.6 + diff --git a/SOURCES/0002-rtw89-Fix-two-spelling-mistakes-in-debug-messages.patch b/SOURCES/0002-rtw89-Fix-two-spelling-mistakes-in-debug-messages.patch new file mode 100644 index 0000000..a28945f --- /dev/null +++ b/SOURCES/0002-rtw89-Fix-two-spelling-mistakes-in-debug-messages.patch @@ -0,0 +1,53 @@ +From 315cb6c6785dfb5f2275d87cadca5a09ad8ec36c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:01 +0100 +Subject: [PATCH 02/36] rtw89: Fix two spelling mistakes in debug messages +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit c51ed74093d45af2a25af7f26dd8d0532f7aec3e +Author: Colin Ian King +Date: Fri Oct 15 11:50:04 2021 +0100 + + rtw89: Fix two spelling mistakes in debug messages + + There are two spelling mistakes in rtw89_debug messages. Fix them. + + Signed-off-by: Colin Ian King + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211015105004.11817-1-colin.king@canonical.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/phy.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +index 53c36cc82c57..ab134856baac 100644 +--- a/drivers/net/wireless/realtek/rtw89/phy.c ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -1715,7 +1715,7 @@ static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) + target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); + } else { + rtw89_debug(rtwdev, RTW89_DBG_CFO, +- "No intersection of cfo torlence windows\n"); ++ "No intersection of cfo tolerance windows\n"); + target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); + } + for (i = 0; i < CFO_TRACK_MAX_USER; i++) +@@ -2749,7 +2749,7 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, + dig->igi_rssi, final_rssi, under_region, val); + } else { + rtw89_debug(rtwdev, RTW89_DBG_DIG, +- "Dynamic PD th dsiabled, Set PD_low_bd=0\n"); ++ "Dynamic PD th disabled, Set PD_low_bd=0\n"); + } + + rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, +-- +2.13.6 + diff --git a/SOURCES/0003-rtw89-Remove-redundant-check-of-ret-after-call-to-rt.patch b/SOURCES/0003-rtw89-Remove-redundant-check-of-ret-after-call-to-rt.patch new file mode 100644 index 0000000..2896da0 --- /dev/null +++ b/SOURCES/0003-rtw89-Remove-redundant-check-of-ret-after-call-to-rt.patch @@ -0,0 +1,49 @@ +From 16c75423c29792209bfc638eaf4bd1f3faf89a44 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:01 +0100 +Subject: [PATCH 03/36] rtw89: Remove redundant check of ret after call to + rtw89_mac_enable_bb_rf +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit f7e7e440550b0b176df3d2ea3e76106bc89915d9 +Author: Colin Ian King +Date: Fri Oct 15 16:21:13 2021 +0100 + + rtw89: Remove redundant check of ret after call to rtw89_mac_enable_bb_rf + + The function rtw89_mac_enable_bb_rf is a void return type, so there is + no return error code to ret, so the following check for an error in ret + is redundant dead code and can be removed. + + Addresses-Coverity: ("Logically dead code") + Fixes: e3ec7017f6a2 ("rtw89: add Realtek 802.11ax driver") + Signed-off-by: Colin Ian King + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211015152113.33179-1-colin.king@canonical.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/mac.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index 0171a5a7b1de..69384c43c046 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -2656,8 +2656,6 @@ int rtw89_mac_init(struct rtw89_dev *rtwdev) + goto fail; + + rtw89_mac_enable_bb_rf(rtwdev); +- if (ret) +- goto fail; + + ret = rtw89_mac_sys_init(rtwdev); + if (ret) +-- +2.13.6 + diff --git a/SOURCES/0004-rtw89-fix-return-value-check-in-rtw89_cam_send_sec_k.patch b/SOURCES/0004-rtw89-fix-return-value-check-in-rtw89_cam_send_sec_k.patch new file mode 100644 index 0000000..19d2c8b --- /dev/null +++ b/SOURCES/0004-rtw89-fix-return-value-check-in-rtw89_cam_send_sec_k.patch @@ -0,0 +1,48 @@ +From 5ca39688aa14fca3a9190140b3a4ee3b1c826341 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:01 +0100 +Subject: [PATCH 04/36] rtw89: fix return value check in + rtw89_cam_send_sec_key_cmd() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit a04310edcd00d6014126483a2d8cd95b4786db25 +Author: Yang Yingliang +Date: Mon Oct 18 11:31:02 2021 +0800 + + rtw89: fix return value check in rtw89_cam_send_sec_key_cmd() + + Fix the return value check which testing the wrong variable + in rtw89_cam_send_sec_key_cmd(). + + Reported-by: Hulk Robot + Fixes: e3ec7017f6a2 ("rtw89: add Realtek 802.11ax driver") + Signed-off-by: Yang Yingliang + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211018033102.1813058-1-yangyingliang@huawei.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/cam.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/cam.c b/drivers/net/wireless/realtek/rtw89/cam.c +index c1e8c76c6aca..ad7a8155dbed 100644 +--- a/drivers/net/wireless/realtek/rtw89/cam.c ++++ b/drivers/net/wireless/realtek/rtw89/cam.c +@@ -77,7 +77,7 @@ static int rtw89_cam_send_sec_key_cmd(struct rtw89_dev *rtwdev, + return 0; + + ext_skb = rtw89_cam_get_sec_key_cmd(rtwdev, sec_cam, true); +- if (!skb) { ++ if (!ext_skb) { + rtw89_err(rtwdev, "failed to get ext sec key command\n"); + return -ENOMEM; + } +-- +2.13.6 + diff --git a/SOURCES/0005-rtw89-remove-unneeded-semicolon.patch b/SOURCES/0005-rtw89-remove-unneeded-semicolon.patch new file mode 100644 index 0000000..2184e24 --- /dev/null +++ b/SOURCES/0005-rtw89-remove-unneeded-semicolon.patch @@ -0,0 +1,47 @@ +From 23e2bf564a1ab65a01eab35189eae40f89368696 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:01 +0100 +Subject: [PATCH 05/36] rtw89: remove unneeded semicolon +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit e0e037b9fe5fbd19b21c0e542e44dd65f1b8cf58 +Author: Yang Li +Date: Tue Oct 19 15:54:54 2021 +0800 + + rtw89: remove unneeded semicolon + + Eliminate the following coccicheck warning: + ./drivers/net/wireless/realtek/rtw89/pci.c:1348:2-3: Unneeded semicolon + + Reported-by: Abaci Robot + Fixes: e3ec7017f6a2 ("rtw89: add Realtek 802.11ax driver") + Signed-off-by: Yang Li + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/1634630094-1156-1-git-send-email-yang.lee@linux.alibaba.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/pci.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c +index e9731012bca9..2c94762e4f93 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.c ++++ b/drivers/net/wireless/realtek/rtw89/pci.c +@@ -1345,7 +1345,7 @@ static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 + default: + rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); + return -EINVAL; +- }; ++ } + rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); + rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); + +-- +2.13.6 + diff --git a/SOURCES/0006-rtw89-fix-error-function-parameter.patch b/SOURCES/0006-rtw89-fix-error-function-parameter.patch new file mode 100644 index 0000000..9be87ed --- /dev/null +++ b/SOURCES/0006-rtw89-fix-error-function-parameter.patch @@ -0,0 +1,47 @@ +From 903a4e9d1c1a8a1790fef08c63c0b173c087dfaa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 06/36] rtw89: fix error function parameter +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit dea857700a75943017488b1d47f6687cfc037642 +Author: Lv Ruyi +Date: Thu Oct 21 04:20:35 2021 +0000 + + rtw89: fix error function parameter + + This patch fixes the following Coccinelle warning: + drivers/net/wireless/realtek/rtw89/rtw8852a.c:753: + WARNING possible condition with no effect (if == else) + + Reported-by: Zeal Robot + Signed-off-by: Lv Ruyi + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211021042035.1042463-1-lv.ruyi@zte.com.cn + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +index b1b87f0aadbb..5c6ffca3a324 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -757,7 +757,7 @@ static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, + else + rtw89_phy_write32_idx(rtwdev, R_P1_MODE, + B_P1_MODE_SEL, +- 1, phy_idx); ++ 0, phy_idx); + /* SCO compensate FC setting */ + sco_comp = rtw8852a_sco_mapping(central_ch); + rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, +-- +2.13.6 + diff --git a/SOURCES/0007-rtw89-remove-duplicate-register-definitions.patch b/SOURCES/0007-rtw89-remove-duplicate-register-definitions.patch new file mode 100644 index 0000000..e0f658f --- /dev/null +++ b/SOURCES/0007-rtw89-remove-duplicate-register-definitions.patch @@ -0,0 +1,46 @@ +From 017a26deb26b162623bd906fb5b25d249bc5b1e8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 07/36] rtw89: remove duplicate register definitions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 090f8a2f7b38f3a1dcf202437e5307761e8e4625 +Author: Kevin Lo +Date: Thu Oct 21 13:44:08 2021 +0800 + + rtw89: remove duplicate register definitions + + Remove duplicate register definitions. + + Signed-off-by: Kevin Lo + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/YXD+KL+xzFsnGShb@ns.kevlo.org + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/pci.h | 5 ----- + 1 file changed, 5 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h +index 34333c441aea..20e6767ea5c4 100644 +--- a/drivers/net/wireless/realtek/rtw89/pci.h ++++ b/drivers/net/wireless/realtek/rtw89/pci.h +@@ -276,11 +276,6 @@ + #define B_AX_CH10_BUSY BIT(0) + + /* Configure */ +-#define R_AX_PCIE_INIT_CFG1 0x1000 +-#define B_AX_PCIE_RXRST_KEEP_REG BIT(23) +-#define B_AX_PCIE_TXRST_KEEP_REG BIT(22) +-#define B_AX_DIS_RXDMA_PRE BIT(2) +- + #define R_AX_PCIE_INIT_CFG2 0x1004 + #define B_AX_WD_ITVL_IDLE GENMASK(27, 24) + #define B_AX_WD_ITVL_ACT GENMASK(19, 16) +-- +2.13.6 + diff --git a/SOURCES/0008-rtw89-fix-return-value-in-hfc_pub_cfg_chk.patch b/SOURCES/0008-rtw89-fix-return-value-in-hfc_pub_cfg_chk.patch new file mode 100644 index 0000000..5cde60b --- /dev/null +++ b/SOURCES/0008-rtw89-fix-return-value-in-hfc_pub_cfg_chk.patch @@ -0,0 +1,46 @@ +From db7fb65e5b6e99616d6f1a327eba6663dc2ca6a4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 08/36] rtw89: fix return value in hfc_pub_cfg_chk +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit c6477cb237048725922f6a786f68b5232abb418f +Author: Kevin Lo +Date: Thu Oct 21 14:32:27 2021 +0800 + + rtw89: fix return value in hfc_pub_cfg_chk + + It seems to me when pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max is true, + it should return -EFAULT rather than 0. Otherwise, the function doesn't need + to exist. + + Signed-off-by: Kevin Lo + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/YXEJey8lKksAZif4@ns.kevlo.org + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/mac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index 69384c43c046..afcd07ab1de7 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -560,7 +560,7 @@ static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) + const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; + + if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) +- return 0; ++ return -EFAULT; + + return 0; + } +-- +2.13.6 + diff --git a/SOURCES/0009-rtw89-Fix-variable-dereferenced-before-check-sta.patch b/SOURCES/0009-rtw89-Fix-variable-dereferenced-before-check-sta.patch new file mode 100644 index 0000000..733210b --- /dev/null +++ b/SOURCES/0009-rtw89-Fix-variable-dereferenced-before-check-sta.patch @@ -0,0 +1,65 @@ +From b18c6b7bcb369bd7dc222cc40c7264a6b5c4fa44 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 09/36] rtw89: Fix variable dereferenced before check 'sta' +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 5d44f0672319c19a41ff0e0e4f0d64164cf9752b +Author: Ping-Ke Shih +Date: Fri Oct 22 14:12:42 2021 +0800 + + rtw89: Fix variable dereferenced before check 'sta' + + The pointer rtwsta is dereferencing pointer sta before sta is being null + checked. Fix this by assigning sta->drv_priv to rtwsta only if sta is not + NULL, otherwise just NULL. + + Fixes: e3ec7017f6a2 ("rtw89: add Realtek 802.11ax driver") + Reported-by: Colin Ian King + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211022061242.8383-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/core.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +index 06fb6e5b1b37..d02ec5a735cb 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.c ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -1412,7 +1412,7 @@ static void rtw89_core_ba_work(struct work_struct *work) + list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { + struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); + struct ieee80211_sta *sta = txq->sta; +- struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; + u8 tid = txq->tid; + + if (!sta) { +@@ -1462,7 +1462,7 @@ static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, + struct ieee80211_hw *hw = rtwdev->hw; + struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); + struct ieee80211_sta *sta = txq->sta; +- struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; + + if (unlikely(skb_get_queue_mapping(skb) == IEEE80211_AC_VO)) + return; +@@ -1534,7 +1534,7 @@ static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, + { + struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; + struct ieee80211_sta *sta = txq->sta; +- struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; ++ struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; + + if (!sta || rtwsta->max_agg_wait <= 0) + return false; +-- +2.13.6 + diff --git a/SOURCES/0010-rtw89-update-partition-size-of-firmware-header-on-sk.patch b/SOURCES/0010-rtw89-update-partition-size-of-firmware-header-on-sk.patch new file mode 100644 index 0000000..7a7eb5c --- /dev/null +++ b/SOURCES/0010-rtw89-update-partition-size-of-firmware-header-on-sk.patch @@ -0,0 +1,79 @@ +From 4d6f3cdaef718e0b5e15bf36fc8d9c3740218996 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 10/36] rtw89: update partition size of firmware header on + skb->data +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 5737b4515deea0829c138ab5201160345ec67d49 +Author: Ping-Ke Shih +Date: Fri Nov 19 13:45:10 2021 +0800 + + rtw89: update partition size of firmware header on skb->data + + The partition size is used to tell hardware the size of piece we are going + to send a firmware. The old code updates the size in constant buffer of + firmware, and leads system crash. + + To fix this, update the size on skb->data after we copy the firmware data + into skb. + + Buglink: https://bugzilla.opensuse.org/show_bug.cgi?id=1188303 + Fixes: e3ec7017f6a2 ("rtw89: add Realtek 802.11ax driver") + Reported-by: Takashi Iwai + Signed-off-by: Ping-Ke Shih + Tested-by: Takashi Iwai + Tested-by: Larry Finger + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211119054512.10620-2-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/fw.c | 2 +- + drivers/net/wireless/realtek/rtw89/fw.h | 6 ++++-- + 2 files changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c +index 212aaf577d3c..65ef3dc9d061 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.c ++++ b/drivers/net/wireless/realtek/rtw89/fw.c +@@ -91,7 +91,6 @@ static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len, + info->section_num = GET_FW_HDR_SEC_NUM(fw); + info->hdr_len = RTW89_FW_HDR_SIZE + + info->section_num * RTW89_FW_SECTION_HDR_SIZE; +- SET_FW_HDR_PART_SIZE(fw, FWDL_SECTION_PER_PKT_LEN); + + bin = fw + info->hdr_len; + +@@ -275,6 +274,7 @@ static int __rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 l + } + + skb_put_data(skb, fw, len); ++ SET_FW_HDR_PART_SIZE(skb->data, FWDL_SECTION_PER_PKT_LEN); + rtw89_h2c_pkt_set_hdr_fwdl(rtwdev, skb, FWCMD_TYPE_H2C, + H2C_CAT_MAC, H2C_CL_MAC_FWDL, + H2C_FUNC_MAC_FWHDR_DL, len); +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +index 7ee0d9323310..36e8d0da6c1e 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.h ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -282,8 +282,10 @@ struct rtw89_h2creg_sch_tx_en { + le32_get_bits(*((__le32 *)(fwhdr) + 6), GENMASK(15, 8)) + #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ + le32_get_bits(*((__le32 *)(fwhdr) + 7), GENMASK(31, 24)) +-#define SET_FW_HDR_PART_SIZE(fwhdr, val) \ +- le32p_replace_bits((__le32 *)(fwhdr) + 7, val, GENMASK(15, 0)) ++static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) ++{ ++ le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); ++} + + #define SET_CTRL_INFO_MACID(table, val) \ + le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)) +-- +2.13.6 + diff --git a/SOURCES/0011-rtw89-fill-regd-field-of-limit-limit_ru-tables-by-en.patch b/SOURCES/0011-rtw89-fill-regd-field-of-limit-limit_ru-tables-by-en.patch new file mode 100644 index 0000000..981efa5 --- /dev/null +++ b/SOURCES/0011-rtw89-fill-regd-field-of-limit-limit_ru-tables-by-en.patch @@ -0,0 +1,10517 @@ +From d49d6bdb2caa2bf89c2c65c130de09d411533d64 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 11/36] rtw89: fill regd field of limit/limit_ru tables by enum +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 02356226692646b52160fbb214fe18e0d2a1c3eb +Author: Zong-Zhe Yang +Date: Mon Nov 1 17:31:03 2021 +0800 + + rtw89: fill regd field of limit/limit_ru tables by enum + + This modification just replaces the number filled in the regd field + with the corresponding enum. No assignment of a value in a table is + changed. Doing this first is because the follow-up patches may adjust + the order of enum declarations. + + Signed-off-by: Zong-Zhe Yang + Signed-off-by: Ping-Ke Shih + Reviewed-by: Brian Norris + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211101093106.28848-2-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + .../net/wireless/realtek/rtw89/rtw8852a_table.c | 10458 +++++++++---------- + 1 file changed, 5229 insertions(+), 5229 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +index 3a4fe7207420..c7ebeed043c5 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -43384,5248 +43384,5248 @@ static const u8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = { + const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [RTW89_RS_LMT_NUM][RTW89_BF_NUM] + [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = { +- [0][0][0][0][0][0] = 56, +- [0][0][0][0][0][1] = 56, +- [0][0][0][0][0][2] = 56, +- [0][0][0][0][0][3] = 56, +- [0][0][0][0][0][4] = 56, +- [0][0][0][0][0][5] = 56, +- [0][0][0][0][0][6] = 56, +- [0][0][0][0][0][7] = 56, +- [0][0][0][0][0][8] = 56, +- [0][0][0][0][0][9] = 56, +- [0][0][0][0][0][10] = 56, +- [0][0][0][0][0][11] = 56, +- [0][0][0][0][0][12] = 48, +- [0][0][0][0][0][13] = 76, +- [0][1][0][0][0][0] = 44, +- [0][1][0][0][0][1] = 44, +- [0][1][0][0][0][2] = 44, +- [0][1][0][0][0][3] = 44, +- [0][1][0][0][0][4] = 44, +- [0][1][0][0][0][5] = 44, +- [0][1][0][0][0][6] = 44, +- [0][1][0][0][0][7] = 44, +- [0][1][0][0][0][8] = 44, +- [0][1][0][0][0][9] = 44, +- [0][1][0][0][0][10] = 44, +- [0][1][0][0][0][11] = 44, +- [0][1][0][0][0][12] = 38, +- [0][1][0][0][0][13] = 64, +- [1][0][0][0][0][0] = 0, +- [1][0][0][0][0][1] = 0, +- [1][0][0][0][0][2] = 58, +- [1][0][0][0][0][3] = 58, +- [1][0][0][0][0][4] = 58, +- [1][0][0][0][0][5] = 58, +- [1][0][0][0][0][6] = 46, +- [1][0][0][0][0][7] = 46, +- [1][0][0][0][0][8] = 46, +- [1][0][0][0][0][9] = 32, +- [1][0][0][0][0][10] = 32, +- [1][0][0][0][0][11] = 0, +- [1][0][0][0][0][12] = 0, +- [1][0][0][0][0][13] = 0, +- [1][1][0][0][0][0] = 0, +- [1][1][0][0][0][1] = 0, +- [1][1][0][0][0][2] = 46, +- [1][1][0][0][0][3] = 46, +- [1][1][0][0][0][4] = 46, +- [1][1][0][0][0][5] = 46, +- [1][1][0][0][0][6] = 46, +- [1][1][0][0][0][7] = 46, +- [1][1][0][0][0][8] = 46, +- [1][1][0][0][0][9] = 24, +- [1][1][0][0][0][10] = 24, +- [1][1][0][0][0][11] = 0, +- [1][1][0][0][0][12] = 0, +- [1][1][0][0][0][13] = 0, +- [0][0][1][0][0][0] = 58, +- [0][0][1][0][0][1] = 58, +- [0][0][1][0][0][2] = 58, +- [0][0][1][0][0][3] = 58, +- [0][0][1][0][0][4] = 58, +- [0][0][1][0][0][5] = 58, +- [0][0][1][0][0][6] = 58, +- [0][0][1][0][0][7] = 58, +- [0][0][1][0][0][8] = 58, +- [0][0][1][0][0][9] = 58, +- [0][0][1][0][0][10] = 58, +- [0][0][1][0][0][11] = 56, +- [0][0][1][0][0][12] = 52, +- [0][0][1][0][0][13] = 0, +- [0][1][1][0][0][0] = 46, +- [0][1][1][0][0][1] = 46, +- [0][1][1][0][0][2] = 46, +- [0][1][1][0][0][3] = 46, +- [0][1][1][0][0][4] = 46, +- [0][1][1][0][0][5] = 46, +- [0][1][1][0][0][6] = 46, +- [0][1][1][0][0][7] = 46, +- [0][1][1][0][0][8] = 46, +- [0][1][1][0][0][9] = 46, +- [0][1][1][0][0][10] = 46, +- [0][1][1][0][0][11] = 42, +- [0][1][1][0][0][12] = 40, +- [0][1][1][0][0][13] = 0, +- [0][0][2][0][0][0] = 58, +- [0][0][2][0][0][1] = 58, +- [0][0][2][0][0][2] = 58, +- [0][0][2][0][0][3] = 58, +- [0][0][2][0][0][4] = 58, +- [0][0][2][0][0][5] = 58, +- [0][0][2][0][0][6] = 58, +- [0][0][2][0][0][7] = 58, +- [0][0][2][0][0][8] = 58, +- [0][0][2][0][0][9] = 58, +- [0][0][2][0][0][10] = 58, +- [0][0][2][0][0][11] = 54, +- [0][0][2][0][0][12] = 50, +- [0][0][2][0][0][13] = 0, +- [0][1][2][0][0][0] = 46, +- [0][1][2][0][0][1] = 46, +- [0][1][2][0][0][2] = 46, +- [0][1][2][0][0][3] = 46, +- [0][1][2][0][0][4] = 46, +- [0][1][2][0][0][5] = 46, +- [0][1][2][0][0][6] = 46, +- [0][1][2][0][0][7] = 46, +- [0][1][2][0][0][8] = 46, +- [0][1][2][0][0][9] = 46, +- [0][1][2][0][0][10] = 46, +- [0][1][2][0][0][11] = 42, +- [0][1][2][0][0][12] = 40, +- [0][1][2][0][0][13] = 0, +- [0][1][2][1][0][0] = 34, +- [0][1][2][1][0][1] = 34, +- [0][1][2][1][0][2] = 34, +- [0][1][2][1][0][3] = 34, +- [0][1][2][1][0][4] = 34, +- [0][1][2][1][0][5] = 34, +- [0][1][2][1][0][6] = 34, +- [0][1][2][1][0][7] = 34, +- [0][1][2][1][0][8] = 34, +- [0][1][2][1][0][9] = 34, +- [0][1][2][1][0][10] = 34, +- [0][1][2][1][0][11] = 34, +- [0][1][2][1][0][12] = 34, +- [0][1][2][1][0][13] = 0, +- [1][0][2][0][0][0] = 0, +- [1][0][2][0][0][1] = 0, +- [1][0][2][0][0][2] = 56, +- [1][0][2][0][0][3] = 56, +- [1][0][2][0][0][4] = 58, +- [1][0][2][0][0][5] = 58, +- [1][0][2][0][0][6] = 54, +- [1][0][2][0][0][7] = 50, +- [1][0][2][0][0][8] = 50, +- [1][0][2][0][0][9] = 42, +- [1][0][2][0][0][10] = 40, +- [1][0][2][0][0][11] = 0, +- [1][0][2][0][0][12] = 0, +- [1][0][2][0][0][13] = 0, +- [1][1][2][0][0][0] = 0, +- [1][1][2][0][0][1] = 0, +- [1][1][2][0][0][2] = 46, +- [1][1][2][0][0][3] = 46, +- [1][1][2][0][0][4] = 46, +- [1][1][2][0][0][5] = 46, +- [1][1][2][0][0][6] = 46, +- [1][1][2][0][0][7] = 46, +- [1][1][2][0][0][8] = 46, +- [1][1][2][0][0][9] = 38, +- [1][1][2][0][0][10] = 36, +- [1][1][2][0][0][11] = 0, +- [1][1][2][0][0][12] = 0, +- [1][1][2][0][0][13] = 0, +- [1][1][2][1][0][0] = 0, +- [1][1][2][1][0][1] = 0, +- [1][1][2][1][0][2] = 34, +- [1][1][2][1][0][3] = 34, +- [1][1][2][1][0][4] = 34, +- [1][1][2][1][0][5] = 34, +- [1][1][2][1][0][6] = 34, +- [1][1][2][1][0][7] = 34, +- [1][1][2][1][0][8] = 34, +- [1][1][2][1][0][9] = 34, +- [1][1][2][1][0][10] = 34, +- [1][1][2][1][0][11] = 0, +- [1][1][2][1][0][12] = 0, +- [1][1][2][1][0][13] = 0, +- [0][0][0][0][2][0] = 76, +- [0][0][0][0][1][0] = 56, +- [0][0][0][0][3][0] = 68, +- [0][0][0][0][5][0] = 76, +- [0][0][0][0][6][0] = 56, +- [0][0][0][0][9][0] = 56, +- [0][0][0][0][8][0] = 60, +- [0][0][0][0][11][0] = 56, +- [0][0][0][0][2][1] = 76, +- [0][0][0][0][1][1] = 56, +- [0][0][0][0][3][1] = 68, +- [0][0][0][0][5][1] = 76, +- [0][0][0][0][6][1] = 56, +- [0][0][0][0][9][1] = 56, +- [0][0][0][0][8][1] = 60, +- [0][0][0][0][11][1] = 56, +- [0][0][0][0][2][2] = 76, +- [0][0][0][0][1][2] = 56, +- [0][0][0][0][3][2] = 68, +- [0][0][0][0][5][2] = 76, +- [0][0][0][0][6][2] = 56, +- [0][0][0][0][9][2] = 56, +- [0][0][0][0][8][2] = 60, +- [0][0][0][0][11][2] = 56, +- [0][0][0][0][2][3] = 76, +- [0][0][0][0][1][3] = 56, +- [0][0][0][0][3][3] = 68, +- [0][0][0][0][5][3] = 76, +- [0][0][0][0][6][3] = 56, +- [0][0][0][0][9][3] = 56, +- [0][0][0][0][8][3] = 60, +- [0][0][0][0][11][3] = 56, +- [0][0][0][0][2][4] = 76, +- [0][0][0][0][1][4] = 56, +- [0][0][0][0][3][4] = 68, +- [0][0][0][0][5][4] = 76, +- [0][0][0][0][6][4] = 56, +- [0][0][0][0][9][4] = 56, +- [0][0][0][0][8][4] = 60, +- [0][0][0][0][11][4] = 56, +- [0][0][0][0][2][5] = 76, +- [0][0][0][0][1][5] = 56, +- [0][0][0][0][3][5] = 68, +- [0][0][0][0][5][5] = 76, +- [0][0][0][0][6][5] = 56, +- [0][0][0][0][9][5] = 56, +- [0][0][0][0][8][5] = 60, +- [0][0][0][0][11][5] = 56, +- [0][0][0][0][2][6] = 76, +- [0][0][0][0][1][6] = 56, +- [0][0][0][0][3][6] = 68, +- [0][0][0][0][5][6] = 76, +- [0][0][0][0][6][6] = 56, +- [0][0][0][0][9][6] = 56, +- [0][0][0][0][8][6] = 60, +- [0][0][0][0][11][6] = 56, +- [0][0][0][0][2][7] = 76, +- [0][0][0][0][1][7] = 56, +- [0][0][0][0][3][7] = 68, +- [0][0][0][0][5][7] = 76, +- [0][0][0][0][6][7] = 56, +- [0][0][0][0][9][7] = 56, +- [0][0][0][0][8][7] = 60, +- [0][0][0][0][11][7] = 56, +- [0][0][0][0][2][8] = 76, +- [0][0][0][0][1][8] = 56, +- [0][0][0][0][3][8] = 68, +- [0][0][0][0][5][8] = 76, +- [0][0][0][0][6][8] = 56, +- [0][0][0][0][9][8] = 56, +- [0][0][0][0][8][8] = 60, +- [0][0][0][0][11][8] = 56, +- [0][0][0][0][2][9] = 76, +- [0][0][0][0][1][9] = 56, +- [0][0][0][0][3][9] = 68, +- [0][0][0][0][5][9] = 76, +- [0][0][0][0][6][9] = 56, +- [0][0][0][0][9][9] = 56, +- [0][0][0][0][8][9] = 60, +- [0][0][0][0][11][9] = 56, +- [0][0][0][0][2][10] = 76, +- [0][0][0][0][1][10] = 56, +- [0][0][0][0][3][10] = 68, +- [0][0][0][0][5][10] = 76, +- [0][0][0][0][6][10] = 56, +- [0][0][0][0][9][10] = 56, +- [0][0][0][0][8][10] = 60, +- [0][0][0][0][11][10] = 56, +- [0][0][0][0][2][11] = 68, +- [0][0][0][0][1][11] = 56, +- [0][0][0][0][3][11] = 68, +- [0][0][0][0][5][11] = 68, +- [0][0][0][0][6][11] = 56, +- [0][0][0][0][9][11] = 56, +- [0][0][0][0][8][11] = 60, +- [0][0][0][0][11][11] = 56, +- [0][0][0][0][2][12] = 48, +- [0][0][0][0][1][12] = 56, +- [0][0][0][0][3][12] = 68, +- [0][0][0][0][5][12] = 48, +- [0][0][0][0][6][12] = 56, +- [0][0][0][0][9][12] = 56, +- [0][0][0][0][8][12] = 60, +- [0][0][0][0][11][12] = 56, +- [0][0][0][0][2][13] = 127, +- [0][0][0][0][1][13] = 127, +- [0][0][0][0][3][13] = 76, +- [0][0][0][0][5][13] = 127, +- [0][0][0][0][6][13] = 127, +- [0][0][0][0][9][13] = 127, +- [0][0][0][0][8][13] = 127, +- [0][0][0][0][11][13] = 127, +- [0][1][0][0][2][0] = 74, +- [0][1][0][0][1][0] = 44, +- [0][1][0][0][3][0] = 56, +- [0][1][0][0][5][0] = 74, +- [0][1][0][0][6][0] = 44, +- [0][1][0][0][9][0] = 44, +- [0][1][0][0][8][0] = 48, +- [0][1][0][0][11][0] = 44, +- [0][1][0][0][2][1] = 76, +- [0][1][0][0][1][1] = 44, +- [0][1][0][0][3][1] = 56, +- [0][1][0][0][5][1] = 76, +- [0][1][0][0][6][1] = 44, +- [0][1][0][0][9][1] = 44, +- [0][1][0][0][8][1] = 48, +- [0][1][0][0][11][1] = 44, +- [0][1][0][0][2][2] = 76, +- [0][1][0][0][1][2] = 44, +- [0][1][0][0][3][2] = 56, +- [0][1][0][0][5][2] = 76, +- [0][1][0][0][6][2] = 44, +- [0][1][0][0][9][2] = 44, +- [0][1][0][0][8][2] = 48, +- [0][1][0][0][11][2] = 44, +- [0][1][0][0][2][3] = 76, +- [0][1][0][0][1][3] = 44, +- [0][1][0][0][3][3] = 56, +- [0][1][0][0][5][3] = 76, +- [0][1][0][0][6][3] = 44, +- [0][1][0][0][9][3] = 44, +- [0][1][0][0][8][3] = 48, +- [0][1][0][0][11][3] = 44, +- [0][1][0][0][2][4] = 76, +- [0][1][0][0][1][4] = 44, +- [0][1][0][0][3][4] = 56, +- [0][1][0][0][5][4] = 76, +- [0][1][0][0][6][4] = 44, +- [0][1][0][0][9][4] = 44, +- [0][1][0][0][8][4] = 48, +- [0][1][0][0][11][4] = 44, +- [0][1][0][0][2][5] = 76, +- [0][1][0][0][1][5] = 44, +- [0][1][0][0][3][5] = 56, +- [0][1][0][0][5][5] = 76, +- [0][1][0][0][6][5] = 44, +- [0][1][0][0][9][5] = 44, +- [0][1][0][0][8][5] = 48, +- [0][1][0][0][11][5] = 44, +- [0][1][0][0][2][6] = 76, +- [0][1][0][0][1][6] = 44, +- [0][1][0][0][3][6] = 56, +- [0][1][0][0][5][6] = 76, +- [0][1][0][0][6][6] = 44, +- [0][1][0][0][9][6] = 44, +- [0][1][0][0][8][6] = 48, +- [0][1][0][0][11][6] = 44, +- [0][1][0][0][2][7] = 76, +- [0][1][0][0][1][7] = 44, +- [0][1][0][0][3][7] = 56, +- [0][1][0][0][5][7] = 76, +- [0][1][0][0][6][7] = 44, +- [0][1][0][0][9][7] = 44, +- [0][1][0][0][8][7] = 48, +- [0][1][0][0][11][7] = 44, +- [0][1][0][0][2][8] = 76, +- [0][1][0][0][1][8] = 44, +- [0][1][0][0][3][8] = 56, +- [0][1][0][0][5][8] = 76, +- [0][1][0][0][6][8] = 44, +- [0][1][0][0][9][8] = 44, +- [0][1][0][0][8][8] = 48, +- [0][1][0][0][11][8] = 44, +- [0][1][0][0][2][9] = 76, +- [0][1][0][0][1][9] = 44, +- [0][1][0][0][3][9] = 56, +- [0][1][0][0][5][9] = 76, +- [0][1][0][0][6][9] = 44, +- [0][1][0][0][9][9] = 44, +- [0][1][0][0][8][9] = 48, +- [0][1][0][0][11][9] = 44, +- [0][1][0][0][2][10] = 62, +- [0][1][0][0][1][10] = 44, +- [0][1][0][0][3][10] = 56, +- [0][1][0][0][5][10] = 62, +- [0][1][0][0][6][10] = 44, +- [0][1][0][0][9][10] = 44, +- [0][1][0][0][8][10] = 48, +- [0][1][0][0][11][10] = 44, +- [0][1][0][0][2][11] = 52, +- [0][1][0][0][1][11] = 44, +- [0][1][0][0][3][11] = 56, +- [0][1][0][0][5][11] = 52, +- [0][1][0][0][6][11] = 44, +- [0][1][0][0][9][11] = 44, +- [0][1][0][0][8][11] = 48, +- [0][1][0][0][11][11] = 44, +- [0][1][0][0][2][12] = 38, +- [0][1][0][0][1][12] = 44, +- [0][1][0][0][3][12] = 56, +- [0][1][0][0][5][12] = 38, +- [0][1][0][0][6][12] = 44, +- [0][1][0][0][9][12] = 44, +- [0][1][0][0][8][12] = 48, +- [0][1][0][0][11][12] = 44, +- [0][1][0][0][2][13] = 127, +- [0][1][0][0][1][13] = 127, +- [0][1][0][0][3][13] = 64, +- [0][1][0][0][5][13] = 127, +- [0][1][0][0][6][13] = 127, +- [0][1][0][0][9][13] = 127, +- [0][1][0][0][8][13] = 127, +- [0][1][0][0][11][13] = 127, +- [1][0][0][0][2][0] = 127, +- [1][0][0][0][1][0] = 127, +- [1][0][0][0][3][0] = 127, +- [1][0][0][0][5][0] = 127, +- [1][0][0][0][6][0] = 127, +- [1][0][0][0][9][0] = 127, +- [1][0][0][0][8][0] = 127, +- [1][0][0][0][11][0] = 127, +- [1][0][0][0][2][1] = 127, +- [1][0][0][0][1][1] = 127, +- [1][0][0][0][3][1] = 127, +- [1][0][0][0][5][1] = 127, +- [1][0][0][0][6][1] = 127, +- [1][0][0][0][9][1] = 127, +- [1][0][0][0][8][1] = 127, +- [1][0][0][0][11][1] = 127, +- [1][0][0][0][2][2] = 60, +- [1][0][0][0][1][2] = 58, +- [1][0][0][0][3][2] = 68, +- [1][0][0][0][5][2] = 60, +- [1][0][0][0][6][2] = 58, +- [1][0][0][0][9][2] = 58, +- [1][0][0][0][8][2] = 60, +- [1][0][0][0][11][2] = 58, +- [1][0][0][0][2][3] = 60, +- [1][0][0][0][1][3] = 58, +- [1][0][0][0][3][3] = 68, +- [1][0][0][0][5][3] = 60, +- [1][0][0][0][6][3] = 58, +- [1][0][0][0][9][3] = 58, +- [1][0][0][0][8][3] = 60, +- [1][0][0][0][11][3] = 58, +- [1][0][0][0][2][4] = 60, +- [1][0][0][0][1][4] = 58, +- [1][0][0][0][3][4] = 68, +- [1][0][0][0][5][4] = 60, +- [1][0][0][0][6][4] = 58, +- [1][0][0][0][9][4] = 58, +- [1][0][0][0][8][4] = 60, +- [1][0][0][0][11][4] = 58, +- [1][0][0][0][2][5] = 60, +- [1][0][0][0][1][5] = 58, +- [1][0][0][0][3][5] = 68, +- [1][0][0][0][5][5] = 60, +- [1][0][0][0][6][5] = 58, +- [1][0][0][0][9][5] = 58, +- [1][0][0][0][8][5] = 60, +- [1][0][0][0][11][5] = 58, +- [1][0][0][0][2][6] = 46, +- [1][0][0][0][1][6] = 58, +- [1][0][0][0][3][6] = 68, +- [1][0][0][0][5][6] = 46, +- [1][0][0][0][6][6] = 58, +- [1][0][0][0][9][6] = 58, +- [1][0][0][0][8][6] = 60, +- [1][0][0][0][11][6] = 58, +- [1][0][0][0][2][7] = 46, +- [1][0][0][0][1][7] = 58, +- [1][0][0][0][3][7] = 68, +- [1][0][0][0][5][7] = 46, +- [1][0][0][0][6][7] = 58, +- [1][0][0][0][9][7] = 58, +- [1][0][0][0][8][7] = 60, +- [1][0][0][0][11][7] = 58, +- [1][0][0][0][2][8] = 46, +- [1][0][0][0][1][8] = 58, +- [1][0][0][0][3][8] = 68, +- [1][0][0][0][5][8] = 46, +- [1][0][0][0][6][8] = 58, +- [1][0][0][0][9][8] = 58, +- [1][0][0][0][8][8] = 60, +- [1][0][0][0][11][8] = 58, +- [1][0][0][0][2][9] = 32, +- [1][0][0][0][1][9] = 58, +- [1][0][0][0][3][9] = 68, +- [1][0][0][0][5][9] = 32, +- [1][0][0][0][6][9] = 58, +- [1][0][0][0][9][9] = 58, +- [1][0][0][0][8][9] = 60, +- [1][0][0][0][11][9] = 58, +- [1][0][0][0][2][10] = 32, +- [1][0][0][0][1][10] = 58, +- [1][0][0][0][3][10] = 68, +- [1][0][0][0][5][10] = 32, +- [1][0][0][0][6][10] = 58, +- [1][0][0][0][9][10] = 58, +- [1][0][0][0][8][10] = 60, +- [1][0][0][0][11][10] = 58, +- [1][0][0][0][2][11] = 127, +- [1][0][0][0][1][11] = 127, +- [1][0][0][0][3][11] = 127, +- [1][0][0][0][5][11] = 127, +- [1][0][0][0][6][11] = 127, +- [1][0][0][0][9][11] = 127, +- [1][0][0][0][8][11] = 127, +- [1][0][0][0][11][11] = 127, +- [1][0][0][0][2][12] = 127, +- [1][0][0][0][1][12] = 127, +- [1][0][0][0][3][12] = 127, +- [1][0][0][0][5][12] = 127, +- [1][0][0][0][6][12] = 127, +- [1][0][0][0][9][12] = 127, +- [1][0][0][0][8][12] = 127, +- [1][0][0][0][11][12] = 127, +- [1][0][0][0][2][13] = 127, +- [1][0][0][0][1][13] = 127, +- [1][0][0][0][3][13] = 127, +- [1][0][0][0][5][13] = 127, +- [1][0][0][0][6][13] = 127, +- [1][0][0][0][9][13] = 127, +- [1][0][0][0][8][13] = 127, +- [1][0][0][0][11][13] = 127, +- [1][1][0][0][2][0] = 127, +- [1][1][0][0][1][0] = 127, +- [1][1][0][0][3][0] = 127, +- [1][1][0][0][5][0] = 127, +- [1][1][0][0][6][0] = 127, +- [1][1][0][0][9][0] = 127, +- [1][1][0][0][8][0] = 127, +- [1][1][0][0][11][0] = 127, +- [1][1][0][0][2][1] = 127, +- [1][1][0][0][1][1] = 127, +- [1][1][0][0][3][1] = 127, +- [1][1][0][0][5][1] = 127, +- [1][1][0][0][6][1] = 127, +- [1][1][0][0][9][1] = 127, +- [1][1][0][0][8][1] = 127, +- [1][1][0][0][11][1] = 127, +- [1][1][0][0][2][2] = 48, +- [1][1][0][0][1][2] = 46, +- [1][1][0][0][3][2] = 56, +- [1][1][0][0][5][2] = 48, +- [1][1][0][0][6][2] = 46, +- [1][1][0][0][9][2] = 46, +- [1][1][0][0][8][2] = 48, +- [1][1][0][0][11][2] = 46, +- [1][1][0][0][2][3] = 48, +- [1][1][0][0][1][3] = 46, +- [1][1][0][0][3][3] = 56, +- [1][1][0][0][5][3] = 48, +- [1][1][0][0][6][3] = 46, +- [1][1][0][0][9][3] = 46, +- [1][1][0][0][8][3] = 48, +- [1][1][0][0][11][3] = 46, +- [1][1][0][0][2][4] = 48, +- [1][1][0][0][1][4] = 46, +- [1][1][0][0][3][4] = 56, +- [1][1][0][0][5][4] = 48, +- [1][1][0][0][6][4] = 46, +- [1][1][0][0][9][4] = 46, +- [1][1][0][0][8][4] = 48, +- [1][1][0][0][11][4] = 46, +- [1][1][0][0][2][5] = 58, +- [1][1][0][0][1][5] = 46, +- [1][1][0][0][3][5] = 56, +- [1][1][0][0][5][5] = 58, +- [1][1][0][0][6][5] = 46, +- [1][1][0][0][9][5] = 46, +- [1][1][0][0][8][5] = 48, +- [1][1][0][0][11][5] = 46, +- [1][1][0][0][2][6] = 46, +- [1][1][0][0][1][6] = 46, +- [1][1][0][0][3][6] = 56, +- [1][1][0][0][5][6] = 46, +- [1][1][0][0][6][6] = 46, +- [1][1][0][0][9][6] = 46, +- [1][1][0][0][8][6] = 48, +- [1][1][0][0][11][6] = 46, +- [1][1][0][0][2][7] = 46, +- [1][1][0][0][1][7] = 46, +- [1][1][0][0][3][7] = 56, +- [1][1][0][0][5][7] = 46, +- [1][1][0][0][6][7] = 46, +- [1][1][0][0][9][7] = 46, +- [1][1][0][0][8][7] = 48, +- [1][1][0][0][11][7] = 46, +- [1][1][0][0][2][8] = 46, +- [1][1][0][0][1][8] = 46, +- [1][1][0][0][3][8] = 56, +- [1][1][0][0][5][8] = 46, +- [1][1][0][0][6][8] = 46, +- [1][1][0][0][9][8] = 46, +- [1][1][0][0][8][8] = 48, +- [1][1][0][0][11][8] = 46, +- [1][1][0][0][2][9] = 24, +- [1][1][0][0][1][9] = 46, +- [1][1][0][0][3][9] = 56, +- [1][1][0][0][5][9] = 24, +- [1][1][0][0][6][9] = 46, +- [1][1][0][0][9][9] = 46, +- [1][1][0][0][8][9] = 48, +- [1][1][0][0][11][9] = 46, +- [1][1][0][0][2][10] = 24, +- [1][1][0][0][1][10] = 46, +- [1][1][0][0][3][10] = 56, +- [1][1][0][0][5][10] = 24, +- [1][1][0][0][6][10] = 46, +- [1][1][0][0][9][10] = 46, +- [1][1][0][0][8][10] = 48, +- [1][1][0][0][11][10] = 46, +- [1][1][0][0][2][11] = 127, +- [1][1][0][0][1][11] = 127, +- [1][1][0][0][3][11] = 127, +- [1][1][0][0][5][11] = 127, +- [1][1][0][0][6][11] = 127, +- [1][1][0][0][9][11] = 127, +- [1][1][0][0][8][11] = 127, +- [1][1][0][0][11][11] = 127, +- [1][1][0][0][2][12] = 127, +- [1][1][0][0][1][12] = 127, +- [1][1][0][0][3][12] = 127, +- [1][1][0][0][5][12] = 127, +- [1][1][0][0][6][12] = 127, +- [1][1][0][0][9][12] = 127, +- [1][1][0][0][8][12] = 127, +- [1][1][0][0][11][12] = 127, +- [1][1][0][0][2][13] = 127, +- [1][1][0][0][1][13] = 127, +- [1][1][0][0][3][13] = 127, +- [1][1][0][0][5][13] = 127, +- [1][1][0][0][6][13] = 127, +- [1][1][0][0][9][13] = 127, +- [1][1][0][0][8][13] = 127, +- [1][1][0][0][11][13] = 127, +- [0][0][1][0][2][0] = 66, +- [0][0][1][0][1][0] = 58, +- [0][0][1][0][3][0] = 76, +- [0][0][1][0][5][0] = 66, +- [0][0][1][0][6][0] = 58, +- [0][0][1][0][9][0] = 58, +- [0][0][1][0][8][0] = 60, +- [0][0][1][0][11][0] = 58, +- [0][0][1][0][2][1] = 66, +- [0][0][1][0][1][1] = 58, +- [0][0][1][0][3][1] = 76, +- [0][0][1][0][5][1] = 66, +- [0][0][1][0][6][1] = 58, +- [0][0][1][0][9][1] = 58, +- [0][0][1][0][8][1] = 60, +- [0][0][1][0][11][1] = 58, +- [0][0][1][0][2][2] = 70, +- [0][0][1][0][1][2] = 58, +- [0][0][1][0][3][2] = 76, +- [0][0][1][0][5][2] = 70, +- [0][0][1][0][6][2] = 58, +- [0][0][1][0][9][2] = 58, +- [0][0][1][0][8][2] = 60, +- [0][0][1][0][11][2] = 58, +- [0][0][1][0][2][3] = 74, +- [0][0][1][0][1][3] = 58, +- [0][0][1][0][3][3] = 76, +- [0][0][1][0][5][3] = 74, +- [0][0][1][0][6][3] = 58, +- [0][0][1][0][9][3] = 58, +- [0][0][1][0][8][3] = 60, +- [0][0][1][0][11][3] = 58, +- [0][0][1][0][2][4] = 78, +- [0][0][1][0][1][4] = 58, +- [0][0][1][0][3][4] = 76, +- [0][0][1][0][5][4] = 78, +- [0][0][1][0][6][4] = 58, +- [0][0][1][0][9][4] = 58, +- [0][0][1][0][8][4] = 60, +- [0][0][1][0][11][4] = 58, +- [0][0][1][0][2][5] = 78, +- [0][0][1][0][1][5] = 58, +- [0][0][1][0][3][5] = 76, +- [0][0][1][0][5][5] = 78, +- [0][0][1][0][6][5] = 58, +- [0][0][1][0][9][5] = 58, +- [0][0][1][0][8][5] = 60, +- [0][0][1][0][11][5] = 58, +- [0][0][1][0][2][6] = 78, +- [0][0][1][0][1][6] = 58, +- [0][0][1][0][3][6] = 76, +- [0][0][1][0][5][6] = 78, +- [0][0][1][0][6][6] = 58, +- [0][0][1][0][9][6] = 58, +- [0][0][1][0][8][6] = 60, +- [0][0][1][0][11][6] = 58, +- [0][0][1][0][2][7] = 74, +- [0][0][1][0][1][7] = 58, +- [0][0][1][0][3][7] = 76, +- [0][0][1][0][5][7] = 74, +- [0][0][1][0][6][7] = 58, +- [0][0][1][0][9][7] = 58, +- [0][0][1][0][8][7] = 60, +- [0][0][1][0][11][7] = 58, +- [0][0][1][0][2][8] = 70, +- [0][0][1][0][1][8] = 58, +- [0][0][1][0][3][8] = 76, +- [0][0][1][0][5][8] = 70, +- [0][0][1][0][6][8] = 58, +- [0][0][1][0][9][8] = 58, +- [0][0][1][0][8][8] = 60, +- [0][0][1][0][11][8] = 58, +- [0][0][1][0][2][9] = 66, +- [0][0][1][0][1][9] = 58, +- [0][0][1][0][3][9] = 76, +- [0][0][1][0][5][9] = 66, +- [0][0][1][0][6][9] = 58, +- [0][0][1][0][9][9] = 58, +- [0][0][1][0][8][9] = 60, +- [0][0][1][0][11][9] = 58, +- [0][0][1][0][2][10] = 66, +- [0][0][1][0][1][10] = 58, +- [0][0][1][0][3][10] = 76, +- [0][0][1][0][5][10] = 66, +- [0][0][1][0][6][10] = 58, +- [0][0][1][0][9][10] = 58, +- [0][0][1][0][8][10] = 60, +- [0][0][1][0][11][10] = 58, +- [0][0][1][0][2][11] = 56, +- [0][0][1][0][1][11] = 58, +- [0][0][1][0][3][11] = 76, +- [0][0][1][0][5][11] = 56, +- [0][0][1][0][6][11] = 58, +- [0][0][1][0][9][11] = 58, +- [0][0][1][0][8][11] = 60, +- [0][0][1][0][11][11] = 58, +- [0][0][1][0][2][12] = 52, +- [0][0][1][0][1][12] = 58, +- [0][0][1][0][3][12] = 76, +- [0][0][1][0][5][12] = 52, +- [0][0][1][0][6][12] = 58, +- [0][0][1][0][9][12] = 58, +- [0][0][1][0][8][12] = 60, +- [0][0][1][0][11][12] = 58, +- [0][0][1][0][2][13] = 127, +- [0][0][1][0][1][13] = 127, +- [0][0][1][0][3][13] = 127, +- [0][0][1][0][5][13] = 127, +- [0][0][1][0][6][13] = 127, +- [0][0][1][0][9][13] = 127, +- [0][0][1][0][8][13] = 127, +- [0][0][1][0][11][13] = 127, +- [0][1][1][0][2][0] = 62, +- [0][1][1][0][1][0] = 46, +- [0][1][1][0][3][0] = 64, +- [0][1][1][0][5][0] = 62, +- [0][1][1][0][6][0] = 46, +- [0][1][1][0][9][0] = 46, +- [0][1][1][0][8][0] = 48, +- [0][1][1][0][11][0] = 46, +- [0][1][1][0][2][1] = 62, +- [0][1][1][0][1][1] = 46, +- [0][1][1][0][3][1] = 64, +- [0][1][1][0][5][1] = 62, +- [0][1][1][0][6][1] = 46, +- [0][1][1][0][9][1] = 46, +- [0][1][1][0][8][1] = 48, +- [0][1][1][0][11][1] = 46, +- [0][1][1][0][2][2] = 66, +- [0][1][1][0][1][2] = 46, +- [0][1][1][0][3][2] = 64, +- [0][1][1][0][5][2] = 66, +- [0][1][1][0][6][2] = 46, +- [0][1][1][0][9][2] = 46, +- [0][1][1][0][8][2] = 48, +- [0][1][1][0][11][2] = 46, +- [0][1][1][0][2][3] = 70, +- [0][1][1][0][1][3] = 46, +- [0][1][1][0][3][3] = 64, +- [0][1][1][0][5][3] = 70, +- [0][1][1][0][6][3] = 46, +- [0][1][1][0][9][3] = 46, +- [0][1][1][0][8][3] = 48, +- [0][1][1][0][11][3] = 46, +- [0][1][1][0][2][4] = 78, +- [0][1][1][0][1][4] = 46, +- [0][1][1][0][3][4] = 64, +- [0][1][1][0][5][4] = 78, +- [0][1][1][0][6][4] = 46, +- [0][1][1][0][9][4] = 46, +- [0][1][1][0][8][4] = 48, +- [0][1][1][0][11][4] = 46, +- [0][1][1][0][2][5] = 78, +- [0][1][1][0][1][5] = 46, +- [0][1][1][0][3][5] = 64, +- [0][1][1][0][5][5] = 78, +- [0][1][1][0][6][5] = 46, +- [0][1][1][0][9][5] = 46, +- [0][1][1][0][8][5] = 48, +- [0][1][1][0][11][5] = 46, +- [0][1][1][0][2][6] = 78, +- [0][1][1][0][1][6] = 46, +- [0][1][1][0][3][6] = 64, +- [0][1][1][0][5][6] = 78, +- [0][1][1][0][6][6] = 46, +- [0][1][1][0][9][6] = 46, +- [0][1][1][0][8][6] = 48, +- [0][1][1][0][11][6] = 46, +- [0][1][1][0][2][7] = 70, +- [0][1][1][0][1][7] = 46, +- [0][1][1][0][3][7] = 64, +- [0][1][1][0][5][7] = 70, +- [0][1][1][0][6][7] = 46, +- [0][1][1][0][9][7] = 46, +- [0][1][1][0][8][7] = 48, +- [0][1][1][0][11][7] = 46, +- [0][1][1][0][2][8] = 66, +- [0][1][1][0][1][8] = 46, +- [0][1][1][0][3][8] = 64, +- [0][1][1][0][5][8] = 66, +- [0][1][1][0][6][8] = 46, +- [0][1][1][0][9][8] = 46, +- [0][1][1][0][8][8] = 48, +- [0][1][1][0][11][8] = 46, +- [0][1][1][0][2][9] = 62, +- [0][1][1][0][1][9] = 46, +- [0][1][1][0][3][9] = 64, +- [0][1][1][0][5][9] = 62, +- [0][1][1][0][6][9] = 46, +- [0][1][1][0][9][9] = 46, +- [0][1][1][0][8][9] = 48, +- [0][1][1][0][11][9] = 46, +- [0][1][1][0][2][10] = 62, +- [0][1][1][0][1][10] = 46, +- [0][1][1][0][3][10] = 64, +- [0][1][1][0][5][10] = 62, +- [0][1][1][0][6][10] = 46, +- [0][1][1][0][9][10] = 46, +- [0][1][1][0][8][10] = 48, +- [0][1][1][0][11][10] = 46, +- [0][1][1][0][2][11] = 42, +- [0][1][1][0][1][11] = 46, +- [0][1][1][0][3][11] = 64, +- [0][1][1][0][5][11] = 42, +- [0][1][1][0][6][11] = 46, +- [0][1][1][0][9][11] = 46, +- [0][1][1][0][8][11] = 48, +- [0][1][1][0][11][11] = 46, +- [0][1][1][0][2][12] = 40, +- [0][1][1][0][1][12] = 46, +- [0][1][1][0][3][12] = 64, +- [0][1][1][0][5][12] = 40, +- [0][1][1][0][6][12] = 46, +- [0][1][1][0][9][12] = 46, +- [0][1][1][0][8][12] = 48, +- [0][1][1][0][11][12] = 46, +- [0][1][1][0][2][13] = 127, +- [0][1][1][0][1][13] = 127, +- [0][1][1][0][3][13] = 127, +- [0][1][1][0][5][13] = 127, +- [0][1][1][0][6][13] = 127, +- [0][1][1][0][9][13] = 127, +- [0][1][1][0][8][13] = 127, +- [0][1][1][0][11][13] = 127, +- [0][0][2][0][2][0] = 66, +- [0][0][2][0][1][0] = 58, +- [0][0][2][0][3][0] = 76, +- [0][0][2][0][5][0] = 66, +- [0][0][2][0][6][0] = 58, +- [0][0][2][0][9][0] = 58, +- [0][0][2][0][8][0] = 60, +- [0][0][2][0][11][0] = 58, +- [0][0][2][0][2][1] = 66, +- [0][0][2][0][1][1] = 58, +- [0][0][2][0][3][1] = 76, +- [0][0][2][0][5][1] = 66, +- [0][0][2][0][6][1] = 58, +- [0][0][2][0][9][1] = 58, +- [0][0][2][0][8][1] = 60, +- [0][0][2][0][11][1] = 58, +- [0][0][2][0][2][2] = 70, +- [0][0][2][0][1][2] = 58, +- [0][0][2][0][3][2] = 76, +- [0][0][2][0][5][2] = 70, +- [0][0][2][0][6][2] = 58, +- [0][0][2][0][9][2] = 58, +- [0][0][2][0][8][2] = 60, +- [0][0][2][0][11][2] = 58, +- [0][0][2][0][2][3] = 74, +- [0][0][2][0][1][3] = 58, +- [0][0][2][0][3][3] = 76, +- [0][0][2][0][5][3] = 74, +- [0][0][2][0][6][3] = 58, +- [0][0][2][0][9][3] = 58, +- [0][0][2][0][8][3] = 60, +- [0][0][2][0][11][3] = 58, +- [0][0][2][0][2][4] = 76, +- [0][0][2][0][1][4] = 58, +- [0][0][2][0][3][4] = 76, +- [0][0][2][0][5][4] = 76, +- [0][0][2][0][6][4] = 58, +- [0][0][2][0][9][4] = 58, +- [0][0][2][0][8][4] = 60, +- [0][0][2][0][11][4] = 58, +- [0][0][2][0][2][5] = 76, +- [0][0][2][0][1][5] = 58, +- [0][0][2][0][3][5] = 76, +- [0][0][2][0][5][5] = 76, +- [0][0][2][0][6][5] = 58, +- [0][0][2][0][9][5] = 58, +- [0][0][2][0][8][5] = 60, +- [0][0][2][0][11][5] = 58, +- [0][0][2][0][2][6] = 76, +- [0][0][2][0][1][6] = 58, +- [0][0][2][0][3][6] = 76, +- [0][0][2][0][5][6] = 76, +- [0][0][2][0][6][6] = 58, +- [0][0][2][0][9][6] = 58, +- [0][0][2][0][8][6] = 60, +- [0][0][2][0][11][6] = 58, +- [0][0][2][0][2][7] = 74, +- [0][0][2][0][1][7] = 58, +- [0][0][2][0][3][7] = 76, +- [0][0][2][0][5][7] = 74, +- [0][0][2][0][6][7] = 58, +- [0][0][2][0][9][7] = 58, +- [0][0][2][0][8][7] = 60, +- [0][0][2][0][11][7] = 58, +- [0][0][2][0][2][8] = 70, +- [0][0][2][0][1][8] = 58, +- [0][0][2][0][3][8] = 76, +- [0][0][2][0][5][8] = 70, +- [0][0][2][0][6][8] = 58, +- [0][0][2][0][9][8] = 58, +- [0][0][2][0][8][8] = 60, +- [0][0][2][0][11][8] = 58, +- [0][0][2][0][2][9] = 66, +- [0][0][2][0][1][9] = 58, +- [0][0][2][0][3][9] = 76, +- [0][0][2][0][5][9] = 66, +- [0][0][2][0][6][9] = 58, +- [0][0][2][0][9][9] = 58, +- [0][0][2][0][8][9] = 60, +- [0][0][2][0][11][9] = 58, +- [0][0][2][0][2][10] = 66, +- [0][0][2][0][1][10] = 58, +- [0][0][2][0][3][10] = 76, +- [0][0][2][0][5][10] = 66, +- [0][0][2][0][6][10] = 58, +- [0][0][2][0][9][10] = 58, +- [0][0][2][0][8][10] = 60, +- [0][0][2][0][11][10] = 58, +- [0][0][2][0][2][11] = 54, +- [0][0][2][0][1][11] = 58, +- [0][0][2][0][3][11] = 76, +- [0][0][2][0][5][11] = 54, +- [0][0][2][0][6][11] = 58, +- [0][0][2][0][9][11] = 58, +- [0][0][2][0][8][11] = 60, +- [0][0][2][0][11][11] = 58, +- [0][0][2][0][2][12] = 50, +- [0][0][2][0][1][12] = 58, +- [0][0][2][0][3][12] = 76, +- [0][0][2][0][5][12] = 50, +- [0][0][2][0][6][12] = 58, +- [0][0][2][0][9][12] = 58, +- [0][0][2][0][8][12] = 60, +- [0][0][2][0][11][12] = 58, +- [0][0][2][0][2][13] = 127, +- [0][0][2][0][1][13] = 127, +- [0][0][2][0][3][13] = 127, +- [0][0][2][0][5][13] = 127, +- [0][0][2][0][6][13] = 127, +- [0][0][2][0][9][13] = 127, +- [0][0][2][0][8][13] = 127, +- [0][0][2][0][11][13] = 127, +- [0][1][2][0][2][0] = 62, +- [0][1][2][0][1][0] = 46, +- [0][1][2][0][3][0] = 64, +- [0][1][2][0][5][0] = 62, +- [0][1][2][0][6][0] = 46, +- [0][1][2][0][9][0] = 46, +- [0][1][2][0][8][0] = 48, +- [0][1][2][0][11][0] = 46, +- [0][1][2][0][2][1] = 62, +- [0][1][2][0][1][1] = 46, +- [0][1][2][0][3][1] = 64, +- [0][1][2][0][5][1] = 62, +- [0][1][2][0][6][1] = 46, +- [0][1][2][0][9][1] = 46, +- [0][1][2][0][8][1] = 48, +- [0][1][2][0][11][1] = 46, +- [0][1][2][0][2][2] = 66, +- [0][1][2][0][1][2] = 46, +- [0][1][2][0][3][2] = 64, +- [0][1][2][0][5][2] = 66, +- [0][1][2][0][6][2] = 46, +- [0][1][2][0][9][2] = 46, +- [0][1][2][0][8][2] = 48, +- [0][1][2][0][11][2] = 46, +- [0][1][2][0][2][3] = 70, +- [0][1][2][0][1][3] = 46, +- [0][1][2][0][3][3] = 64, +- [0][1][2][0][5][3] = 70, +- [0][1][2][0][6][3] = 46, +- [0][1][2][0][9][3] = 46, +- [0][1][2][0][8][3] = 48, +- [0][1][2][0][11][3] = 46, +- [0][1][2][0][2][4] = 76, +- [0][1][2][0][1][4] = 46, +- [0][1][2][0][3][4] = 64, +- [0][1][2][0][5][4] = 76, +- [0][1][2][0][6][4] = 46, +- [0][1][2][0][9][4] = 46, +- [0][1][2][0][8][4] = 48, +- [0][1][2][0][11][4] = 46, +- [0][1][2][0][2][5] = 76, +- [0][1][2][0][1][5] = 46, +- [0][1][2][0][3][5] = 64, +- [0][1][2][0][5][5] = 76, +- [0][1][2][0][6][5] = 46, +- [0][1][2][0][9][5] = 46, +- [0][1][2][0][8][5] = 48, +- [0][1][2][0][11][5] = 46, +- [0][1][2][0][2][6] = 76, +- [0][1][2][0][1][6] = 46, +- [0][1][2][0][3][6] = 64, +- [0][1][2][0][5][6] = 76, +- [0][1][2][0][6][6] = 46, +- [0][1][2][0][9][6] = 46, +- [0][1][2][0][8][6] = 48, +- [0][1][2][0][11][6] = 46, +- [0][1][2][0][2][7] = 68, +- [0][1][2][0][1][7] = 46, +- [0][1][2][0][3][7] = 64, +- [0][1][2][0][5][7] = 68, +- [0][1][2][0][6][7] = 46, +- [0][1][2][0][9][7] = 46, +- [0][1][2][0][8][7] = 48, +- [0][1][2][0][11][7] = 46, +- [0][1][2][0][2][8] = 64, +- [0][1][2][0][1][8] = 46, +- [0][1][2][0][3][8] = 64, +- [0][1][2][0][5][8] = 64, +- [0][1][2][0][6][8] = 46, +- [0][1][2][0][9][8] = 46, +- [0][1][2][0][8][8] = 48, +- [0][1][2][0][11][8] = 46, +- [0][1][2][0][2][9] = 60, +- [0][1][2][0][1][9] = 46, +- [0][1][2][0][3][9] = 64, +- [0][1][2][0][5][9] = 60, +- [0][1][2][0][6][9] = 46, +- [0][1][2][0][9][9] = 46, +- [0][1][2][0][8][9] = 48, +- [0][1][2][0][11][9] = 46, +- [0][1][2][0][2][10] = 60, +- [0][1][2][0][1][10] = 46, +- [0][1][2][0][3][10] = 64, +- [0][1][2][0][5][10] = 60, +- [0][1][2][0][6][10] = 46, +- [0][1][2][0][9][10] = 46, +- [0][1][2][0][8][10] = 48, +- [0][1][2][0][11][10] = 46, +- [0][1][2][0][2][11] = 42, +- [0][1][2][0][1][11] = 46, +- [0][1][2][0][3][11] = 64, +- [0][1][2][0][5][11] = 42, +- [0][1][2][0][6][11] = 46, +- [0][1][2][0][9][11] = 46, +- [0][1][2][0][8][11] = 48, +- [0][1][2][0][11][11] = 46, +- [0][1][2][0][2][12] = 40, +- [0][1][2][0][1][12] = 46, +- [0][1][2][0][3][12] = 64, +- [0][1][2][0][5][12] = 40, +- [0][1][2][0][6][12] = 46, +- [0][1][2][0][9][12] = 46, +- [0][1][2][0][8][12] = 48, +- [0][1][2][0][11][12] = 46, +- [0][1][2][0][2][13] = 127, +- [0][1][2][0][1][13] = 127, +- [0][1][2][0][3][13] = 127, +- [0][1][2][0][5][13] = 127, +- [0][1][2][0][6][13] = 127, +- [0][1][2][0][9][13] = 127, +- [0][1][2][0][8][13] = 127, +- [0][1][2][0][11][13] = 127, +- [0][1][2][1][2][0] = 62, +- [0][1][2][1][1][0] = 34, +- [0][1][2][1][3][0] = 64, +- [0][1][2][1][5][0] = 62, +- [0][1][2][1][6][0] = 34, +- [0][1][2][1][9][0] = 34, +- [0][1][2][1][8][0] = 36, +- [0][1][2][1][11][0] = 34, +- [0][1][2][1][2][1] = 62, +- [0][1][2][1][1][1] = 34, +- [0][1][2][1][3][1] = 64, +- [0][1][2][1][5][1] = 62, +- [0][1][2][1][6][1] = 34, +- [0][1][2][1][9][1] = 34, +- [0][1][2][1][8][1] = 36, +- [0][1][2][1][11][1] = 34, +- [0][1][2][1][2][2] = 66, +- [0][1][2][1][1][2] = 34, +- [0][1][2][1][3][2] = 64, +- [0][1][2][1][5][2] = 66, +- [0][1][2][1][6][2] = 34, +- [0][1][2][1][9][2] = 34, +- [0][1][2][1][8][2] = 36, +- [0][1][2][1][11][2] = 34, +- [0][1][2][1][2][3] = 70, +- [0][1][2][1][1][3] = 34, +- [0][1][2][1][3][3] = 64, +- [0][1][2][1][5][3] = 70, +- [0][1][2][1][6][3] = 34, +- [0][1][2][1][9][3] = 34, +- [0][1][2][1][8][3] = 36, +- [0][1][2][1][11][3] = 34, +- [0][1][2][1][2][4] = 76, +- [0][1][2][1][1][4] = 34, +- [0][1][2][1][3][4] = 64, +- [0][1][2][1][5][4] = 76, +- [0][1][2][1][6][4] = 34, +- [0][1][2][1][9][4] = 34, +- [0][1][2][1][8][4] = 36, +- [0][1][2][1][11][4] = 34, +- [0][1][2][1][2][5] = 76, +- [0][1][2][1][1][5] = 34, +- [0][1][2][1][3][5] = 64, +- [0][1][2][1][5][5] = 76, +- [0][1][2][1][6][5] = 34, +- [0][1][2][1][9][5] = 34, +- [0][1][2][1][8][5] = 36, +- [0][1][2][1][11][5] = 34, +- [0][1][2][1][2][6] = 76, +- [0][1][2][1][1][6] = 34, +- [0][1][2][1][3][6] = 64, +- [0][1][2][1][5][6] = 76, +- [0][1][2][1][6][6] = 34, +- [0][1][2][1][9][6] = 34, +- [0][1][2][1][8][6] = 36, +- [0][1][2][1][11][6] = 34, +- [0][1][2][1][2][7] = 68, +- [0][1][2][1][1][7] = 34, +- [0][1][2][1][3][7] = 64, +- [0][1][2][1][5][7] = 68, +- [0][1][2][1][6][7] = 34, +- [0][1][2][1][9][7] = 34, +- [0][1][2][1][8][7] = 36, +- [0][1][2][1][11][7] = 34, +- [0][1][2][1][2][8] = 64, +- [0][1][2][1][1][8] = 34, +- [0][1][2][1][3][8] = 64, +- [0][1][2][1][5][8] = 64, +- [0][1][2][1][6][8] = 34, +- [0][1][2][1][9][8] = 34, +- [0][1][2][1][8][8] = 36, +- [0][1][2][1][11][8] = 34, +- [0][1][2][1][2][9] = 60, +- [0][1][2][1][1][9] = 34, +- [0][1][2][1][3][9] = 64, +- [0][1][2][1][5][9] = 60, +- [0][1][2][1][6][9] = 34, +- [0][1][2][1][9][9] = 34, +- [0][1][2][1][8][9] = 36, +- [0][1][2][1][11][9] = 34, +- [0][1][2][1][2][10] = 60, +- [0][1][2][1][1][10] = 34, +- [0][1][2][1][3][10] = 64, +- [0][1][2][1][5][10] = 60, +- [0][1][2][1][6][10] = 34, +- [0][1][2][1][9][10] = 34, +- [0][1][2][1][8][10] = 36, +- [0][1][2][1][11][10] = 34, +- [0][1][2][1][2][11] = 42, +- [0][1][2][1][1][11] = 34, +- [0][1][2][1][3][11] = 64, +- [0][1][2][1][5][11] = 42, +- [0][1][2][1][6][11] = 34, +- [0][1][2][1][9][11] = 34, +- [0][1][2][1][8][11] = 36, +- [0][1][2][1][11][11] = 34, +- [0][1][2][1][2][12] = 40, +- [0][1][2][1][1][12] = 34, +- [0][1][2][1][3][12] = 64, +- [0][1][2][1][5][12] = 40, +- [0][1][2][1][6][12] = 34, +- [0][1][2][1][9][12] = 34, +- [0][1][2][1][8][12] = 36, +- [0][1][2][1][11][12] = 34, +- [0][1][2][1][2][13] = 127, +- [0][1][2][1][1][13] = 127, +- [0][1][2][1][3][13] = 127, +- [0][1][2][1][5][13] = 127, +- [0][1][2][1][6][13] = 127, +- [0][1][2][1][9][13] = 127, +- [0][1][2][1][8][13] = 127, +- [0][1][2][1][11][13] = 127, +- [1][0][2][0][2][0] = 127, +- [1][0][2][0][1][0] = 127, +- [1][0][2][0][3][0] = 127, +- [1][0][2][0][5][0] = 127, +- [1][0][2][0][6][0] = 127, +- [1][0][2][0][9][0] = 127, +- [1][0][2][0][8][0] = 127, +- [1][0][2][0][11][0] = 127, +- [1][0][2][0][2][1] = 127, +- [1][0][2][0][1][1] = 127, +- [1][0][2][0][3][1] = 127, +- [1][0][2][0][5][1] = 127, +- [1][0][2][0][6][1] = 127, +- [1][0][2][0][9][1] = 127, +- [1][0][2][0][8][1] = 127, +- [1][0][2][0][11][1] = 127, +- [1][0][2][0][2][2] = 56, +- [1][0][2][0][1][2] = 58, +- [1][0][2][0][3][2] = 76, +- [1][0][2][0][5][2] = 56, +- [1][0][2][0][6][2] = 58, +- [1][0][2][0][9][2] = 58, +- [1][0][2][0][8][2] = 60, +- [1][0][2][0][11][2] = 58, +- [1][0][2][0][2][3] = 56, +- [1][0][2][0][1][3] = 58, +- [1][0][2][0][3][3] = 76, +- [1][0][2][0][5][3] = 56, +- [1][0][2][0][6][3] = 58, +- [1][0][2][0][9][3] = 58, +- [1][0][2][0][8][3] = 60, +- [1][0][2][0][11][3] = 58, +- [1][0][2][0][2][4] = 60, +- [1][0][2][0][1][4] = 58, +- [1][0][2][0][3][4] = 76, +- [1][0][2][0][5][4] = 60, +- [1][0][2][0][6][4] = 58, +- [1][0][2][0][9][4] = 58, +- [1][0][2][0][8][4] = 60, +- [1][0][2][0][11][4] = 58, +- [1][0][2][0][2][5] = 64, +- [1][0][2][0][1][5] = 58, +- [1][0][2][0][3][5] = 76, +- [1][0][2][0][5][5] = 64, +- [1][0][2][0][6][5] = 58, +- [1][0][2][0][9][5] = 58, +- [1][0][2][0][8][5] = 60, +- [1][0][2][0][11][5] = 58, +- [1][0][2][0][2][6] = 54, +- [1][0][2][0][1][6] = 58, +- [1][0][2][0][3][6] = 76, +- [1][0][2][0][5][6] = 54, +- [1][0][2][0][6][6] = 58, +- [1][0][2][0][9][6] = 58, +- [1][0][2][0][8][6] = 60, +- [1][0][2][0][11][6] = 58, +- [1][0][2][0][2][7] = 50, +- [1][0][2][0][1][7] = 58, +- [1][0][2][0][3][7] = 76, +- [1][0][2][0][5][7] = 50, +- [1][0][2][0][6][7] = 58, +- [1][0][2][0][9][7] = 58, +- [1][0][2][0][8][7] = 60, +- [1][0][2][0][11][7] = 58, +- [1][0][2][0][2][8] = 50, +- [1][0][2][0][1][8] = 58, +- [1][0][2][0][3][8] = 76, +- [1][0][2][0][5][8] = 50, +- [1][0][2][0][6][8] = 58, +- [1][0][2][0][9][8] = 58, +- [1][0][2][0][8][8] = 60, +- [1][0][2][0][11][8] = 58, +- [1][0][2][0][2][9] = 42, +- [1][0][2][0][1][9] = 58, +- [1][0][2][0][3][9] = 76, +- [1][0][2][0][5][9] = 42, +- [1][0][2][0][6][9] = 58, +- [1][0][2][0][9][9] = 58, +- [1][0][2][0][8][9] = 60, +- [1][0][2][0][11][9] = 58, +- [1][0][2][0][2][10] = 40, +- [1][0][2][0][1][10] = 58, +- [1][0][2][0][3][10] = 76, +- [1][0][2][0][5][10] = 40, +- [1][0][2][0][6][10] = 58, +- [1][0][2][0][9][10] = 58, +- [1][0][2][0][8][10] = 60, +- [1][0][2][0][11][10] = 58, +- [1][0][2][0][2][11] = 127, +- [1][0][2][0][1][11] = 127, +- [1][0][2][0][3][11] = 127, +- [1][0][2][0][5][11] = 127, +- [1][0][2][0][6][11] = 127, +- [1][0][2][0][9][11] = 127, +- [1][0][2][0][8][11] = 127, +- [1][0][2][0][11][11] = 127, +- [1][0][2][0][2][12] = 127, +- [1][0][2][0][1][12] = 127, +- [1][0][2][0][3][12] = 127, +- [1][0][2][0][5][12] = 127, +- [1][0][2][0][6][12] = 127, +- [1][0][2][0][9][12] = 127, +- [1][0][2][0][8][12] = 127, +- [1][0][2][0][11][12] = 127, +- [1][0][2][0][2][13] = 127, +- [1][0][2][0][1][13] = 127, +- [1][0][2][0][3][13] = 127, +- [1][0][2][0][5][13] = 127, +- [1][0][2][0][6][13] = 127, +- [1][0][2][0][9][13] = 127, +- [1][0][2][0][8][13] = 127, +- [1][0][2][0][11][13] = 127, +- [1][1][2][0][2][0] = 127, +- [1][1][2][0][1][0] = 127, +- [1][1][2][0][3][0] = 127, +- [1][1][2][0][5][0] = 127, +- [1][1][2][0][6][0] = 127, +- [1][1][2][0][9][0] = 127, +- [1][1][2][0][8][0] = 127, +- [1][1][2][0][11][0] = 127, +- [1][1][2][0][2][1] = 127, +- [1][1][2][0][1][1] = 127, +- [1][1][2][0][3][1] = 127, +- [1][1][2][0][5][1] = 127, +- [1][1][2][0][6][1] = 127, +- [1][1][2][0][9][1] = 127, +- [1][1][2][0][8][1] = 127, +- [1][1][2][0][11][1] = 127, +- [1][1][2][0][2][2] = 52, +- [1][1][2][0][1][2] = 46, +- [1][1][2][0][3][2] = 64, +- [1][1][2][0][5][2] = 52, +- [1][1][2][0][6][2] = 46, +- [1][1][2][0][9][2] = 46, +- [1][1][2][0][8][2] = 48, +- [1][1][2][0][11][2] = 46, +- [1][1][2][0][2][3] = 52, +- [1][1][2][0][1][3] = 46, +- [1][1][2][0][3][3] = 64, +- [1][1][2][0][5][3] = 52, +- [1][1][2][0][6][3] = 46, +- [1][1][2][0][9][3] = 46, +- [1][1][2][0][8][3] = 48, +- [1][1][2][0][11][3] = 46, +- [1][1][2][0][2][4] = 56, +- [1][1][2][0][1][4] = 46, +- [1][1][2][0][3][4] = 64, +- [1][1][2][0][5][4] = 56, +- [1][1][2][0][6][4] = 46, +- [1][1][2][0][9][4] = 46, +- [1][1][2][0][8][4] = 48, +- [1][1][2][0][11][4] = 46, +- [1][1][2][0][2][5] = 60, +- [1][1][2][0][1][5] = 46, +- [1][1][2][0][3][5] = 64, +- [1][1][2][0][5][5] = 60, +- [1][1][2][0][6][5] = 46, +- [1][1][2][0][9][5] = 46, +- [1][1][2][0][8][5] = 48, +- [1][1][2][0][11][5] = 46, +- [1][1][2][0][2][6] = 54, +- [1][1][2][0][1][6] = 46, +- [1][1][2][0][3][6] = 64, +- [1][1][2][0][5][6] = 52, +- [1][1][2][0][6][6] = 46, +- [1][1][2][0][9][6] = 46, +- [1][1][2][0][8][6] = 48, +- [1][1][2][0][11][6] = 46, +- [1][1][2][0][2][7] = 50, +- [1][1][2][0][1][7] = 46, +- [1][1][2][0][3][7] = 64, +- [1][1][2][0][5][7] = 48, +- [1][1][2][0][6][7] = 46, +- [1][1][2][0][9][7] = 46, +- [1][1][2][0][8][7] = 48, +- [1][1][2][0][11][7] = 46, +- [1][1][2][0][2][8] = 50, +- [1][1][2][0][1][8] = 46, +- [1][1][2][0][3][8] = 64, +- [1][1][2][0][5][8] = 48, +- [1][1][2][0][6][8] = 46, +- [1][1][2][0][9][8] = 46, +- [1][1][2][0][8][8] = 48, +- [1][1][2][0][11][8] = 46, +- [1][1][2][0][2][9] = 38, +- [1][1][2][0][1][9] = 46, +- [1][1][2][0][3][9] = 64, +- [1][1][2][0][5][9] = 38, +- [1][1][2][0][6][9] = 46, +- [1][1][2][0][9][9] = 46, +- [1][1][2][0][8][9] = 48, +- [1][1][2][0][11][9] = 46, +- [1][1][2][0][2][10] = 36, +- [1][1][2][0][1][10] = 46, +- [1][1][2][0][3][10] = 64, +- [1][1][2][0][5][10] = 36, +- [1][1][2][0][6][10] = 46, +- [1][1][2][0][9][10] = 46, +- [1][1][2][0][8][10] = 48, +- [1][1][2][0][11][10] = 46, +- [1][1][2][0][2][11] = 127, +- [1][1][2][0][1][11] = 127, +- [1][1][2][0][3][11] = 127, +- [1][1][2][0][5][11] = 127, +- [1][1][2][0][6][11] = 127, +- [1][1][2][0][9][11] = 127, +- [1][1][2][0][8][11] = 127, +- [1][1][2][0][11][11] = 127, +- [1][1][2][0][2][12] = 127, +- [1][1][2][0][1][12] = 127, +- [1][1][2][0][3][12] = 127, +- [1][1][2][0][5][12] = 127, +- [1][1][2][0][6][12] = 127, +- [1][1][2][0][9][12] = 127, +- [1][1][2][0][8][12] = 127, +- [1][1][2][0][11][12] = 127, +- [1][1][2][0][2][13] = 127, +- [1][1][2][0][1][13] = 127, +- [1][1][2][0][3][13] = 127, +- [1][1][2][0][5][13] = 127, +- [1][1][2][0][6][13] = 127, +- [1][1][2][0][9][13] = 127, +- [1][1][2][0][8][13] = 127, +- [1][1][2][0][11][13] = 127, +- [1][1][2][1][2][0] = 127, +- [1][1][2][1][1][0] = 127, +- [1][1][2][1][3][0] = 127, +- [1][1][2][1][5][0] = 127, +- [1][1][2][1][6][0] = 127, +- [1][1][2][1][9][0] = 127, +- [1][1][2][1][8][0] = 127, +- [1][1][2][1][11][0] = 127, +- [1][1][2][1][2][1] = 127, +- [1][1][2][1][1][1] = 127, +- [1][1][2][1][3][1] = 127, +- [1][1][2][1][5][1] = 127, +- [1][1][2][1][6][1] = 127, +- [1][1][2][1][9][1] = 127, +- [1][1][2][1][8][1] = 127, +- [1][1][2][1][11][1] = 127, +- [1][1][2][1][2][2] = 52, +- [1][1][2][1][1][2] = 34, +- [1][1][2][1][3][2] = 64, +- [1][1][2][1][5][2] = 52, +- [1][1][2][1][6][2] = 34, +- [1][1][2][1][9][2] = 34, +- [1][1][2][1][8][2] = 36, +- [1][1][2][1][11][2] = 34, +- [1][1][2][1][2][3] = 52, +- [1][1][2][1][1][3] = 34, +- [1][1][2][1][3][3] = 64, +- [1][1][2][1][5][3] = 52, +- [1][1][2][1][6][3] = 34, +- [1][1][2][1][9][3] = 34, +- [1][1][2][1][8][3] = 36, +- [1][1][2][1][11][3] = 34, +- [1][1][2][1][2][4] = 56, +- [1][1][2][1][1][4] = 34, +- [1][1][2][1][3][4] = 64, +- [1][1][2][1][5][4] = 56, +- [1][1][2][1][6][4] = 34, +- [1][1][2][1][9][4] = 34, +- [1][1][2][1][8][4] = 36, +- [1][1][2][1][11][4] = 34, +- [1][1][2][1][2][5] = 60, +- [1][1][2][1][1][5] = 34, +- [1][1][2][1][3][5] = 64, +- [1][1][2][1][5][5] = 60, +- [1][1][2][1][6][5] = 34, +- [1][1][2][1][9][5] = 34, +- [1][1][2][1][8][5] = 36, +- [1][1][2][1][11][5] = 34, +- [1][1][2][1][2][6] = 54, +- [1][1][2][1][1][6] = 34, +- [1][1][2][1][3][6] = 64, +- [1][1][2][1][5][6] = 52, +- [1][1][2][1][6][6] = 34, +- [1][1][2][1][9][6] = 34, +- [1][1][2][1][8][6] = 36, +- [1][1][2][1][11][6] = 34, +- [1][1][2][1][2][7] = 50, +- [1][1][2][1][1][7] = 34, +- [1][1][2][1][3][7] = 64, +- [1][1][2][1][5][7] = 48, +- [1][1][2][1][6][7] = 34, +- [1][1][2][1][9][7] = 34, +- [1][1][2][1][8][7] = 36, +- [1][1][2][1][11][7] = 34, +- [1][1][2][1][2][8] = 50, +- [1][1][2][1][1][8] = 34, +- [1][1][2][1][3][8] = 64, +- [1][1][2][1][5][8] = 48, +- [1][1][2][1][6][8] = 34, +- [1][1][2][1][9][8] = 34, +- [1][1][2][1][8][8] = 36, +- [1][1][2][1][11][8] = 34, +- [1][1][2][1][2][9] = 38, +- [1][1][2][1][1][9] = 34, +- [1][1][2][1][3][9] = 64, +- [1][1][2][1][5][9] = 38, +- [1][1][2][1][6][9] = 34, +- [1][1][2][1][9][9] = 34, +- [1][1][2][1][8][9] = 36, +- [1][1][2][1][11][9] = 34, +- [1][1][2][1][2][10] = 36, +- [1][1][2][1][1][10] = 34, +- [1][1][2][1][3][10] = 64, +- [1][1][2][1][5][10] = 36, +- [1][1][2][1][6][10] = 34, +- [1][1][2][1][9][10] = 34, +- [1][1][2][1][8][10] = 36, +- [1][1][2][1][11][10] = 34, +- [1][1][2][1][2][11] = 127, +- [1][1][2][1][1][11] = 127, +- [1][1][2][1][3][11] = 127, +- [1][1][2][1][5][11] = 127, +- [1][1][2][1][6][11] = 127, +- [1][1][2][1][9][11] = 127, +- [1][1][2][1][8][11] = 127, +- [1][1][2][1][11][11] = 127, +- [1][1][2][1][2][12] = 127, +- [1][1][2][1][1][12] = 127, +- [1][1][2][1][3][12] = 127, +- [1][1][2][1][5][12] = 127, +- [1][1][2][1][6][12] = 127, +- [1][1][2][1][9][12] = 127, +- [1][1][2][1][8][12] = 127, +- [1][1][2][1][11][12] = 127, +- [1][1][2][1][2][13] = 127, +- [1][1][2][1][1][13] = 127, +- [1][1][2][1][3][13] = 127, +- [1][1][2][1][5][13] = 127, +- [1][1][2][1][6][13] = 127, +- [1][1][2][1][9][13] = 127, +- [1][1][2][1][8][13] = 127, +- [1][1][2][1][11][13] = 127, ++ [0][0][0][0][RTW89_WW][0] = 56, ++ [0][0][0][0][RTW89_WW][1] = 56, ++ [0][0][0][0][RTW89_WW][2] = 56, ++ [0][0][0][0][RTW89_WW][3] = 56, ++ [0][0][0][0][RTW89_WW][4] = 56, ++ [0][0][0][0][RTW89_WW][5] = 56, ++ [0][0][0][0][RTW89_WW][6] = 56, ++ [0][0][0][0][RTW89_WW][7] = 56, ++ [0][0][0][0][RTW89_WW][8] = 56, ++ [0][0][0][0][RTW89_WW][9] = 56, ++ [0][0][0][0][RTW89_WW][10] = 56, ++ [0][0][0][0][RTW89_WW][11] = 56, ++ [0][0][0][0][RTW89_WW][12] = 48, ++ [0][0][0][0][RTW89_WW][13] = 76, ++ [0][1][0][0][RTW89_WW][0] = 44, ++ [0][1][0][0][RTW89_WW][1] = 44, ++ [0][1][0][0][RTW89_WW][2] = 44, ++ [0][1][0][0][RTW89_WW][3] = 44, ++ [0][1][0][0][RTW89_WW][4] = 44, ++ [0][1][0][0][RTW89_WW][5] = 44, ++ [0][1][0][0][RTW89_WW][6] = 44, ++ [0][1][0][0][RTW89_WW][7] = 44, ++ [0][1][0][0][RTW89_WW][8] = 44, ++ [0][1][0][0][RTW89_WW][9] = 44, ++ [0][1][0][0][RTW89_WW][10] = 44, ++ [0][1][0][0][RTW89_WW][11] = 44, ++ [0][1][0][0][RTW89_WW][12] = 38, ++ [0][1][0][0][RTW89_WW][13] = 64, ++ [1][0][0][0][RTW89_WW][0] = 0, ++ [1][0][0][0][RTW89_WW][1] = 0, ++ [1][0][0][0][RTW89_WW][2] = 58, ++ [1][0][0][0][RTW89_WW][3] = 58, ++ [1][0][0][0][RTW89_WW][4] = 58, ++ [1][0][0][0][RTW89_WW][5] = 58, ++ [1][0][0][0][RTW89_WW][6] = 46, ++ [1][0][0][0][RTW89_WW][7] = 46, ++ [1][0][0][0][RTW89_WW][8] = 46, ++ [1][0][0][0][RTW89_WW][9] = 32, ++ [1][0][0][0][RTW89_WW][10] = 32, ++ [1][0][0][0][RTW89_WW][11] = 0, ++ [1][0][0][0][RTW89_WW][12] = 0, ++ [1][0][0][0][RTW89_WW][13] = 0, ++ [1][1][0][0][RTW89_WW][0] = 0, ++ [1][1][0][0][RTW89_WW][1] = 0, ++ [1][1][0][0][RTW89_WW][2] = 46, ++ [1][1][0][0][RTW89_WW][3] = 46, ++ [1][1][0][0][RTW89_WW][4] = 46, ++ [1][1][0][0][RTW89_WW][5] = 46, ++ [1][1][0][0][RTW89_WW][6] = 46, ++ [1][1][0][0][RTW89_WW][7] = 46, ++ [1][1][0][0][RTW89_WW][8] = 46, ++ [1][1][0][0][RTW89_WW][9] = 24, ++ [1][1][0][0][RTW89_WW][10] = 24, ++ [1][1][0][0][RTW89_WW][11] = 0, ++ [1][1][0][0][RTW89_WW][12] = 0, ++ [1][1][0][0][RTW89_WW][13] = 0, ++ [0][0][1][0][RTW89_WW][0] = 58, ++ [0][0][1][0][RTW89_WW][1] = 58, ++ [0][0][1][0][RTW89_WW][2] = 58, ++ [0][0][1][0][RTW89_WW][3] = 58, ++ [0][0][1][0][RTW89_WW][4] = 58, ++ [0][0][1][0][RTW89_WW][5] = 58, ++ [0][0][1][0][RTW89_WW][6] = 58, ++ [0][0][1][0][RTW89_WW][7] = 58, ++ [0][0][1][0][RTW89_WW][8] = 58, ++ [0][0][1][0][RTW89_WW][9] = 58, ++ [0][0][1][0][RTW89_WW][10] = 58, ++ [0][0][1][0][RTW89_WW][11] = 56, ++ [0][0][1][0][RTW89_WW][12] = 52, ++ [0][0][1][0][RTW89_WW][13] = 0, ++ [0][1][1][0][RTW89_WW][0] = 46, ++ [0][1][1][0][RTW89_WW][1] = 46, ++ [0][1][1][0][RTW89_WW][2] = 46, ++ [0][1][1][0][RTW89_WW][3] = 46, ++ [0][1][1][0][RTW89_WW][4] = 46, ++ [0][1][1][0][RTW89_WW][5] = 46, ++ [0][1][1][0][RTW89_WW][6] = 46, ++ [0][1][1][0][RTW89_WW][7] = 46, ++ [0][1][1][0][RTW89_WW][8] = 46, ++ [0][1][1][0][RTW89_WW][9] = 46, ++ [0][1][1][0][RTW89_WW][10] = 46, ++ [0][1][1][0][RTW89_WW][11] = 42, ++ [0][1][1][0][RTW89_WW][12] = 40, ++ [0][1][1][0][RTW89_WW][13] = 0, ++ [0][0][2][0][RTW89_WW][0] = 58, ++ [0][0][2][0][RTW89_WW][1] = 58, ++ [0][0][2][0][RTW89_WW][2] = 58, ++ [0][0][2][0][RTW89_WW][3] = 58, ++ [0][0][2][0][RTW89_WW][4] = 58, ++ [0][0][2][0][RTW89_WW][5] = 58, ++ [0][0][2][0][RTW89_WW][6] = 58, ++ [0][0][2][0][RTW89_WW][7] = 58, ++ [0][0][2][0][RTW89_WW][8] = 58, ++ [0][0][2][0][RTW89_WW][9] = 58, ++ [0][0][2][0][RTW89_WW][10] = 58, ++ [0][0][2][0][RTW89_WW][11] = 54, ++ [0][0][2][0][RTW89_WW][12] = 50, ++ [0][0][2][0][RTW89_WW][13] = 0, ++ [0][1][2][0][RTW89_WW][0] = 46, ++ [0][1][2][0][RTW89_WW][1] = 46, ++ [0][1][2][0][RTW89_WW][2] = 46, ++ [0][1][2][0][RTW89_WW][3] = 46, ++ [0][1][2][0][RTW89_WW][4] = 46, ++ [0][1][2][0][RTW89_WW][5] = 46, ++ [0][1][2][0][RTW89_WW][6] = 46, ++ [0][1][2][0][RTW89_WW][7] = 46, ++ [0][1][2][0][RTW89_WW][8] = 46, ++ [0][1][2][0][RTW89_WW][9] = 46, ++ [0][1][2][0][RTW89_WW][10] = 46, ++ [0][1][2][0][RTW89_WW][11] = 42, ++ [0][1][2][0][RTW89_WW][12] = 40, ++ [0][1][2][0][RTW89_WW][13] = 0, ++ [0][1][2][1][RTW89_WW][0] = 34, ++ [0][1][2][1][RTW89_WW][1] = 34, ++ [0][1][2][1][RTW89_WW][2] = 34, ++ [0][1][2][1][RTW89_WW][3] = 34, ++ [0][1][2][1][RTW89_WW][4] = 34, ++ [0][1][2][1][RTW89_WW][5] = 34, ++ [0][1][2][1][RTW89_WW][6] = 34, ++ [0][1][2][1][RTW89_WW][7] = 34, ++ [0][1][2][1][RTW89_WW][8] = 34, ++ [0][1][2][1][RTW89_WW][9] = 34, ++ [0][1][2][1][RTW89_WW][10] = 34, ++ [0][1][2][1][RTW89_WW][11] = 34, ++ [0][1][2][1][RTW89_WW][12] = 34, ++ [0][1][2][1][RTW89_WW][13] = 0, ++ [1][0][2][0][RTW89_WW][0] = 0, ++ [1][0][2][0][RTW89_WW][1] = 0, ++ [1][0][2][0][RTW89_WW][2] = 56, ++ [1][0][2][0][RTW89_WW][3] = 56, ++ [1][0][2][0][RTW89_WW][4] = 58, ++ [1][0][2][0][RTW89_WW][5] = 58, ++ [1][0][2][0][RTW89_WW][6] = 54, ++ [1][0][2][0][RTW89_WW][7] = 50, ++ [1][0][2][0][RTW89_WW][8] = 50, ++ [1][0][2][0][RTW89_WW][9] = 42, ++ [1][0][2][0][RTW89_WW][10] = 40, ++ [1][0][2][0][RTW89_WW][11] = 0, ++ [1][0][2][0][RTW89_WW][12] = 0, ++ [1][0][2][0][RTW89_WW][13] = 0, ++ [1][1][2][0][RTW89_WW][0] = 0, ++ [1][1][2][0][RTW89_WW][1] = 0, ++ [1][1][2][0][RTW89_WW][2] = 46, ++ [1][1][2][0][RTW89_WW][3] = 46, ++ [1][1][2][0][RTW89_WW][4] = 46, ++ [1][1][2][0][RTW89_WW][5] = 46, ++ [1][1][2][0][RTW89_WW][6] = 46, ++ [1][1][2][0][RTW89_WW][7] = 46, ++ [1][1][2][0][RTW89_WW][8] = 46, ++ [1][1][2][0][RTW89_WW][9] = 38, ++ [1][1][2][0][RTW89_WW][10] = 36, ++ [1][1][2][0][RTW89_WW][11] = 0, ++ [1][1][2][0][RTW89_WW][12] = 0, ++ [1][1][2][0][RTW89_WW][13] = 0, ++ [1][1][2][1][RTW89_WW][0] = 0, ++ [1][1][2][1][RTW89_WW][1] = 0, ++ [1][1][2][1][RTW89_WW][2] = 34, ++ [1][1][2][1][RTW89_WW][3] = 34, ++ [1][1][2][1][RTW89_WW][4] = 34, ++ [1][1][2][1][RTW89_WW][5] = 34, ++ [1][1][2][1][RTW89_WW][6] = 34, ++ [1][1][2][1][RTW89_WW][7] = 34, ++ [1][1][2][1][RTW89_WW][8] = 34, ++ [1][1][2][1][RTW89_WW][9] = 34, ++ [1][1][2][1][RTW89_WW][10] = 34, ++ [1][1][2][1][RTW89_WW][11] = 0, ++ [1][1][2][1][RTW89_WW][12] = 0, ++ [1][1][2][1][RTW89_WW][13] = 0, ++ [0][0][0][0][RTW89_FCC][0] = 76, ++ [0][0][0][0][RTW89_ETSI][0] = 56, ++ [0][0][0][0][RTW89_MKK][0] = 68, ++ [0][0][0][0][RTW89_IC][0] = 76, ++ [0][0][0][0][RTW89_KCC][0] = 56, ++ [0][0][0][0][RTW89_ACMA][0] = 56, ++ [0][0][0][0][RTW89_CHILE][0] = 60, ++ [0][0][0][0][RTW89_UKRAINE][0] = 56, ++ [0][0][0][0][RTW89_FCC][1] = 76, ++ [0][0][0][0][RTW89_ETSI][1] = 56, ++ [0][0][0][0][RTW89_MKK][1] = 68, ++ [0][0][0][0][RTW89_IC][1] = 76, ++ [0][0][0][0][RTW89_KCC][1] = 56, ++ [0][0][0][0][RTW89_ACMA][1] = 56, ++ [0][0][0][0][RTW89_CHILE][1] = 60, ++ [0][0][0][0][RTW89_UKRAINE][1] = 56, ++ [0][0][0][0][RTW89_FCC][2] = 76, ++ [0][0][0][0][RTW89_ETSI][2] = 56, ++ [0][0][0][0][RTW89_MKK][2] = 68, ++ [0][0][0][0][RTW89_IC][2] = 76, ++ [0][0][0][0][RTW89_KCC][2] = 56, ++ [0][0][0][0][RTW89_ACMA][2] = 56, ++ [0][0][0][0][RTW89_CHILE][2] = 60, ++ [0][0][0][0][RTW89_UKRAINE][2] = 56, ++ [0][0][0][0][RTW89_FCC][3] = 76, ++ [0][0][0][0][RTW89_ETSI][3] = 56, ++ [0][0][0][0][RTW89_MKK][3] = 68, ++ [0][0][0][0][RTW89_IC][3] = 76, ++ [0][0][0][0][RTW89_KCC][3] = 56, ++ [0][0][0][0][RTW89_ACMA][3] = 56, ++ [0][0][0][0][RTW89_CHILE][3] = 60, ++ [0][0][0][0][RTW89_UKRAINE][3] = 56, ++ [0][0][0][0][RTW89_FCC][4] = 76, ++ [0][0][0][0][RTW89_ETSI][4] = 56, ++ [0][0][0][0][RTW89_MKK][4] = 68, ++ [0][0][0][0][RTW89_IC][4] = 76, ++ [0][0][0][0][RTW89_KCC][4] = 56, ++ [0][0][0][0][RTW89_ACMA][4] = 56, ++ [0][0][0][0][RTW89_CHILE][4] = 60, ++ [0][0][0][0][RTW89_UKRAINE][4] = 56, ++ [0][0][0][0][RTW89_FCC][5] = 76, ++ [0][0][0][0][RTW89_ETSI][5] = 56, ++ [0][0][0][0][RTW89_MKK][5] = 68, ++ [0][0][0][0][RTW89_IC][5] = 76, ++ [0][0][0][0][RTW89_KCC][5] = 56, ++ [0][0][0][0][RTW89_ACMA][5] = 56, ++ [0][0][0][0][RTW89_CHILE][5] = 60, ++ [0][0][0][0][RTW89_UKRAINE][5] = 56, ++ [0][0][0][0][RTW89_FCC][6] = 76, ++ [0][0][0][0][RTW89_ETSI][6] = 56, ++ [0][0][0][0][RTW89_MKK][6] = 68, ++ [0][0][0][0][RTW89_IC][6] = 76, ++ [0][0][0][0][RTW89_KCC][6] = 56, ++ [0][0][0][0][RTW89_ACMA][6] = 56, ++ [0][0][0][0][RTW89_CHILE][6] = 60, ++ [0][0][0][0][RTW89_UKRAINE][6] = 56, ++ [0][0][0][0][RTW89_FCC][7] = 76, ++ [0][0][0][0][RTW89_ETSI][7] = 56, ++ [0][0][0][0][RTW89_MKK][7] = 68, ++ [0][0][0][0][RTW89_IC][7] = 76, ++ [0][0][0][0][RTW89_KCC][7] = 56, ++ [0][0][0][0][RTW89_ACMA][7] = 56, ++ [0][0][0][0][RTW89_CHILE][7] = 60, ++ [0][0][0][0][RTW89_UKRAINE][7] = 56, ++ [0][0][0][0][RTW89_FCC][8] = 76, ++ [0][0][0][0][RTW89_ETSI][8] = 56, ++ [0][0][0][0][RTW89_MKK][8] = 68, ++ [0][0][0][0][RTW89_IC][8] = 76, ++ [0][0][0][0][RTW89_KCC][8] = 56, ++ [0][0][0][0][RTW89_ACMA][8] = 56, ++ [0][0][0][0][RTW89_CHILE][8] = 60, ++ [0][0][0][0][RTW89_UKRAINE][8] = 56, ++ [0][0][0][0][RTW89_FCC][9] = 76, ++ [0][0][0][0][RTW89_ETSI][9] = 56, ++ [0][0][0][0][RTW89_MKK][9] = 68, ++ [0][0][0][0][RTW89_IC][9] = 76, ++ [0][0][0][0][RTW89_KCC][9] = 56, ++ [0][0][0][0][RTW89_ACMA][9] = 56, ++ [0][0][0][0][RTW89_CHILE][9] = 60, ++ [0][0][0][0][RTW89_UKRAINE][9] = 56, ++ [0][0][0][0][RTW89_FCC][10] = 76, ++ [0][0][0][0][RTW89_ETSI][10] = 56, ++ [0][0][0][0][RTW89_MKK][10] = 68, ++ [0][0][0][0][RTW89_IC][10] = 76, ++ [0][0][0][0][RTW89_KCC][10] = 56, ++ [0][0][0][0][RTW89_ACMA][10] = 56, ++ [0][0][0][0][RTW89_CHILE][10] = 60, ++ [0][0][0][0][RTW89_UKRAINE][10] = 56, ++ [0][0][0][0][RTW89_FCC][11] = 68, ++ [0][0][0][0][RTW89_ETSI][11] = 56, ++ [0][0][0][0][RTW89_MKK][11] = 68, ++ [0][0][0][0][RTW89_IC][11] = 68, ++ [0][0][0][0][RTW89_KCC][11] = 56, ++ [0][0][0][0][RTW89_ACMA][11] = 56, ++ [0][0][0][0][RTW89_CHILE][11] = 60, ++ [0][0][0][0][RTW89_UKRAINE][11] = 56, ++ [0][0][0][0][RTW89_FCC][12] = 48, ++ [0][0][0][0][RTW89_ETSI][12] = 56, ++ [0][0][0][0][RTW89_MKK][12] = 68, ++ [0][0][0][0][RTW89_IC][12] = 48, ++ [0][0][0][0][RTW89_KCC][12] = 56, ++ [0][0][0][0][RTW89_ACMA][12] = 56, ++ [0][0][0][0][RTW89_CHILE][12] = 60, ++ [0][0][0][0][RTW89_UKRAINE][12] = 56, ++ [0][0][0][0][RTW89_FCC][13] = 127, ++ [0][0][0][0][RTW89_ETSI][13] = 127, ++ [0][0][0][0][RTW89_MKK][13] = 76, ++ [0][0][0][0][RTW89_IC][13] = 127, ++ [0][0][0][0][RTW89_KCC][13] = 127, ++ [0][0][0][0][RTW89_ACMA][13] = 127, ++ [0][0][0][0][RTW89_CHILE][13] = 127, ++ [0][0][0][0][RTW89_UKRAINE][13] = 127, ++ [0][1][0][0][RTW89_FCC][0] = 74, ++ [0][1][0][0][RTW89_ETSI][0] = 44, ++ [0][1][0][0][RTW89_MKK][0] = 56, ++ [0][1][0][0][RTW89_IC][0] = 74, ++ [0][1][0][0][RTW89_KCC][0] = 44, ++ [0][1][0][0][RTW89_ACMA][0] = 44, ++ [0][1][0][0][RTW89_CHILE][0] = 48, ++ [0][1][0][0][RTW89_UKRAINE][0] = 44, ++ [0][1][0][0][RTW89_FCC][1] = 76, ++ [0][1][0][0][RTW89_ETSI][1] = 44, ++ [0][1][0][0][RTW89_MKK][1] = 56, ++ [0][1][0][0][RTW89_IC][1] = 76, ++ [0][1][0][0][RTW89_KCC][1] = 44, ++ [0][1][0][0][RTW89_ACMA][1] = 44, ++ [0][1][0][0][RTW89_CHILE][1] = 48, ++ [0][1][0][0][RTW89_UKRAINE][1] = 44, ++ [0][1][0][0][RTW89_FCC][2] = 76, ++ [0][1][0][0][RTW89_ETSI][2] = 44, ++ [0][1][0][0][RTW89_MKK][2] = 56, ++ [0][1][0][0][RTW89_IC][2] = 76, ++ [0][1][0][0][RTW89_KCC][2] = 44, ++ [0][1][0][0][RTW89_ACMA][2] = 44, ++ [0][1][0][0][RTW89_CHILE][2] = 48, ++ [0][1][0][0][RTW89_UKRAINE][2] = 44, ++ [0][1][0][0][RTW89_FCC][3] = 76, ++ [0][1][0][0][RTW89_ETSI][3] = 44, ++ [0][1][0][0][RTW89_MKK][3] = 56, ++ [0][1][0][0][RTW89_IC][3] = 76, ++ [0][1][0][0][RTW89_KCC][3] = 44, ++ [0][1][0][0][RTW89_ACMA][3] = 44, ++ [0][1][0][0][RTW89_CHILE][3] = 48, ++ [0][1][0][0][RTW89_UKRAINE][3] = 44, ++ [0][1][0][0][RTW89_FCC][4] = 76, ++ [0][1][0][0][RTW89_ETSI][4] = 44, ++ [0][1][0][0][RTW89_MKK][4] = 56, ++ [0][1][0][0][RTW89_IC][4] = 76, ++ [0][1][0][0][RTW89_KCC][4] = 44, ++ [0][1][0][0][RTW89_ACMA][4] = 44, ++ [0][1][0][0][RTW89_CHILE][4] = 48, ++ [0][1][0][0][RTW89_UKRAINE][4] = 44, ++ [0][1][0][0][RTW89_FCC][5] = 76, ++ [0][1][0][0][RTW89_ETSI][5] = 44, ++ [0][1][0][0][RTW89_MKK][5] = 56, ++ [0][1][0][0][RTW89_IC][5] = 76, ++ [0][1][0][0][RTW89_KCC][5] = 44, ++ [0][1][0][0][RTW89_ACMA][5] = 44, ++ [0][1][0][0][RTW89_CHILE][5] = 48, ++ [0][1][0][0][RTW89_UKRAINE][5] = 44, ++ [0][1][0][0][RTW89_FCC][6] = 76, ++ [0][1][0][0][RTW89_ETSI][6] = 44, ++ [0][1][0][0][RTW89_MKK][6] = 56, ++ [0][1][0][0][RTW89_IC][6] = 76, ++ [0][1][0][0][RTW89_KCC][6] = 44, ++ [0][1][0][0][RTW89_ACMA][6] = 44, ++ [0][1][0][0][RTW89_CHILE][6] = 48, ++ [0][1][0][0][RTW89_UKRAINE][6] = 44, ++ [0][1][0][0][RTW89_FCC][7] = 76, ++ [0][1][0][0][RTW89_ETSI][7] = 44, ++ [0][1][0][0][RTW89_MKK][7] = 56, ++ [0][1][0][0][RTW89_IC][7] = 76, ++ [0][1][0][0][RTW89_KCC][7] = 44, ++ [0][1][0][0][RTW89_ACMA][7] = 44, ++ [0][1][0][0][RTW89_CHILE][7] = 48, ++ [0][1][0][0][RTW89_UKRAINE][7] = 44, ++ [0][1][0][0][RTW89_FCC][8] = 76, ++ [0][1][0][0][RTW89_ETSI][8] = 44, ++ [0][1][0][0][RTW89_MKK][8] = 56, ++ [0][1][0][0][RTW89_IC][8] = 76, ++ [0][1][0][0][RTW89_KCC][8] = 44, ++ [0][1][0][0][RTW89_ACMA][8] = 44, ++ [0][1][0][0][RTW89_CHILE][8] = 48, ++ [0][1][0][0][RTW89_UKRAINE][8] = 44, ++ [0][1][0][0][RTW89_FCC][9] = 76, ++ [0][1][0][0][RTW89_ETSI][9] = 44, ++ [0][1][0][0][RTW89_MKK][9] = 56, ++ [0][1][0][0][RTW89_IC][9] = 76, ++ [0][1][0][0][RTW89_KCC][9] = 44, ++ [0][1][0][0][RTW89_ACMA][9] = 44, ++ [0][1][0][0][RTW89_CHILE][9] = 48, ++ [0][1][0][0][RTW89_UKRAINE][9] = 44, ++ [0][1][0][0][RTW89_FCC][10] = 62, ++ [0][1][0][0][RTW89_ETSI][10] = 44, ++ [0][1][0][0][RTW89_MKK][10] = 56, ++ [0][1][0][0][RTW89_IC][10] = 62, ++ [0][1][0][0][RTW89_KCC][10] = 44, ++ [0][1][0][0][RTW89_ACMA][10] = 44, ++ [0][1][0][0][RTW89_CHILE][10] = 48, ++ [0][1][0][0][RTW89_UKRAINE][10] = 44, ++ [0][1][0][0][RTW89_FCC][11] = 52, ++ [0][1][0][0][RTW89_ETSI][11] = 44, ++ [0][1][0][0][RTW89_MKK][11] = 56, ++ [0][1][0][0][RTW89_IC][11] = 52, ++ [0][1][0][0][RTW89_KCC][11] = 44, ++ [0][1][0][0][RTW89_ACMA][11] = 44, ++ [0][1][0][0][RTW89_CHILE][11] = 48, ++ [0][1][0][0][RTW89_UKRAINE][11] = 44, ++ [0][1][0][0][RTW89_FCC][12] = 38, ++ [0][1][0][0][RTW89_ETSI][12] = 44, ++ [0][1][0][0][RTW89_MKK][12] = 56, ++ [0][1][0][0][RTW89_IC][12] = 38, ++ [0][1][0][0][RTW89_KCC][12] = 44, ++ [0][1][0][0][RTW89_ACMA][12] = 44, ++ [0][1][0][0][RTW89_CHILE][12] = 48, ++ [0][1][0][0][RTW89_UKRAINE][12] = 44, ++ [0][1][0][0][RTW89_FCC][13] = 127, ++ [0][1][0][0][RTW89_ETSI][13] = 127, ++ [0][1][0][0][RTW89_MKK][13] = 64, ++ [0][1][0][0][RTW89_IC][13] = 127, ++ [0][1][0][0][RTW89_KCC][13] = 127, ++ [0][1][0][0][RTW89_ACMA][13] = 127, ++ [0][1][0][0][RTW89_CHILE][13] = 127, ++ [0][1][0][0][RTW89_UKRAINE][13] = 127, ++ [1][0][0][0][RTW89_FCC][0] = 127, ++ [1][0][0][0][RTW89_ETSI][0] = 127, ++ [1][0][0][0][RTW89_MKK][0] = 127, ++ [1][0][0][0][RTW89_IC][0] = 127, ++ [1][0][0][0][RTW89_KCC][0] = 127, ++ [1][0][0][0][RTW89_ACMA][0] = 127, ++ [1][0][0][0][RTW89_CHILE][0] = 127, ++ [1][0][0][0][RTW89_UKRAINE][0] = 127, ++ [1][0][0][0][RTW89_FCC][1] = 127, ++ [1][0][0][0][RTW89_ETSI][1] = 127, ++ [1][0][0][0][RTW89_MKK][1] = 127, ++ [1][0][0][0][RTW89_IC][1] = 127, ++ [1][0][0][0][RTW89_KCC][1] = 127, ++ [1][0][0][0][RTW89_ACMA][1] = 127, ++ [1][0][0][0][RTW89_CHILE][1] = 127, ++ [1][0][0][0][RTW89_UKRAINE][1] = 127, ++ [1][0][0][0][RTW89_FCC][2] = 60, ++ [1][0][0][0][RTW89_ETSI][2] = 58, ++ [1][0][0][0][RTW89_MKK][2] = 68, ++ [1][0][0][0][RTW89_IC][2] = 60, ++ [1][0][0][0][RTW89_KCC][2] = 58, ++ [1][0][0][0][RTW89_ACMA][2] = 58, ++ [1][0][0][0][RTW89_CHILE][2] = 60, ++ [1][0][0][0][RTW89_UKRAINE][2] = 58, ++ [1][0][0][0][RTW89_FCC][3] = 60, ++ [1][0][0][0][RTW89_ETSI][3] = 58, ++ [1][0][0][0][RTW89_MKK][3] = 68, ++ [1][0][0][0][RTW89_IC][3] = 60, ++ [1][0][0][0][RTW89_KCC][3] = 58, ++ [1][0][0][0][RTW89_ACMA][3] = 58, ++ [1][0][0][0][RTW89_CHILE][3] = 60, ++ [1][0][0][0][RTW89_UKRAINE][3] = 58, ++ [1][0][0][0][RTW89_FCC][4] = 60, ++ [1][0][0][0][RTW89_ETSI][4] = 58, ++ [1][0][0][0][RTW89_MKK][4] = 68, ++ [1][0][0][0][RTW89_IC][4] = 60, ++ [1][0][0][0][RTW89_KCC][4] = 58, ++ [1][0][0][0][RTW89_ACMA][4] = 58, ++ [1][0][0][0][RTW89_CHILE][4] = 60, ++ [1][0][0][0][RTW89_UKRAINE][4] = 58, ++ [1][0][0][0][RTW89_FCC][5] = 60, ++ [1][0][0][0][RTW89_ETSI][5] = 58, ++ [1][0][0][0][RTW89_MKK][5] = 68, ++ [1][0][0][0][RTW89_IC][5] = 60, ++ [1][0][0][0][RTW89_KCC][5] = 58, ++ [1][0][0][0][RTW89_ACMA][5] = 58, ++ [1][0][0][0][RTW89_CHILE][5] = 60, ++ [1][0][0][0][RTW89_UKRAINE][5] = 58, ++ [1][0][0][0][RTW89_FCC][6] = 46, ++ [1][0][0][0][RTW89_ETSI][6] = 58, ++ [1][0][0][0][RTW89_MKK][6] = 68, ++ [1][0][0][0][RTW89_IC][6] = 46, ++ [1][0][0][0][RTW89_KCC][6] = 58, ++ [1][0][0][0][RTW89_ACMA][6] = 58, ++ [1][0][0][0][RTW89_CHILE][6] = 60, ++ [1][0][0][0][RTW89_UKRAINE][6] = 58, ++ [1][0][0][0][RTW89_FCC][7] = 46, ++ [1][0][0][0][RTW89_ETSI][7] = 58, ++ [1][0][0][0][RTW89_MKK][7] = 68, ++ [1][0][0][0][RTW89_IC][7] = 46, ++ [1][0][0][0][RTW89_KCC][7] = 58, ++ [1][0][0][0][RTW89_ACMA][7] = 58, ++ [1][0][0][0][RTW89_CHILE][7] = 60, ++ [1][0][0][0][RTW89_UKRAINE][7] = 58, ++ [1][0][0][0][RTW89_FCC][8] = 46, ++ [1][0][0][0][RTW89_ETSI][8] = 58, ++ [1][0][0][0][RTW89_MKK][8] = 68, ++ [1][0][0][0][RTW89_IC][8] = 46, ++ [1][0][0][0][RTW89_KCC][8] = 58, ++ [1][0][0][0][RTW89_ACMA][8] = 58, ++ [1][0][0][0][RTW89_CHILE][8] = 60, ++ [1][0][0][0][RTW89_UKRAINE][8] = 58, ++ [1][0][0][0][RTW89_FCC][9] = 32, ++ [1][0][0][0][RTW89_ETSI][9] = 58, ++ [1][0][0][0][RTW89_MKK][9] = 68, ++ [1][0][0][0][RTW89_IC][9] = 32, ++ [1][0][0][0][RTW89_KCC][9] = 58, ++ [1][0][0][0][RTW89_ACMA][9] = 58, ++ [1][0][0][0][RTW89_CHILE][9] = 60, ++ [1][0][0][0][RTW89_UKRAINE][9] = 58, ++ [1][0][0][0][RTW89_FCC][10] = 32, ++ [1][0][0][0][RTW89_ETSI][10] = 58, ++ [1][0][0][0][RTW89_MKK][10] = 68, ++ [1][0][0][0][RTW89_IC][10] = 32, ++ [1][0][0][0][RTW89_KCC][10] = 58, ++ [1][0][0][0][RTW89_ACMA][10] = 58, ++ [1][0][0][0][RTW89_CHILE][10] = 60, ++ [1][0][0][0][RTW89_UKRAINE][10] = 58, ++ [1][0][0][0][RTW89_FCC][11] = 127, ++ [1][0][0][0][RTW89_ETSI][11] = 127, ++ [1][0][0][0][RTW89_MKK][11] = 127, ++ [1][0][0][0][RTW89_IC][11] = 127, ++ [1][0][0][0][RTW89_KCC][11] = 127, ++ [1][0][0][0][RTW89_ACMA][11] = 127, ++ [1][0][0][0][RTW89_CHILE][11] = 127, ++ [1][0][0][0][RTW89_UKRAINE][11] = 127, ++ [1][0][0][0][RTW89_FCC][12] = 127, ++ [1][0][0][0][RTW89_ETSI][12] = 127, ++ [1][0][0][0][RTW89_MKK][12] = 127, ++ [1][0][0][0][RTW89_IC][12] = 127, ++ [1][0][0][0][RTW89_KCC][12] = 127, ++ [1][0][0][0][RTW89_ACMA][12] = 127, ++ [1][0][0][0][RTW89_CHILE][12] = 127, ++ [1][0][0][0][RTW89_UKRAINE][12] = 127, ++ [1][0][0][0][RTW89_FCC][13] = 127, ++ [1][0][0][0][RTW89_ETSI][13] = 127, ++ [1][0][0][0][RTW89_MKK][13] = 127, ++ [1][0][0][0][RTW89_IC][13] = 127, ++ [1][0][0][0][RTW89_KCC][13] = 127, ++ [1][0][0][0][RTW89_ACMA][13] = 127, ++ [1][0][0][0][RTW89_CHILE][13] = 127, ++ [1][0][0][0][RTW89_UKRAINE][13] = 127, ++ [1][1][0][0][RTW89_FCC][0] = 127, ++ [1][1][0][0][RTW89_ETSI][0] = 127, ++ [1][1][0][0][RTW89_MKK][0] = 127, ++ [1][1][0][0][RTW89_IC][0] = 127, ++ [1][1][0][0][RTW89_KCC][0] = 127, ++ [1][1][0][0][RTW89_ACMA][0] = 127, ++ [1][1][0][0][RTW89_CHILE][0] = 127, ++ [1][1][0][0][RTW89_UKRAINE][0] = 127, ++ [1][1][0][0][RTW89_FCC][1] = 127, ++ [1][1][0][0][RTW89_ETSI][1] = 127, ++ [1][1][0][0][RTW89_MKK][1] = 127, ++ [1][1][0][0][RTW89_IC][1] = 127, ++ [1][1][0][0][RTW89_KCC][1] = 127, ++ [1][1][0][0][RTW89_ACMA][1] = 127, ++ [1][1][0][0][RTW89_CHILE][1] = 127, ++ [1][1][0][0][RTW89_UKRAINE][1] = 127, ++ [1][1][0][0][RTW89_FCC][2] = 48, ++ [1][1][0][0][RTW89_ETSI][2] = 46, ++ [1][1][0][0][RTW89_MKK][2] = 56, ++ [1][1][0][0][RTW89_IC][2] = 48, ++ [1][1][0][0][RTW89_KCC][2] = 46, ++ [1][1][0][0][RTW89_ACMA][2] = 46, ++ [1][1][0][0][RTW89_CHILE][2] = 48, ++ [1][1][0][0][RTW89_UKRAINE][2] = 46, ++ [1][1][0][0][RTW89_FCC][3] = 48, ++ [1][1][0][0][RTW89_ETSI][3] = 46, ++ [1][1][0][0][RTW89_MKK][3] = 56, ++ [1][1][0][0][RTW89_IC][3] = 48, ++ [1][1][0][0][RTW89_KCC][3] = 46, ++ [1][1][0][0][RTW89_ACMA][3] = 46, ++ [1][1][0][0][RTW89_CHILE][3] = 48, ++ [1][1][0][0][RTW89_UKRAINE][3] = 46, ++ [1][1][0][0][RTW89_FCC][4] = 48, ++ [1][1][0][0][RTW89_ETSI][4] = 46, ++ [1][1][0][0][RTW89_MKK][4] = 56, ++ [1][1][0][0][RTW89_IC][4] = 48, ++ [1][1][0][0][RTW89_KCC][4] = 46, ++ [1][1][0][0][RTW89_ACMA][4] = 46, ++ [1][1][0][0][RTW89_CHILE][4] = 48, ++ [1][1][0][0][RTW89_UKRAINE][4] = 46, ++ [1][1][0][0][RTW89_FCC][5] = 58, ++ [1][1][0][0][RTW89_ETSI][5] = 46, ++ [1][1][0][0][RTW89_MKK][5] = 56, ++ [1][1][0][0][RTW89_IC][5] = 58, ++ [1][1][0][0][RTW89_KCC][5] = 46, ++ [1][1][0][0][RTW89_ACMA][5] = 46, ++ [1][1][0][0][RTW89_CHILE][5] = 48, ++ [1][1][0][0][RTW89_UKRAINE][5] = 46, ++ [1][1][0][0][RTW89_FCC][6] = 46, ++ [1][1][0][0][RTW89_ETSI][6] = 46, ++ [1][1][0][0][RTW89_MKK][6] = 56, ++ [1][1][0][0][RTW89_IC][6] = 46, ++ [1][1][0][0][RTW89_KCC][6] = 46, ++ [1][1][0][0][RTW89_ACMA][6] = 46, ++ [1][1][0][0][RTW89_CHILE][6] = 48, ++ [1][1][0][0][RTW89_UKRAINE][6] = 46, ++ [1][1][0][0][RTW89_FCC][7] = 46, ++ [1][1][0][0][RTW89_ETSI][7] = 46, ++ [1][1][0][0][RTW89_MKK][7] = 56, ++ [1][1][0][0][RTW89_IC][7] = 46, ++ [1][1][0][0][RTW89_KCC][7] = 46, ++ [1][1][0][0][RTW89_ACMA][7] = 46, ++ [1][1][0][0][RTW89_CHILE][7] = 48, ++ [1][1][0][0][RTW89_UKRAINE][7] = 46, ++ [1][1][0][0][RTW89_FCC][8] = 46, ++ [1][1][0][0][RTW89_ETSI][8] = 46, ++ [1][1][0][0][RTW89_MKK][8] = 56, ++ [1][1][0][0][RTW89_IC][8] = 46, ++ [1][1][0][0][RTW89_KCC][8] = 46, ++ [1][1][0][0][RTW89_ACMA][8] = 46, ++ [1][1][0][0][RTW89_CHILE][8] = 48, ++ [1][1][0][0][RTW89_UKRAINE][8] = 46, ++ [1][1][0][0][RTW89_FCC][9] = 24, ++ [1][1][0][0][RTW89_ETSI][9] = 46, ++ [1][1][0][0][RTW89_MKK][9] = 56, ++ [1][1][0][0][RTW89_IC][9] = 24, ++ [1][1][0][0][RTW89_KCC][9] = 46, ++ [1][1][0][0][RTW89_ACMA][9] = 46, ++ [1][1][0][0][RTW89_CHILE][9] = 48, ++ [1][1][0][0][RTW89_UKRAINE][9] = 46, ++ [1][1][0][0][RTW89_FCC][10] = 24, ++ [1][1][0][0][RTW89_ETSI][10] = 46, ++ [1][1][0][0][RTW89_MKK][10] = 56, ++ [1][1][0][0][RTW89_IC][10] = 24, ++ [1][1][0][0][RTW89_KCC][10] = 46, ++ [1][1][0][0][RTW89_ACMA][10] = 46, ++ [1][1][0][0][RTW89_CHILE][10] = 48, ++ [1][1][0][0][RTW89_UKRAINE][10] = 46, ++ [1][1][0][0][RTW89_FCC][11] = 127, ++ [1][1][0][0][RTW89_ETSI][11] = 127, ++ [1][1][0][0][RTW89_MKK][11] = 127, ++ [1][1][0][0][RTW89_IC][11] = 127, ++ [1][1][0][0][RTW89_KCC][11] = 127, ++ [1][1][0][0][RTW89_ACMA][11] = 127, ++ [1][1][0][0][RTW89_CHILE][11] = 127, ++ [1][1][0][0][RTW89_UKRAINE][11] = 127, ++ [1][1][0][0][RTW89_FCC][12] = 127, ++ [1][1][0][0][RTW89_ETSI][12] = 127, ++ [1][1][0][0][RTW89_MKK][12] = 127, ++ [1][1][0][0][RTW89_IC][12] = 127, ++ [1][1][0][0][RTW89_KCC][12] = 127, ++ [1][1][0][0][RTW89_ACMA][12] = 127, ++ [1][1][0][0][RTW89_CHILE][12] = 127, ++ [1][1][0][0][RTW89_UKRAINE][12] = 127, ++ [1][1][0][0][RTW89_FCC][13] = 127, ++ [1][1][0][0][RTW89_ETSI][13] = 127, ++ [1][1][0][0][RTW89_MKK][13] = 127, ++ [1][1][0][0][RTW89_IC][13] = 127, ++ [1][1][0][0][RTW89_KCC][13] = 127, ++ [1][1][0][0][RTW89_ACMA][13] = 127, ++ [1][1][0][0][RTW89_CHILE][13] = 127, ++ [1][1][0][0][RTW89_UKRAINE][13] = 127, ++ [0][0][1][0][RTW89_FCC][0] = 66, ++ [0][0][1][0][RTW89_ETSI][0] = 58, ++ [0][0][1][0][RTW89_MKK][0] = 76, ++ [0][0][1][0][RTW89_IC][0] = 66, ++ [0][0][1][0][RTW89_KCC][0] = 58, ++ [0][0][1][0][RTW89_ACMA][0] = 58, ++ [0][0][1][0][RTW89_CHILE][0] = 60, ++ [0][0][1][0][RTW89_UKRAINE][0] = 58, ++ [0][0][1][0][RTW89_FCC][1] = 66, ++ [0][0][1][0][RTW89_ETSI][1] = 58, ++ [0][0][1][0][RTW89_MKK][1] = 76, ++ [0][0][1][0][RTW89_IC][1] = 66, ++ [0][0][1][0][RTW89_KCC][1] = 58, ++ [0][0][1][0][RTW89_ACMA][1] = 58, ++ [0][0][1][0][RTW89_CHILE][1] = 60, ++ [0][0][1][0][RTW89_UKRAINE][1] = 58, ++ [0][0][1][0][RTW89_FCC][2] = 70, ++ [0][0][1][0][RTW89_ETSI][2] = 58, ++ [0][0][1][0][RTW89_MKK][2] = 76, ++ [0][0][1][0][RTW89_IC][2] = 70, ++ [0][0][1][0][RTW89_KCC][2] = 58, ++ [0][0][1][0][RTW89_ACMA][2] = 58, ++ [0][0][1][0][RTW89_CHILE][2] = 60, ++ [0][0][1][0][RTW89_UKRAINE][2] = 58, ++ [0][0][1][0][RTW89_FCC][3] = 74, ++ [0][0][1][0][RTW89_ETSI][3] = 58, ++ [0][0][1][0][RTW89_MKK][3] = 76, ++ [0][0][1][0][RTW89_IC][3] = 74, ++ [0][0][1][0][RTW89_KCC][3] = 58, ++ [0][0][1][0][RTW89_ACMA][3] = 58, ++ [0][0][1][0][RTW89_CHILE][3] = 60, ++ [0][0][1][0][RTW89_UKRAINE][3] = 58, ++ [0][0][1][0][RTW89_FCC][4] = 78, ++ [0][0][1][0][RTW89_ETSI][4] = 58, ++ [0][0][1][0][RTW89_MKK][4] = 76, ++ [0][0][1][0][RTW89_IC][4] = 78, ++ [0][0][1][0][RTW89_KCC][4] = 58, ++ [0][0][1][0][RTW89_ACMA][4] = 58, ++ [0][0][1][0][RTW89_CHILE][4] = 60, ++ [0][0][1][0][RTW89_UKRAINE][4] = 58, ++ [0][0][1][0][RTW89_FCC][5] = 78, ++ [0][0][1][0][RTW89_ETSI][5] = 58, ++ [0][0][1][0][RTW89_MKK][5] = 76, ++ [0][0][1][0][RTW89_IC][5] = 78, ++ [0][0][1][0][RTW89_KCC][5] = 58, ++ [0][0][1][0][RTW89_ACMA][5] = 58, ++ [0][0][1][0][RTW89_CHILE][5] = 60, ++ [0][0][1][0][RTW89_UKRAINE][5] = 58, ++ [0][0][1][0][RTW89_FCC][6] = 78, ++ [0][0][1][0][RTW89_ETSI][6] = 58, ++ [0][0][1][0][RTW89_MKK][6] = 76, ++ [0][0][1][0][RTW89_IC][6] = 78, ++ [0][0][1][0][RTW89_KCC][6] = 58, ++ [0][0][1][0][RTW89_ACMA][6] = 58, ++ [0][0][1][0][RTW89_CHILE][6] = 60, ++ [0][0][1][0][RTW89_UKRAINE][6] = 58, ++ [0][0][1][0][RTW89_FCC][7] = 74, ++ [0][0][1][0][RTW89_ETSI][7] = 58, ++ [0][0][1][0][RTW89_MKK][7] = 76, ++ [0][0][1][0][RTW89_IC][7] = 74, ++ [0][0][1][0][RTW89_KCC][7] = 58, ++ [0][0][1][0][RTW89_ACMA][7] = 58, ++ [0][0][1][0][RTW89_CHILE][7] = 60, ++ [0][0][1][0][RTW89_UKRAINE][7] = 58, ++ [0][0][1][0][RTW89_FCC][8] = 70, ++ [0][0][1][0][RTW89_ETSI][8] = 58, ++ [0][0][1][0][RTW89_MKK][8] = 76, ++ [0][0][1][0][RTW89_IC][8] = 70, ++ [0][0][1][0][RTW89_KCC][8] = 58, ++ [0][0][1][0][RTW89_ACMA][8] = 58, ++ [0][0][1][0][RTW89_CHILE][8] = 60, ++ [0][0][1][0][RTW89_UKRAINE][8] = 58, ++ [0][0][1][0][RTW89_FCC][9] = 66, ++ [0][0][1][0][RTW89_ETSI][9] = 58, ++ [0][0][1][0][RTW89_MKK][9] = 76, ++ [0][0][1][0][RTW89_IC][9] = 66, ++ [0][0][1][0][RTW89_KCC][9] = 58, ++ [0][0][1][0][RTW89_ACMA][9] = 58, ++ [0][0][1][0][RTW89_CHILE][9] = 60, ++ [0][0][1][0][RTW89_UKRAINE][9] = 58, ++ [0][0][1][0][RTW89_FCC][10] = 66, ++ [0][0][1][0][RTW89_ETSI][10] = 58, ++ [0][0][1][0][RTW89_MKK][10] = 76, ++ [0][0][1][0][RTW89_IC][10] = 66, ++ [0][0][1][0][RTW89_KCC][10] = 58, ++ [0][0][1][0][RTW89_ACMA][10] = 58, ++ [0][0][1][0][RTW89_CHILE][10] = 60, ++ [0][0][1][0][RTW89_UKRAINE][10] = 58, ++ [0][0][1][0][RTW89_FCC][11] = 56, ++ [0][0][1][0][RTW89_ETSI][11] = 58, ++ [0][0][1][0][RTW89_MKK][11] = 76, ++ [0][0][1][0][RTW89_IC][11] = 56, ++ [0][0][1][0][RTW89_KCC][11] = 58, ++ [0][0][1][0][RTW89_ACMA][11] = 58, ++ [0][0][1][0][RTW89_CHILE][11] = 60, ++ [0][0][1][0][RTW89_UKRAINE][11] = 58, ++ [0][0][1][0][RTW89_FCC][12] = 52, ++ [0][0][1][0][RTW89_ETSI][12] = 58, ++ [0][0][1][0][RTW89_MKK][12] = 76, ++ [0][0][1][0][RTW89_IC][12] = 52, ++ [0][0][1][0][RTW89_KCC][12] = 58, ++ [0][0][1][0][RTW89_ACMA][12] = 58, ++ [0][0][1][0][RTW89_CHILE][12] = 60, ++ [0][0][1][0][RTW89_UKRAINE][12] = 58, ++ [0][0][1][0][RTW89_FCC][13] = 127, ++ [0][0][1][0][RTW89_ETSI][13] = 127, ++ [0][0][1][0][RTW89_MKK][13] = 127, ++ [0][0][1][0][RTW89_IC][13] = 127, ++ [0][0][1][0][RTW89_KCC][13] = 127, ++ [0][0][1][0][RTW89_ACMA][13] = 127, ++ [0][0][1][0][RTW89_CHILE][13] = 127, ++ [0][0][1][0][RTW89_UKRAINE][13] = 127, ++ [0][1][1][0][RTW89_FCC][0] = 62, ++ [0][1][1][0][RTW89_ETSI][0] = 46, ++ [0][1][1][0][RTW89_MKK][0] = 64, ++ [0][1][1][0][RTW89_IC][0] = 62, ++ [0][1][1][0][RTW89_KCC][0] = 46, ++ [0][1][1][0][RTW89_ACMA][0] = 46, ++ [0][1][1][0][RTW89_CHILE][0] = 48, ++ [0][1][1][0][RTW89_UKRAINE][0] = 46, ++ [0][1][1][0][RTW89_FCC][1] = 62, ++ [0][1][1][0][RTW89_ETSI][1] = 46, ++ [0][1][1][0][RTW89_MKK][1] = 64, ++ [0][1][1][0][RTW89_IC][1] = 62, ++ [0][1][1][0][RTW89_KCC][1] = 46, ++ [0][1][1][0][RTW89_ACMA][1] = 46, ++ [0][1][1][0][RTW89_CHILE][1] = 48, ++ [0][1][1][0][RTW89_UKRAINE][1] = 46, ++ [0][1][1][0][RTW89_FCC][2] = 66, ++ [0][1][1][0][RTW89_ETSI][2] = 46, ++ [0][1][1][0][RTW89_MKK][2] = 64, ++ [0][1][1][0][RTW89_IC][2] = 66, ++ [0][1][1][0][RTW89_KCC][2] = 46, ++ [0][1][1][0][RTW89_ACMA][2] = 46, ++ [0][1][1][0][RTW89_CHILE][2] = 48, ++ [0][1][1][0][RTW89_UKRAINE][2] = 46, ++ [0][1][1][0][RTW89_FCC][3] = 70, ++ [0][1][1][0][RTW89_ETSI][3] = 46, ++ [0][1][1][0][RTW89_MKK][3] = 64, ++ [0][1][1][0][RTW89_IC][3] = 70, ++ [0][1][1][0][RTW89_KCC][3] = 46, ++ [0][1][1][0][RTW89_ACMA][3] = 46, ++ [0][1][1][0][RTW89_CHILE][3] = 48, ++ [0][1][1][0][RTW89_UKRAINE][3] = 46, ++ [0][1][1][0][RTW89_FCC][4] = 78, ++ [0][1][1][0][RTW89_ETSI][4] = 46, ++ [0][1][1][0][RTW89_MKK][4] = 64, ++ [0][1][1][0][RTW89_IC][4] = 78, ++ [0][1][1][0][RTW89_KCC][4] = 46, ++ [0][1][1][0][RTW89_ACMA][4] = 46, ++ [0][1][1][0][RTW89_CHILE][4] = 48, ++ [0][1][1][0][RTW89_UKRAINE][4] = 46, ++ [0][1][1][0][RTW89_FCC][5] = 78, ++ [0][1][1][0][RTW89_ETSI][5] = 46, ++ [0][1][1][0][RTW89_MKK][5] = 64, ++ [0][1][1][0][RTW89_IC][5] = 78, ++ [0][1][1][0][RTW89_KCC][5] = 46, ++ [0][1][1][0][RTW89_ACMA][5] = 46, ++ [0][1][1][0][RTW89_CHILE][5] = 48, ++ [0][1][1][0][RTW89_UKRAINE][5] = 46, ++ [0][1][1][0][RTW89_FCC][6] = 78, ++ [0][1][1][0][RTW89_ETSI][6] = 46, ++ [0][1][1][0][RTW89_MKK][6] = 64, ++ [0][1][1][0][RTW89_IC][6] = 78, ++ [0][1][1][0][RTW89_KCC][6] = 46, ++ [0][1][1][0][RTW89_ACMA][6] = 46, ++ [0][1][1][0][RTW89_CHILE][6] = 48, ++ [0][1][1][0][RTW89_UKRAINE][6] = 46, ++ [0][1][1][0][RTW89_FCC][7] = 70, ++ [0][1][1][0][RTW89_ETSI][7] = 46, ++ [0][1][1][0][RTW89_MKK][7] = 64, ++ [0][1][1][0][RTW89_IC][7] = 70, ++ [0][1][1][0][RTW89_KCC][7] = 46, ++ [0][1][1][0][RTW89_ACMA][7] = 46, ++ [0][1][1][0][RTW89_CHILE][7] = 48, ++ [0][1][1][0][RTW89_UKRAINE][7] = 46, ++ [0][1][1][0][RTW89_FCC][8] = 66, ++ [0][1][1][0][RTW89_ETSI][8] = 46, ++ [0][1][1][0][RTW89_MKK][8] = 64, ++ [0][1][1][0][RTW89_IC][8] = 66, ++ [0][1][1][0][RTW89_KCC][8] = 46, ++ [0][1][1][0][RTW89_ACMA][8] = 46, ++ [0][1][1][0][RTW89_CHILE][8] = 48, ++ [0][1][1][0][RTW89_UKRAINE][8] = 46, ++ [0][1][1][0][RTW89_FCC][9] = 62, ++ [0][1][1][0][RTW89_ETSI][9] = 46, ++ [0][1][1][0][RTW89_MKK][9] = 64, ++ [0][1][1][0][RTW89_IC][9] = 62, ++ [0][1][1][0][RTW89_KCC][9] = 46, ++ [0][1][1][0][RTW89_ACMA][9] = 46, ++ [0][1][1][0][RTW89_CHILE][9] = 48, ++ [0][1][1][0][RTW89_UKRAINE][9] = 46, ++ [0][1][1][0][RTW89_FCC][10] = 62, ++ [0][1][1][0][RTW89_ETSI][10] = 46, ++ [0][1][1][0][RTW89_MKK][10] = 64, ++ [0][1][1][0][RTW89_IC][10] = 62, ++ [0][1][1][0][RTW89_KCC][10] = 46, ++ [0][1][1][0][RTW89_ACMA][10] = 46, ++ [0][1][1][0][RTW89_CHILE][10] = 48, ++ [0][1][1][0][RTW89_UKRAINE][10] = 46, ++ [0][1][1][0][RTW89_FCC][11] = 42, ++ [0][1][1][0][RTW89_ETSI][11] = 46, ++ [0][1][1][0][RTW89_MKK][11] = 64, ++ [0][1][1][0][RTW89_IC][11] = 42, ++ [0][1][1][0][RTW89_KCC][11] = 46, ++ [0][1][1][0][RTW89_ACMA][11] = 46, ++ [0][1][1][0][RTW89_CHILE][11] = 48, ++ [0][1][1][0][RTW89_UKRAINE][11] = 46, ++ [0][1][1][0][RTW89_FCC][12] = 40, ++ [0][1][1][0][RTW89_ETSI][12] = 46, ++ [0][1][1][0][RTW89_MKK][12] = 64, ++ [0][1][1][0][RTW89_IC][12] = 40, ++ [0][1][1][0][RTW89_KCC][12] = 46, ++ [0][1][1][0][RTW89_ACMA][12] = 46, ++ [0][1][1][0][RTW89_CHILE][12] = 48, ++ [0][1][1][0][RTW89_UKRAINE][12] = 46, ++ [0][1][1][0][RTW89_FCC][13] = 127, ++ [0][1][1][0][RTW89_ETSI][13] = 127, ++ [0][1][1][0][RTW89_MKK][13] = 127, ++ [0][1][1][0][RTW89_IC][13] = 127, ++ [0][1][1][0][RTW89_KCC][13] = 127, ++ [0][1][1][0][RTW89_ACMA][13] = 127, ++ [0][1][1][0][RTW89_CHILE][13] = 127, ++ [0][1][1][0][RTW89_UKRAINE][13] = 127, ++ [0][0][2][0][RTW89_FCC][0] = 66, ++ [0][0][2][0][RTW89_ETSI][0] = 58, ++ [0][0][2][0][RTW89_MKK][0] = 76, ++ [0][0][2][0][RTW89_IC][0] = 66, ++ [0][0][2][0][RTW89_KCC][0] = 58, ++ [0][0][2][0][RTW89_ACMA][0] = 58, ++ [0][0][2][0][RTW89_CHILE][0] = 60, ++ [0][0][2][0][RTW89_UKRAINE][0] = 58, ++ [0][0][2][0][RTW89_FCC][1] = 66, ++ [0][0][2][0][RTW89_ETSI][1] = 58, ++ [0][0][2][0][RTW89_MKK][1] = 76, ++ [0][0][2][0][RTW89_IC][1] = 66, ++ [0][0][2][0][RTW89_KCC][1] = 58, ++ [0][0][2][0][RTW89_ACMA][1] = 58, ++ [0][0][2][0][RTW89_CHILE][1] = 60, ++ [0][0][2][0][RTW89_UKRAINE][1] = 58, ++ [0][0][2][0][RTW89_FCC][2] = 70, ++ [0][0][2][0][RTW89_ETSI][2] = 58, ++ [0][0][2][0][RTW89_MKK][2] = 76, ++ [0][0][2][0][RTW89_IC][2] = 70, ++ [0][0][2][0][RTW89_KCC][2] = 58, ++ [0][0][2][0][RTW89_ACMA][2] = 58, ++ [0][0][2][0][RTW89_CHILE][2] = 60, ++ [0][0][2][0][RTW89_UKRAINE][2] = 58, ++ [0][0][2][0][RTW89_FCC][3] = 74, ++ [0][0][2][0][RTW89_ETSI][3] = 58, ++ [0][0][2][0][RTW89_MKK][3] = 76, ++ [0][0][2][0][RTW89_IC][3] = 74, ++ [0][0][2][0][RTW89_KCC][3] = 58, ++ [0][0][2][0][RTW89_ACMA][3] = 58, ++ [0][0][2][0][RTW89_CHILE][3] = 60, ++ [0][0][2][0][RTW89_UKRAINE][3] = 58, ++ [0][0][2][0][RTW89_FCC][4] = 76, ++ [0][0][2][0][RTW89_ETSI][4] = 58, ++ [0][0][2][0][RTW89_MKK][4] = 76, ++ [0][0][2][0][RTW89_IC][4] = 76, ++ [0][0][2][0][RTW89_KCC][4] = 58, ++ [0][0][2][0][RTW89_ACMA][4] = 58, ++ [0][0][2][0][RTW89_CHILE][4] = 60, ++ [0][0][2][0][RTW89_UKRAINE][4] = 58, ++ [0][0][2][0][RTW89_FCC][5] = 76, ++ [0][0][2][0][RTW89_ETSI][5] = 58, ++ [0][0][2][0][RTW89_MKK][5] = 76, ++ [0][0][2][0][RTW89_IC][5] = 76, ++ [0][0][2][0][RTW89_KCC][5] = 58, ++ [0][0][2][0][RTW89_ACMA][5] = 58, ++ [0][0][2][0][RTW89_CHILE][5] = 60, ++ [0][0][2][0][RTW89_UKRAINE][5] = 58, ++ [0][0][2][0][RTW89_FCC][6] = 76, ++ [0][0][2][0][RTW89_ETSI][6] = 58, ++ [0][0][2][0][RTW89_MKK][6] = 76, ++ [0][0][2][0][RTW89_IC][6] = 76, ++ [0][0][2][0][RTW89_KCC][6] = 58, ++ [0][0][2][0][RTW89_ACMA][6] = 58, ++ [0][0][2][0][RTW89_CHILE][6] = 60, ++ [0][0][2][0][RTW89_UKRAINE][6] = 58, ++ [0][0][2][0][RTW89_FCC][7] = 74, ++ [0][0][2][0][RTW89_ETSI][7] = 58, ++ [0][0][2][0][RTW89_MKK][7] = 76, ++ [0][0][2][0][RTW89_IC][7] = 74, ++ [0][0][2][0][RTW89_KCC][7] = 58, ++ [0][0][2][0][RTW89_ACMA][7] = 58, ++ [0][0][2][0][RTW89_CHILE][7] = 60, ++ [0][0][2][0][RTW89_UKRAINE][7] = 58, ++ [0][0][2][0][RTW89_FCC][8] = 70, ++ [0][0][2][0][RTW89_ETSI][8] = 58, ++ [0][0][2][0][RTW89_MKK][8] = 76, ++ [0][0][2][0][RTW89_IC][8] = 70, ++ [0][0][2][0][RTW89_KCC][8] = 58, ++ [0][0][2][0][RTW89_ACMA][8] = 58, ++ [0][0][2][0][RTW89_CHILE][8] = 60, ++ [0][0][2][0][RTW89_UKRAINE][8] = 58, ++ [0][0][2][0][RTW89_FCC][9] = 66, ++ [0][0][2][0][RTW89_ETSI][9] = 58, ++ [0][0][2][0][RTW89_MKK][9] = 76, ++ [0][0][2][0][RTW89_IC][9] = 66, ++ [0][0][2][0][RTW89_KCC][9] = 58, ++ [0][0][2][0][RTW89_ACMA][9] = 58, ++ [0][0][2][0][RTW89_CHILE][9] = 60, ++ [0][0][2][0][RTW89_UKRAINE][9] = 58, ++ [0][0][2][0][RTW89_FCC][10] = 66, ++ [0][0][2][0][RTW89_ETSI][10] = 58, ++ [0][0][2][0][RTW89_MKK][10] = 76, ++ [0][0][2][0][RTW89_IC][10] = 66, ++ [0][0][2][0][RTW89_KCC][10] = 58, ++ [0][0][2][0][RTW89_ACMA][10] = 58, ++ [0][0][2][0][RTW89_CHILE][10] = 60, ++ [0][0][2][0][RTW89_UKRAINE][10] = 58, ++ [0][0][2][0][RTW89_FCC][11] = 54, ++ [0][0][2][0][RTW89_ETSI][11] = 58, ++ [0][0][2][0][RTW89_MKK][11] = 76, ++ [0][0][2][0][RTW89_IC][11] = 54, ++ [0][0][2][0][RTW89_KCC][11] = 58, ++ [0][0][2][0][RTW89_ACMA][11] = 58, ++ [0][0][2][0][RTW89_CHILE][11] = 60, ++ [0][0][2][0][RTW89_UKRAINE][11] = 58, ++ [0][0][2][0][RTW89_FCC][12] = 50, ++ [0][0][2][0][RTW89_ETSI][12] = 58, ++ [0][0][2][0][RTW89_MKK][12] = 76, ++ [0][0][2][0][RTW89_IC][12] = 50, ++ [0][0][2][0][RTW89_KCC][12] = 58, ++ [0][0][2][0][RTW89_ACMA][12] = 58, ++ [0][0][2][0][RTW89_CHILE][12] = 60, ++ [0][0][2][0][RTW89_UKRAINE][12] = 58, ++ [0][0][2][0][RTW89_FCC][13] = 127, ++ [0][0][2][0][RTW89_ETSI][13] = 127, ++ [0][0][2][0][RTW89_MKK][13] = 127, ++ [0][0][2][0][RTW89_IC][13] = 127, ++ [0][0][2][0][RTW89_KCC][13] = 127, ++ [0][0][2][0][RTW89_ACMA][13] = 127, ++ [0][0][2][0][RTW89_CHILE][13] = 127, ++ [0][0][2][0][RTW89_UKRAINE][13] = 127, ++ [0][1][2][0][RTW89_FCC][0] = 62, ++ [0][1][2][0][RTW89_ETSI][0] = 46, ++ [0][1][2][0][RTW89_MKK][0] = 64, ++ [0][1][2][0][RTW89_IC][0] = 62, ++ [0][1][2][0][RTW89_KCC][0] = 46, ++ [0][1][2][0][RTW89_ACMA][0] = 46, ++ [0][1][2][0][RTW89_CHILE][0] = 48, ++ [0][1][2][0][RTW89_UKRAINE][0] = 46, ++ [0][1][2][0][RTW89_FCC][1] = 62, ++ [0][1][2][0][RTW89_ETSI][1] = 46, ++ [0][1][2][0][RTW89_MKK][1] = 64, ++ [0][1][2][0][RTW89_IC][1] = 62, ++ [0][1][2][0][RTW89_KCC][1] = 46, ++ [0][1][2][0][RTW89_ACMA][1] = 46, ++ [0][1][2][0][RTW89_CHILE][1] = 48, ++ [0][1][2][0][RTW89_UKRAINE][1] = 46, ++ [0][1][2][0][RTW89_FCC][2] = 66, ++ [0][1][2][0][RTW89_ETSI][2] = 46, ++ [0][1][2][0][RTW89_MKK][2] = 64, ++ [0][1][2][0][RTW89_IC][2] = 66, ++ [0][1][2][0][RTW89_KCC][2] = 46, ++ [0][1][2][0][RTW89_ACMA][2] = 46, ++ [0][1][2][0][RTW89_CHILE][2] = 48, ++ [0][1][2][0][RTW89_UKRAINE][2] = 46, ++ [0][1][2][0][RTW89_FCC][3] = 70, ++ [0][1][2][0][RTW89_ETSI][3] = 46, ++ [0][1][2][0][RTW89_MKK][3] = 64, ++ [0][1][2][0][RTW89_IC][3] = 70, ++ [0][1][2][0][RTW89_KCC][3] = 46, ++ [0][1][2][0][RTW89_ACMA][3] = 46, ++ [0][1][2][0][RTW89_CHILE][3] = 48, ++ [0][1][2][0][RTW89_UKRAINE][3] = 46, ++ [0][1][2][0][RTW89_FCC][4] = 76, ++ [0][1][2][0][RTW89_ETSI][4] = 46, ++ [0][1][2][0][RTW89_MKK][4] = 64, ++ [0][1][2][0][RTW89_IC][4] = 76, ++ [0][1][2][0][RTW89_KCC][4] = 46, ++ [0][1][2][0][RTW89_ACMA][4] = 46, ++ [0][1][2][0][RTW89_CHILE][4] = 48, ++ [0][1][2][0][RTW89_UKRAINE][4] = 46, ++ [0][1][2][0][RTW89_FCC][5] = 76, ++ [0][1][2][0][RTW89_ETSI][5] = 46, ++ [0][1][2][0][RTW89_MKK][5] = 64, ++ [0][1][2][0][RTW89_IC][5] = 76, ++ [0][1][2][0][RTW89_KCC][5] = 46, ++ [0][1][2][0][RTW89_ACMA][5] = 46, ++ [0][1][2][0][RTW89_CHILE][5] = 48, ++ [0][1][2][0][RTW89_UKRAINE][5] = 46, ++ [0][1][2][0][RTW89_FCC][6] = 76, ++ [0][1][2][0][RTW89_ETSI][6] = 46, ++ [0][1][2][0][RTW89_MKK][6] = 64, ++ [0][1][2][0][RTW89_IC][6] = 76, ++ [0][1][2][0][RTW89_KCC][6] = 46, ++ [0][1][2][0][RTW89_ACMA][6] = 46, ++ [0][1][2][0][RTW89_CHILE][6] = 48, ++ [0][1][2][0][RTW89_UKRAINE][6] = 46, ++ [0][1][2][0][RTW89_FCC][7] = 68, ++ [0][1][2][0][RTW89_ETSI][7] = 46, ++ [0][1][2][0][RTW89_MKK][7] = 64, ++ [0][1][2][0][RTW89_IC][7] = 68, ++ [0][1][2][0][RTW89_KCC][7] = 46, ++ [0][1][2][0][RTW89_ACMA][7] = 46, ++ [0][1][2][0][RTW89_CHILE][7] = 48, ++ [0][1][2][0][RTW89_UKRAINE][7] = 46, ++ [0][1][2][0][RTW89_FCC][8] = 64, ++ [0][1][2][0][RTW89_ETSI][8] = 46, ++ [0][1][2][0][RTW89_MKK][8] = 64, ++ [0][1][2][0][RTW89_IC][8] = 64, ++ [0][1][2][0][RTW89_KCC][8] = 46, ++ [0][1][2][0][RTW89_ACMA][8] = 46, ++ [0][1][2][0][RTW89_CHILE][8] = 48, ++ [0][1][2][0][RTW89_UKRAINE][8] = 46, ++ [0][1][2][0][RTW89_FCC][9] = 60, ++ [0][1][2][0][RTW89_ETSI][9] = 46, ++ [0][1][2][0][RTW89_MKK][9] = 64, ++ [0][1][2][0][RTW89_IC][9] = 60, ++ [0][1][2][0][RTW89_KCC][9] = 46, ++ [0][1][2][0][RTW89_ACMA][9] = 46, ++ [0][1][2][0][RTW89_CHILE][9] = 48, ++ [0][1][2][0][RTW89_UKRAINE][9] = 46, ++ [0][1][2][0][RTW89_FCC][10] = 60, ++ [0][1][2][0][RTW89_ETSI][10] = 46, ++ [0][1][2][0][RTW89_MKK][10] = 64, ++ [0][1][2][0][RTW89_IC][10] = 60, ++ [0][1][2][0][RTW89_KCC][10] = 46, ++ [0][1][2][0][RTW89_ACMA][10] = 46, ++ [0][1][2][0][RTW89_CHILE][10] = 48, ++ [0][1][2][0][RTW89_UKRAINE][10] = 46, ++ [0][1][2][0][RTW89_FCC][11] = 42, ++ [0][1][2][0][RTW89_ETSI][11] = 46, ++ [0][1][2][0][RTW89_MKK][11] = 64, ++ [0][1][2][0][RTW89_IC][11] = 42, ++ [0][1][2][0][RTW89_KCC][11] = 46, ++ [0][1][2][0][RTW89_ACMA][11] = 46, ++ [0][1][2][0][RTW89_CHILE][11] = 48, ++ [0][1][2][0][RTW89_UKRAINE][11] = 46, ++ [0][1][2][0][RTW89_FCC][12] = 40, ++ [0][1][2][0][RTW89_ETSI][12] = 46, ++ [0][1][2][0][RTW89_MKK][12] = 64, ++ [0][1][2][0][RTW89_IC][12] = 40, ++ [0][1][2][0][RTW89_KCC][12] = 46, ++ [0][1][2][0][RTW89_ACMA][12] = 46, ++ [0][1][2][0][RTW89_CHILE][12] = 48, ++ [0][1][2][0][RTW89_UKRAINE][12] = 46, ++ [0][1][2][0][RTW89_FCC][13] = 127, ++ [0][1][2][0][RTW89_ETSI][13] = 127, ++ [0][1][2][0][RTW89_MKK][13] = 127, ++ [0][1][2][0][RTW89_IC][13] = 127, ++ [0][1][2][0][RTW89_KCC][13] = 127, ++ [0][1][2][0][RTW89_ACMA][13] = 127, ++ [0][1][2][0][RTW89_CHILE][13] = 127, ++ [0][1][2][0][RTW89_UKRAINE][13] = 127, ++ [0][1][2][1][RTW89_FCC][0] = 62, ++ [0][1][2][1][RTW89_ETSI][0] = 34, ++ [0][1][2][1][RTW89_MKK][0] = 64, ++ [0][1][2][1][RTW89_IC][0] = 62, ++ [0][1][2][1][RTW89_KCC][0] = 34, ++ [0][1][2][1][RTW89_ACMA][0] = 34, ++ [0][1][2][1][RTW89_CHILE][0] = 36, ++ [0][1][2][1][RTW89_UKRAINE][0] = 34, ++ [0][1][2][1][RTW89_FCC][1] = 62, ++ [0][1][2][1][RTW89_ETSI][1] = 34, ++ [0][1][2][1][RTW89_MKK][1] = 64, ++ [0][1][2][1][RTW89_IC][1] = 62, ++ [0][1][2][1][RTW89_KCC][1] = 34, ++ [0][1][2][1][RTW89_ACMA][1] = 34, ++ [0][1][2][1][RTW89_CHILE][1] = 36, ++ [0][1][2][1][RTW89_UKRAINE][1] = 34, ++ [0][1][2][1][RTW89_FCC][2] = 66, ++ [0][1][2][1][RTW89_ETSI][2] = 34, ++ [0][1][2][1][RTW89_MKK][2] = 64, ++ [0][1][2][1][RTW89_IC][2] = 66, ++ [0][1][2][1][RTW89_KCC][2] = 34, ++ [0][1][2][1][RTW89_ACMA][2] = 34, ++ [0][1][2][1][RTW89_CHILE][2] = 36, ++ [0][1][2][1][RTW89_UKRAINE][2] = 34, ++ [0][1][2][1][RTW89_FCC][3] = 70, ++ [0][1][2][1][RTW89_ETSI][3] = 34, ++ [0][1][2][1][RTW89_MKK][3] = 64, ++ [0][1][2][1][RTW89_IC][3] = 70, ++ [0][1][2][1][RTW89_KCC][3] = 34, ++ [0][1][2][1][RTW89_ACMA][3] = 34, ++ [0][1][2][1][RTW89_CHILE][3] = 36, ++ [0][1][2][1][RTW89_UKRAINE][3] = 34, ++ [0][1][2][1][RTW89_FCC][4] = 76, ++ [0][1][2][1][RTW89_ETSI][4] = 34, ++ [0][1][2][1][RTW89_MKK][4] = 64, ++ [0][1][2][1][RTW89_IC][4] = 76, ++ [0][1][2][1][RTW89_KCC][4] = 34, ++ [0][1][2][1][RTW89_ACMA][4] = 34, ++ [0][1][2][1][RTW89_CHILE][4] = 36, ++ [0][1][2][1][RTW89_UKRAINE][4] = 34, ++ [0][1][2][1][RTW89_FCC][5] = 76, ++ [0][1][2][1][RTW89_ETSI][5] = 34, ++ [0][1][2][1][RTW89_MKK][5] = 64, ++ [0][1][2][1][RTW89_IC][5] = 76, ++ [0][1][2][1][RTW89_KCC][5] = 34, ++ [0][1][2][1][RTW89_ACMA][5] = 34, ++ [0][1][2][1][RTW89_CHILE][5] = 36, ++ [0][1][2][1][RTW89_UKRAINE][5] = 34, ++ [0][1][2][1][RTW89_FCC][6] = 76, ++ [0][1][2][1][RTW89_ETSI][6] = 34, ++ [0][1][2][1][RTW89_MKK][6] = 64, ++ [0][1][2][1][RTW89_IC][6] = 76, ++ [0][1][2][1][RTW89_KCC][6] = 34, ++ [0][1][2][1][RTW89_ACMA][6] = 34, ++ [0][1][2][1][RTW89_CHILE][6] = 36, ++ [0][1][2][1][RTW89_UKRAINE][6] = 34, ++ [0][1][2][1][RTW89_FCC][7] = 68, ++ [0][1][2][1][RTW89_ETSI][7] = 34, ++ [0][1][2][1][RTW89_MKK][7] = 64, ++ [0][1][2][1][RTW89_IC][7] = 68, ++ [0][1][2][1][RTW89_KCC][7] = 34, ++ [0][1][2][1][RTW89_ACMA][7] = 34, ++ [0][1][2][1][RTW89_CHILE][7] = 36, ++ [0][1][2][1][RTW89_UKRAINE][7] = 34, ++ [0][1][2][1][RTW89_FCC][8] = 64, ++ [0][1][2][1][RTW89_ETSI][8] = 34, ++ [0][1][2][1][RTW89_MKK][8] = 64, ++ [0][1][2][1][RTW89_IC][8] = 64, ++ [0][1][2][1][RTW89_KCC][8] = 34, ++ [0][1][2][1][RTW89_ACMA][8] = 34, ++ [0][1][2][1][RTW89_CHILE][8] = 36, ++ [0][1][2][1][RTW89_UKRAINE][8] = 34, ++ [0][1][2][1][RTW89_FCC][9] = 60, ++ [0][1][2][1][RTW89_ETSI][9] = 34, ++ [0][1][2][1][RTW89_MKK][9] = 64, ++ [0][1][2][1][RTW89_IC][9] = 60, ++ [0][1][2][1][RTW89_KCC][9] = 34, ++ [0][1][2][1][RTW89_ACMA][9] = 34, ++ [0][1][2][1][RTW89_CHILE][9] = 36, ++ [0][1][2][1][RTW89_UKRAINE][9] = 34, ++ [0][1][2][1][RTW89_FCC][10] = 60, ++ [0][1][2][1][RTW89_ETSI][10] = 34, ++ [0][1][2][1][RTW89_MKK][10] = 64, ++ [0][1][2][1][RTW89_IC][10] = 60, ++ [0][1][2][1][RTW89_KCC][10] = 34, ++ [0][1][2][1][RTW89_ACMA][10] = 34, ++ [0][1][2][1][RTW89_CHILE][10] = 36, ++ [0][1][2][1][RTW89_UKRAINE][10] = 34, ++ [0][1][2][1][RTW89_FCC][11] = 42, ++ [0][1][2][1][RTW89_ETSI][11] = 34, ++ [0][1][2][1][RTW89_MKK][11] = 64, ++ [0][1][2][1][RTW89_IC][11] = 42, ++ [0][1][2][1][RTW89_KCC][11] = 34, ++ [0][1][2][1][RTW89_ACMA][11] = 34, ++ [0][1][2][1][RTW89_CHILE][11] = 36, ++ [0][1][2][1][RTW89_UKRAINE][11] = 34, ++ [0][1][2][1][RTW89_FCC][12] = 40, ++ [0][1][2][1][RTW89_ETSI][12] = 34, ++ [0][1][2][1][RTW89_MKK][12] = 64, ++ [0][1][2][1][RTW89_IC][12] = 40, ++ [0][1][2][1][RTW89_KCC][12] = 34, ++ [0][1][2][1][RTW89_ACMA][12] = 34, ++ [0][1][2][1][RTW89_CHILE][12] = 36, ++ [0][1][2][1][RTW89_UKRAINE][12] = 34, ++ [0][1][2][1][RTW89_FCC][13] = 127, ++ [0][1][2][1][RTW89_ETSI][13] = 127, ++ [0][1][2][1][RTW89_MKK][13] = 127, ++ [0][1][2][1][RTW89_IC][13] = 127, ++ [0][1][2][1][RTW89_KCC][13] = 127, ++ [0][1][2][1][RTW89_ACMA][13] = 127, ++ [0][1][2][1][RTW89_CHILE][13] = 127, ++ [0][1][2][1][RTW89_UKRAINE][13] = 127, ++ [1][0][2][0][RTW89_FCC][0] = 127, ++ [1][0][2][0][RTW89_ETSI][0] = 127, ++ [1][0][2][0][RTW89_MKK][0] = 127, ++ [1][0][2][0][RTW89_IC][0] = 127, ++ [1][0][2][0][RTW89_KCC][0] = 127, ++ [1][0][2][0][RTW89_ACMA][0] = 127, ++ [1][0][2][0][RTW89_CHILE][0] = 127, ++ [1][0][2][0][RTW89_UKRAINE][0] = 127, ++ [1][0][2][0][RTW89_FCC][1] = 127, ++ [1][0][2][0][RTW89_ETSI][1] = 127, ++ [1][0][2][0][RTW89_MKK][1] = 127, ++ [1][0][2][0][RTW89_IC][1] = 127, ++ [1][0][2][0][RTW89_KCC][1] = 127, ++ [1][0][2][0][RTW89_ACMA][1] = 127, ++ [1][0][2][0][RTW89_CHILE][1] = 127, ++ [1][0][2][0][RTW89_UKRAINE][1] = 127, ++ [1][0][2][0][RTW89_FCC][2] = 56, ++ [1][0][2][0][RTW89_ETSI][2] = 58, ++ [1][0][2][0][RTW89_MKK][2] = 76, ++ [1][0][2][0][RTW89_IC][2] = 56, ++ [1][0][2][0][RTW89_KCC][2] = 58, ++ [1][0][2][0][RTW89_ACMA][2] = 58, ++ [1][0][2][0][RTW89_CHILE][2] = 60, ++ [1][0][2][0][RTW89_UKRAINE][2] = 58, ++ [1][0][2][0][RTW89_FCC][3] = 56, ++ [1][0][2][0][RTW89_ETSI][3] = 58, ++ [1][0][2][0][RTW89_MKK][3] = 76, ++ [1][0][2][0][RTW89_IC][3] = 56, ++ [1][0][2][0][RTW89_KCC][3] = 58, ++ [1][0][2][0][RTW89_ACMA][3] = 58, ++ [1][0][2][0][RTW89_CHILE][3] = 60, ++ [1][0][2][0][RTW89_UKRAINE][3] = 58, ++ [1][0][2][0][RTW89_FCC][4] = 60, ++ [1][0][2][0][RTW89_ETSI][4] = 58, ++ [1][0][2][0][RTW89_MKK][4] = 76, ++ [1][0][2][0][RTW89_IC][4] = 60, ++ [1][0][2][0][RTW89_KCC][4] = 58, ++ [1][0][2][0][RTW89_ACMA][4] = 58, ++ [1][0][2][0][RTW89_CHILE][4] = 60, ++ [1][0][2][0][RTW89_UKRAINE][4] = 58, ++ [1][0][2][0][RTW89_FCC][5] = 64, ++ [1][0][2][0][RTW89_ETSI][5] = 58, ++ [1][0][2][0][RTW89_MKK][5] = 76, ++ [1][0][2][0][RTW89_IC][5] = 64, ++ [1][0][2][0][RTW89_KCC][5] = 58, ++ [1][0][2][0][RTW89_ACMA][5] = 58, ++ [1][0][2][0][RTW89_CHILE][5] = 60, ++ [1][0][2][0][RTW89_UKRAINE][5] = 58, ++ [1][0][2][0][RTW89_FCC][6] = 54, ++ [1][0][2][0][RTW89_ETSI][6] = 58, ++ [1][0][2][0][RTW89_MKK][6] = 76, ++ [1][0][2][0][RTW89_IC][6] = 54, ++ [1][0][2][0][RTW89_KCC][6] = 58, ++ [1][0][2][0][RTW89_ACMA][6] = 58, ++ [1][0][2][0][RTW89_CHILE][6] = 60, ++ [1][0][2][0][RTW89_UKRAINE][6] = 58, ++ [1][0][2][0][RTW89_FCC][7] = 50, ++ [1][0][2][0][RTW89_ETSI][7] = 58, ++ [1][0][2][0][RTW89_MKK][7] = 76, ++ [1][0][2][0][RTW89_IC][7] = 50, ++ [1][0][2][0][RTW89_KCC][7] = 58, ++ [1][0][2][0][RTW89_ACMA][7] = 58, ++ [1][0][2][0][RTW89_CHILE][7] = 60, ++ [1][0][2][0][RTW89_UKRAINE][7] = 58, ++ [1][0][2][0][RTW89_FCC][8] = 50, ++ [1][0][2][0][RTW89_ETSI][8] = 58, ++ [1][0][2][0][RTW89_MKK][8] = 76, ++ [1][0][2][0][RTW89_IC][8] = 50, ++ [1][0][2][0][RTW89_KCC][8] = 58, ++ [1][0][2][0][RTW89_ACMA][8] = 58, ++ [1][0][2][0][RTW89_CHILE][8] = 60, ++ [1][0][2][0][RTW89_UKRAINE][8] = 58, ++ [1][0][2][0][RTW89_FCC][9] = 42, ++ [1][0][2][0][RTW89_ETSI][9] = 58, ++ [1][0][2][0][RTW89_MKK][9] = 76, ++ [1][0][2][0][RTW89_IC][9] = 42, ++ [1][0][2][0][RTW89_KCC][9] = 58, ++ [1][0][2][0][RTW89_ACMA][9] = 58, ++ [1][0][2][0][RTW89_CHILE][9] = 60, ++ [1][0][2][0][RTW89_UKRAINE][9] = 58, ++ [1][0][2][0][RTW89_FCC][10] = 40, ++ [1][0][2][0][RTW89_ETSI][10] = 58, ++ [1][0][2][0][RTW89_MKK][10] = 76, ++ [1][0][2][0][RTW89_IC][10] = 40, ++ [1][0][2][0][RTW89_KCC][10] = 58, ++ [1][0][2][0][RTW89_ACMA][10] = 58, ++ [1][0][2][0][RTW89_CHILE][10] = 60, ++ [1][0][2][0][RTW89_UKRAINE][10] = 58, ++ [1][0][2][0][RTW89_FCC][11] = 127, ++ [1][0][2][0][RTW89_ETSI][11] = 127, ++ [1][0][2][0][RTW89_MKK][11] = 127, ++ [1][0][2][0][RTW89_IC][11] = 127, ++ [1][0][2][0][RTW89_KCC][11] = 127, ++ [1][0][2][0][RTW89_ACMA][11] = 127, ++ [1][0][2][0][RTW89_CHILE][11] = 127, ++ [1][0][2][0][RTW89_UKRAINE][11] = 127, ++ [1][0][2][0][RTW89_FCC][12] = 127, ++ [1][0][2][0][RTW89_ETSI][12] = 127, ++ [1][0][2][0][RTW89_MKK][12] = 127, ++ [1][0][2][0][RTW89_IC][12] = 127, ++ [1][0][2][0][RTW89_KCC][12] = 127, ++ [1][0][2][0][RTW89_ACMA][12] = 127, ++ [1][0][2][0][RTW89_CHILE][12] = 127, ++ [1][0][2][0][RTW89_UKRAINE][12] = 127, ++ [1][0][2][0][RTW89_FCC][13] = 127, ++ [1][0][2][0][RTW89_ETSI][13] = 127, ++ [1][0][2][0][RTW89_MKK][13] = 127, ++ [1][0][2][0][RTW89_IC][13] = 127, ++ [1][0][2][0][RTW89_KCC][13] = 127, ++ [1][0][2][0][RTW89_ACMA][13] = 127, ++ [1][0][2][0][RTW89_CHILE][13] = 127, ++ [1][0][2][0][RTW89_UKRAINE][13] = 127, ++ [1][1][2][0][RTW89_FCC][0] = 127, ++ [1][1][2][0][RTW89_ETSI][0] = 127, ++ [1][1][2][0][RTW89_MKK][0] = 127, ++ [1][1][2][0][RTW89_IC][0] = 127, ++ [1][1][2][0][RTW89_KCC][0] = 127, ++ [1][1][2][0][RTW89_ACMA][0] = 127, ++ [1][1][2][0][RTW89_CHILE][0] = 127, ++ [1][1][2][0][RTW89_UKRAINE][0] = 127, ++ [1][1][2][0][RTW89_FCC][1] = 127, ++ [1][1][2][0][RTW89_ETSI][1] = 127, ++ [1][1][2][0][RTW89_MKK][1] = 127, ++ [1][1][2][0][RTW89_IC][1] = 127, ++ [1][1][2][0][RTW89_KCC][1] = 127, ++ [1][1][2][0][RTW89_ACMA][1] = 127, ++ [1][1][2][0][RTW89_CHILE][1] = 127, ++ [1][1][2][0][RTW89_UKRAINE][1] = 127, ++ [1][1][2][0][RTW89_FCC][2] = 52, ++ [1][1][2][0][RTW89_ETSI][2] = 46, ++ [1][1][2][0][RTW89_MKK][2] = 64, ++ [1][1][2][0][RTW89_IC][2] = 52, ++ [1][1][2][0][RTW89_KCC][2] = 46, ++ [1][1][2][0][RTW89_ACMA][2] = 46, ++ [1][1][2][0][RTW89_CHILE][2] = 48, ++ [1][1][2][0][RTW89_UKRAINE][2] = 46, ++ [1][1][2][0][RTW89_FCC][3] = 52, ++ [1][1][2][0][RTW89_ETSI][3] = 46, ++ [1][1][2][0][RTW89_MKK][3] = 64, ++ [1][1][2][0][RTW89_IC][3] = 52, ++ [1][1][2][0][RTW89_KCC][3] = 46, ++ [1][1][2][0][RTW89_ACMA][3] = 46, ++ [1][1][2][0][RTW89_CHILE][3] = 48, ++ [1][1][2][0][RTW89_UKRAINE][3] = 46, ++ [1][1][2][0][RTW89_FCC][4] = 56, ++ [1][1][2][0][RTW89_ETSI][4] = 46, ++ [1][1][2][0][RTW89_MKK][4] = 64, ++ [1][1][2][0][RTW89_IC][4] = 56, ++ [1][1][2][0][RTW89_KCC][4] = 46, ++ [1][1][2][0][RTW89_ACMA][4] = 46, ++ [1][1][2][0][RTW89_CHILE][4] = 48, ++ [1][1][2][0][RTW89_UKRAINE][4] = 46, ++ [1][1][2][0][RTW89_FCC][5] = 60, ++ [1][1][2][0][RTW89_ETSI][5] = 46, ++ [1][1][2][0][RTW89_MKK][5] = 64, ++ [1][1][2][0][RTW89_IC][5] = 60, ++ [1][1][2][0][RTW89_KCC][5] = 46, ++ [1][1][2][0][RTW89_ACMA][5] = 46, ++ [1][1][2][0][RTW89_CHILE][5] = 48, ++ [1][1][2][0][RTW89_UKRAINE][5] = 46, ++ [1][1][2][0][RTW89_FCC][6] = 54, ++ [1][1][2][0][RTW89_ETSI][6] = 46, ++ [1][1][2][0][RTW89_MKK][6] = 64, ++ [1][1][2][0][RTW89_IC][6] = 52, ++ [1][1][2][0][RTW89_KCC][6] = 46, ++ [1][1][2][0][RTW89_ACMA][6] = 46, ++ [1][1][2][0][RTW89_CHILE][6] = 48, ++ [1][1][2][0][RTW89_UKRAINE][6] = 46, ++ [1][1][2][0][RTW89_FCC][7] = 50, ++ [1][1][2][0][RTW89_ETSI][7] = 46, ++ [1][1][2][0][RTW89_MKK][7] = 64, ++ [1][1][2][0][RTW89_IC][7] = 48, ++ [1][1][2][0][RTW89_KCC][7] = 46, ++ [1][1][2][0][RTW89_ACMA][7] = 46, ++ [1][1][2][0][RTW89_CHILE][7] = 48, ++ [1][1][2][0][RTW89_UKRAINE][7] = 46, ++ [1][1][2][0][RTW89_FCC][8] = 50, ++ [1][1][2][0][RTW89_ETSI][8] = 46, ++ [1][1][2][0][RTW89_MKK][8] = 64, ++ [1][1][2][0][RTW89_IC][8] = 48, ++ [1][1][2][0][RTW89_KCC][8] = 46, ++ [1][1][2][0][RTW89_ACMA][8] = 46, ++ [1][1][2][0][RTW89_CHILE][8] = 48, ++ [1][1][2][0][RTW89_UKRAINE][8] = 46, ++ [1][1][2][0][RTW89_FCC][9] = 38, ++ [1][1][2][0][RTW89_ETSI][9] = 46, ++ [1][1][2][0][RTW89_MKK][9] = 64, ++ [1][1][2][0][RTW89_IC][9] = 38, ++ [1][1][2][0][RTW89_KCC][9] = 46, ++ [1][1][2][0][RTW89_ACMA][9] = 46, ++ [1][1][2][0][RTW89_CHILE][9] = 48, ++ [1][1][2][0][RTW89_UKRAINE][9] = 46, ++ [1][1][2][0][RTW89_FCC][10] = 36, ++ [1][1][2][0][RTW89_ETSI][10] = 46, ++ [1][1][2][0][RTW89_MKK][10] = 64, ++ [1][1][2][0][RTW89_IC][10] = 36, ++ [1][1][2][0][RTW89_KCC][10] = 46, ++ [1][1][2][0][RTW89_ACMA][10] = 46, ++ [1][1][2][0][RTW89_CHILE][10] = 48, ++ [1][1][2][0][RTW89_UKRAINE][10] = 46, ++ [1][1][2][0][RTW89_FCC][11] = 127, ++ [1][1][2][0][RTW89_ETSI][11] = 127, ++ [1][1][2][0][RTW89_MKK][11] = 127, ++ [1][1][2][0][RTW89_IC][11] = 127, ++ [1][1][2][0][RTW89_KCC][11] = 127, ++ [1][1][2][0][RTW89_ACMA][11] = 127, ++ [1][1][2][0][RTW89_CHILE][11] = 127, ++ [1][1][2][0][RTW89_UKRAINE][11] = 127, ++ [1][1][2][0][RTW89_FCC][12] = 127, ++ [1][1][2][0][RTW89_ETSI][12] = 127, ++ [1][1][2][0][RTW89_MKK][12] = 127, ++ [1][1][2][0][RTW89_IC][12] = 127, ++ [1][1][2][0][RTW89_KCC][12] = 127, ++ [1][1][2][0][RTW89_ACMA][12] = 127, ++ [1][1][2][0][RTW89_CHILE][12] = 127, ++ [1][1][2][0][RTW89_UKRAINE][12] = 127, ++ [1][1][2][0][RTW89_FCC][13] = 127, ++ [1][1][2][0][RTW89_ETSI][13] = 127, ++ [1][1][2][0][RTW89_MKK][13] = 127, ++ [1][1][2][0][RTW89_IC][13] = 127, ++ [1][1][2][0][RTW89_KCC][13] = 127, ++ [1][1][2][0][RTW89_ACMA][13] = 127, ++ [1][1][2][0][RTW89_CHILE][13] = 127, ++ [1][1][2][0][RTW89_UKRAINE][13] = 127, ++ [1][1][2][1][RTW89_FCC][0] = 127, ++ [1][1][2][1][RTW89_ETSI][0] = 127, ++ [1][1][2][1][RTW89_MKK][0] = 127, ++ [1][1][2][1][RTW89_IC][0] = 127, ++ [1][1][2][1][RTW89_KCC][0] = 127, ++ [1][1][2][1][RTW89_ACMA][0] = 127, ++ [1][1][2][1][RTW89_CHILE][0] = 127, ++ [1][1][2][1][RTW89_UKRAINE][0] = 127, ++ [1][1][2][1][RTW89_FCC][1] = 127, ++ [1][1][2][1][RTW89_ETSI][1] = 127, ++ [1][1][2][1][RTW89_MKK][1] = 127, ++ [1][1][2][1][RTW89_IC][1] = 127, ++ [1][1][2][1][RTW89_KCC][1] = 127, ++ [1][1][2][1][RTW89_ACMA][1] = 127, ++ [1][1][2][1][RTW89_CHILE][1] = 127, ++ [1][1][2][1][RTW89_UKRAINE][1] = 127, ++ [1][1][2][1][RTW89_FCC][2] = 52, ++ [1][1][2][1][RTW89_ETSI][2] = 34, ++ [1][1][2][1][RTW89_MKK][2] = 64, ++ [1][1][2][1][RTW89_IC][2] = 52, ++ [1][1][2][1][RTW89_KCC][2] = 34, ++ [1][1][2][1][RTW89_ACMA][2] = 34, ++ [1][1][2][1][RTW89_CHILE][2] = 36, ++ [1][1][2][1][RTW89_UKRAINE][2] = 34, ++ [1][1][2][1][RTW89_FCC][3] = 52, ++ [1][1][2][1][RTW89_ETSI][3] = 34, ++ [1][1][2][1][RTW89_MKK][3] = 64, ++ [1][1][2][1][RTW89_IC][3] = 52, ++ [1][1][2][1][RTW89_KCC][3] = 34, ++ [1][1][2][1][RTW89_ACMA][3] = 34, ++ [1][1][2][1][RTW89_CHILE][3] = 36, ++ [1][1][2][1][RTW89_UKRAINE][3] = 34, ++ [1][1][2][1][RTW89_FCC][4] = 56, ++ [1][1][2][1][RTW89_ETSI][4] = 34, ++ [1][1][2][1][RTW89_MKK][4] = 64, ++ [1][1][2][1][RTW89_IC][4] = 56, ++ [1][1][2][1][RTW89_KCC][4] = 34, ++ [1][1][2][1][RTW89_ACMA][4] = 34, ++ [1][1][2][1][RTW89_CHILE][4] = 36, ++ [1][1][2][1][RTW89_UKRAINE][4] = 34, ++ [1][1][2][1][RTW89_FCC][5] = 60, ++ [1][1][2][1][RTW89_ETSI][5] = 34, ++ [1][1][2][1][RTW89_MKK][5] = 64, ++ [1][1][2][1][RTW89_IC][5] = 60, ++ [1][1][2][1][RTW89_KCC][5] = 34, ++ [1][1][2][1][RTW89_ACMA][5] = 34, ++ [1][1][2][1][RTW89_CHILE][5] = 36, ++ [1][1][2][1][RTW89_UKRAINE][5] = 34, ++ [1][1][2][1][RTW89_FCC][6] = 54, ++ [1][1][2][1][RTW89_ETSI][6] = 34, ++ [1][1][2][1][RTW89_MKK][6] = 64, ++ [1][1][2][1][RTW89_IC][6] = 52, ++ [1][1][2][1][RTW89_KCC][6] = 34, ++ [1][1][2][1][RTW89_ACMA][6] = 34, ++ [1][1][2][1][RTW89_CHILE][6] = 36, ++ [1][1][2][1][RTW89_UKRAINE][6] = 34, ++ [1][1][2][1][RTW89_FCC][7] = 50, ++ [1][1][2][1][RTW89_ETSI][7] = 34, ++ [1][1][2][1][RTW89_MKK][7] = 64, ++ [1][1][2][1][RTW89_IC][7] = 48, ++ [1][1][2][1][RTW89_KCC][7] = 34, ++ [1][1][2][1][RTW89_ACMA][7] = 34, ++ [1][1][2][1][RTW89_CHILE][7] = 36, ++ [1][1][2][1][RTW89_UKRAINE][7] = 34, ++ [1][1][2][1][RTW89_FCC][8] = 50, ++ [1][1][2][1][RTW89_ETSI][8] = 34, ++ [1][1][2][1][RTW89_MKK][8] = 64, ++ [1][1][2][1][RTW89_IC][8] = 48, ++ [1][1][2][1][RTW89_KCC][8] = 34, ++ [1][1][2][1][RTW89_ACMA][8] = 34, ++ [1][1][2][1][RTW89_CHILE][8] = 36, ++ [1][1][2][1][RTW89_UKRAINE][8] = 34, ++ [1][1][2][1][RTW89_FCC][9] = 38, ++ [1][1][2][1][RTW89_ETSI][9] = 34, ++ [1][1][2][1][RTW89_MKK][9] = 64, ++ [1][1][2][1][RTW89_IC][9] = 38, ++ [1][1][2][1][RTW89_KCC][9] = 34, ++ [1][1][2][1][RTW89_ACMA][9] = 34, ++ [1][1][2][1][RTW89_CHILE][9] = 36, ++ [1][1][2][1][RTW89_UKRAINE][9] = 34, ++ [1][1][2][1][RTW89_FCC][10] = 36, ++ [1][1][2][1][RTW89_ETSI][10] = 34, ++ [1][1][2][1][RTW89_MKK][10] = 64, ++ [1][1][2][1][RTW89_IC][10] = 36, ++ [1][1][2][1][RTW89_KCC][10] = 34, ++ [1][1][2][1][RTW89_ACMA][10] = 34, ++ [1][1][2][1][RTW89_CHILE][10] = 36, ++ [1][1][2][1][RTW89_UKRAINE][10] = 34, ++ [1][1][2][1][RTW89_FCC][11] = 127, ++ [1][1][2][1][RTW89_ETSI][11] = 127, ++ [1][1][2][1][RTW89_MKK][11] = 127, ++ [1][1][2][1][RTW89_IC][11] = 127, ++ [1][1][2][1][RTW89_KCC][11] = 127, ++ [1][1][2][1][RTW89_ACMA][11] = 127, ++ [1][1][2][1][RTW89_CHILE][11] = 127, ++ [1][1][2][1][RTW89_UKRAINE][11] = 127, ++ [1][1][2][1][RTW89_FCC][12] = 127, ++ [1][1][2][1][RTW89_ETSI][12] = 127, ++ [1][1][2][1][RTW89_MKK][12] = 127, ++ [1][1][2][1][RTW89_IC][12] = 127, ++ [1][1][2][1][RTW89_KCC][12] = 127, ++ [1][1][2][1][RTW89_ACMA][12] = 127, ++ [1][1][2][1][RTW89_CHILE][12] = 127, ++ [1][1][2][1][RTW89_UKRAINE][12] = 127, ++ [1][1][2][1][RTW89_FCC][13] = 127, ++ [1][1][2][1][RTW89_ETSI][13] = 127, ++ [1][1][2][1][RTW89_MKK][13] = 127, ++ [1][1][2][1][RTW89_IC][13] = 127, ++ [1][1][2][1][RTW89_KCC][13] = 127, ++ [1][1][2][1][RTW89_ACMA][13] = 127, ++ [1][1][2][1][RTW89_CHILE][13] = 127, ++ [1][1][2][1][RTW89_UKRAINE][13] = 127, + }; + + const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] + [RTW89_RS_LMT_NUM][RTW89_BF_NUM] + [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = { +- [0][0][1][0][0][0] = 30, +- [0][0][1][0][0][2] = 30, +- [0][0][1][0][0][4] = 30, +- [0][0][1][0][0][6] = 30, +- [0][0][1][0][0][8] = 52, +- [0][0][1][0][0][10] = 52, +- [0][0][1][0][0][12] = 52, +- [0][0][1][0][0][14] = 52, +- [0][0][1][0][0][15] = 52, +- [0][0][1][0][0][17] = 52, +- [0][0][1][0][0][19] = 52, +- [0][0][1][0][0][21] = 52, +- [0][0][1][0][0][23] = 52, +- [0][0][1][0][0][25] = 52, +- [0][0][1][0][0][27] = 52, +- [0][0][1][0][0][29] = 52, +- [0][0][1][0][0][31] = 52, +- [0][0][1][0][0][33] = 52, +- [0][0][1][0][0][35] = 52, +- [0][0][1][0][0][37] = 54, +- [0][0][1][0][0][38] = 28, +- [0][0][1][0][0][40] = 28, +- [0][0][1][0][0][42] = 28, +- [0][0][1][0][0][44] = 28, +- [0][0][1][0][0][46] = 28, +- [0][1][1][0][0][0] = 18, +- [0][1][1][0][0][2] = 18, +- [0][1][1][0][0][4] = 18, +- [0][1][1][0][0][6] = 18, +- [0][1][1][0][0][8] = 40, +- [0][1][1][0][0][10] = 40, +- [0][1][1][0][0][12] = 40, +- [0][1][1][0][0][14] = 40, +- [0][1][1][0][0][15] = 40, +- [0][1][1][0][0][17] = 40, +- [0][1][1][0][0][19] = 40, +- [0][1][1][0][0][21] = 40, +- [0][1][1][0][0][23] = 40, +- [0][1][1][0][0][25] = 40, +- [0][1][1][0][0][27] = 40, +- [0][1][1][0][0][29] = 40, +- [0][1][1][0][0][31] = 40, +- [0][1][1][0][0][33] = 40, +- [0][1][1][0][0][35] = 40, +- [0][1][1][0][0][37] = 42, +- [0][1][1][0][0][38] = 16, +- [0][1][1][0][0][40] = 16, +- [0][1][1][0][0][42] = 16, +- [0][1][1][0][0][44] = 16, +- [0][1][1][0][0][46] = 16, +- [0][0][2][0][0][0] = 30, +- [0][0][2][0][0][2] = 30, +- [0][0][2][0][0][4] = 30, +- [0][0][2][0][0][6] = 30, +- [0][0][2][0][0][8] = 52, +- [0][0][2][0][0][10] = 52, +- [0][0][2][0][0][12] = 52, +- [0][0][2][0][0][14] = 52, +- [0][0][2][0][0][15] = 52, +- [0][0][2][0][0][17] = 52, +- [0][0][2][0][0][19] = 52, +- [0][0][2][0][0][21] = 52, +- [0][0][2][0][0][23] = 52, +- [0][0][2][0][0][25] = 52, +- [0][0][2][0][0][27] = 52, +- [0][0][2][0][0][29] = 52, +- [0][0][2][0][0][31] = 52, +- [0][0][2][0][0][33] = 52, +- [0][0][2][0][0][35] = 52, +- [0][0][2][0][0][37] = 54, +- [0][0][2][0][0][38] = 28, +- [0][0][2][0][0][40] = 28, +- [0][0][2][0][0][42] = 28, +- [0][0][2][0][0][44] = 28, +- [0][0][2][0][0][46] = 28, +- [0][1][2][0][0][0] = 18, +- [0][1][2][0][0][2] = 18, +- [0][1][2][0][0][4] = 18, +- [0][1][2][0][0][6] = 18, +- [0][1][2][0][0][8] = 40, +- [0][1][2][0][0][10] = 40, +- [0][1][2][0][0][12] = 40, +- [0][1][2][0][0][14] = 40, +- [0][1][2][0][0][15] = 40, +- [0][1][2][0][0][17] = 40, +- [0][1][2][0][0][19] = 40, +- [0][1][2][0][0][21] = 40, +- [0][1][2][0][0][23] = 40, +- [0][1][2][0][0][25] = 40, +- [0][1][2][0][0][27] = 40, +- [0][1][2][0][0][29] = 40, +- [0][1][2][0][0][31] = 40, +- [0][1][2][0][0][33] = 40, +- [0][1][2][0][0][35] = 40, +- [0][1][2][0][0][37] = 42, +- [0][1][2][0][0][38] = 16, +- [0][1][2][0][0][40] = 16, +- [0][1][2][0][0][42] = 16, +- [0][1][2][0][0][44] = 16, +- [0][1][2][0][0][46] = 16, +- [0][1][2][1][0][0] = 6, +- [0][1][2][1][0][2] = 6, +- [0][1][2][1][0][4] = 6, +- [0][1][2][1][0][6] = 6, +- [0][1][2][1][0][8] = 28, +- [0][1][2][1][0][10] = 28, +- [0][1][2][1][0][12] = 28, +- [0][1][2][1][0][14] = 28, +- [0][1][2][1][0][15] = 28, +- [0][1][2][1][0][17] = 28, +- [0][1][2][1][0][19] = 28, +- [0][1][2][1][0][21] = 28, +- [0][1][2][1][0][23] = 28, +- [0][1][2][1][0][25] = 28, +- [0][1][2][1][0][27] = 28, +- [0][1][2][1][0][29] = 28, +- [0][1][2][1][0][31] = 28, +- [0][1][2][1][0][33] = 28, +- [0][1][2][1][0][35] = 28, +- [0][1][2][1][0][37] = 30, +- [0][1][2][1][0][38] = 4, +- [0][1][2][1][0][40] = 4, +- [0][1][2][1][0][42] = 4, +- [0][1][2][1][0][44] = 4, +- [0][1][2][1][0][46] = 4, +- [1][0][2][0][0][1] = 30, +- [1][0][2][0][0][5] = 30, +- [1][0][2][0][0][9] = 52, +- [1][0][2][0][0][13] = 52, +- [1][0][2][0][0][16] = 52, +- [1][0][2][0][0][20] = 52, +- [1][0][2][0][0][24] = 52, +- [1][0][2][0][0][28] = 52, +- [1][0][2][0][0][32] = 52, +- [1][0][2][0][0][36] = 54, +- [1][0][2][0][0][39] = 28, +- [1][0][2][0][0][43] = 28, +- [1][1][2][0][0][1] = 18, +- [1][1][2][0][0][5] = 18, +- [1][1][2][0][0][9] = 40, +- [1][1][2][0][0][13] = 40, +- [1][1][2][0][0][16] = 40, +- [1][1][2][0][0][20] = 40, +- [1][1][2][0][0][24] = 40, +- [1][1][2][0][0][28] = 40, +- [1][1][2][0][0][32] = 40, +- [1][1][2][0][0][36] = 42, +- [1][1][2][0][0][39] = 16, +- [1][1][2][0][0][43] = 16, +- [1][1][2][1][0][1] = 6, +- [1][1][2][1][0][5] = 6, +- [1][1][2][1][0][9] = 28, +- [1][1][2][1][0][13] = 28, +- [1][1][2][1][0][16] = 28, +- [1][1][2][1][0][20] = 28, +- [1][1][2][1][0][24] = 28, +- [1][1][2][1][0][28] = 28, +- [1][1][2][1][0][32] = 28, +- [1][1][2][1][0][36] = 30, +- [1][1][2][1][0][39] = 4, +- [1][1][2][1][0][43] = 4, +- [2][0][2][0][0][3] = 30, +- [2][0][2][0][0][11] = 52, +- [2][0][2][0][0][18] = 52, +- [2][0][2][0][0][26] = 52, +- [2][0][2][0][0][34] = 54, +- [2][0][2][0][0][41] = 28, +- [2][1][2][0][0][3] = 18, +- [2][1][2][0][0][11] = 40, +- [2][1][2][0][0][18] = 40, +- [2][1][2][0][0][26] = 40, +- [2][1][2][0][0][34] = 42, +- [2][1][2][0][0][41] = 16, +- [2][1][2][1][0][3] = 6, +- [2][1][2][1][0][11] = 28, +- [2][1][2][1][0][18] = 28, +- [2][1][2][1][0][26] = 28, +- [2][1][2][1][0][34] = 30, +- [2][1][2][1][0][41] = 4, +- [0][0][1][0][2][0] = 76, +- [0][0][1][0][1][0] = 58, +- [0][0][1][0][3][0] = 62, +- [0][0][1][0][5][0] = 62, +- [0][0][1][0][6][0] = 58, +- [0][0][1][0][9][0] = 58, +- [0][0][1][0][8][0] = 30, +- [0][0][1][0][11][0] = 52, +- [0][0][1][0][2][2] = 76, +- [0][0][1][0][1][2] = 58, +- [0][0][1][0][3][2] = 62, +- [0][0][1][0][5][2] = 62, +- [0][0][1][0][6][2] = 58, +- [0][0][1][0][9][2] = 58, +- [0][0][1][0][8][2] = 30, +- [0][0][1][0][11][2] = 52, +- [0][0][1][0][2][4] = 76, +- [0][0][1][0][1][4] = 58, +- [0][0][1][0][3][4] = 62, +- [0][0][1][0][5][4] = 62, +- [0][0][1][0][6][4] = 58, +- [0][0][1][0][9][4] = 58, +- [0][0][1][0][8][4] = 30, +- [0][0][1][0][11][4] = 52, +- [0][0][1][0][2][6] = 76, +- [0][0][1][0][1][6] = 58, +- [0][0][1][0][3][6] = 62, +- [0][0][1][0][5][6] = 62, +- [0][0][1][0][6][6] = 54, +- [0][0][1][0][9][6] = 58, +- [0][0][1][0][8][6] = 30, +- [0][0][1][0][11][6] = 52, +- [0][0][1][0][2][8] = 76, +- [0][0][1][0][1][8] = 58, +- [0][0][1][0][3][8] = 62, +- [0][0][1][0][5][8] = 64, +- [0][0][1][0][6][8] = 58, +- [0][0][1][0][9][8] = 58, +- [0][0][1][0][8][8] = 54, +- [0][0][1][0][11][8] = 52, +- [0][0][1][0][2][10] = 76, +- [0][0][1][0][1][10] = 58, +- [0][0][1][0][3][10] = 62, +- [0][0][1][0][5][10] = 64, +- [0][0][1][0][6][10] = 58, +- [0][0][1][0][9][10] = 58, +- [0][0][1][0][8][10] = 54, +- [0][0][1][0][11][10] = 52, +- [0][0][1][0][2][12] = 76, +- [0][0][1][0][1][12] = 58, +- [0][0][1][0][3][12] = 62, +- [0][0][1][0][5][12] = 64, +- [0][0][1][0][6][12] = 58, +- [0][0][1][0][9][12] = 58, +- [0][0][1][0][8][12] = 54, +- [0][0][1][0][11][12] = 52, +- [0][0][1][0][2][14] = 76, +- [0][0][1][0][1][14] = 58, +- [0][0][1][0][3][14] = 62, +- [0][0][1][0][5][14] = 64, +- [0][0][1][0][6][14] = 58, +- [0][0][1][0][9][14] = 58, +- [0][0][1][0][8][14] = 54, +- [0][0][1][0][11][14] = 52, +- [0][0][1][0][2][15] = 76, +- [0][0][1][0][1][15] = 58, +- [0][0][1][0][3][15] = 76, +- [0][0][1][0][5][15] = 76, +- [0][0][1][0][6][15] = 58, +- [0][0][1][0][9][15] = 58, +- [0][0][1][0][8][15] = 54, +- [0][0][1][0][11][15] = 52, +- [0][0][1][0][2][17] = 76, +- [0][0][1][0][1][17] = 58, +- [0][0][1][0][3][17] = 76, +- [0][0][1][0][5][17] = 76, +- [0][0][1][0][6][17] = 58, +- [0][0][1][0][9][17] = 58, +- [0][0][1][0][8][17] = 54, +- [0][0][1][0][11][17] = 52, +- [0][0][1][0][2][19] = 76, +- [0][0][1][0][1][19] = 58, +- [0][0][1][0][3][19] = 76, +- [0][0][1][0][5][19] = 76, +- [0][0][1][0][6][19] = 58, +- [0][0][1][0][9][19] = 58, +- [0][0][1][0][8][19] = 54, +- [0][0][1][0][11][19] = 52, +- [0][0][1][0][2][21] = 76, +- [0][0][1][0][1][21] = 58, +- [0][0][1][0][3][21] = 76, +- [0][0][1][0][5][21] = 76, +- [0][0][1][0][6][21] = 58, +- [0][0][1][0][9][21] = 58, +- [0][0][1][0][8][21] = 54, +- [0][0][1][0][11][21] = 52, +- [0][0][1][0][2][23] = 76, +- [0][0][1][0][1][23] = 58, +- [0][0][1][0][3][23] = 76, +- [0][0][1][0][5][23] = 76, +- [0][0][1][0][6][23] = 58, +- [0][0][1][0][9][23] = 58, +- [0][0][1][0][8][23] = 54, +- [0][0][1][0][11][23] = 52, +- [0][0][1][0][2][25] = 76, +- [0][0][1][0][1][25] = 58, +- [0][0][1][0][3][25] = 76, +- [0][0][1][0][5][25] = 127, +- [0][0][1][0][6][25] = 58, +- [0][0][1][0][9][25] = 127, +- [0][0][1][0][8][25] = 54, +- [0][0][1][0][11][25] = 52, +- [0][0][1][0][2][27] = 76, +- [0][0][1][0][1][27] = 58, +- [0][0][1][0][3][27] = 76, +- [0][0][1][0][5][27] = 127, +- [0][0][1][0][6][27] = 58, +- [0][0][1][0][9][27] = 127, +- [0][0][1][0][8][27] = 54, +- [0][0][1][0][11][27] = 52, +- [0][0][1][0][2][29] = 76, +- [0][0][1][0][1][29] = 58, +- [0][0][1][0][3][29] = 76, +- [0][0][1][0][5][29] = 127, +- [0][0][1][0][6][29] = 58, +- [0][0][1][0][9][29] = 127, +- [0][0][1][0][8][29] = 54, +- [0][0][1][0][11][29] = 52, +- [0][0][1][0][2][31] = 76, +- [0][0][1][0][1][31] = 58, +- [0][0][1][0][3][31] = 76, +- [0][0][1][0][5][31] = 76, +- [0][0][1][0][6][31] = 58, +- [0][0][1][0][9][31] = 58, +- [0][0][1][0][8][31] = 54, +- [0][0][1][0][11][31] = 52, +- [0][0][1][0][2][33] = 76, +- [0][0][1][0][1][33] = 58, +- [0][0][1][0][3][33] = 76, +- [0][0][1][0][5][33] = 76, +- [0][0][1][0][6][33] = 58, +- [0][0][1][0][9][33] = 58, +- [0][0][1][0][8][33] = 54, +- [0][0][1][0][11][33] = 52, +- [0][0][1][0][2][35] = 74, +- [0][0][1][0][1][35] = 58, +- [0][0][1][0][3][35] = 76, +- [0][0][1][0][5][35] = 74, +- [0][0][1][0][6][35] = 58, +- [0][0][1][0][9][35] = 58, +- [0][0][1][0][8][35] = 54, +- [0][0][1][0][11][35] = 52, +- [0][0][1][0][2][37] = 76, +- [0][0][1][0][1][37] = 127, +- [0][0][1][0][3][37] = 76, +- [0][0][1][0][5][37] = 76, +- [0][0][1][0][6][37] = 58, +- [0][0][1][0][9][37] = 76, +- [0][0][1][0][8][37] = 54, +- [0][0][1][0][11][37] = 127, +- [0][0][1][0][2][38] = 76, +- [0][0][1][0][1][38] = 28, +- [0][0][1][0][3][38] = 127, +- [0][0][1][0][5][38] = 76, +- [0][0][1][0][6][38] = 28, +- [0][0][1][0][9][38] = 76, +- [0][0][1][0][8][38] = 54, +- [0][0][1][0][11][38] = 52, +- [0][0][1][0][2][40] = 76, +- [0][0][1][0][1][40] = 28, +- [0][0][1][0][3][40] = 127, +- [0][0][1][0][5][40] = 76, +- [0][0][1][0][6][40] = 28, +- [0][0][1][0][9][40] = 76, +- [0][0][1][0][8][40] = 54, +- [0][0][1][0][11][40] = 52, +- [0][0][1][0][2][42] = 76, +- [0][0][1][0][1][42] = 28, +- [0][0][1][0][3][42] = 127, +- [0][0][1][0][5][42] = 76, +- [0][0][1][0][6][42] = 28, +- [0][0][1][0][9][42] = 76, +- [0][0][1][0][8][42] = 54, +- [0][0][1][0][11][42] = 52, +- [0][0][1][0][2][44] = 76, +- [0][0][1][0][1][44] = 28, +- [0][0][1][0][3][44] = 127, +- [0][0][1][0][5][44] = 76, +- [0][0][1][0][6][44] = 28, +- [0][0][1][0][9][44] = 76, +- [0][0][1][0][8][44] = 54, +- [0][0][1][0][11][44] = 52, +- [0][0][1][0][2][46] = 76, +- [0][0][1][0][1][46] = 28, +- [0][0][1][0][3][46] = 127, +- [0][0][1][0][5][46] = 76, +- [0][0][1][0][6][46] = 28, +- [0][0][1][0][9][46] = 76, +- [0][0][1][0][8][46] = 54, +- [0][0][1][0][11][46] = 52, +- [0][1][1][0][2][0] = 68, +- [0][1][1][0][1][0] = 46, +- [0][1][1][0][3][0] = 50, +- [0][1][1][0][5][0] = 40, +- [0][1][1][0][6][0] = 46, +- [0][1][1][0][9][0] = 46, +- [0][1][1][0][8][0] = 18, +- [0][1][1][0][11][0] = 40, +- [0][1][1][0][2][2] = 68, +- [0][1][1][0][1][2] = 46, +- [0][1][1][0][3][2] = 50, +- [0][1][1][0][5][2] = 40, +- [0][1][1][0][6][2] = 46, +- [0][1][1][0][9][2] = 46, +- [0][1][1][0][8][2] = 18, +- [0][1][1][0][11][2] = 40, +- [0][1][1][0][2][4] = 68, +- [0][1][1][0][1][4] = 46, +- [0][1][1][0][3][4] = 50, +- [0][1][1][0][5][4] = 40, +- [0][1][1][0][6][4] = 46, +- [0][1][1][0][9][4] = 46, +- [0][1][1][0][8][4] = 18, +- [0][1][1][0][11][4] = 40, +- [0][1][1][0][2][6] = 68, +- [0][1][1][0][1][6] = 46, +- [0][1][1][0][3][6] = 50, +- [0][1][1][0][5][6] = 40, +- [0][1][1][0][6][6] = 36, +- [0][1][1][0][9][6] = 46, +- [0][1][1][0][8][6] = 18, +- [0][1][1][0][11][6] = 40, +- [0][1][1][0][2][8] = 68, +- [0][1][1][0][1][8] = 46, +- [0][1][1][0][3][8] = 50, +- [0][1][1][0][5][8] = 52, +- [0][1][1][0][6][8] = 46, +- [0][1][1][0][9][8] = 46, +- [0][1][1][0][8][8] = 42, +- [0][1][1][0][11][8] = 40, +- [0][1][1][0][2][10] = 68, +- [0][1][1][0][1][10] = 46, +- [0][1][1][0][3][10] = 50, +- [0][1][1][0][5][10] = 52, +- [0][1][1][0][6][10] = 46, +- [0][1][1][0][9][10] = 46, +- [0][1][1][0][8][10] = 42, +- [0][1][1][0][11][10] = 40, +- [0][1][1][0][2][12] = 68, +- [0][1][1][0][1][12] = 46, +- [0][1][1][0][3][12] = 50, +- [0][1][1][0][5][12] = 52, +- [0][1][1][0][6][12] = 46, +- [0][1][1][0][9][12] = 46, +- [0][1][1][0][8][12] = 42, +- [0][1][1][0][11][12] = 40, +- [0][1][1][0][2][14] = 68, +- [0][1][1][0][1][14] = 46, +- [0][1][1][0][3][14] = 50, +- [0][1][1][0][5][14] = 52, +- [0][1][1][0][6][14] = 46, +- [0][1][1][0][9][14] = 46, +- [0][1][1][0][8][14] = 42, +- [0][1][1][0][11][14] = 40, +- [0][1][1][0][2][15] = 68, +- [0][1][1][0][1][15] = 46, +- [0][1][1][0][3][15] = 70, +- [0][1][1][0][5][15] = 68, +- [0][1][1][0][6][15] = 46, +- [0][1][1][0][9][15] = 46, +- [0][1][1][0][8][15] = 42, +- [0][1][1][0][11][15] = 40, +- [0][1][1][0][2][17] = 68, +- [0][1][1][0][1][17] = 46, +- [0][1][1][0][3][17] = 70, +- [0][1][1][0][5][17] = 68, +- [0][1][1][0][6][17] = 46, +- [0][1][1][0][9][17] = 46, +- [0][1][1][0][8][17] = 42, +- [0][1][1][0][11][17] = 40, +- [0][1][1][0][2][19] = 68, +- [0][1][1][0][1][19] = 46, +- [0][1][1][0][3][19] = 70, +- [0][1][1][0][5][19] = 68, +- [0][1][1][0][6][19] = 46, +- [0][1][1][0][9][19] = 46, +- [0][1][1][0][8][19] = 42, +- [0][1][1][0][11][19] = 40, +- [0][1][1][0][2][21] = 68, +- [0][1][1][0][1][21] = 46, +- [0][1][1][0][3][21] = 70, +- [0][1][1][0][5][21] = 68, +- [0][1][1][0][6][21] = 46, +- [0][1][1][0][9][21] = 46, +- [0][1][1][0][8][21] = 42, +- [0][1][1][0][11][21] = 40, +- [0][1][1][0][2][23] = 68, +- [0][1][1][0][1][23] = 46, +- [0][1][1][0][3][23] = 70, +- [0][1][1][0][5][23] = 68, +- [0][1][1][0][6][23] = 46, +- [0][1][1][0][9][23] = 46, +- [0][1][1][0][8][23] = 42, +- [0][1][1][0][11][23] = 40, +- [0][1][1][0][2][25] = 68, +- [0][1][1][0][1][25] = 46, +- [0][1][1][0][3][25] = 70, +- [0][1][1][0][5][25] = 127, +- [0][1][1][0][6][25] = 46, +- [0][1][1][0][9][25] = 127, +- [0][1][1][0][8][25] = 42, +- [0][1][1][0][11][25] = 40, +- [0][1][1][0][2][27] = 68, +- [0][1][1][0][1][27] = 46, +- [0][1][1][0][3][27] = 70, +- [0][1][1][0][5][27] = 127, +- [0][1][1][0][6][27] = 46, +- [0][1][1][0][9][27] = 127, +- [0][1][1][0][8][27] = 42, +- [0][1][1][0][11][27] = 40, +- [0][1][1][0][2][29] = 68, +- [0][1][1][0][1][29] = 46, +- [0][1][1][0][3][29] = 70, +- [0][1][1][0][5][29] = 127, +- [0][1][1][0][6][29] = 46, +- [0][1][1][0][9][29] = 127, +- [0][1][1][0][8][29] = 42, +- [0][1][1][0][11][29] = 40, +- [0][1][1][0][2][31] = 68, +- [0][1][1][0][1][31] = 46, +- [0][1][1][0][3][31] = 70, +- [0][1][1][0][5][31] = 68, +- [0][1][1][0][6][31] = 46, +- [0][1][1][0][9][31] = 46, +- [0][1][1][0][8][31] = 42, +- [0][1][1][0][11][31] = 40, +- [0][1][1][0][2][33] = 68, +- [0][1][1][0][1][33] = 46, +- [0][1][1][0][3][33] = 70, +- [0][1][1][0][5][33] = 68, +- [0][1][1][0][6][33] = 46, +- [0][1][1][0][9][33] = 46, +- [0][1][1][0][8][33] = 42, +- [0][1][1][0][11][33] = 40, +- [0][1][1][0][2][35] = 66, +- [0][1][1][0][1][35] = 46, +- [0][1][1][0][3][35] = 70, +- [0][1][1][0][5][35] = 66, +- [0][1][1][0][6][35] = 46, +- [0][1][1][0][9][35] = 46, +- [0][1][1][0][8][35] = 42, +- [0][1][1][0][11][35] = 40, +- [0][1][1][0][2][37] = 68, +- [0][1][1][0][1][37] = 127, +- [0][1][1][0][3][37] = 70, +- [0][1][1][0][5][37] = 68, +- [0][1][1][0][6][37] = 46, +- [0][1][1][0][9][37] = 68, +- [0][1][1][0][8][37] = 42, +- [0][1][1][0][11][37] = 127, +- [0][1][1][0][2][38] = 76, +- [0][1][1][0][1][38] = 16, +- [0][1][1][0][3][38] = 127, +- [0][1][1][0][5][38] = 76, +- [0][1][1][0][6][38] = 16, +- [0][1][1][0][9][38] = 76, +- [0][1][1][0][8][38] = 42, +- [0][1][1][0][11][38] = 40, +- [0][1][1][0][2][40] = 76, +- [0][1][1][0][1][40] = 16, +- [0][1][1][0][3][40] = 127, +- [0][1][1][0][5][40] = 76, +- [0][1][1][0][6][40] = 16, +- [0][1][1][0][9][40] = 76, +- [0][1][1][0][8][40] = 42, +- [0][1][1][0][11][40] = 40, +- [0][1][1][0][2][42] = 76, +- [0][1][1][0][1][42] = 16, +- [0][1][1][0][3][42] = 127, +- [0][1][1][0][5][42] = 76, +- [0][1][1][0][6][42] = 16, +- [0][1][1][0][9][42] = 76, +- [0][1][1][0][8][42] = 42, +- [0][1][1][0][11][42] = 40, +- [0][1][1][0][2][44] = 76, +- [0][1][1][0][1][44] = 16, +- [0][1][1][0][3][44] = 127, +- [0][1][1][0][5][44] = 76, +- [0][1][1][0][6][44] = 16, +- [0][1][1][0][9][44] = 76, +- [0][1][1][0][8][44] = 42, +- [0][1][1][0][11][44] = 40, +- [0][1][1][0][2][46] = 76, +- [0][1][1][0][1][46] = 16, +- [0][1][1][0][3][46] = 127, +- [0][1][1][0][5][46] = 76, +- [0][1][1][0][6][46] = 16, +- [0][1][1][0][9][46] = 76, +- [0][1][1][0][8][46] = 42, +- [0][1][1][0][11][46] = 40, +- [0][0][2][0][2][0] = 76, +- [0][0][2][0][1][0] = 58, +- [0][0][2][0][3][0] = 62, +- [0][0][2][0][5][0] = 62, +- [0][0][2][0][6][0] = 58, +- [0][0][2][0][9][0] = 58, +- [0][0][2][0][8][0] = 30, +- [0][0][2][0][11][0] = 52, +- [0][0][2][0][2][2] = 76, +- [0][0][2][0][1][2] = 58, +- [0][0][2][0][3][2] = 62, +- [0][0][2][0][5][2] = 62, +- [0][0][2][0][6][2] = 58, +- [0][0][2][0][9][2] = 58, +- [0][0][2][0][8][2] = 30, +- [0][0][2][0][11][2] = 52, +- [0][0][2][0][2][4] = 76, +- [0][0][2][0][1][4] = 58, +- [0][0][2][0][3][4] = 62, +- [0][0][2][0][5][4] = 62, +- [0][0][2][0][6][4] = 58, +- [0][0][2][0][9][4] = 58, +- [0][0][2][0][8][4] = 30, +- [0][0][2][0][11][4] = 52, +- [0][0][2][0][2][6] = 76, +- [0][0][2][0][1][6] = 58, +- [0][0][2][0][3][6] = 62, +- [0][0][2][0][5][6] = 62, +- [0][0][2][0][6][6] = 54, +- [0][0][2][0][9][6] = 58, +- [0][0][2][0][8][6] = 30, +- [0][0][2][0][11][6] = 52, +- [0][0][2][0][2][8] = 76, +- [0][0][2][0][1][8] = 58, +- [0][0][2][0][3][8] = 62, +- [0][0][2][0][5][8] = 64, +- [0][0][2][0][6][8] = 58, +- [0][0][2][0][9][8] = 58, +- [0][0][2][0][8][8] = 54, +- [0][0][2][0][11][8] = 52, +- [0][0][2][0][2][10] = 76, +- [0][0][2][0][1][10] = 58, +- [0][0][2][0][3][10] = 62, +- [0][0][2][0][5][10] = 64, +- [0][0][2][0][6][10] = 58, +- [0][0][2][0][9][10] = 58, +- [0][0][2][0][8][10] = 54, +- [0][0][2][0][11][10] = 52, +- [0][0][2][0][2][12] = 76, +- [0][0][2][0][1][12] = 58, +- [0][0][2][0][3][12] = 62, +- [0][0][2][0][5][12] = 64, +- [0][0][2][0][6][12] = 58, +- [0][0][2][0][9][12] = 58, +- [0][0][2][0][8][12] = 54, +- [0][0][2][0][11][12] = 52, +- [0][0][2][0][2][14] = 76, +- [0][0][2][0][1][14] = 58, +- [0][0][2][0][3][14] = 62, +- [0][0][2][0][5][14] = 64, +- [0][0][2][0][6][14] = 58, +- [0][0][2][0][9][14] = 58, +- [0][0][2][0][8][14] = 54, +- [0][0][2][0][11][14] = 52, +- [0][0][2][0][2][15] = 74, +- [0][0][2][0][1][15] = 58, +- [0][0][2][0][3][15] = 76, +- [0][0][2][0][5][15] = 74, +- [0][0][2][0][6][15] = 58, +- [0][0][2][0][9][15] = 58, +- [0][0][2][0][8][15] = 54, +- [0][0][2][0][11][15] = 52, +- [0][0][2][0][2][17] = 76, +- [0][0][2][0][1][17] = 58, +- [0][0][2][0][3][17] = 76, +- [0][0][2][0][5][17] = 76, +- [0][0][2][0][6][17] = 58, +- [0][0][2][0][9][17] = 58, +- [0][0][2][0][8][17] = 54, +- [0][0][2][0][11][17] = 52, +- [0][0][2][0][2][19] = 76, +- [0][0][2][0][1][19] = 58, +- [0][0][2][0][3][19] = 76, +- [0][0][2][0][5][19] = 76, +- [0][0][2][0][6][19] = 58, +- [0][0][2][0][9][19] = 58, +- [0][0][2][0][8][19] = 54, +- [0][0][2][0][11][19] = 52, +- [0][0][2][0][2][21] = 76, +- [0][0][2][0][1][21] = 58, +- [0][0][2][0][3][21] = 76, +- [0][0][2][0][5][21] = 76, +- [0][0][2][0][6][21] = 58, +- [0][0][2][0][9][21] = 58, +- [0][0][2][0][8][21] = 54, +- [0][0][2][0][11][21] = 52, +- [0][0][2][0][2][23] = 76, +- [0][0][2][0][1][23] = 58, +- [0][0][2][0][3][23] = 76, +- [0][0][2][0][5][23] = 76, +- [0][0][2][0][6][23] = 58, +- [0][0][2][0][9][23] = 58, +- [0][0][2][0][8][23] = 54, +- [0][0][2][0][11][23] = 52, +- [0][0][2][0][2][25] = 76, +- [0][0][2][0][1][25] = 58, +- [0][0][2][0][3][25] = 76, +- [0][0][2][0][5][25] = 127, +- [0][0][2][0][6][25] = 58, +- [0][0][2][0][9][25] = 127, +- [0][0][2][0][8][25] = 54, +- [0][0][2][0][11][25] = 52, +- [0][0][2][0][2][27] = 76, +- [0][0][2][0][1][27] = 58, +- [0][0][2][0][3][27] = 76, +- [0][0][2][0][5][27] = 127, +- [0][0][2][0][6][27] = 58, +- [0][0][2][0][9][27] = 127, +- [0][0][2][0][8][27] = 54, +- [0][0][2][0][11][27] = 52, +- [0][0][2][0][2][29] = 76, +- [0][0][2][0][1][29] = 58, +- [0][0][2][0][3][29] = 76, +- [0][0][2][0][5][29] = 127, +- [0][0][2][0][6][29] = 58, +- [0][0][2][0][9][29] = 127, +- [0][0][2][0][8][29] = 54, +- [0][0][2][0][11][29] = 52, +- [0][0][2][0][2][31] = 76, +- [0][0][2][0][1][31] = 58, +- [0][0][2][0][3][31] = 76, +- [0][0][2][0][5][31] = 76, +- [0][0][2][0][6][31] = 58, +- [0][0][2][0][9][31] = 58, +- [0][0][2][0][8][31] = 54, +- [0][0][2][0][11][31] = 52, +- [0][0][2][0][2][33] = 76, +- [0][0][2][0][1][33] = 58, +- [0][0][2][0][3][33] = 76, +- [0][0][2][0][5][33] = 76, +- [0][0][2][0][6][33] = 58, +- [0][0][2][0][9][33] = 58, +- [0][0][2][0][8][33] = 54, +- [0][0][2][0][11][33] = 52, +- [0][0][2][0][2][35] = 70, +- [0][0][2][0][1][35] = 58, +- [0][0][2][0][3][35] = 76, +- [0][0][2][0][5][35] = 70, +- [0][0][2][0][6][35] = 58, +- [0][0][2][0][9][35] = 58, +- [0][0][2][0][8][35] = 54, +- [0][0][2][0][11][35] = 52, +- [0][0][2][0][2][37] = 76, +- [0][0][2][0][1][37] = 127, +- [0][0][2][0][3][37] = 76, +- [0][0][2][0][5][37] = 76, +- [0][0][2][0][6][37] = 58, +- [0][0][2][0][9][37] = 76, +- [0][0][2][0][8][37] = 54, +- [0][0][2][0][11][37] = 127, +- [0][0][2][0][2][38] = 76, +- [0][0][2][0][1][38] = 28, +- [0][0][2][0][3][38] = 127, +- [0][0][2][0][5][38] = 76, +- [0][0][2][0][6][38] = 28, +- [0][0][2][0][9][38] = 76, +- [0][0][2][0][8][38] = 54, +- [0][0][2][0][11][38] = 52, +- [0][0][2][0][2][40] = 76, +- [0][0][2][0][1][40] = 28, +- [0][0][2][0][3][40] = 127, +- [0][0][2][0][5][40] = 76, +- [0][0][2][0][6][40] = 28, +- [0][0][2][0][9][40] = 76, +- [0][0][2][0][8][40] = 54, +- [0][0][2][0][11][40] = 52, +- [0][0][2][0][2][42] = 76, +- [0][0][2][0][1][42] = 28, +- [0][0][2][0][3][42] = 127, +- [0][0][2][0][5][42] = 76, +- [0][0][2][0][6][42] = 28, +- [0][0][2][0][9][42] = 76, +- [0][0][2][0][8][42] = 54, +- [0][0][2][0][11][42] = 52, +- [0][0][2][0][2][44] = 76, +- [0][0][2][0][1][44] = 28, +- [0][0][2][0][3][44] = 127, +- [0][0][2][0][5][44] = 76, +- [0][0][2][0][6][44] = 28, +- [0][0][2][0][9][44] = 76, +- [0][0][2][0][8][44] = 54, +- [0][0][2][0][11][44] = 52, +- [0][0][2][0][2][46] = 76, +- [0][0][2][0][1][46] = 28, +- [0][0][2][0][3][46] = 127, +- [0][0][2][0][5][46] = 76, +- [0][0][2][0][6][46] = 28, +- [0][0][2][0][9][46] = 76, +- [0][0][2][0][8][46] = 54, +- [0][0][2][0][11][46] = 52, +- [0][1][2][0][2][0] = 68, +- [0][1][2][0][1][0] = 46, +- [0][1][2][0][3][0] = 50, +- [0][1][2][0][5][0] = 40, +- [0][1][2][0][6][0] = 46, +- [0][1][2][0][9][0] = 46, +- [0][1][2][0][8][0] = 18, +- [0][1][2][0][11][0] = 40, +- [0][1][2][0][2][2] = 68, +- [0][1][2][0][1][2] = 46, +- [0][1][2][0][3][2] = 50, +- [0][1][2][0][5][2] = 40, +- [0][1][2][0][6][2] = 46, +- [0][1][2][0][9][2] = 46, +- [0][1][2][0][8][2] = 18, +- [0][1][2][0][11][2] = 40, +- [0][1][2][0][2][4] = 68, +- [0][1][2][0][1][4] = 46, +- [0][1][2][0][3][4] = 50, +- [0][1][2][0][5][4] = 40, +- [0][1][2][0][6][4] = 46, +- [0][1][2][0][9][4] = 46, +- [0][1][2][0][8][4] = 18, +- [0][1][2][0][11][4] = 40, +- [0][1][2][0][2][6] = 68, +- [0][1][2][0][1][6] = 46, +- [0][1][2][0][3][6] = 50, +- [0][1][2][0][5][6] = 40, +- [0][1][2][0][6][6] = 36, +- [0][1][2][0][9][6] = 46, +- [0][1][2][0][8][6] = 18, +- [0][1][2][0][11][6] = 40, +- [0][1][2][0][2][8] = 68, +- [0][1][2][0][1][8] = 46, +- [0][1][2][0][3][8] = 50, +- [0][1][2][0][5][8] = 52, +- [0][1][2][0][6][8] = 46, +- [0][1][2][0][9][8] = 46, +- [0][1][2][0][8][8] = 42, +- [0][1][2][0][11][8] = 40, +- [0][1][2][0][2][10] = 68, +- [0][1][2][0][1][10] = 46, +- [0][1][2][0][3][10] = 50, +- [0][1][2][0][5][10] = 52, +- [0][1][2][0][6][10] = 46, +- [0][1][2][0][9][10] = 46, +- [0][1][2][0][8][10] = 42, +- [0][1][2][0][11][10] = 40, +- [0][1][2][0][2][12] = 68, +- [0][1][2][0][1][12] = 46, +- [0][1][2][0][3][12] = 50, +- [0][1][2][0][5][12] = 52, +- [0][1][2][0][6][12] = 46, +- [0][1][2][0][9][12] = 46, +- [0][1][2][0][8][12] = 42, +- [0][1][2][0][11][12] = 40, +- [0][1][2][0][2][14] = 68, +- [0][1][2][0][1][14] = 46, +- [0][1][2][0][3][14] = 50, +- [0][1][2][0][5][14] = 52, +- [0][1][2][0][6][14] = 46, +- [0][1][2][0][9][14] = 46, +- [0][1][2][0][8][14] = 42, +- [0][1][2][0][11][14] = 40, +- [0][1][2][0][2][15] = 68, +- [0][1][2][0][1][15] = 46, +- [0][1][2][0][3][15] = 70, +- [0][1][2][0][5][15] = 68, +- [0][1][2][0][6][15] = 46, +- [0][1][2][0][9][15] = 46, +- [0][1][2][0][8][15] = 42, +- [0][1][2][0][11][15] = 40, +- [0][1][2][0][2][17] = 68, +- [0][1][2][0][1][17] = 46, +- [0][1][2][0][3][17] = 70, +- [0][1][2][0][5][17] = 68, +- [0][1][2][0][6][17] = 46, +- [0][1][2][0][9][17] = 46, +- [0][1][2][0][8][17] = 42, +- [0][1][2][0][11][17] = 40, +- [0][1][2][0][2][19] = 68, +- [0][1][2][0][1][19] = 46, +- [0][1][2][0][3][19] = 70, +- [0][1][2][0][5][19] = 68, +- [0][1][2][0][6][19] = 46, +- [0][1][2][0][9][19] = 46, +- [0][1][2][0][8][19] = 42, +- [0][1][2][0][11][19] = 40, +- [0][1][2][0][2][21] = 68, +- [0][1][2][0][1][21] = 46, +- [0][1][2][0][3][21] = 70, +- [0][1][2][0][5][21] = 68, +- [0][1][2][0][6][21] = 46, +- [0][1][2][0][9][21] = 46, +- [0][1][2][0][8][21] = 42, +- [0][1][2][0][11][21] = 40, +- [0][1][2][0][2][23] = 68, +- [0][1][2][0][1][23] = 46, +- [0][1][2][0][3][23] = 70, +- [0][1][2][0][5][23] = 68, +- [0][1][2][0][6][23] = 46, +- [0][1][2][0][9][23] = 46, +- [0][1][2][0][8][23] = 42, +- [0][1][2][0][11][23] = 40, +- [0][1][2][0][2][25] = 68, +- [0][1][2][0][1][25] = 46, +- [0][1][2][0][3][25] = 70, +- [0][1][2][0][5][25] = 127, +- [0][1][2][0][6][25] = 46, +- [0][1][2][0][9][25] = 127, +- [0][1][2][0][8][25] = 42, +- [0][1][2][0][11][25] = 40, +- [0][1][2][0][2][27] = 68, +- [0][1][2][0][1][27] = 46, +- [0][1][2][0][3][27] = 70, +- [0][1][2][0][5][27] = 127, +- [0][1][2][0][6][27] = 46, +- [0][1][2][0][9][27] = 127, +- [0][1][2][0][8][27] = 42, +- [0][1][2][0][11][27] = 40, +- [0][1][2][0][2][29] = 68, +- [0][1][2][0][1][29] = 46, +- [0][1][2][0][3][29] = 70, +- [0][1][2][0][5][29] = 127, +- [0][1][2][0][6][29] = 46, +- [0][1][2][0][9][29] = 127, +- [0][1][2][0][8][29] = 42, +- [0][1][2][0][11][29] = 40, +- [0][1][2][0][2][31] = 68, +- [0][1][2][0][1][31] = 46, +- [0][1][2][0][3][31] = 70, +- [0][1][2][0][5][31] = 68, +- [0][1][2][0][6][31] = 46, +- [0][1][2][0][9][31] = 46, +- [0][1][2][0][8][31] = 42, +- [0][1][2][0][11][31] = 40, +- [0][1][2][0][2][33] = 68, +- [0][1][2][0][1][33] = 46, +- [0][1][2][0][3][33] = 70, +- [0][1][2][0][5][33] = 68, +- [0][1][2][0][6][33] = 46, +- [0][1][2][0][9][33] = 46, +- [0][1][2][0][8][33] = 42, +- [0][1][2][0][11][33] = 40, +- [0][1][2][0][2][35] = 64, +- [0][1][2][0][1][35] = 46, +- [0][1][2][0][3][35] = 70, +- [0][1][2][0][5][35] = 64, +- [0][1][2][0][6][35] = 46, +- [0][1][2][0][9][35] = 46, +- [0][1][2][0][8][35] = 42, +- [0][1][2][0][11][35] = 40, +- [0][1][2][0][2][37] = 68, +- [0][1][2][0][1][37] = 127, +- [0][1][2][0][3][37] = 70, +- [0][1][2][0][5][37] = 68, +- [0][1][2][0][6][37] = 46, +- [0][1][2][0][9][37] = 68, +- [0][1][2][0][8][37] = 42, +- [0][1][2][0][11][37] = 127, +- [0][1][2][0][2][38] = 76, +- [0][1][2][0][1][38] = 16, +- [0][1][2][0][3][38] = 127, +- [0][1][2][0][5][38] = 76, +- [0][1][2][0][6][38] = 16, +- [0][1][2][0][9][38] = 76, +- [0][1][2][0][8][38] = 42, +- [0][1][2][0][11][38] = 40, +- [0][1][2][0][2][40] = 76, +- [0][1][2][0][1][40] = 16, +- [0][1][2][0][3][40] = 127, +- [0][1][2][0][5][40] = 76, +- [0][1][2][0][6][40] = 16, +- [0][1][2][0][9][40] = 76, +- [0][1][2][0][8][40] = 42, +- [0][1][2][0][11][40] = 40, +- [0][1][2][0][2][42] = 76, +- [0][1][2][0][1][42] = 16, +- [0][1][2][0][3][42] = 127, +- [0][1][2][0][5][42] = 76, +- [0][1][2][0][6][42] = 16, +- [0][1][2][0][9][42] = 76, +- [0][1][2][0][8][42] = 42, +- [0][1][2][0][11][42] = 40, +- [0][1][2][0][2][44] = 76, +- [0][1][2][0][1][44] = 16, +- [0][1][2][0][3][44] = 127, +- [0][1][2][0][5][44] = 76, +- [0][1][2][0][6][44] = 16, +- [0][1][2][0][9][44] = 76, +- [0][1][2][0][8][44] = 42, +- [0][1][2][0][11][44] = 40, +- [0][1][2][0][2][46] = 76, +- [0][1][2][0][1][46] = 16, +- [0][1][2][0][3][46] = 127, +- [0][1][2][0][5][46] = 76, +- [0][1][2][0][6][46] = 16, +- [0][1][2][0][9][46] = 76, +- [0][1][2][0][8][46] = 42, +- [0][1][2][0][11][46] = 40, +- [0][1][2][1][2][0] = 68, +- [0][1][2][1][1][0] = 34, +- [0][1][2][1][3][0] = 50, +- [0][1][2][1][5][0] = 38, +- [0][1][2][1][6][0] = 34, +- [0][1][2][1][9][0] = 34, +- [0][1][2][1][8][0] = 6, +- [0][1][2][1][11][0] = 28, +- [0][1][2][1][2][2] = 68, +- [0][1][2][1][1][2] = 34, +- [0][1][2][1][3][2] = 50, +- [0][1][2][1][5][2] = 38, +- [0][1][2][1][6][2] = 34, +- [0][1][2][1][9][2] = 34, +- [0][1][2][1][8][2] = 6, +- [0][1][2][1][11][2] = 28, +- [0][1][2][1][2][4] = 68, +- [0][1][2][1][1][4] = 34, +- [0][1][2][1][3][4] = 50, +- [0][1][2][1][5][4] = 38, +- [0][1][2][1][6][4] = 34, +- [0][1][2][1][9][4] = 34, +- [0][1][2][1][8][4] = 6, +- [0][1][2][1][11][4] = 28, +- [0][1][2][1][2][6] = 68, +- [0][1][2][1][1][6] = 34, +- [0][1][2][1][3][6] = 50, +- [0][1][2][1][5][6] = 38, +- [0][1][2][1][6][6] = 34, +- [0][1][2][1][9][6] = 34, +- [0][1][2][1][8][6] = 6, +- [0][1][2][1][11][6] = 28, +- [0][1][2][1][2][8] = 68, +- [0][1][2][1][1][8] = 34, +- [0][1][2][1][3][8] = 50, +- [0][1][2][1][5][8] = 38, +- [0][1][2][1][6][8] = 34, +- [0][1][2][1][9][8] = 34, +- [0][1][2][1][8][8] = 30, +- [0][1][2][1][11][8] = 28, +- [0][1][2][1][2][10] = 68, +- [0][1][2][1][1][10] = 34, +- [0][1][2][1][3][10] = 50, +- [0][1][2][1][5][10] = 38, +- [0][1][2][1][6][10] = 34, +- [0][1][2][1][9][10] = 34, +- [0][1][2][1][8][10] = 30, +- [0][1][2][1][11][10] = 28, +- [0][1][2][1][2][12] = 68, +- [0][1][2][1][1][12] = 34, +- [0][1][2][1][3][12] = 50, +- [0][1][2][1][5][12] = 38, +- [0][1][2][1][6][12] = 34, +- [0][1][2][1][9][12] = 34, +- [0][1][2][1][8][12] = 30, +- [0][1][2][1][11][12] = 28, +- [0][1][2][1][2][14] = 68, +- [0][1][2][1][1][14] = 34, +- [0][1][2][1][3][14] = 50, +- [0][1][2][1][5][14] = 38, +- [0][1][2][1][6][14] = 34, +- [0][1][2][1][9][14] = 34, +- [0][1][2][1][8][14] = 30, +- [0][1][2][1][11][14] = 28, +- [0][1][2][1][2][15] = 68, +- [0][1][2][1][1][15] = 34, +- [0][1][2][1][3][15] = 70, +- [0][1][2][1][5][15] = 62, +- [0][1][2][1][6][15] = 34, +- [0][1][2][1][9][15] = 34, +- [0][1][2][1][8][15] = 30, +- [0][1][2][1][11][15] = 28, +- [0][1][2][1][2][17] = 68, +- [0][1][2][1][1][17] = 34, +- [0][1][2][1][3][17] = 70, +- [0][1][2][1][5][17] = 62, +- [0][1][2][1][6][17] = 34, +- [0][1][2][1][9][17] = 34, +- [0][1][2][1][8][17] = 30, +- [0][1][2][1][11][17] = 28, +- [0][1][2][1][2][19] = 68, +- [0][1][2][1][1][19] = 34, +- [0][1][2][1][3][19] = 70, +- [0][1][2][1][5][19] = 62, +- [0][1][2][1][6][19] = 34, +- [0][1][2][1][9][19] = 34, +- [0][1][2][1][8][19] = 30, +- [0][1][2][1][11][19] = 28, +- [0][1][2][1][2][21] = 68, +- [0][1][2][1][1][21] = 34, +- [0][1][2][1][3][21] = 70, +- [0][1][2][1][5][21] = 62, +- [0][1][2][1][6][21] = 34, +- [0][1][2][1][9][21] = 34, +- [0][1][2][1][8][21] = 30, +- [0][1][2][1][11][21] = 28, +- [0][1][2][1][2][23] = 68, +- [0][1][2][1][1][23] = 34, +- [0][1][2][1][3][23] = 70, +- [0][1][2][1][5][23] = 62, +- [0][1][2][1][6][23] = 34, +- [0][1][2][1][9][23] = 34, +- [0][1][2][1][8][23] = 30, +- [0][1][2][1][11][23] = 28, +- [0][1][2][1][2][25] = 68, +- [0][1][2][1][1][25] = 34, +- [0][1][2][1][3][25] = 70, +- [0][1][2][1][5][25] = 127, +- [0][1][2][1][6][25] = 34, +- [0][1][2][1][9][25] = 127, +- [0][1][2][1][8][25] = 30, +- [0][1][2][1][11][25] = 28, +- [0][1][2][1][2][27] = 68, +- [0][1][2][1][1][27] = 34, +- [0][1][2][1][3][27] = 70, +- [0][1][2][1][5][27] = 127, +- [0][1][2][1][6][27] = 34, +- [0][1][2][1][9][27] = 127, +- [0][1][2][1][8][27] = 30, +- [0][1][2][1][11][27] = 28, +- [0][1][2][1][2][29] = 68, +- [0][1][2][1][1][29] = 34, +- [0][1][2][1][3][29] = 70, +- [0][1][2][1][5][29] = 127, +- [0][1][2][1][6][29] = 34, +- [0][1][2][1][9][29] = 127, +- [0][1][2][1][8][29] = 30, +- [0][1][2][1][11][29] = 28, +- [0][1][2][1][2][31] = 68, +- [0][1][2][1][1][31] = 34, +- [0][1][2][1][3][31] = 70, +- [0][1][2][1][5][31] = 62, +- [0][1][2][1][6][31] = 34, +- [0][1][2][1][9][31] = 34, +- [0][1][2][1][8][31] = 30, +- [0][1][2][1][11][31] = 28, +- [0][1][2][1][2][33] = 68, +- [0][1][2][1][1][33] = 34, +- [0][1][2][1][3][33] = 70, +- [0][1][2][1][5][33] = 62, +- [0][1][2][1][6][33] = 34, +- [0][1][2][1][9][33] = 34, +- [0][1][2][1][8][33] = 30, +- [0][1][2][1][11][33] = 28, +- [0][1][2][1][2][35] = 64, +- [0][1][2][1][1][35] = 34, +- [0][1][2][1][3][35] = 70, +- [0][1][2][1][5][35] = 62, +- [0][1][2][1][6][35] = 34, +- [0][1][2][1][9][35] = 34, +- [0][1][2][1][8][35] = 30, +- [0][1][2][1][11][35] = 28, +- [0][1][2][1][2][37] = 68, +- [0][1][2][1][1][37] = 127, +- [0][1][2][1][3][37] = 70, +- [0][1][2][1][5][37] = 62, +- [0][1][2][1][6][37] = 34, +- [0][1][2][1][9][37] = 68, +- [0][1][2][1][8][37] = 30, +- [0][1][2][1][11][37] = 127, +- [0][1][2][1][2][38] = 76, +- [0][1][2][1][1][38] = 4, +- [0][1][2][1][3][38] = 127, +- [0][1][2][1][5][38] = 76, +- [0][1][2][1][6][38] = 4, +- [0][1][2][1][9][38] = 76, +- [0][1][2][1][8][38] = 30, +- [0][1][2][1][11][38] = 28, +- [0][1][2][1][2][40] = 76, +- [0][1][2][1][1][40] = 4, +- [0][1][2][1][3][40] = 127, +- [0][1][2][1][5][40] = 76, +- [0][1][2][1][6][40] = 4, +- [0][1][2][1][9][40] = 76, +- [0][1][2][1][8][40] = 30, +- [0][1][2][1][11][40] = 28, +- [0][1][2][1][2][42] = 76, +- [0][1][2][1][1][42] = 4, +- [0][1][2][1][3][42] = 127, +- [0][1][2][1][5][42] = 76, +- [0][1][2][1][6][42] = 4, +- [0][1][2][1][9][42] = 76, +- [0][1][2][1][8][42] = 30, +- [0][1][2][1][11][42] = 28, +- [0][1][2][1][2][44] = 76, +- [0][1][2][1][1][44] = 4, +- [0][1][2][1][3][44] = 127, +- [0][1][2][1][5][44] = 76, +- [0][1][2][1][6][44] = 4, +- [0][1][2][1][9][44] = 76, +- [0][1][2][1][8][44] = 30, +- [0][1][2][1][11][44] = 28, +- [0][1][2][1][2][46] = 76, +- [0][1][2][1][1][46] = 4, +- [0][1][2][1][3][46] = 127, +- [0][1][2][1][5][46] = 76, +- [0][1][2][1][6][46] = 4, +- [0][1][2][1][9][46] = 76, +- [0][1][2][1][8][46] = 30, +- [0][1][2][1][11][46] = 28, +- [1][0][2][0][2][1] = 68, +- [1][0][2][0][1][1] = 64, +- [1][0][2][0][3][1] = 62, +- [1][0][2][0][5][1] = 64, +- [1][0][2][0][6][1] = 64, +- [1][0][2][0][9][1] = 64, +- [1][0][2][0][8][1] = 30, +- [1][0][2][0][11][1] = 52, +- [1][0][2][0][2][5] = 72, +- [1][0][2][0][1][5] = 64, +- [1][0][2][0][3][5] = 62, +- [1][0][2][0][5][5] = 64, +- [1][0][2][0][6][5] = 60, +- [1][0][2][0][9][5] = 64, +- [1][0][2][0][8][5] = 30, +- [1][0][2][0][11][5] = 52, +- [1][0][2][0][2][9] = 72, +- [1][0][2][0][1][9] = 64, +- [1][0][2][0][3][9] = 62, +- [1][0][2][0][5][9] = 64, +- [1][0][2][0][6][9] = 64, +- [1][0][2][0][9][9] = 64, +- [1][0][2][0][8][9] = 54, +- [1][0][2][0][11][9] = 52, +- [1][0][2][0][2][13] = 66, +- [1][0][2][0][1][13] = 64, +- [1][0][2][0][3][13] = 62, +- [1][0][2][0][5][13] = 64, +- [1][0][2][0][6][13] = 64, +- [1][0][2][0][9][13] = 64, +- [1][0][2][0][8][13] = 54, +- [1][0][2][0][11][13] = 52, +- [1][0][2][0][2][16] = 62, +- [1][0][2][0][1][16] = 64, +- [1][0][2][0][3][16] = 72, +- [1][0][2][0][5][16] = 62, +- [1][0][2][0][6][16] = 64, +- [1][0][2][0][9][16] = 64, +- [1][0][2][0][8][16] = 54, +- [1][0][2][0][11][16] = 52, +- [1][0][2][0][2][20] = 72, +- [1][0][2][0][1][20] = 64, +- [1][0][2][0][3][20] = 72, +- [1][0][2][0][5][20] = 72, +- [1][0][2][0][6][20] = 64, +- [1][0][2][0][9][20] = 64, +- [1][0][2][0][8][20] = 54, +- [1][0][2][0][11][20] = 52, +- [1][0][2][0][2][24] = 72, +- [1][0][2][0][1][24] = 64, +- [1][0][2][0][3][24] = 72, +- [1][0][2][0][5][24] = 127, +- [1][0][2][0][6][24] = 64, +- [1][0][2][0][9][24] = 127, +- [1][0][2][0][8][24] = 54, +- [1][0][2][0][11][24] = 52, +- [1][0][2][0][2][28] = 72, +- [1][0][2][0][1][28] = 64, +- [1][0][2][0][3][28] = 72, +- [1][0][2][0][5][28] = 127, +- [1][0][2][0][6][28] = 64, +- [1][0][2][0][9][28] = 127, +- [1][0][2][0][8][28] = 54, +- [1][0][2][0][11][28] = 52, +- [1][0][2][0][2][32] = 72, +- [1][0][2][0][1][32] = 64, +- [1][0][2][0][3][32] = 72, +- [1][0][2][0][5][32] = 72, +- [1][0][2][0][6][32] = 64, +- [1][0][2][0][9][32] = 64, +- [1][0][2][0][8][32] = 54, +- [1][0][2][0][11][32] = 52, +- [1][0][2][0][2][36] = 72, +- [1][0][2][0][1][36] = 127, +- [1][0][2][0][3][36] = 72, +- [1][0][2][0][5][36] = 72, +- [1][0][2][0][6][36] = 64, +- [1][0][2][0][9][36] = 72, +- [1][0][2][0][8][36] = 54, +- [1][0][2][0][11][36] = 127, +- [1][0][2][0][2][39] = 72, +- [1][0][2][0][1][39] = 28, +- [1][0][2][0][3][39] = 127, +- [1][0][2][0][5][39] = 72, +- [1][0][2][0][6][39] = 28, +- [1][0][2][0][9][39] = 72, +- [1][0][2][0][8][39] = 54, +- [1][0][2][0][11][39] = 52, +- [1][0][2][0][2][43] = 72, +- [1][0][2][0][1][43] = 28, +- [1][0][2][0][3][43] = 127, +- [1][0][2][0][5][43] = 72, +- [1][0][2][0][6][43] = 28, +- [1][0][2][0][9][43] = 72, +- [1][0][2][0][8][43] = 54, +- [1][0][2][0][11][43] = 52, +- [1][1][2][0][2][1] = 58, +- [1][1][2][0][1][1] = 52, +- [1][1][2][0][3][1] = 50, +- [1][1][2][0][5][1] = 52, +- [1][1][2][0][6][1] = 52, +- [1][1][2][0][9][1] = 52, +- [1][1][2][0][8][1] = 18, +- [1][1][2][0][11][1] = 40, +- [1][1][2][0][2][5] = 72, +- [1][1][2][0][1][5] = 52, +- [1][1][2][0][3][5] = 50, +- [1][1][2][0][5][5] = 52, +- [1][1][2][0][6][5] = 46, +- [1][1][2][0][9][5] = 52, +- [1][1][2][0][8][5] = 18, +- [1][1][2][0][11][5] = 40, +- [1][1][2][0][2][9] = 72, +- [1][1][2][0][1][9] = 52, +- [1][1][2][0][3][9] = 50, +- [1][1][2][0][5][9] = 52, +- [1][1][2][0][6][9] = 52, +- [1][1][2][0][9][9] = 52, +- [1][1][2][0][8][9] = 42, +- [1][1][2][0][11][9] = 40, +- [1][1][2][0][2][13] = 58, +- [1][1][2][0][1][13] = 52, +- [1][1][2][0][3][13] = 50, +- [1][1][2][0][5][13] = 52, +- [1][1][2][0][6][13] = 52, +- [1][1][2][0][9][13] = 52, +- [1][1][2][0][8][13] = 42, +- [1][1][2][0][11][13] = 40, +- [1][1][2][0][2][16] = 56, +- [1][1][2][0][1][16] = 52, +- [1][1][2][0][3][16] = 72, +- [1][1][2][0][5][16] = 56, +- [1][1][2][0][6][16] = 52, +- [1][1][2][0][9][16] = 52, +- [1][1][2][0][8][16] = 42, +- [1][1][2][0][11][16] = 40, +- [1][1][2][0][2][20] = 72, +- [1][1][2][0][1][20] = 52, +- [1][1][2][0][3][20] = 72, +- [1][1][2][0][5][20] = 72, +- [1][1][2][0][6][20] = 52, +- [1][1][2][0][9][20] = 52, +- [1][1][2][0][8][20] = 42, +- [1][1][2][0][11][20] = 40, +- [1][1][2][0][2][24] = 72, +- [1][1][2][0][1][24] = 52, +- [1][1][2][0][3][24] = 72, +- [1][1][2][0][5][24] = 127, +- [1][1][2][0][6][24] = 52, +- [1][1][2][0][9][24] = 127, +- [1][1][2][0][8][24] = 42, +- [1][1][2][0][11][24] = 40, +- [1][1][2][0][2][28] = 72, +- [1][1][2][0][1][28] = 52, +- [1][1][2][0][3][28] = 72, +- [1][1][2][0][5][28] = 127, +- [1][1][2][0][6][28] = 52, +- [1][1][2][0][9][28] = 127, +- [1][1][2][0][8][28] = 42, +- [1][1][2][0][11][28] = 40, +- [1][1][2][0][2][32] = 68, +- [1][1][2][0][1][32] = 52, +- [1][1][2][0][3][32] = 72, +- [1][1][2][0][5][32] = 68, +- [1][1][2][0][6][32] = 52, +- [1][1][2][0][9][32] = 52, +- [1][1][2][0][8][32] = 42, +- [1][1][2][0][11][32] = 40, +- [1][1][2][0][2][36] = 72, +- [1][1][2][0][1][36] = 127, +- [1][1][2][0][3][36] = 72, +- [1][1][2][0][5][36] = 72, +- [1][1][2][0][6][36] = 52, +- [1][1][2][0][9][36] = 72, +- [1][1][2][0][8][36] = 42, +- [1][1][2][0][11][36] = 127, +- [1][1][2][0][2][39] = 72, +- [1][1][2][0][1][39] = 16, +- [1][1][2][0][3][39] = 127, +- [1][1][2][0][5][39] = 72, +- [1][1][2][0][6][39] = 16, +- [1][1][2][0][9][39] = 72, +- [1][1][2][0][8][39] = 42, +- [1][1][2][0][11][39] = 40, +- [1][1][2][0][2][43] = 72, +- [1][1][2][0][1][43] = 16, +- [1][1][2][0][3][43] = 127, +- [1][1][2][0][5][43] = 72, +- [1][1][2][0][6][43] = 16, +- [1][1][2][0][9][43] = 72, +- [1][1][2][0][8][43] = 42, +- [1][1][2][0][11][43] = 40, +- [1][1][2][1][2][1] = 58, +- [1][1][2][1][1][1] = 40, +- [1][1][2][1][3][1] = 50, +- [1][1][2][1][5][1] = 40, +- [1][1][2][1][6][1] = 40, +- [1][1][2][1][9][1] = 40, +- [1][1][2][1][8][1] = 6, +- [1][1][2][1][11][1] = 28, +- [1][1][2][1][2][5] = 68, +- [1][1][2][1][1][5] = 40, +- [1][1][2][1][3][5] = 50, +- [1][1][2][1][5][5] = 40, +- [1][1][2][1][6][5] = 40, +- [1][1][2][1][9][5] = 40, +- [1][1][2][1][8][5] = 6, +- [1][1][2][1][11][5] = 28, +- [1][1][2][1][2][9] = 68, +- [1][1][2][1][1][9] = 40, +- [1][1][2][1][3][9] = 50, +- [1][1][2][1][5][9] = 40, +- [1][1][2][1][6][9] = 40, +- [1][1][2][1][9][9] = 40, +- [1][1][2][1][8][9] = 30, +- [1][1][2][1][11][9] = 28, +- [1][1][2][1][2][13] = 58, +- [1][1][2][1][1][13] = 40, +- [1][1][2][1][3][13] = 50, +- [1][1][2][1][5][13] = 40, +- [1][1][2][1][6][13] = 40, +- [1][1][2][1][9][13] = 40, +- [1][1][2][1][8][13] = 30, +- [1][1][2][1][11][13] = 28, +- [1][1][2][1][2][16] = 56, +- [1][1][2][1][1][16] = 40, +- [1][1][2][1][3][16] = 72, +- [1][1][2][1][5][16] = 56, +- [1][1][2][1][6][16] = 40, +- [1][1][2][1][9][16] = 40, +- [1][1][2][1][8][16] = 30, +- [1][1][2][1][11][16] = 28, +- [1][1][2][1][2][20] = 68, +- [1][1][2][1][1][20] = 40, +- [1][1][2][1][3][20] = 72, +- [1][1][2][1][5][20] = 68, +- [1][1][2][1][6][20] = 40, +- [1][1][2][1][9][20] = 40, +- [1][1][2][1][8][20] = 30, +- [1][1][2][1][11][20] = 28, +- [1][1][2][1][2][24] = 68, +- [1][1][2][1][1][24] = 40, +- [1][1][2][1][3][24] = 72, +- [1][1][2][1][5][24] = 127, +- [1][1][2][1][6][24] = 40, +- [1][1][2][1][9][24] = 127, +- [1][1][2][1][8][24] = 30, +- [1][1][2][1][11][24] = 28, +- [1][1][2][1][2][28] = 68, +- [1][1][2][1][1][28] = 40, +- [1][1][2][1][3][28] = 72, +- [1][1][2][1][5][28] = 127, +- [1][1][2][1][6][28] = 40, +- [1][1][2][1][9][28] = 127, +- [1][1][2][1][8][28] = 30, +- [1][1][2][1][11][28] = 28, +- [1][1][2][1][2][32] = 68, +- [1][1][2][1][1][32] = 40, +- [1][1][2][1][3][32] = 72, +- [1][1][2][1][5][32] = 68, +- [1][1][2][1][6][32] = 40, +- [1][1][2][1][9][32] = 40, +- [1][1][2][1][8][32] = 30, +- [1][1][2][1][11][32] = 28, +- [1][1][2][1][2][36] = 68, +- [1][1][2][1][1][36] = 127, +- [1][1][2][1][3][36] = 72, +- [1][1][2][1][5][36] = 68, +- [1][1][2][1][6][36] = 40, +- [1][1][2][1][9][36] = 68, +- [1][1][2][1][8][36] = 30, +- [1][1][2][1][11][36] = 127, +- [1][1][2][1][2][39] = 72, +- [1][1][2][1][1][39] = 4, +- [1][1][2][1][3][39] = 127, +- [1][1][2][1][5][39] = 72, +- [1][1][2][1][6][39] = 4, +- [1][1][2][1][9][39] = 72, +- [1][1][2][1][8][39] = 30, +- [1][1][2][1][11][39] = 28, +- [1][1][2][1][2][43] = 72, +- [1][1][2][1][1][43] = 4, +- [1][1][2][1][3][43] = 127, +- [1][1][2][1][5][43] = 72, +- [1][1][2][1][6][43] = 4, +- [1][1][2][1][9][43] = 72, +- [1][1][2][1][8][43] = 30, +- [1][1][2][1][11][43] = 28, +- [2][0][2][0][2][3] = 64, +- [2][0][2][0][1][3] = 64, +- [2][0][2][0][3][3] = 64, +- [2][0][2][0][5][3] = 62, +- [2][0][2][0][6][3] = 64, +- [2][0][2][0][9][3] = 64, +- [2][0][2][0][8][3] = 30, +- [2][0][2][0][11][3] = 52, +- [2][0][2][0][2][11] = 64, +- [2][0][2][0][1][11] = 64, +- [2][0][2][0][3][11] = 64, +- [2][0][2][0][5][11] = 62, +- [2][0][2][0][6][11] = 64, +- [2][0][2][0][9][11] = 64, +- [2][0][2][0][8][11] = 54, +- [2][0][2][0][11][11] = 52, +- [2][0][2][0][2][18] = 62, +- [2][0][2][0][1][18] = 64, +- [2][0][2][0][3][18] = 72, +- [2][0][2][0][5][18] = 66, +- [2][0][2][0][6][18] = 64, +- [2][0][2][0][9][18] = 64, +- [2][0][2][0][8][18] = 54, +- [2][0][2][0][11][18] = 52, +- [2][0][2][0][2][26] = 72, +- [2][0][2][0][1][26] = 64, +- [2][0][2][0][3][26] = 72, +- [2][0][2][0][5][26] = 127, +- [2][0][2][0][6][26] = 64, +- [2][0][2][0][9][26] = 127, +- [2][0][2][0][8][26] = 54, +- [2][0][2][0][11][26] = 52, +- [2][0][2][0][2][34] = 72, +- [2][0][2][0][1][34] = 127, +- [2][0][2][0][3][34] = 72, +- [2][0][2][0][5][34] = 72, +- [2][0][2][0][6][34] = 64, +- [2][0][2][0][9][34] = 72, +- [2][0][2][0][8][34] = 54, +- [2][0][2][0][11][34] = 127, +- [2][0][2][0][2][41] = 72, +- [2][0][2][0][1][41] = 28, +- [2][0][2][0][3][41] = 127, +- [2][0][2][0][5][41] = 72, +- [2][0][2][0][6][41] = 28, +- [2][0][2][0][9][41] = 72, +- [2][0][2][0][8][41] = 54, +- [2][0][2][0][11][41] = 52, +- [2][1][2][0][2][3] = 56, +- [2][1][2][0][1][3] = 52, +- [2][1][2][0][3][3] = 52, +- [2][1][2][0][5][3] = 52, +- [2][1][2][0][6][3] = 52, +- [2][1][2][0][9][3] = 52, +- [2][1][2][0][8][3] = 18, +- [2][1][2][0][11][3] = 40, +- [2][1][2][0][2][11] = 56, +- [2][1][2][0][1][11] = 52, +- [2][1][2][0][3][11] = 52, +- [2][1][2][0][5][11] = 52, +- [2][1][2][0][6][11] = 52, +- [2][1][2][0][9][11] = 52, +- [2][1][2][0][8][11] = 42, +- [2][1][2][0][11][11] = 40, +- [2][1][2][0][2][18] = 56, +- [2][1][2][0][1][18] = 52, +- [2][1][2][0][3][18] = 72, +- [2][1][2][0][5][18] = 56, +- [2][1][2][0][6][18] = 52, +- [2][1][2][0][9][18] = 52, +- [2][1][2][0][8][18] = 42, +- [2][1][2][0][11][18] = 40, +- [2][1][2][0][2][26] = 72, +- [2][1][2][0][1][26] = 52, +- [2][1][2][0][3][26] = 72, +- [2][1][2][0][5][26] = 127, +- [2][1][2][0][6][26] = 52, +- [2][1][2][0][9][26] = 127, +- [2][1][2][0][8][26] = 42, +- [2][1][2][0][11][26] = 40, +- [2][1][2][0][2][34] = 72, +- [2][1][2][0][1][34] = 127, +- [2][1][2][0][3][34] = 72, +- [2][1][2][0][5][34] = 72, +- [2][1][2][0][6][34] = 52, +- [2][1][2][0][9][34] = 72, +- [2][1][2][0][8][34] = 42, +- [2][1][2][0][11][34] = 127, +- [2][1][2][0][2][41] = 72, +- [2][1][2][0][1][41] = 16, +- [2][1][2][0][3][41] = 127, +- [2][1][2][0][5][41] = 72, +- [2][1][2][0][6][41] = 16, +- [2][1][2][0][9][41] = 72, +- [2][1][2][0][8][41] = 42, +- [2][1][2][0][11][41] = 40, +- [2][1][2][1][2][3] = 56, +- [2][1][2][1][1][3] = 40, +- [2][1][2][1][3][3] = 52, +- [2][1][2][1][5][3] = 40, +- [2][1][2][1][6][3] = 40, +- [2][1][2][1][9][3] = 40, +- [2][1][2][1][8][3] = 6, +- [2][1][2][1][11][3] = 28, +- [2][1][2][1][2][11] = 56, +- [2][1][2][1][1][11] = 40, +- [2][1][2][1][3][11] = 52, +- [2][1][2][1][5][11] = 40, +- [2][1][2][1][6][11] = 40, +- [2][1][2][1][9][11] = 40, +- [2][1][2][1][8][11] = 30, +- [2][1][2][1][11][11] = 28, +- [2][1][2][1][2][18] = 56, +- [2][1][2][1][1][18] = 40, +- [2][1][2][1][3][18] = 72, +- [2][1][2][1][5][18] = 56, +- [2][1][2][1][6][18] = 40, +- [2][1][2][1][9][18] = 40, +- [2][1][2][1][8][18] = 30, +- [2][1][2][1][11][18] = 28, +- [2][1][2][1][2][26] = 68, +- [2][1][2][1][1][26] = 40, +- [2][1][2][1][3][26] = 72, +- [2][1][2][1][5][26] = 127, +- [2][1][2][1][6][26] = 40, +- [2][1][2][1][9][26] = 127, +- [2][1][2][1][8][26] = 30, +- [2][1][2][1][11][26] = 28, +- [2][1][2][1][2][34] = 68, +- [2][1][2][1][1][34] = 127, +- [2][1][2][1][3][34] = 72, +- [2][1][2][1][5][34] = 68, +- [2][1][2][1][6][34] = 40, +- [2][1][2][1][9][34] = 68, +- [2][1][2][1][8][34] = 30, +- [2][1][2][1][11][34] = 127, +- [2][1][2][1][2][41] = 72, +- [2][1][2][1][1][41] = 4, +- [2][1][2][1][3][41] = 127, +- [2][1][2][1][5][41] = 72, +- [2][1][2][1][6][41] = 4, +- [2][1][2][1][9][41] = 72, +- [2][1][2][1][8][41] = 30, +- [2][1][2][1][11][41] = 28, ++ [0][0][1][0][RTW89_WW][0] = 30, ++ [0][0][1][0][RTW89_WW][2] = 30, ++ [0][0][1][0][RTW89_WW][4] = 30, ++ [0][0][1][0][RTW89_WW][6] = 30, ++ [0][0][1][0][RTW89_WW][8] = 52, ++ [0][0][1][0][RTW89_WW][10] = 52, ++ [0][0][1][0][RTW89_WW][12] = 52, ++ [0][0][1][0][RTW89_WW][14] = 52, ++ [0][0][1][0][RTW89_WW][15] = 52, ++ [0][0][1][0][RTW89_WW][17] = 52, ++ [0][0][1][0][RTW89_WW][19] = 52, ++ [0][0][1][0][RTW89_WW][21] = 52, ++ [0][0][1][0][RTW89_WW][23] = 52, ++ [0][0][1][0][RTW89_WW][25] = 52, ++ [0][0][1][0][RTW89_WW][27] = 52, ++ [0][0][1][0][RTW89_WW][29] = 52, ++ [0][0][1][0][RTW89_WW][31] = 52, ++ [0][0][1][0][RTW89_WW][33] = 52, ++ [0][0][1][0][RTW89_WW][35] = 52, ++ [0][0][1][0][RTW89_WW][37] = 54, ++ [0][0][1][0][RTW89_WW][38] = 28, ++ [0][0][1][0][RTW89_WW][40] = 28, ++ [0][0][1][0][RTW89_WW][42] = 28, ++ [0][0][1][0][RTW89_WW][44] = 28, ++ [0][0][1][0][RTW89_WW][46] = 28, ++ [0][1][1][0][RTW89_WW][0] = 18, ++ [0][1][1][0][RTW89_WW][2] = 18, ++ [0][1][1][0][RTW89_WW][4] = 18, ++ [0][1][1][0][RTW89_WW][6] = 18, ++ [0][1][1][0][RTW89_WW][8] = 40, ++ [0][1][1][0][RTW89_WW][10] = 40, ++ [0][1][1][0][RTW89_WW][12] = 40, ++ [0][1][1][0][RTW89_WW][14] = 40, ++ [0][1][1][0][RTW89_WW][15] = 40, ++ [0][1][1][0][RTW89_WW][17] = 40, ++ [0][1][1][0][RTW89_WW][19] = 40, ++ [0][1][1][0][RTW89_WW][21] = 40, ++ [0][1][1][0][RTW89_WW][23] = 40, ++ [0][1][1][0][RTW89_WW][25] = 40, ++ [0][1][1][0][RTW89_WW][27] = 40, ++ [0][1][1][0][RTW89_WW][29] = 40, ++ [0][1][1][0][RTW89_WW][31] = 40, ++ [0][1][1][0][RTW89_WW][33] = 40, ++ [0][1][1][0][RTW89_WW][35] = 40, ++ [0][1][1][0][RTW89_WW][37] = 42, ++ [0][1][1][0][RTW89_WW][38] = 16, ++ [0][1][1][0][RTW89_WW][40] = 16, ++ [0][1][1][0][RTW89_WW][42] = 16, ++ [0][1][1][0][RTW89_WW][44] = 16, ++ [0][1][1][0][RTW89_WW][46] = 16, ++ [0][0][2][0][RTW89_WW][0] = 30, ++ [0][0][2][0][RTW89_WW][2] = 30, ++ [0][0][2][0][RTW89_WW][4] = 30, ++ [0][0][2][0][RTW89_WW][6] = 30, ++ [0][0][2][0][RTW89_WW][8] = 52, ++ [0][0][2][0][RTW89_WW][10] = 52, ++ [0][0][2][0][RTW89_WW][12] = 52, ++ [0][0][2][0][RTW89_WW][14] = 52, ++ [0][0][2][0][RTW89_WW][15] = 52, ++ [0][0][2][0][RTW89_WW][17] = 52, ++ [0][0][2][0][RTW89_WW][19] = 52, ++ [0][0][2][0][RTW89_WW][21] = 52, ++ [0][0][2][0][RTW89_WW][23] = 52, ++ [0][0][2][0][RTW89_WW][25] = 52, ++ [0][0][2][0][RTW89_WW][27] = 52, ++ [0][0][2][0][RTW89_WW][29] = 52, ++ [0][0][2][0][RTW89_WW][31] = 52, ++ [0][0][2][0][RTW89_WW][33] = 52, ++ [0][0][2][0][RTW89_WW][35] = 52, ++ [0][0][2][0][RTW89_WW][37] = 54, ++ [0][0][2][0][RTW89_WW][38] = 28, ++ [0][0][2][0][RTW89_WW][40] = 28, ++ [0][0][2][0][RTW89_WW][42] = 28, ++ [0][0][2][0][RTW89_WW][44] = 28, ++ [0][0][2][0][RTW89_WW][46] = 28, ++ [0][1][2][0][RTW89_WW][0] = 18, ++ [0][1][2][0][RTW89_WW][2] = 18, ++ [0][1][2][0][RTW89_WW][4] = 18, ++ [0][1][2][0][RTW89_WW][6] = 18, ++ [0][1][2][0][RTW89_WW][8] = 40, ++ [0][1][2][0][RTW89_WW][10] = 40, ++ [0][1][2][0][RTW89_WW][12] = 40, ++ [0][1][2][0][RTW89_WW][14] = 40, ++ [0][1][2][0][RTW89_WW][15] = 40, ++ [0][1][2][0][RTW89_WW][17] = 40, ++ [0][1][2][0][RTW89_WW][19] = 40, ++ [0][1][2][0][RTW89_WW][21] = 40, ++ [0][1][2][0][RTW89_WW][23] = 40, ++ [0][1][2][0][RTW89_WW][25] = 40, ++ [0][1][2][0][RTW89_WW][27] = 40, ++ [0][1][2][0][RTW89_WW][29] = 40, ++ [0][1][2][0][RTW89_WW][31] = 40, ++ [0][1][2][0][RTW89_WW][33] = 40, ++ [0][1][2][0][RTW89_WW][35] = 40, ++ [0][1][2][0][RTW89_WW][37] = 42, ++ [0][1][2][0][RTW89_WW][38] = 16, ++ [0][1][2][0][RTW89_WW][40] = 16, ++ [0][1][2][0][RTW89_WW][42] = 16, ++ [0][1][2][0][RTW89_WW][44] = 16, ++ [0][1][2][0][RTW89_WW][46] = 16, ++ [0][1][2][1][RTW89_WW][0] = 6, ++ [0][1][2][1][RTW89_WW][2] = 6, ++ [0][1][2][1][RTW89_WW][4] = 6, ++ [0][1][2][1][RTW89_WW][6] = 6, ++ [0][1][2][1][RTW89_WW][8] = 28, ++ [0][1][2][1][RTW89_WW][10] = 28, ++ [0][1][2][1][RTW89_WW][12] = 28, ++ [0][1][2][1][RTW89_WW][14] = 28, ++ [0][1][2][1][RTW89_WW][15] = 28, ++ [0][1][2][1][RTW89_WW][17] = 28, ++ [0][1][2][1][RTW89_WW][19] = 28, ++ [0][1][2][1][RTW89_WW][21] = 28, ++ [0][1][2][1][RTW89_WW][23] = 28, ++ [0][1][2][1][RTW89_WW][25] = 28, ++ [0][1][2][1][RTW89_WW][27] = 28, ++ [0][1][2][1][RTW89_WW][29] = 28, ++ [0][1][2][1][RTW89_WW][31] = 28, ++ [0][1][2][1][RTW89_WW][33] = 28, ++ [0][1][2][1][RTW89_WW][35] = 28, ++ [0][1][2][1][RTW89_WW][37] = 30, ++ [0][1][2][1][RTW89_WW][38] = 4, ++ [0][1][2][1][RTW89_WW][40] = 4, ++ [0][1][2][1][RTW89_WW][42] = 4, ++ [0][1][2][1][RTW89_WW][44] = 4, ++ [0][1][2][1][RTW89_WW][46] = 4, ++ [1][0][2][0][RTW89_WW][1] = 30, ++ [1][0][2][0][RTW89_WW][5] = 30, ++ [1][0][2][0][RTW89_WW][9] = 52, ++ [1][0][2][0][RTW89_WW][13] = 52, ++ [1][0][2][0][RTW89_WW][16] = 52, ++ [1][0][2][0][RTW89_WW][20] = 52, ++ [1][0][2][0][RTW89_WW][24] = 52, ++ [1][0][2][0][RTW89_WW][28] = 52, ++ [1][0][2][0][RTW89_WW][32] = 52, ++ [1][0][2][0][RTW89_WW][36] = 54, ++ [1][0][2][0][RTW89_WW][39] = 28, ++ [1][0][2][0][RTW89_WW][43] = 28, ++ [1][1][2][0][RTW89_WW][1] = 18, ++ [1][1][2][0][RTW89_WW][5] = 18, ++ [1][1][2][0][RTW89_WW][9] = 40, ++ [1][1][2][0][RTW89_WW][13] = 40, ++ [1][1][2][0][RTW89_WW][16] = 40, ++ [1][1][2][0][RTW89_WW][20] = 40, ++ [1][1][2][0][RTW89_WW][24] = 40, ++ [1][1][2][0][RTW89_WW][28] = 40, ++ [1][1][2][0][RTW89_WW][32] = 40, ++ [1][1][2][0][RTW89_WW][36] = 42, ++ [1][1][2][0][RTW89_WW][39] = 16, ++ [1][1][2][0][RTW89_WW][43] = 16, ++ [1][1][2][1][RTW89_WW][1] = 6, ++ [1][1][2][1][RTW89_WW][5] = 6, ++ [1][1][2][1][RTW89_WW][9] = 28, ++ [1][1][2][1][RTW89_WW][13] = 28, ++ [1][1][2][1][RTW89_WW][16] = 28, ++ [1][1][2][1][RTW89_WW][20] = 28, ++ [1][1][2][1][RTW89_WW][24] = 28, ++ [1][1][2][1][RTW89_WW][28] = 28, ++ [1][1][2][1][RTW89_WW][32] = 28, ++ [1][1][2][1][RTW89_WW][36] = 30, ++ [1][1][2][1][RTW89_WW][39] = 4, ++ [1][1][2][1][RTW89_WW][43] = 4, ++ [2][0][2][0][RTW89_WW][3] = 30, ++ [2][0][2][0][RTW89_WW][11] = 52, ++ [2][0][2][0][RTW89_WW][18] = 52, ++ [2][0][2][0][RTW89_WW][26] = 52, ++ [2][0][2][0][RTW89_WW][34] = 54, ++ [2][0][2][0][RTW89_WW][41] = 28, ++ [2][1][2][0][RTW89_WW][3] = 18, ++ [2][1][2][0][RTW89_WW][11] = 40, ++ [2][1][2][0][RTW89_WW][18] = 40, ++ [2][1][2][0][RTW89_WW][26] = 40, ++ [2][1][2][0][RTW89_WW][34] = 42, ++ [2][1][2][0][RTW89_WW][41] = 16, ++ [2][1][2][1][RTW89_WW][3] = 6, ++ [2][1][2][1][RTW89_WW][11] = 28, ++ [2][1][2][1][RTW89_WW][18] = 28, ++ [2][1][2][1][RTW89_WW][26] = 28, ++ [2][1][2][1][RTW89_WW][34] = 30, ++ [2][1][2][1][RTW89_WW][41] = 4, ++ [0][0][1][0][RTW89_FCC][0] = 76, ++ [0][0][1][0][RTW89_ETSI][0] = 58, ++ [0][0][1][0][RTW89_MKK][0] = 62, ++ [0][0][1][0][RTW89_IC][0] = 62, ++ [0][0][1][0][RTW89_KCC][0] = 58, ++ [0][0][1][0][RTW89_ACMA][0] = 58, ++ [0][0][1][0][RTW89_CHILE][0] = 30, ++ [0][0][1][0][RTW89_UKRAINE][0] = 52, ++ [0][0][1][0][RTW89_FCC][2] = 76, ++ [0][0][1][0][RTW89_ETSI][2] = 58, ++ [0][0][1][0][RTW89_MKK][2] = 62, ++ [0][0][1][0][RTW89_IC][2] = 62, ++ [0][0][1][0][RTW89_KCC][2] = 58, ++ [0][0][1][0][RTW89_ACMA][2] = 58, ++ [0][0][1][0][RTW89_CHILE][2] = 30, ++ [0][0][1][0][RTW89_UKRAINE][2] = 52, ++ [0][0][1][0][RTW89_FCC][4] = 76, ++ [0][0][1][0][RTW89_ETSI][4] = 58, ++ [0][0][1][0][RTW89_MKK][4] = 62, ++ [0][0][1][0][RTW89_IC][4] = 62, ++ [0][0][1][0][RTW89_KCC][4] = 58, ++ [0][0][1][0][RTW89_ACMA][4] = 58, ++ [0][0][1][0][RTW89_CHILE][4] = 30, ++ [0][0][1][0][RTW89_UKRAINE][4] = 52, ++ [0][0][1][0][RTW89_FCC][6] = 76, ++ [0][0][1][0][RTW89_ETSI][6] = 58, ++ [0][0][1][0][RTW89_MKK][6] = 62, ++ [0][0][1][0][RTW89_IC][6] = 62, ++ [0][0][1][0][RTW89_KCC][6] = 54, ++ [0][0][1][0][RTW89_ACMA][6] = 58, ++ [0][0][1][0][RTW89_CHILE][6] = 30, ++ [0][0][1][0][RTW89_UKRAINE][6] = 52, ++ [0][0][1][0][RTW89_FCC][8] = 76, ++ [0][0][1][0][RTW89_ETSI][8] = 58, ++ [0][0][1][0][RTW89_MKK][8] = 62, ++ [0][0][1][0][RTW89_IC][8] = 64, ++ [0][0][1][0][RTW89_KCC][8] = 58, ++ [0][0][1][0][RTW89_ACMA][8] = 58, ++ [0][0][1][0][RTW89_CHILE][8] = 54, ++ [0][0][1][0][RTW89_UKRAINE][8] = 52, ++ [0][0][1][0][RTW89_FCC][10] = 76, ++ [0][0][1][0][RTW89_ETSI][10] = 58, ++ [0][0][1][0][RTW89_MKK][10] = 62, ++ [0][0][1][0][RTW89_IC][10] = 64, ++ [0][0][1][0][RTW89_KCC][10] = 58, ++ [0][0][1][0][RTW89_ACMA][10] = 58, ++ [0][0][1][0][RTW89_CHILE][10] = 54, ++ [0][0][1][0][RTW89_UKRAINE][10] = 52, ++ [0][0][1][0][RTW89_FCC][12] = 76, ++ [0][0][1][0][RTW89_ETSI][12] = 58, ++ [0][0][1][0][RTW89_MKK][12] = 62, ++ [0][0][1][0][RTW89_IC][12] = 64, ++ [0][0][1][0][RTW89_KCC][12] = 58, ++ [0][0][1][0][RTW89_ACMA][12] = 58, ++ [0][0][1][0][RTW89_CHILE][12] = 54, ++ [0][0][1][0][RTW89_UKRAINE][12] = 52, ++ [0][0][1][0][RTW89_FCC][14] = 76, ++ [0][0][1][0][RTW89_ETSI][14] = 58, ++ [0][0][1][0][RTW89_MKK][14] = 62, ++ [0][0][1][0][RTW89_IC][14] = 64, ++ [0][0][1][0][RTW89_KCC][14] = 58, ++ [0][0][1][0][RTW89_ACMA][14] = 58, ++ [0][0][1][0][RTW89_CHILE][14] = 54, ++ [0][0][1][0][RTW89_UKRAINE][14] = 52, ++ [0][0][1][0][RTW89_FCC][15] = 76, ++ [0][0][1][0][RTW89_ETSI][15] = 58, ++ [0][0][1][0][RTW89_MKK][15] = 76, ++ [0][0][1][0][RTW89_IC][15] = 76, ++ [0][0][1][0][RTW89_KCC][15] = 58, ++ [0][0][1][0][RTW89_ACMA][15] = 58, ++ [0][0][1][0][RTW89_CHILE][15] = 54, ++ [0][0][1][0][RTW89_UKRAINE][15] = 52, ++ [0][0][1][0][RTW89_FCC][17] = 76, ++ [0][0][1][0][RTW89_ETSI][17] = 58, ++ [0][0][1][0][RTW89_MKK][17] = 76, ++ [0][0][1][0][RTW89_IC][17] = 76, ++ [0][0][1][0][RTW89_KCC][17] = 58, ++ [0][0][1][0][RTW89_ACMA][17] = 58, ++ [0][0][1][0][RTW89_CHILE][17] = 54, ++ [0][0][1][0][RTW89_UKRAINE][17] = 52, ++ [0][0][1][0][RTW89_FCC][19] = 76, ++ [0][0][1][0][RTW89_ETSI][19] = 58, ++ [0][0][1][0][RTW89_MKK][19] = 76, ++ [0][0][1][0][RTW89_IC][19] = 76, ++ [0][0][1][0][RTW89_KCC][19] = 58, ++ [0][0][1][0][RTW89_ACMA][19] = 58, ++ [0][0][1][0][RTW89_CHILE][19] = 54, ++ [0][0][1][0][RTW89_UKRAINE][19] = 52, ++ [0][0][1][0][RTW89_FCC][21] = 76, ++ [0][0][1][0][RTW89_ETSI][21] = 58, ++ [0][0][1][0][RTW89_MKK][21] = 76, ++ [0][0][1][0][RTW89_IC][21] = 76, ++ [0][0][1][0][RTW89_KCC][21] = 58, ++ [0][0][1][0][RTW89_ACMA][21] = 58, ++ [0][0][1][0][RTW89_CHILE][21] = 54, ++ [0][0][1][0][RTW89_UKRAINE][21] = 52, ++ [0][0][1][0][RTW89_FCC][23] = 76, ++ [0][0][1][0][RTW89_ETSI][23] = 58, ++ [0][0][1][0][RTW89_MKK][23] = 76, ++ [0][0][1][0][RTW89_IC][23] = 76, ++ [0][0][1][0][RTW89_KCC][23] = 58, ++ [0][0][1][0][RTW89_ACMA][23] = 58, ++ [0][0][1][0][RTW89_CHILE][23] = 54, ++ [0][0][1][0][RTW89_UKRAINE][23] = 52, ++ [0][0][1][0][RTW89_FCC][25] = 76, ++ [0][0][1][0][RTW89_ETSI][25] = 58, ++ [0][0][1][0][RTW89_MKK][25] = 76, ++ [0][0][1][0][RTW89_IC][25] = 127, ++ [0][0][1][0][RTW89_KCC][25] = 58, ++ [0][0][1][0][RTW89_ACMA][25] = 127, ++ [0][0][1][0][RTW89_CHILE][25] = 54, ++ [0][0][1][0][RTW89_UKRAINE][25] = 52, ++ [0][0][1][0][RTW89_FCC][27] = 76, ++ [0][0][1][0][RTW89_ETSI][27] = 58, ++ [0][0][1][0][RTW89_MKK][27] = 76, ++ [0][0][1][0][RTW89_IC][27] = 127, ++ [0][0][1][0][RTW89_KCC][27] = 58, ++ [0][0][1][0][RTW89_ACMA][27] = 127, ++ [0][0][1][0][RTW89_CHILE][27] = 54, ++ [0][0][1][0][RTW89_UKRAINE][27] = 52, ++ [0][0][1][0][RTW89_FCC][29] = 76, ++ [0][0][1][0][RTW89_ETSI][29] = 58, ++ [0][0][1][0][RTW89_MKK][29] = 76, ++ [0][0][1][0][RTW89_IC][29] = 127, ++ [0][0][1][0][RTW89_KCC][29] = 58, ++ [0][0][1][0][RTW89_ACMA][29] = 127, ++ [0][0][1][0][RTW89_CHILE][29] = 54, ++ [0][0][1][0][RTW89_UKRAINE][29] = 52, ++ [0][0][1][0][RTW89_FCC][31] = 76, ++ [0][0][1][0][RTW89_ETSI][31] = 58, ++ [0][0][1][0][RTW89_MKK][31] = 76, ++ [0][0][1][0][RTW89_IC][31] = 76, ++ [0][0][1][0][RTW89_KCC][31] = 58, ++ [0][0][1][0][RTW89_ACMA][31] = 58, ++ [0][0][1][0][RTW89_CHILE][31] = 54, ++ [0][0][1][0][RTW89_UKRAINE][31] = 52, ++ [0][0][1][0][RTW89_FCC][33] = 76, ++ [0][0][1][0][RTW89_ETSI][33] = 58, ++ [0][0][1][0][RTW89_MKK][33] = 76, ++ [0][0][1][0][RTW89_IC][33] = 76, ++ [0][0][1][0][RTW89_KCC][33] = 58, ++ [0][0][1][0][RTW89_ACMA][33] = 58, ++ [0][0][1][0][RTW89_CHILE][33] = 54, ++ [0][0][1][0][RTW89_UKRAINE][33] = 52, ++ [0][0][1][0][RTW89_FCC][35] = 74, ++ [0][0][1][0][RTW89_ETSI][35] = 58, ++ [0][0][1][0][RTW89_MKK][35] = 76, ++ [0][0][1][0][RTW89_IC][35] = 74, ++ [0][0][1][0][RTW89_KCC][35] = 58, ++ [0][0][1][0][RTW89_ACMA][35] = 58, ++ [0][0][1][0][RTW89_CHILE][35] = 54, ++ [0][0][1][0][RTW89_UKRAINE][35] = 52, ++ [0][0][1][0][RTW89_FCC][37] = 76, ++ [0][0][1][0][RTW89_ETSI][37] = 127, ++ [0][0][1][0][RTW89_MKK][37] = 76, ++ [0][0][1][0][RTW89_IC][37] = 76, ++ [0][0][1][0][RTW89_KCC][37] = 58, ++ [0][0][1][0][RTW89_ACMA][37] = 76, ++ [0][0][1][0][RTW89_CHILE][37] = 54, ++ [0][0][1][0][RTW89_UKRAINE][37] = 127, ++ [0][0][1][0][RTW89_FCC][38] = 76, ++ [0][0][1][0][RTW89_ETSI][38] = 28, ++ [0][0][1][0][RTW89_MKK][38] = 127, ++ [0][0][1][0][RTW89_IC][38] = 76, ++ [0][0][1][0][RTW89_KCC][38] = 28, ++ [0][0][1][0][RTW89_ACMA][38] = 76, ++ [0][0][1][0][RTW89_CHILE][38] = 54, ++ [0][0][1][0][RTW89_UKRAINE][38] = 52, ++ [0][0][1][0][RTW89_FCC][40] = 76, ++ [0][0][1][0][RTW89_ETSI][40] = 28, ++ [0][0][1][0][RTW89_MKK][40] = 127, ++ [0][0][1][0][RTW89_IC][40] = 76, ++ [0][0][1][0][RTW89_KCC][40] = 28, ++ [0][0][1][0][RTW89_ACMA][40] = 76, ++ [0][0][1][0][RTW89_CHILE][40] = 54, ++ [0][0][1][0][RTW89_UKRAINE][40] = 52, ++ [0][0][1][0][RTW89_FCC][42] = 76, ++ [0][0][1][0][RTW89_ETSI][42] = 28, ++ [0][0][1][0][RTW89_MKK][42] = 127, ++ [0][0][1][0][RTW89_IC][42] = 76, ++ [0][0][1][0][RTW89_KCC][42] = 28, ++ [0][0][1][0][RTW89_ACMA][42] = 76, ++ [0][0][1][0][RTW89_CHILE][42] = 54, ++ [0][0][1][0][RTW89_UKRAINE][42] = 52, ++ [0][0][1][0][RTW89_FCC][44] = 76, ++ [0][0][1][0][RTW89_ETSI][44] = 28, ++ [0][0][1][0][RTW89_MKK][44] = 127, ++ [0][0][1][0][RTW89_IC][44] = 76, ++ [0][0][1][0][RTW89_KCC][44] = 28, ++ [0][0][1][0][RTW89_ACMA][44] = 76, ++ [0][0][1][0][RTW89_CHILE][44] = 54, ++ [0][0][1][0][RTW89_UKRAINE][44] = 52, ++ [0][0][1][0][RTW89_FCC][46] = 76, ++ [0][0][1][0][RTW89_ETSI][46] = 28, ++ [0][0][1][0][RTW89_MKK][46] = 127, ++ [0][0][1][0][RTW89_IC][46] = 76, ++ [0][0][1][0][RTW89_KCC][46] = 28, ++ [0][0][1][0][RTW89_ACMA][46] = 76, ++ [0][0][1][0][RTW89_CHILE][46] = 54, ++ [0][0][1][0][RTW89_UKRAINE][46] = 52, ++ [0][1][1][0][RTW89_FCC][0] = 68, ++ [0][1][1][0][RTW89_ETSI][0] = 46, ++ [0][1][1][0][RTW89_MKK][0] = 50, ++ [0][1][1][0][RTW89_IC][0] = 40, ++ [0][1][1][0][RTW89_KCC][0] = 46, ++ [0][1][1][0][RTW89_ACMA][0] = 46, ++ [0][1][1][0][RTW89_CHILE][0] = 18, ++ [0][1][1][0][RTW89_UKRAINE][0] = 40, ++ [0][1][1][0][RTW89_FCC][2] = 68, ++ [0][1][1][0][RTW89_ETSI][2] = 46, ++ [0][1][1][0][RTW89_MKK][2] = 50, ++ [0][1][1][0][RTW89_IC][2] = 40, ++ [0][1][1][0][RTW89_KCC][2] = 46, ++ [0][1][1][0][RTW89_ACMA][2] = 46, ++ [0][1][1][0][RTW89_CHILE][2] = 18, ++ [0][1][1][0][RTW89_UKRAINE][2] = 40, ++ [0][1][1][0][RTW89_FCC][4] = 68, ++ [0][1][1][0][RTW89_ETSI][4] = 46, ++ [0][1][1][0][RTW89_MKK][4] = 50, ++ [0][1][1][0][RTW89_IC][4] = 40, ++ [0][1][1][0][RTW89_KCC][4] = 46, ++ [0][1][1][0][RTW89_ACMA][4] = 46, ++ [0][1][1][0][RTW89_CHILE][4] = 18, ++ [0][1][1][0][RTW89_UKRAINE][4] = 40, ++ [0][1][1][0][RTW89_FCC][6] = 68, ++ [0][1][1][0][RTW89_ETSI][6] = 46, ++ [0][1][1][0][RTW89_MKK][6] = 50, ++ [0][1][1][0][RTW89_IC][6] = 40, ++ [0][1][1][0][RTW89_KCC][6] = 36, ++ [0][1][1][0][RTW89_ACMA][6] = 46, ++ [0][1][1][0][RTW89_CHILE][6] = 18, ++ [0][1][1][0][RTW89_UKRAINE][6] = 40, ++ [0][1][1][0][RTW89_FCC][8] = 68, ++ [0][1][1][0][RTW89_ETSI][8] = 46, ++ [0][1][1][0][RTW89_MKK][8] = 50, ++ [0][1][1][0][RTW89_IC][8] = 52, ++ [0][1][1][0][RTW89_KCC][8] = 46, ++ [0][1][1][0][RTW89_ACMA][8] = 46, ++ [0][1][1][0][RTW89_CHILE][8] = 42, ++ [0][1][1][0][RTW89_UKRAINE][8] = 40, ++ [0][1][1][0][RTW89_FCC][10] = 68, ++ [0][1][1][0][RTW89_ETSI][10] = 46, ++ [0][1][1][0][RTW89_MKK][10] = 50, ++ [0][1][1][0][RTW89_IC][10] = 52, ++ [0][1][1][0][RTW89_KCC][10] = 46, ++ [0][1][1][0][RTW89_ACMA][10] = 46, ++ [0][1][1][0][RTW89_CHILE][10] = 42, ++ [0][1][1][0][RTW89_UKRAINE][10] = 40, ++ [0][1][1][0][RTW89_FCC][12] = 68, ++ [0][1][1][0][RTW89_ETSI][12] = 46, ++ [0][1][1][0][RTW89_MKK][12] = 50, ++ [0][1][1][0][RTW89_IC][12] = 52, ++ [0][1][1][0][RTW89_KCC][12] = 46, ++ [0][1][1][0][RTW89_ACMA][12] = 46, ++ [0][1][1][0][RTW89_CHILE][12] = 42, ++ [0][1][1][0][RTW89_UKRAINE][12] = 40, ++ [0][1][1][0][RTW89_FCC][14] = 68, ++ [0][1][1][0][RTW89_ETSI][14] = 46, ++ [0][1][1][0][RTW89_MKK][14] = 50, ++ [0][1][1][0][RTW89_IC][14] = 52, ++ [0][1][1][0][RTW89_KCC][14] = 46, ++ [0][1][1][0][RTW89_ACMA][14] = 46, ++ [0][1][1][0][RTW89_CHILE][14] = 42, ++ [0][1][1][0][RTW89_UKRAINE][14] = 40, ++ [0][1][1][0][RTW89_FCC][15] = 68, ++ [0][1][1][0][RTW89_ETSI][15] = 46, ++ [0][1][1][0][RTW89_MKK][15] = 70, ++ [0][1][1][0][RTW89_IC][15] = 68, ++ [0][1][1][0][RTW89_KCC][15] = 46, ++ [0][1][1][0][RTW89_ACMA][15] = 46, ++ [0][1][1][0][RTW89_CHILE][15] = 42, ++ [0][1][1][0][RTW89_UKRAINE][15] = 40, ++ [0][1][1][0][RTW89_FCC][17] = 68, ++ [0][1][1][0][RTW89_ETSI][17] = 46, ++ [0][1][1][0][RTW89_MKK][17] = 70, ++ [0][1][1][0][RTW89_IC][17] = 68, ++ [0][1][1][0][RTW89_KCC][17] = 46, ++ [0][1][1][0][RTW89_ACMA][17] = 46, ++ [0][1][1][0][RTW89_CHILE][17] = 42, ++ [0][1][1][0][RTW89_UKRAINE][17] = 40, ++ [0][1][1][0][RTW89_FCC][19] = 68, ++ [0][1][1][0][RTW89_ETSI][19] = 46, ++ [0][1][1][0][RTW89_MKK][19] = 70, ++ [0][1][1][0][RTW89_IC][19] = 68, ++ [0][1][1][0][RTW89_KCC][19] = 46, ++ [0][1][1][0][RTW89_ACMA][19] = 46, ++ [0][1][1][0][RTW89_CHILE][19] = 42, ++ [0][1][1][0][RTW89_UKRAINE][19] = 40, ++ [0][1][1][0][RTW89_FCC][21] = 68, ++ [0][1][1][0][RTW89_ETSI][21] = 46, ++ [0][1][1][0][RTW89_MKK][21] = 70, ++ [0][1][1][0][RTW89_IC][21] = 68, ++ [0][1][1][0][RTW89_KCC][21] = 46, ++ [0][1][1][0][RTW89_ACMA][21] = 46, ++ [0][1][1][0][RTW89_CHILE][21] = 42, ++ [0][1][1][0][RTW89_UKRAINE][21] = 40, ++ [0][1][1][0][RTW89_FCC][23] = 68, ++ [0][1][1][0][RTW89_ETSI][23] = 46, ++ [0][1][1][0][RTW89_MKK][23] = 70, ++ [0][1][1][0][RTW89_IC][23] = 68, ++ [0][1][1][0][RTW89_KCC][23] = 46, ++ [0][1][1][0][RTW89_ACMA][23] = 46, ++ [0][1][1][0][RTW89_CHILE][23] = 42, ++ [0][1][1][0][RTW89_UKRAINE][23] = 40, ++ [0][1][1][0][RTW89_FCC][25] = 68, ++ [0][1][1][0][RTW89_ETSI][25] = 46, ++ [0][1][1][0][RTW89_MKK][25] = 70, ++ [0][1][1][0][RTW89_IC][25] = 127, ++ [0][1][1][0][RTW89_KCC][25] = 46, ++ [0][1][1][0][RTW89_ACMA][25] = 127, ++ [0][1][1][0][RTW89_CHILE][25] = 42, ++ [0][1][1][0][RTW89_UKRAINE][25] = 40, ++ [0][1][1][0][RTW89_FCC][27] = 68, ++ [0][1][1][0][RTW89_ETSI][27] = 46, ++ [0][1][1][0][RTW89_MKK][27] = 70, ++ [0][1][1][0][RTW89_IC][27] = 127, ++ [0][1][1][0][RTW89_KCC][27] = 46, ++ [0][1][1][0][RTW89_ACMA][27] = 127, ++ [0][1][1][0][RTW89_CHILE][27] = 42, ++ [0][1][1][0][RTW89_UKRAINE][27] = 40, ++ [0][1][1][0][RTW89_FCC][29] = 68, ++ [0][1][1][0][RTW89_ETSI][29] = 46, ++ [0][1][1][0][RTW89_MKK][29] = 70, ++ [0][1][1][0][RTW89_IC][29] = 127, ++ [0][1][1][0][RTW89_KCC][29] = 46, ++ [0][1][1][0][RTW89_ACMA][29] = 127, ++ [0][1][1][0][RTW89_CHILE][29] = 42, ++ [0][1][1][0][RTW89_UKRAINE][29] = 40, ++ [0][1][1][0][RTW89_FCC][31] = 68, ++ [0][1][1][0][RTW89_ETSI][31] = 46, ++ [0][1][1][0][RTW89_MKK][31] = 70, ++ [0][1][1][0][RTW89_IC][31] = 68, ++ [0][1][1][0][RTW89_KCC][31] = 46, ++ [0][1][1][0][RTW89_ACMA][31] = 46, ++ [0][1][1][0][RTW89_CHILE][31] = 42, ++ [0][1][1][0][RTW89_UKRAINE][31] = 40, ++ [0][1][1][0][RTW89_FCC][33] = 68, ++ [0][1][1][0][RTW89_ETSI][33] = 46, ++ [0][1][1][0][RTW89_MKK][33] = 70, ++ [0][1][1][0][RTW89_IC][33] = 68, ++ [0][1][1][0][RTW89_KCC][33] = 46, ++ [0][1][1][0][RTW89_ACMA][33] = 46, ++ [0][1][1][0][RTW89_CHILE][33] = 42, ++ [0][1][1][0][RTW89_UKRAINE][33] = 40, ++ [0][1][1][0][RTW89_FCC][35] = 66, ++ [0][1][1][0][RTW89_ETSI][35] = 46, ++ [0][1][1][0][RTW89_MKK][35] = 70, ++ [0][1][1][0][RTW89_IC][35] = 66, ++ [0][1][1][0][RTW89_KCC][35] = 46, ++ [0][1][1][0][RTW89_ACMA][35] = 46, ++ [0][1][1][0][RTW89_CHILE][35] = 42, ++ [0][1][1][0][RTW89_UKRAINE][35] = 40, ++ [0][1][1][0][RTW89_FCC][37] = 68, ++ [0][1][1][0][RTW89_ETSI][37] = 127, ++ [0][1][1][0][RTW89_MKK][37] = 70, ++ [0][1][1][0][RTW89_IC][37] = 68, ++ [0][1][1][0][RTW89_KCC][37] = 46, ++ [0][1][1][0][RTW89_ACMA][37] = 68, ++ [0][1][1][0][RTW89_CHILE][37] = 42, ++ [0][1][1][0][RTW89_UKRAINE][37] = 127, ++ [0][1][1][0][RTW89_FCC][38] = 76, ++ [0][1][1][0][RTW89_ETSI][38] = 16, ++ [0][1][1][0][RTW89_MKK][38] = 127, ++ [0][1][1][0][RTW89_IC][38] = 76, ++ [0][1][1][0][RTW89_KCC][38] = 16, ++ [0][1][1][0][RTW89_ACMA][38] = 76, ++ [0][1][1][0][RTW89_CHILE][38] = 42, ++ [0][1][1][0][RTW89_UKRAINE][38] = 40, ++ [0][1][1][0][RTW89_FCC][40] = 76, ++ [0][1][1][0][RTW89_ETSI][40] = 16, ++ [0][1][1][0][RTW89_MKK][40] = 127, ++ [0][1][1][0][RTW89_IC][40] = 76, ++ [0][1][1][0][RTW89_KCC][40] = 16, ++ [0][1][1][0][RTW89_ACMA][40] = 76, ++ [0][1][1][0][RTW89_CHILE][40] = 42, ++ [0][1][1][0][RTW89_UKRAINE][40] = 40, ++ [0][1][1][0][RTW89_FCC][42] = 76, ++ [0][1][1][0][RTW89_ETSI][42] = 16, ++ [0][1][1][0][RTW89_MKK][42] = 127, ++ [0][1][1][0][RTW89_IC][42] = 76, ++ [0][1][1][0][RTW89_KCC][42] = 16, ++ [0][1][1][0][RTW89_ACMA][42] = 76, ++ [0][1][1][0][RTW89_CHILE][42] = 42, ++ [0][1][1][0][RTW89_UKRAINE][42] = 40, ++ [0][1][1][0][RTW89_FCC][44] = 76, ++ [0][1][1][0][RTW89_ETSI][44] = 16, ++ [0][1][1][0][RTW89_MKK][44] = 127, ++ [0][1][1][0][RTW89_IC][44] = 76, ++ [0][1][1][0][RTW89_KCC][44] = 16, ++ [0][1][1][0][RTW89_ACMA][44] = 76, ++ [0][1][1][0][RTW89_CHILE][44] = 42, ++ [0][1][1][0][RTW89_UKRAINE][44] = 40, ++ [0][1][1][0][RTW89_FCC][46] = 76, ++ [0][1][1][0][RTW89_ETSI][46] = 16, ++ [0][1][1][0][RTW89_MKK][46] = 127, ++ [0][1][1][0][RTW89_IC][46] = 76, ++ [0][1][1][0][RTW89_KCC][46] = 16, ++ [0][1][1][0][RTW89_ACMA][46] = 76, ++ [0][1][1][0][RTW89_CHILE][46] = 42, ++ [0][1][1][0][RTW89_UKRAINE][46] = 40, ++ [0][0][2][0][RTW89_FCC][0] = 76, ++ [0][0][2][0][RTW89_ETSI][0] = 58, ++ [0][0][2][0][RTW89_MKK][0] = 62, ++ [0][0][2][0][RTW89_IC][0] = 62, ++ [0][0][2][0][RTW89_KCC][0] = 58, ++ [0][0][2][0][RTW89_ACMA][0] = 58, ++ [0][0][2][0][RTW89_CHILE][0] = 30, ++ [0][0][2][0][RTW89_UKRAINE][0] = 52, ++ [0][0][2][0][RTW89_FCC][2] = 76, ++ [0][0][2][0][RTW89_ETSI][2] = 58, ++ [0][0][2][0][RTW89_MKK][2] = 62, ++ [0][0][2][0][RTW89_IC][2] = 62, ++ [0][0][2][0][RTW89_KCC][2] = 58, ++ [0][0][2][0][RTW89_ACMA][2] = 58, ++ [0][0][2][0][RTW89_CHILE][2] = 30, ++ [0][0][2][0][RTW89_UKRAINE][2] = 52, ++ [0][0][2][0][RTW89_FCC][4] = 76, ++ [0][0][2][0][RTW89_ETSI][4] = 58, ++ [0][0][2][0][RTW89_MKK][4] = 62, ++ [0][0][2][0][RTW89_IC][4] = 62, ++ [0][0][2][0][RTW89_KCC][4] = 58, ++ [0][0][2][0][RTW89_ACMA][4] = 58, ++ [0][0][2][0][RTW89_CHILE][4] = 30, ++ [0][0][2][0][RTW89_UKRAINE][4] = 52, ++ [0][0][2][0][RTW89_FCC][6] = 76, ++ [0][0][2][0][RTW89_ETSI][6] = 58, ++ [0][0][2][0][RTW89_MKK][6] = 62, ++ [0][0][2][0][RTW89_IC][6] = 62, ++ [0][0][2][0][RTW89_KCC][6] = 54, ++ [0][0][2][0][RTW89_ACMA][6] = 58, ++ [0][0][2][0][RTW89_CHILE][6] = 30, ++ [0][0][2][0][RTW89_UKRAINE][6] = 52, ++ [0][0][2][0][RTW89_FCC][8] = 76, ++ [0][0][2][0][RTW89_ETSI][8] = 58, ++ [0][0][2][0][RTW89_MKK][8] = 62, ++ [0][0][2][0][RTW89_IC][8] = 64, ++ [0][0][2][0][RTW89_KCC][8] = 58, ++ [0][0][2][0][RTW89_ACMA][8] = 58, ++ [0][0][2][0][RTW89_CHILE][8] = 54, ++ [0][0][2][0][RTW89_UKRAINE][8] = 52, ++ [0][0][2][0][RTW89_FCC][10] = 76, ++ [0][0][2][0][RTW89_ETSI][10] = 58, ++ [0][0][2][0][RTW89_MKK][10] = 62, ++ [0][0][2][0][RTW89_IC][10] = 64, ++ [0][0][2][0][RTW89_KCC][10] = 58, ++ [0][0][2][0][RTW89_ACMA][10] = 58, ++ [0][0][2][0][RTW89_CHILE][10] = 54, ++ [0][0][2][0][RTW89_UKRAINE][10] = 52, ++ [0][0][2][0][RTW89_FCC][12] = 76, ++ [0][0][2][0][RTW89_ETSI][12] = 58, ++ [0][0][2][0][RTW89_MKK][12] = 62, ++ [0][0][2][0][RTW89_IC][12] = 64, ++ [0][0][2][0][RTW89_KCC][12] = 58, ++ [0][0][2][0][RTW89_ACMA][12] = 58, ++ [0][0][2][0][RTW89_CHILE][12] = 54, ++ [0][0][2][0][RTW89_UKRAINE][12] = 52, ++ [0][0][2][0][RTW89_FCC][14] = 76, ++ [0][0][2][0][RTW89_ETSI][14] = 58, ++ [0][0][2][0][RTW89_MKK][14] = 62, ++ [0][0][2][0][RTW89_IC][14] = 64, ++ [0][0][2][0][RTW89_KCC][14] = 58, ++ [0][0][2][0][RTW89_ACMA][14] = 58, ++ [0][0][2][0][RTW89_CHILE][14] = 54, ++ [0][0][2][0][RTW89_UKRAINE][14] = 52, ++ [0][0][2][0][RTW89_FCC][15] = 74, ++ [0][0][2][0][RTW89_ETSI][15] = 58, ++ [0][0][2][0][RTW89_MKK][15] = 76, ++ [0][0][2][0][RTW89_IC][15] = 74, ++ [0][0][2][0][RTW89_KCC][15] = 58, ++ [0][0][2][0][RTW89_ACMA][15] = 58, ++ [0][0][2][0][RTW89_CHILE][15] = 54, ++ [0][0][2][0][RTW89_UKRAINE][15] = 52, ++ [0][0][2][0][RTW89_FCC][17] = 76, ++ [0][0][2][0][RTW89_ETSI][17] = 58, ++ [0][0][2][0][RTW89_MKK][17] = 76, ++ [0][0][2][0][RTW89_IC][17] = 76, ++ [0][0][2][0][RTW89_KCC][17] = 58, ++ [0][0][2][0][RTW89_ACMA][17] = 58, ++ [0][0][2][0][RTW89_CHILE][17] = 54, ++ [0][0][2][0][RTW89_UKRAINE][17] = 52, ++ [0][0][2][0][RTW89_FCC][19] = 76, ++ [0][0][2][0][RTW89_ETSI][19] = 58, ++ [0][0][2][0][RTW89_MKK][19] = 76, ++ [0][0][2][0][RTW89_IC][19] = 76, ++ [0][0][2][0][RTW89_KCC][19] = 58, ++ [0][0][2][0][RTW89_ACMA][19] = 58, ++ [0][0][2][0][RTW89_CHILE][19] = 54, ++ [0][0][2][0][RTW89_UKRAINE][19] = 52, ++ [0][0][2][0][RTW89_FCC][21] = 76, ++ [0][0][2][0][RTW89_ETSI][21] = 58, ++ [0][0][2][0][RTW89_MKK][21] = 76, ++ [0][0][2][0][RTW89_IC][21] = 76, ++ [0][0][2][0][RTW89_KCC][21] = 58, ++ [0][0][2][0][RTW89_ACMA][21] = 58, ++ [0][0][2][0][RTW89_CHILE][21] = 54, ++ [0][0][2][0][RTW89_UKRAINE][21] = 52, ++ [0][0][2][0][RTW89_FCC][23] = 76, ++ [0][0][2][0][RTW89_ETSI][23] = 58, ++ [0][0][2][0][RTW89_MKK][23] = 76, ++ [0][0][2][0][RTW89_IC][23] = 76, ++ [0][0][2][0][RTW89_KCC][23] = 58, ++ [0][0][2][0][RTW89_ACMA][23] = 58, ++ [0][0][2][0][RTW89_CHILE][23] = 54, ++ [0][0][2][0][RTW89_UKRAINE][23] = 52, ++ [0][0][2][0][RTW89_FCC][25] = 76, ++ [0][0][2][0][RTW89_ETSI][25] = 58, ++ [0][0][2][0][RTW89_MKK][25] = 76, ++ [0][0][2][0][RTW89_IC][25] = 127, ++ [0][0][2][0][RTW89_KCC][25] = 58, ++ [0][0][2][0][RTW89_ACMA][25] = 127, ++ [0][0][2][0][RTW89_CHILE][25] = 54, ++ [0][0][2][0][RTW89_UKRAINE][25] = 52, ++ [0][0][2][0][RTW89_FCC][27] = 76, ++ [0][0][2][0][RTW89_ETSI][27] = 58, ++ [0][0][2][0][RTW89_MKK][27] = 76, ++ [0][0][2][0][RTW89_IC][27] = 127, ++ [0][0][2][0][RTW89_KCC][27] = 58, ++ [0][0][2][0][RTW89_ACMA][27] = 127, ++ [0][0][2][0][RTW89_CHILE][27] = 54, ++ [0][0][2][0][RTW89_UKRAINE][27] = 52, ++ [0][0][2][0][RTW89_FCC][29] = 76, ++ [0][0][2][0][RTW89_ETSI][29] = 58, ++ [0][0][2][0][RTW89_MKK][29] = 76, ++ [0][0][2][0][RTW89_IC][29] = 127, ++ [0][0][2][0][RTW89_KCC][29] = 58, ++ [0][0][2][0][RTW89_ACMA][29] = 127, ++ [0][0][2][0][RTW89_CHILE][29] = 54, ++ [0][0][2][0][RTW89_UKRAINE][29] = 52, ++ [0][0][2][0][RTW89_FCC][31] = 76, ++ [0][0][2][0][RTW89_ETSI][31] = 58, ++ [0][0][2][0][RTW89_MKK][31] = 76, ++ [0][0][2][0][RTW89_IC][31] = 76, ++ [0][0][2][0][RTW89_KCC][31] = 58, ++ [0][0][2][0][RTW89_ACMA][31] = 58, ++ [0][0][2][0][RTW89_CHILE][31] = 54, ++ [0][0][2][0][RTW89_UKRAINE][31] = 52, ++ [0][0][2][0][RTW89_FCC][33] = 76, ++ [0][0][2][0][RTW89_ETSI][33] = 58, ++ [0][0][2][0][RTW89_MKK][33] = 76, ++ [0][0][2][0][RTW89_IC][33] = 76, ++ [0][0][2][0][RTW89_KCC][33] = 58, ++ [0][0][2][0][RTW89_ACMA][33] = 58, ++ [0][0][2][0][RTW89_CHILE][33] = 54, ++ [0][0][2][0][RTW89_UKRAINE][33] = 52, ++ [0][0][2][0][RTW89_FCC][35] = 70, ++ [0][0][2][0][RTW89_ETSI][35] = 58, ++ [0][0][2][0][RTW89_MKK][35] = 76, ++ [0][0][2][0][RTW89_IC][35] = 70, ++ [0][0][2][0][RTW89_KCC][35] = 58, ++ [0][0][2][0][RTW89_ACMA][35] = 58, ++ [0][0][2][0][RTW89_CHILE][35] = 54, ++ [0][0][2][0][RTW89_UKRAINE][35] = 52, ++ [0][0][2][0][RTW89_FCC][37] = 76, ++ [0][0][2][0][RTW89_ETSI][37] = 127, ++ [0][0][2][0][RTW89_MKK][37] = 76, ++ [0][0][2][0][RTW89_IC][37] = 76, ++ [0][0][2][0][RTW89_KCC][37] = 58, ++ [0][0][2][0][RTW89_ACMA][37] = 76, ++ [0][0][2][0][RTW89_CHILE][37] = 54, ++ [0][0][2][0][RTW89_UKRAINE][37] = 127, ++ [0][0][2][0][RTW89_FCC][38] = 76, ++ [0][0][2][0][RTW89_ETSI][38] = 28, ++ [0][0][2][0][RTW89_MKK][38] = 127, ++ [0][0][2][0][RTW89_IC][38] = 76, ++ [0][0][2][0][RTW89_KCC][38] = 28, ++ [0][0][2][0][RTW89_ACMA][38] = 76, ++ [0][0][2][0][RTW89_CHILE][38] = 54, ++ [0][0][2][0][RTW89_UKRAINE][38] = 52, ++ [0][0][2][0][RTW89_FCC][40] = 76, ++ [0][0][2][0][RTW89_ETSI][40] = 28, ++ [0][0][2][0][RTW89_MKK][40] = 127, ++ [0][0][2][0][RTW89_IC][40] = 76, ++ [0][0][2][0][RTW89_KCC][40] = 28, ++ [0][0][2][0][RTW89_ACMA][40] = 76, ++ [0][0][2][0][RTW89_CHILE][40] = 54, ++ [0][0][2][0][RTW89_UKRAINE][40] = 52, ++ [0][0][2][0][RTW89_FCC][42] = 76, ++ [0][0][2][0][RTW89_ETSI][42] = 28, ++ [0][0][2][0][RTW89_MKK][42] = 127, ++ [0][0][2][0][RTW89_IC][42] = 76, ++ [0][0][2][0][RTW89_KCC][42] = 28, ++ [0][0][2][0][RTW89_ACMA][42] = 76, ++ [0][0][2][0][RTW89_CHILE][42] = 54, ++ [0][0][2][0][RTW89_UKRAINE][42] = 52, ++ [0][0][2][0][RTW89_FCC][44] = 76, ++ [0][0][2][0][RTW89_ETSI][44] = 28, ++ [0][0][2][0][RTW89_MKK][44] = 127, ++ [0][0][2][0][RTW89_IC][44] = 76, ++ [0][0][2][0][RTW89_KCC][44] = 28, ++ [0][0][2][0][RTW89_ACMA][44] = 76, ++ [0][0][2][0][RTW89_CHILE][44] = 54, ++ [0][0][2][0][RTW89_UKRAINE][44] = 52, ++ [0][0][2][0][RTW89_FCC][46] = 76, ++ [0][0][2][0][RTW89_ETSI][46] = 28, ++ [0][0][2][0][RTW89_MKK][46] = 127, ++ [0][0][2][0][RTW89_IC][46] = 76, ++ [0][0][2][0][RTW89_KCC][46] = 28, ++ [0][0][2][0][RTW89_ACMA][46] = 76, ++ [0][0][2][0][RTW89_CHILE][46] = 54, ++ [0][0][2][0][RTW89_UKRAINE][46] = 52, ++ [0][1][2][0][RTW89_FCC][0] = 68, ++ [0][1][2][0][RTW89_ETSI][0] = 46, ++ [0][1][2][0][RTW89_MKK][0] = 50, ++ [0][1][2][0][RTW89_IC][0] = 40, ++ [0][1][2][0][RTW89_KCC][0] = 46, ++ [0][1][2][0][RTW89_ACMA][0] = 46, ++ [0][1][2][0][RTW89_CHILE][0] = 18, ++ [0][1][2][0][RTW89_UKRAINE][0] = 40, ++ [0][1][2][0][RTW89_FCC][2] = 68, ++ [0][1][2][0][RTW89_ETSI][2] = 46, ++ [0][1][2][0][RTW89_MKK][2] = 50, ++ [0][1][2][0][RTW89_IC][2] = 40, ++ [0][1][2][0][RTW89_KCC][2] = 46, ++ [0][1][2][0][RTW89_ACMA][2] = 46, ++ [0][1][2][0][RTW89_CHILE][2] = 18, ++ [0][1][2][0][RTW89_UKRAINE][2] = 40, ++ [0][1][2][0][RTW89_FCC][4] = 68, ++ [0][1][2][0][RTW89_ETSI][4] = 46, ++ [0][1][2][0][RTW89_MKK][4] = 50, ++ [0][1][2][0][RTW89_IC][4] = 40, ++ [0][1][2][0][RTW89_KCC][4] = 46, ++ [0][1][2][0][RTW89_ACMA][4] = 46, ++ [0][1][2][0][RTW89_CHILE][4] = 18, ++ [0][1][2][0][RTW89_UKRAINE][4] = 40, ++ [0][1][2][0][RTW89_FCC][6] = 68, ++ [0][1][2][0][RTW89_ETSI][6] = 46, ++ [0][1][2][0][RTW89_MKK][6] = 50, ++ [0][1][2][0][RTW89_IC][6] = 40, ++ [0][1][2][0][RTW89_KCC][6] = 36, ++ [0][1][2][0][RTW89_ACMA][6] = 46, ++ [0][1][2][0][RTW89_CHILE][6] = 18, ++ [0][1][2][0][RTW89_UKRAINE][6] = 40, ++ [0][1][2][0][RTW89_FCC][8] = 68, ++ [0][1][2][0][RTW89_ETSI][8] = 46, ++ [0][1][2][0][RTW89_MKK][8] = 50, ++ [0][1][2][0][RTW89_IC][8] = 52, ++ [0][1][2][0][RTW89_KCC][8] = 46, ++ [0][1][2][0][RTW89_ACMA][8] = 46, ++ [0][1][2][0][RTW89_CHILE][8] = 42, ++ [0][1][2][0][RTW89_UKRAINE][8] = 40, ++ [0][1][2][0][RTW89_FCC][10] = 68, ++ [0][1][2][0][RTW89_ETSI][10] = 46, ++ [0][1][2][0][RTW89_MKK][10] = 50, ++ [0][1][2][0][RTW89_IC][10] = 52, ++ [0][1][2][0][RTW89_KCC][10] = 46, ++ [0][1][2][0][RTW89_ACMA][10] = 46, ++ [0][1][2][0][RTW89_CHILE][10] = 42, ++ [0][1][2][0][RTW89_UKRAINE][10] = 40, ++ [0][1][2][0][RTW89_FCC][12] = 68, ++ [0][1][2][0][RTW89_ETSI][12] = 46, ++ [0][1][2][0][RTW89_MKK][12] = 50, ++ [0][1][2][0][RTW89_IC][12] = 52, ++ [0][1][2][0][RTW89_KCC][12] = 46, ++ [0][1][2][0][RTW89_ACMA][12] = 46, ++ [0][1][2][0][RTW89_CHILE][12] = 42, ++ [0][1][2][0][RTW89_UKRAINE][12] = 40, ++ [0][1][2][0][RTW89_FCC][14] = 68, ++ [0][1][2][0][RTW89_ETSI][14] = 46, ++ [0][1][2][0][RTW89_MKK][14] = 50, ++ [0][1][2][0][RTW89_IC][14] = 52, ++ [0][1][2][0][RTW89_KCC][14] = 46, ++ [0][1][2][0][RTW89_ACMA][14] = 46, ++ [0][1][2][0][RTW89_CHILE][14] = 42, ++ [0][1][2][0][RTW89_UKRAINE][14] = 40, ++ [0][1][2][0][RTW89_FCC][15] = 68, ++ [0][1][2][0][RTW89_ETSI][15] = 46, ++ [0][1][2][0][RTW89_MKK][15] = 70, ++ [0][1][2][0][RTW89_IC][15] = 68, ++ [0][1][2][0][RTW89_KCC][15] = 46, ++ [0][1][2][0][RTW89_ACMA][15] = 46, ++ [0][1][2][0][RTW89_CHILE][15] = 42, ++ [0][1][2][0][RTW89_UKRAINE][15] = 40, ++ [0][1][2][0][RTW89_FCC][17] = 68, ++ [0][1][2][0][RTW89_ETSI][17] = 46, ++ [0][1][2][0][RTW89_MKK][17] = 70, ++ [0][1][2][0][RTW89_IC][17] = 68, ++ [0][1][2][0][RTW89_KCC][17] = 46, ++ [0][1][2][0][RTW89_ACMA][17] = 46, ++ [0][1][2][0][RTW89_CHILE][17] = 42, ++ [0][1][2][0][RTW89_UKRAINE][17] = 40, ++ [0][1][2][0][RTW89_FCC][19] = 68, ++ [0][1][2][0][RTW89_ETSI][19] = 46, ++ [0][1][2][0][RTW89_MKK][19] = 70, ++ [0][1][2][0][RTW89_IC][19] = 68, ++ [0][1][2][0][RTW89_KCC][19] = 46, ++ [0][1][2][0][RTW89_ACMA][19] = 46, ++ [0][1][2][0][RTW89_CHILE][19] = 42, ++ [0][1][2][0][RTW89_UKRAINE][19] = 40, ++ [0][1][2][0][RTW89_FCC][21] = 68, ++ [0][1][2][0][RTW89_ETSI][21] = 46, ++ [0][1][2][0][RTW89_MKK][21] = 70, ++ [0][1][2][0][RTW89_IC][21] = 68, ++ [0][1][2][0][RTW89_KCC][21] = 46, ++ [0][1][2][0][RTW89_ACMA][21] = 46, ++ [0][1][2][0][RTW89_CHILE][21] = 42, ++ [0][1][2][0][RTW89_UKRAINE][21] = 40, ++ [0][1][2][0][RTW89_FCC][23] = 68, ++ [0][1][2][0][RTW89_ETSI][23] = 46, ++ [0][1][2][0][RTW89_MKK][23] = 70, ++ [0][1][2][0][RTW89_IC][23] = 68, ++ [0][1][2][0][RTW89_KCC][23] = 46, ++ [0][1][2][0][RTW89_ACMA][23] = 46, ++ [0][1][2][0][RTW89_CHILE][23] = 42, ++ [0][1][2][0][RTW89_UKRAINE][23] = 40, ++ [0][1][2][0][RTW89_FCC][25] = 68, ++ [0][1][2][0][RTW89_ETSI][25] = 46, ++ [0][1][2][0][RTW89_MKK][25] = 70, ++ [0][1][2][0][RTW89_IC][25] = 127, ++ [0][1][2][0][RTW89_KCC][25] = 46, ++ [0][1][2][0][RTW89_ACMA][25] = 127, ++ [0][1][2][0][RTW89_CHILE][25] = 42, ++ [0][1][2][0][RTW89_UKRAINE][25] = 40, ++ [0][1][2][0][RTW89_FCC][27] = 68, ++ [0][1][2][0][RTW89_ETSI][27] = 46, ++ [0][1][2][0][RTW89_MKK][27] = 70, ++ [0][1][2][0][RTW89_IC][27] = 127, ++ [0][1][2][0][RTW89_KCC][27] = 46, ++ [0][1][2][0][RTW89_ACMA][27] = 127, ++ [0][1][2][0][RTW89_CHILE][27] = 42, ++ [0][1][2][0][RTW89_UKRAINE][27] = 40, ++ [0][1][2][0][RTW89_FCC][29] = 68, ++ [0][1][2][0][RTW89_ETSI][29] = 46, ++ [0][1][2][0][RTW89_MKK][29] = 70, ++ [0][1][2][0][RTW89_IC][29] = 127, ++ [0][1][2][0][RTW89_KCC][29] = 46, ++ [0][1][2][0][RTW89_ACMA][29] = 127, ++ [0][1][2][0][RTW89_CHILE][29] = 42, ++ [0][1][2][0][RTW89_UKRAINE][29] = 40, ++ [0][1][2][0][RTW89_FCC][31] = 68, ++ [0][1][2][0][RTW89_ETSI][31] = 46, ++ [0][1][2][0][RTW89_MKK][31] = 70, ++ [0][1][2][0][RTW89_IC][31] = 68, ++ [0][1][2][0][RTW89_KCC][31] = 46, ++ [0][1][2][0][RTW89_ACMA][31] = 46, ++ [0][1][2][0][RTW89_CHILE][31] = 42, ++ [0][1][2][0][RTW89_UKRAINE][31] = 40, ++ [0][1][2][0][RTW89_FCC][33] = 68, ++ [0][1][2][0][RTW89_ETSI][33] = 46, ++ [0][1][2][0][RTW89_MKK][33] = 70, ++ [0][1][2][0][RTW89_IC][33] = 68, ++ [0][1][2][0][RTW89_KCC][33] = 46, ++ [0][1][2][0][RTW89_ACMA][33] = 46, ++ [0][1][2][0][RTW89_CHILE][33] = 42, ++ [0][1][2][0][RTW89_UKRAINE][33] = 40, ++ [0][1][2][0][RTW89_FCC][35] = 64, ++ [0][1][2][0][RTW89_ETSI][35] = 46, ++ [0][1][2][0][RTW89_MKK][35] = 70, ++ [0][1][2][0][RTW89_IC][35] = 64, ++ [0][1][2][0][RTW89_KCC][35] = 46, ++ [0][1][2][0][RTW89_ACMA][35] = 46, ++ [0][1][2][0][RTW89_CHILE][35] = 42, ++ [0][1][2][0][RTW89_UKRAINE][35] = 40, ++ [0][1][2][0][RTW89_FCC][37] = 68, ++ [0][1][2][0][RTW89_ETSI][37] = 127, ++ [0][1][2][0][RTW89_MKK][37] = 70, ++ [0][1][2][0][RTW89_IC][37] = 68, ++ [0][1][2][0][RTW89_KCC][37] = 46, ++ [0][1][2][0][RTW89_ACMA][37] = 68, ++ [0][1][2][0][RTW89_CHILE][37] = 42, ++ [0][1][2][0][RTW89_UKRAINE][37] = 127, ++ [0][1][2][0][RTW89_FCC][38] = 76, ++ [0][1][2][0][RTW89_ETSI][38] = 16, ++ [0][1][2][0][RTW89_MKK][38] = 127, ++ [0][1][2][0][RTW89_IC][38] = 76, ++ [0][1][2][0][RTW89_KCC][38] = 16, ++ [0][1][2][0][RTW89_ACMA][38] = 76, ++ [0][1][2][0][RTW89_CHILE][38] = 42, ++ [0][1][2][0][RTW89_UKRAINE][38] = 40, ++ [0][1][2][0][RTW89_FCC][40] = 76, ++ [0][1][2][0][RTW89_ETSI][40] = 16, ++ [0][1][2][0][RTW89_MKK][40] = 127, ++ [0][1][2][0][RTW89_IC][40] = 76, ++ [0][1][2][0][RTW89_KCC][40] = 16, ++ [0][1][2][0][RTW89_ACMA][40] = 76, ++ [0][1][2][0][RTW89_CHILE][40] = 42, ++ [0][1][2][0][RTW89_UKRAINE][40] = 40, ++ [0][1][2][0][RTW89_FCC][42] = 76, ++ [0][1][2][0][RTW89_ETSI][42] = 16, ++ [0][1][2][0][RTW89_MKK][42] = 127, ++ [0][1][2][0][RTW89_IC][42] = 76, ++ [0][1][2][0][RTW89_KCC][42] = 16, ++ [0][1][2][0][RTW89_ACMA][42] = 76, ++ [0][1][2][0][RTW89_CHILE][42] = 42, ++ [0][1][2][0][RTW89_UKRAINE][42] = 40, ++ [0][1][2][0][RTW89_FCC][44] = 76, ++ [0][1][2][0][RTW89_ETSI][44] = 16, ++ [0][1][2][0][RTW89_MKK][44] = 127, ++ [0][1][2][0][RTW89_IC][44] = 76, ++ [0][1][2][0][RTW89_KCC][44] = 16, ++ [0][1][2][0][RTW89_ACMA][44] = 76, ++ [0][1][2][0][RTW89_CHILE][44] = 42, ++ [0][1][2][0][RTW89_UKRAINE][44] = 40, ++ [0][1][2][0][RTW89_FCC][46] = 76, ++ [0][1][2][0][RTW89_ETSI][46] = 16, ++ [0][1][2][0][RTW89_MKK][46] = 127, ++ [0][1][2][0][RTW89_IC][46] = 76, ++ [0][1][2][0][RTW89_KCC][46] = 16, ++ [0][1][2][0][RTW89_ACMA][46] = 76, ++ [0][1][2][0][RTW89_CHILE][46] = 42, ++ [0][1][2][0][RTW89_UKRAINE][46] = 40, ++ [0][1][2][1][RTW89_FCC][0] = 68, ++ [0][1][2][1][RTW89_ETSI][0] = 34, ++ [0][1][2][1][RTW89_MKK][0] = 50, ++ [0][1][2][1][RTW89_IC][0] = 38, ++ [0][1][2][1][RTW89_KCC][0] = 34, ++ [0][1][2][1][RTW89_ACMA][0] = 34, ++ [0][1][2][1][RTW89_CHILE][0] = 6, ++ [0][1][2][1][RTW89_UKRAINE][0] = 28, ++ [0][1][2][1][RTW89_FCC][2] = 68, ++ [0][1][2][1][RTW89_ETSI][2] = 34, ++ [0][1][2][1][RTW89_MKK][2] = 50, ++ [0][1][2][1][RTW89_IC][2] = 38, ++ [0][1][2][1][RTW89_KCC][2] = 34, ++ [0][1][2][1][RTW89_ACMA][2] = 34, ++ [0][1][2][1][RTW89_CHILE][2] = 6, ++ [0][1][2][1][RTW89_UKRAINE][2] = 28, ++ [0][1][2][1][RTW89_FCC][4] = 68, ++ [0][1][2][1][RTW89_ETSI][4] = 34, ++ [0][1][2][1][RTW89_MKK][4] = 50, ++ [0][1][2][1][RTW89_IC][4] = 38, ++ [0][1][2][1][RTW89_KCC][4] = 34, ++ [0][1][2][1][RTW89_ACMA][4] = 34, ++ [0][1][2][1][RTW89_CHILE][4] = 6, ++ [0][1][2][1][RTW89_UKRAINE][4] = 28, ++ [0][1][2][1][RTW89_FCC][6] = 68, ++ [0][1][2][1][RTW89_ETSI][6] = 34, ++ [0][1][2][1][RTW89_MKK][6] = 50, ++ [0][1][2][1][RTW89_IC][6] = 38, ++ [0][1][2][1][RTW89_KCC][6] = 34, ++ [0][1][2][1][RTW89_ACMA][6] = 34, ++ [0][1][2][1][RTW89_CHILE][6] = 6, ++ [0][1][2][1][RTW89_UKRAINE][6] = 28, ++ [0][1][2][1][RTW89_FCC][8] = 68, ++ [0][1][2][1][RTW89_ETSI][8] = 34, ++ [0][1][2][1][RTW89_MKK][8] = 50, ++ [0][1][2][1][RTW89_IC][8] = 38, ++ [0][1][2][1][RTW89_KCC][8] = 34, ++ [0][1][2][1][RTW89_ACMA][8] = 34, ++ [0][1][2][1][RTW89_CHILE][8] = 30, ++ [0][1][2][1][RTW89_UKRAINE][8] = 28, ++ [0][1][2][1][RTW89_FCC][10] = 68, ++ [0][1][2][1][RTW89_ETSI][10] = 34, ++ [0][1][2][1][RTW89_MKK][10] = 50, ++ [0][1][2][1][RTW89_IC][10] = 38, ++ [0][1][2][1][RTW89_KCC][10] = 34, ++ [0][1][2][1][RTW89_ACMA][10] = 34, ++ [0][1][2][1][RTW89_CHILE][10] = 30, ++ [0][1][2][1][RTW89_UKRAINE][10] = 28, ++ [0][1][2][1][RTW89_FCC][12] = 68, ++ [0][1][2][1][RTW89_ETSI][12] = 34, ++ [0][1][2][1][RTW89_MKK][12] = 50, ++ [0][1][2][1][RTW89_IC][12] = 38, ++ [0][1][2][1][RTW89_KCC][12] = 34, ++ [0][1][2][1][RTW89_ACMA][12] = 34, ++ [0][1][2][1][RTW89_CHILE][12] = 30, ++ [0][1][2][1][RTW89_UKRAINE][12] = 28, ++ [0][1][2][1][RTW89_FCC][14] = 68, ++ [0][1][2][1][RTW89_ETSI][14] = 34, ++ [0][1][2][1][RTW89_MKK][14] = 50, ++ [0][1][2][1][RTW89_IC][14] = 38, ++ [0][1][2][1][RTW89_KCC][14] = 34, ++ [0][1][2][1][RTW89_ACMA][14] = 34, ++ [0][1][2][1][RTW89_CHILE][14] = 30, ++ [0][1][2][1][RTW89_UKRAINE][14] = 28, ++ [0][1][2][1][RTW89_FCC][15] = 68, ++ [0][1][2][1][RTW89_ETSI][15] = 34, ++ [0][1][2][1][RTW89_MKK][15] = 70, ++ [0][1][2][1][RTW89_IC][15] = 62, ++ [0][1][2][1][RTW89_KCC][15] = 34, ++ [0][1][2][1][RTW89_ACMA][15] = 34, ++ [0][1][2][1][RTW89_CHILE][15] = 30, ++ [0][1][2][1][RTW89_UKRAINE][15] = 28, ++ [0][1][2][1][RTW89_FCC][17] = 68, ++ [0][1][2][1][RTW89_ETSI][17] = 34, ++ [0][1][2][1][RTW89_MKK][17] = 70, ++ [0][1][2][1][RTW89_IC][17] = 62, ++ [0][1][2][1][RTW89_KCC][17] = 34, ++ [0][1][2][1][RTW89_ACMA][17] = 34, ++ [0][1][2][1][RTW89_CHILE][17] = 30, ++ [0][1][2][1][RTW89_UKRAINE][17] = 28, ++ [0][1][2][1][RTW89_FCC][19] = 68, ++ [0][1][2][1][RTW89_ETSI][19] = 34, ++ [0][1][2][1][RTW89_MKK][19] = 70, ++ [0][1][2][1][RTW89_IC][19] = 62, ++ [0][1][2][1][RTW89_KCC][19] = 34, ++ [0][1][2][1][RTW89_ACMA][19] = 34, ++ [0][1][2][1][RTW89_CHILE][19] = 30, ++ [0][1][2][1][RTW89_UKRAINE][19] = 28, ++ [0][1][2][1][RTW89_FCC][21] = 68, ++ [0][1][2][1][RTW89_ETSI][21] = 34, ++ [0][1][2][1][RTW89_MKK][21] = 70, ++ [0][1][2][1][RTW89_IC][21] = 62, ++ [0][1][2][1][RTW89_KCC][21] = 34, ++ [0][1][2][1][RTW89_ACMA][21] = 34, ++ [0][1][2][1][RTW89_CHILE][21] = 30, ++ [0][1][2][1][RTW89_UKRAINE][21] = 28, ++ [0][1][2][1][RTW89_FCC][23] = 68, ++ [0][1][2][1][RTW89_ETSI][23] = 34, ++ [0][1][2][1][RTW89_MKK][23] = 70, ++ [0][1][2][1][RTW89_IC][23] = 62, ++ [0][1][2][1][RTW89_KCC][23] = 34, ++ [0][1][2][1][RTW89_ACMA][23] = 34, ++ [0][1][2][1][RTW89_CHILE][23] = 30, ++ [0][1][2][1][RTW89_UKRAINE][23] = 28, ++ [0][1][2][1][RTW89_FCC][25] = 68, ++ [0][1][2][1][RTW89_ETSI][25] = 34, ++ [0][1][2][1][RTW89_MKK][25] = 70, ++ [0][1][2][1][RTW89_IC][25] = 127, ++ [0][1][2][1][RTW89_KCC][25] = 34, ++ [0][1][2][1][RTW89_ACMA][25] = 127, ++ [0][1][2][1][RTW89_CHILE][25] = 30, ++ [0][1][2][1][RTW89_UKRAINE][25] = 28, ++ [0][1][2][1][RTW89_FCC][27] = 68, ++ [0][1][2][1][RTW89_ETSI][27] = 34, ++ [0][1][2][1][RTW89_MKK][27] = 70, ++ [0][1][2][1][RTW89_IC][27] = 127, ++ [0][1][2][1][RTW89_KCC][27] = 34, ++ [0][1][2][1][RTW89_ACMA][27] = 127, ++ [0][1][2][1][RTW89_CHILE][27] = 30, ++ [0][1][2][1][RTW89_UKRAINE][27] = 28, ++ [0][1][2][1][RTW89_FCC][29] = 68, ++ [0][1][2][1][RTW89_ETSI][29] = 34, ++ [0][1][2][1][RTW89_MKK][29] = 70, ++ [0][1][2][1][RTW89_IC][29] = 127, ++ [0][1][2][1][RTW89_KCC][29] = 34, ++ [0][1][2][1][RTW89_ACMA][29] = 127, ++ [0][1][2][1][RTW89_CHILE][29] = 30, ++ [0][1][2][1][RTW89_UKRAINE][29] = 28, ++ [0][1][2][1][RTW89_FCC][31] = 68, ++ [0][1][2][1][RTW89_ETSI][31] = 34, ++ [0][1][2][1][RTW89_MKK][31] = 70, ++ [0][1][2][1][RTW89_IC][31] = 62, ++ [0][1][2][1][RTW89_KCC][31] = 34, ++ [0][1][2][1][RTW89_ACMA][31] = 34, ++ [0][1][2][1][RTW89_CHILE][31] = 30, ++ [0][1][2][1][RTW89_UKRAINE][31] = 28, ++ [0][1][2][1][RTW89_FCC][33] = 68, ++ [0][1][2][1][RTW89_ETSI][33] = 34, ++ [0][1][2][1][RTW89_MKK][33] = 70, ++ [0][1][2][1][RTW89_IC][33] = 62, ++ [0][1][2][1][RTW89_KCC][33] = 34, ++ [0][1][2][1][RTW89_ACMA][33] = 34, ++ [0][1][2][1][RTW89_CHILE][33] = 30, ++ [0][1][2][1][RTW89_UKRAINE][33] = 28, ++ [0][1][2][1][RTW89_FCC][35] = 64, ++ [0][1][2][1][RTW89_ETSI][35] = 34, ++ [0][1][2][1][RTW89_MKK][35] = 70, ++ [0][1][2][1][RTW89_IC][35] = 62, ++ [0][1][2][1][RTW89_KCC][35] = 34, ++ [0][1][2][1][RTW89_ACMA][35] = 34, ++ [0][1][2][1][RTW89_CHILE][35] = 30, ++ [0][1][2][1][RTW89_UKRAINE][35] = 28, ++ [0][1][2][1][RTW89_FCC][37] = 68, ++ [0][1][2][1][RTW89_ETSI][37] = 127, ++ [0][1][2][1][RTW89_MKK][37] = 70, ++ [0][1][2][1][RTW89_IC][37] = 62, ++ [0][1][2][1][RTW89_KCC][37] = 34, ++ [0][1][2][1][RTW89_ACMA][37] = 68, ++ [0][1][2][1][RTW89_CHILE][37] = 30, ++ [0][1][2][1][RTW89_UKRAINE][37] = 127, ++ [0][1][2][1][RTW89_FCC][38] = 76, ++ [0][1][2][1][RTW89_ETSI][38] = 4, ++ [0][1][2][1][RTW89_MKK][38] = 127, ++ [0][1][2][1][RTW89_IC][38] = 76, ++ [0][1][2][1][RTW89_KCC][38] = 4, ++ [0][1][2][1][RTW89_ACMA][38] = 76, ++ [0][1][2][1][RTW89_CHILE][38] = 30, ++ [0][1][2][1][RTW89_UKRAINE][38] = 28, ++ [0][1][2][1][RTW89_FCC][40] = 76, ++ [0][1][2][1][RTW89_ETSI][40] = 4, ++ [0][1][2][1][RTW89_MKK][40] = 127, ++ [0][1][2][1][RTW89_IC][40] = 76, ++ [0][1][2][1][RTW89_KCC][40] = 4, ++ [0][1][2][1][RTW89_ACMA][40] = 76, ++ [0][1][2][1][RTW89_CHILE][40] = 30, ++ [0][1][2][1][RTW89_UKRAINE][40] = 28, ++ [0][1][2][1][RTW89_FCC][42] = 76, ++ [0][1][2][1][RTW89_ETSI][42] = 4, ++ [0][1][2][1][RTW89_MKK][42] = 127, ++ [0][1][2][1][RTW89_IC][42] = 76, ++ [0][1][2][1][RTW89_KCC][42] = 4, ++ [0][1][2][1][RTW89_ACMA][42] = 76, ++ [0][1][2][1][RTW89_CHILE][42] = 30, ++ [0][1][2][1][RTW89_UKRAINE][42] = 28, ++ [0][1][2][1][RTW89_FCC][44] = 76, ++ [0][1][2][1][RTW89_ETSI][44] = 4, ++ [0][1][2][1][RTW89_MKK][44] = 127, ++ [0][1][2][1][RTW89_IC][44] = 76, ++ [0][1][2][1][RTW89_KCC][44] = 4, ++ [0][1][2][1][RTW89_ACMA][44] = 76, ++ [0][1][2][1][RTW89_CHILE][44] = 30, ++ [0][1][2][1][RTW89_UKRAINE][44] = 28, ++ [0][1][2][1][RTW89_FCC][46] = 76, ++ [0][1][2][1][RTW89_ETSI][46] = 4, ++ [0][1][2][1][RTW89_MKK][46] = 127, ++ [0][1][2][1][RTW89_IC][46] = 76, ++ [0][1][2][1][RTW89_KCC][46] = 4, ++ [0][1][2][1][RTW89_ACMA][46] = 76, ++ [0][1][2][1][RTW89_CHILE][46] = 30, ++ [0][1][2][1][RTW89_UKRAINE][46] = 28, ++ [1][0][2][0][RTW89_FCC][1] = 68, ++ [1][0][2][0][RTW89_ETSI][1] = 64, ++ [1][0][2][0][RTW89_MKK][1] = 62, ++ [1][0][2][0][RTW89_IC][1] = 64, ++ [1][0][2][0][RTW89_KCC][1] = 64, ++ [1][0][2][0][RTW89_ACMA][1] = 64, ++ [1][0][2][0][RTW89_CHILE][1] = 30, ++ [1][0][2][0][RTW89_UKRAINE][1] = 52, ++ [1][0][2][0][RTW89_FCC][5] = 72, ++ [1][0][2][0][RTW89_ETSI][5] = 64, ++ [1][0][2][0][RTW89_MKK][5] = 62, ++ [1][0][2][0][RTW89_IC][5] = 64, ++ [1][0][2][0][RTW89_KCC][5] = 60, ++ [1][0][2][0][RTW89_ACMA][5] = 64, ++ [1][0][2][0][RTW89_CHILE][5] = 30, ++ [1][0][2][0][RTW89_UKRAINE][5] = 52, ++ [1][0][2][0][RTW89_FCC][9] = 72, ++ [1][0][2][0][RTW89_ETSI][9] = 64, ++ [1][0][2][0][RTW89_MKK][9] = 62, ++ [1][0][2][0][RTW89_IC][9] = 64, ++ [1][0][2][0][RTW89_KCC][9] = 64, ++ [1][0][2][0][RTW89_ACMA][9] = 64, ++ [1][0][2][0][RTW89_CHILE][9] = 54, ++ [1][0][2][0][RTW89_UKRAINE][9] = 52, ++ [1][0][2][0][RTW89_FCC][13] = 66, ++ [1][0][2][0][RTW89_ETSI][13] = 64, ++ [1][0][2][0][RTW89_MKK][13] = 62, ++ [1][0][2][0][RTW89_IC][13] = 64, ++ [1][0][2][0][RTW89_KCC][13] = 64, ++ [1][0][2][0][RTW89_ACMA][13] = 64, ++ [1][0][2][0][RTW89_CHILE][13] = 54, ++ [1][0][2][0][RTW89_UKRAINE][13] = 52, ++ [1][0][2][0][RTW89_FCC][16] = 62, ++ [1][0][2][0][RTW89_ETSI][16] = 64, ++ [1][0][2][0][RTW89_MKK][16] = 72, ++ [1][0][2][0][RTW89_IC][16] = 62, ++ [1][0][2][0][RTW89_KCC][16] = 64, ++ [1][0][2][0][RTW89_ACMA][16] = 64, ++ [1][0][2][0][RTW89_CHILE][16] = 54, ++ [1][0][2][0][RTW89_UKRAINE][16] = 52, ++ [1][0][2][0][RTW89_FCC][20] = 72, ++ [1][0][2][0][RTW89_ETSI][20] = 64, ++ [1][0][2][0][RTW89_MKK][20] = 72, ++ [1][0][2][0][RTW89_IC][20] = 72, ++ [1][0][2][0][RTW89_KCC][20] = 64, ++ [1][0][2][0][RTW89_ACMA][20] = 64, ++ [1][0][2][0][RTW89_CHILE][20] = 54, ++ [1][0][2][0][RTW89_UKRAINE][20] = 52, ++ [1][0][2][0][RTW89_FCC][24] = 72, ++ [1][0][2][0][RTW89_ETSI][24] = 64, ++ [1][0][2][0][RTW89_MKK][24] = 72, ++ [1][0][2][0][RTW89_IC][24] = 127, ++ [1][0][2][0][RTW89_KCC][24] = 64, ++ [1][0][2][0][RTW89_ACMA][24] = 127, ++ [1][0][2][0][RTW89_CHILE][24] = 54, ++ [1][0][2][0][RTW89_UKRAINE][24] = 52, ++ [1][0][2][0][RTW89_FCC][28] = 72, ++ [1][0][2][0][RTW89_ETSI][28] = 64, ++ [1][0][2][0][RTW89_MKK][28] = 72, ++ [1][0][2][0][RTW89_IC][28] = 127, ++ [1][0][2][0][RTW89_KCC][28] = 64, ++ [1][0][2][0][RTW89_ACMA][28] = 127, ++ [1][0][2][0][RTW89_CHILE][28] = 54, ++ [1][0][2][0][RTW89_UKRAINE][28] = 52, ++ [1][0][2][0][RTW89_FCC][32] = 72, ++ [1][0][2][0][RTW89_ETSI][32] = 64, ++ [1][0][2][0][RTW89_MKK][32] = 72, ++ [1][0][2][0][RTW89_IC][32] = 72, ++ [1][0][2][0][RTW89_KCC][32] = 64, ++ [1][0][2][0][RTW89_ACMA][32] = 64, ++ [1][0][2][0][RTW89_CHILE][32] = 54, ++ [1][0][2][0][RTW89_UKRAINE][32] = 52, ++ [1][0][2][0][RTW89_FCC][36] = 72, ++ [1][0][2][0][RTW89_ETSI][36] = 127, ++ [1][0][2][0][RTW89_MKK][36] = 72, ++ [1][0][2][0][RTW89_IC][36] = 72, ++ [1][0][2][0][RTW89_KCC][36] = 64, ++ [1][0][2][0][RTW89_ACMA][36] = 72, ++ [1][0][2][0][RTW89_CHILE][36] = 54, ++ [1][0][2][0][RTW89_UKRAINE][36] = 127, ++ [1][0][2][0][RTW89_FCC][39] = 72, ++ [1][0][2][0][RTW89_ETSI][39] = 28, ++ [1][0][2][0][RTW89_MKK][39] = 127, ++ [1][0][2][0][RTW89_IC][39] = 72, ++ [1][0][2][0][RTW89_KCC][39] = 28, ++ [1][0][2][0][RTW89_ACMA][39] = 72, ++ [1][0][2][0][RTW89_CHILE][39] = 54, ++ [1][0][2][0][RTW89_UKRAINE][39] = 52, ++ [1][0][2][0][RTW89_FCC][43] = 72, ++ [1][0][2][0][RTW89_ETSI][43] = 28, ++ [1][0][2][0][RTW89_MKK][43] = 127, ++ [1][0][2][0][RTW89_IC][43] = 72, ++ [1][0][2][0][RTW89_KCC][43] = 28, ++ [1][0][2][0][RTW89_ACMA][43] = 72, ++ [1][0][2][0][RTW89_CHILE][43] = 54, ++ [1][0][2][0][RTW89_UKRAINE][43] = 52, ++ [1][1][2][0][RTW89_FCC][1] = 58, ++ [1][1][2][0][RTW89_ETSI][1] = 52, ++ [1][1][2][0][RTW89_MKK][1] = 50, ++ [1][1][2][0][RTW89_IC][1] = 52, ++ [1][1][2][0][RTW89_KCC][1] = 52, ++ [1][1][2][0][RTW89_ACMA][1] = 52, ++ [1][1][2][0][RTW89_CHILE][1] = 18, ++ [1][1][2][0][RTW89_UKRAINE][1] = 40, ++ [1][1][2][0][RTW89_FCC][5] = 72, ++ [1][1][2][0][RTW89_ETSI][5] = 52, ++ [1][1][2][0][RTW89_MKK][5] = 50, ++ [1][1][2][0][RTW89_IC][5] = 52, ++ [1][1][2][0][RTW89_KCC][5] = 46, ++ [1][1][2][0][RTW89_ACMA][5] = 52, ++ [1][1][2][0][RTW89_CHILE][5] = 18, ++ [1][1][2][0][RTW89_UKRAINE][5] = 40, ++ [1][1][2][0][RTW89_FCC][9] = 72, ++ [1][1][2][0][RTW89_ETSI][9] = 52, ++ [1][1][2][0][RTW89_MKK][9] = 50, ++ [1][1][2][0][RTW89_IC][9] = 52, ++ [1][1][2][0][RTW89_KCC][9] = 52, ++ [1][1][2][0][RTW89_ACMA][9] = 52, ++ [1][1][2][0][RTW89_CHILE][9] = 42, ++ [1][1][2][0][RTW89_UKRAINE][9] = 40, ++ [1][1][2][0][RTW89_FCC][13] = 58, ++ [1][1][2][0][RTW89_ETSI][13] = 52, ++ [1][1][2][0][RTW89_MKK][13] = 50, ++ [1][1][2][0][RTW89_IC][13] = 52, ++ [1][1][2][0][RTW89_KCC][13] = 52, ++ [1][1][2][0][RTW89_ACMA][13] = 52, ++ [1][1][2][0][RTW89_CHILE][13] = 42, ++ [1][1][2][0][RTW89_UKRAINE][13] = 40, ++ [1][1][2][0][RTW89_FCC][16] = 56, ++ [1][1][2][0][RTW89_ETSI][16] = 52, ++ [1][1][2][0][RTW89_MKK][16] = 72, ++ [1][1][2][0][RTW89_IC][16] = 56, ++ [1][1][2][0][RTW89_KCC][16] = 52, ++ [1][1][2][0][RTW89_ACMA][16] = 52, ++ [1][1][2][0][RTW89_CHILE][16] = 42, ++ [1][1][2][0][RTW89_UKRAINE][16] = 40, ++ [1][1][2][0][RTW89_FCC][20] = 72, ++ [1][1][2][0][RTW89_ETSI][20] = 52, ++ [1][1][2][0][RTW89_MKK][20] = 72, ++ [1][1][2][0][RTW89_IC][20] = 72, ++ [1][1][2][0][RTW89_KCC][20] = 52, ++ [1][1][2][0][RTW89_ACMA][20] = 52, ++ [1][1][2][0][RTW89_CHILE][20] = 42, ++ [1][1][2][0][RTW89_UKRAINE][20] = 40, ++ [1][1][2][0][RTW89_FCC][24] = 72, ++ [1][1][2][0][RTW89_ETSI][24] = 52, ++ [1][1][2][0][RTW89_MKK][24] = 72, ++ [1][1][2][0][RTW89_IC][24] = 127, ++ [1][1][2][0][RTW89_KCC][24] = 52, ++ [1][1][2][0][RTW89_ACMA][24] = 127, ++ [1][1][2][0][RTW89_CHILE][24] = 42, ++ [1][1][2][0][RTW89_UKRAINE][24] = 40, ++ [1][1][2][0][RTW89_FCC][28] = 72, ++ [1][1][2][0][RTW89_ETSI][28] = 52, ++ [1][1][2][0][RTW89_MKK][28] = 72, ++ [1][1][2][0][RTW89_IC][28] = 127, ++ [1][1][2][0][RTW89_KCC][28] = 52, ++ [1][1][2][0][RTW89_ACMA][28] = 127, ++ [1][1][2][0][RTW89_CHILE][28] = 42, ++ [1][1][2][0][RTW89_UKRAINE][28] = 40, ++ [1][1][2][0][RTW89_FCC][32] = 68, ++ [1][1][2][0][RTW89_ETSI][32] = 52, ++ [1][1][2][0][RTW89_MKK][32] = 72, ++ [1][1][2][0][RTW89_IC][32] = 68, ++ [1][1][2][0][RTW89_KCC][32] = 52, ++ [1][1][2][0][RTW89_ACMA][32] = 52, ++ [1][1][2][0][RTW89_CHILE][32] = 42, ++ [1][1][2][0][RTW89_UKRAINE][32] = 40, ++ [1][1][2][0][RTW89_FCC][36] = 72, ++ [1][1][2][0][RTW89_ETSI][36] = 127, ++ [1][1][2][0][RTW89_MKK][36] = 72, ++ [1][1][2][0][RTW89_IC][36] = 72, ++ [1][1][2][0][RTW89_KCC][36] = 52, ++ [1][1][2][0][RTW89_ACMA][36] = 72, ++ [1][1][2][0][RTW89_CHILE][36] = 42, ++ [1][1][2][0][RTW89_UKRAINE][36] = 127, ++ [1][1][2][0][RTW89_FCC][39] = 72, ++ [1][1][2][0][RTW89_ETSI][39] = 16, ++ [1][1][2][0][RTW89_MKK][39] = 127, ++ [1][1][2][0][RTW89_IC][39] = 72, ++ [1][1][2][0][RTW89_KCC][39] = 16, ++ [1][1][2][0][RTW89_ACMA][39] = 72, ++ [1][1][2][0][RTW89_CHILE][39] = 42, ++ [1][1][2][0][RTW89_UKRAINE][39] = 40, ++ [1][1][2][0][RTW89_FCC][43] = 72, ++ [1][1][2][0][RTW89_ETSI][43] = 16, ++ [1][1][2][0][RTW89_MKK][43] = 127, ++ [1][1][2][0][RTW89_IC][43] = 72, ++ [1][1][2][0][RTW89_KCC][43] = 16, ++ [1][1][2][0][RTW89_ACMA][43] = 72, ++ [1][1][2][0][RTW89_CHILE][43] = 42, ++ [1][1][2][0][RTW89_UKRAINE][43] = 40, ++ [1][1][2][1][RTW89_FCC][1] = 58, ++ [1][1][2][1][RTW89_ETSI][1] = 40, ++ [1][1][2][1][RTW89_MKK][1] = 50, ++ [1][1][2][1][RTW89_IC][1] = 40, ++ [1][1][2][1][RTW89_KCC][1] = 40, ++ [1][1][2][1][RTW89_ACMA][1] = 40, ++ [1][1][2][1][RTW89_CHILE][1] = 6, ++ [1][1][2][1][RTW89_UKRAINE][1] = 28, ++ [1][1][2][1][RTW89_FCC][5] = 68, ++ [1][1][2][1][RTW89_ETSI][5] = 40, ++ [1][1][2][1][RTW89_MKK][5] = 50, ++ [1][1][2][1][RTW89_IC][5] = 40, ++ [1][1][2][1][RTW89_KCC][5] = 40, ++ [1][1][2][1][RTW89_ACMA][5] = 40, ++ [1][1][2][1][RTW89_CHILE][5] = 6, ++ [1][1][2][1][RTW89_UKRAINE][5] = 28, ++ [1][1][2][1][RTW89_FCC][9] = 68, ++ [1][1][2][1][RTW89_ETSI][9] = 40, ++ [1][1][2][1][RTW89_MKK][9] = 50, ++ [1][1][2][1][RTW89_IC][9] = 40, ++ [1][1][2][1][RTW89_KCC][9] = 40, ++ [1][1][2][1][RTW89_ACMA][9] = 40, ++ [1][1][2][1][RTW89_CHILE][9] = 30, ++ [1][1][2][1][RTW89_UKRAINE][9] = 28, ++ [1][1][2][1][RTW89_FCC][13] = 58, ++ [1][1][2][1][RTW89_ETSI][13] = 40, ++ [1][1][2][1][RTW89_MKK][13] = 50, ++ [1][1][2][1][RTW89_IC][13] = 40, ++ [1][1][2][1][RTW89_KCC][13] = 40, ++ [1][1][2][1][RTW89_ACMA][13] = 40, ++ [1][1][2][1][RTW89_CHILE][13] = 30, ++ [1][1][2][1][RTW89_UKRAINE][13] = 28, ++ [1][1][2][1][RTW89_FCC][16] = 56, ++ [1][1][2][1][RTW89_ETSI][16] = 40, ++ [1][1][2][1][RTW89_MKK][16] = 72, ++ [1][1][2][1][RTW89_IC][16] = 56, ++ [1][1][2][1][RTW89_KCC][16] = 40, ++ [1][1][2][1][RTW89_ACMA][16] = 40, ++ [1][1][2][1][RTW89_CHILE][16] = 30, ++ [1][1][2][1][RTW89_UKRAINE][16] = 28, ++ [1][1][2][1][RTW89_FCC][20] = 68, ++ [1][1][2][1][RTW89_ETSI][20] = 40, ++ [1][1][2][1][RTW89_MKK][20] = 72, ++ [1][1][2][1][RTW89_IC][20] = 68, ++ [1][1][2][1][RTW89_KCC][20] = 40, ++ [1][1][2][1][RTW89_ACMA][20] = 40, ++ [1][1][2][1][RTW89_CHILE][20] = 30, ++ [1][1][2][1][RTW89_UKRAINE][20] = 28, ++ [1][1][2][1][RTW89_FCC][24] = 68, ++ [1][1][2][1][RTW89_ETSI][24] = 40, ++ [1][1][2][1][RTW89_MKK][24] = 72, ++ [1][1][2][1][RTW89_IC][24] = 127, ++ [1][1][2][1][RTW89_KCC][24] = 40, ++ [1][1][2][1][RTW89_ACMA][24] = 127, ++ [1][1][2][1][RTW89_CHILE][24] = 30, ++ [1][1][2][1][RTW89_UKRAINE][24] = 28, ++ [1][1][2][1][RTW89_FCC][28] = 68, ++ [1][1][2][1][RTW89_ETSI][28] = 40, ++ [1][1][2][1][RTW89_MKK][28] = 72, ++ [1][1][2][1][RTW89_IC][28] = 127, ++ [1][1][2][1][RTW89_KCC][28] = 40, ++ [1][1][2][1][RTW89_ACMA][28] = 127, ++ [1][1][2][1][RTW89_CHILE][28] = 30, ++ [1][1][2][1][RTW89_UKRAINE][28] = 28, ++ [1][1][2][1][RTW89_FCC][32] = 68, ++ [1][1][2][1][RTW89_ETSI][32] = 40, ++ [1][1][2][1][RTW89_MKK][32] = 72, ++ [1][1][2][1][RTW89_IC][32] = 68, ++ [1][1][2][1][RTW89_KCC][32] = 40, ++ [1][1][2][1][RTW89_ACMA][32] = 40, ++ [1][1][2][1][RTW89_CHILE][32] = 30, ++ [1][1][2][1][RTW89_UKRAINE][32] = 28, ++ [1][1][2][1][RTW89_FCC][36] = 68, ++ [1][1][2][1][RTW89_ETSI][36] = 127, ++ [1][1][2][1][RTW89_MKK][36] = 72, ++ [1][1][2][1][RTW89_IC][36] = 68, ++ [1][1][2][1][RTW89_KCC][36] = 40, ++ [1][1][2][1][RTW89_ACMA][36] = 68, ++ [1][1][2][1][RTW89_CHILE][36] = 30, ++ [1][1][2][1][RTW89_UKRAINE][36] = 127, ++ [1][1][2][1][RTW89_FCC][39] = 72, ++ [1][1][2][1][RTW89_ETSI][39] = 4, ++ [1][1][2][1][RTW89_MKK][39] = 127, ++ [1][1][2][1][RTW89_IC][39] = 72, ++ [1][1][2][1][RTW89_KCC][39] = 4, ++ [1][1][2][1][RTW89_ACMA][39] = 72, ++ [1][1][2][1][RTW89_CHILE][39] = 30, ++ [1][1][2][1][RTW89_UKRAINE][39] = 28, ++ [1][1][2][1][RTW89_FCC][43] = 72, ++ [1][1][2][1][RTW89_ETSI][43] = 4, ++ [1][1][2][1][RTW89_MKK][43] = 127, ++ [1][1][2][1][RTW89_IC][43] = 72, ++ [1][1][2][1][RTW89_KCC][43] = 4, ++ [1][1][2][1][RTW89_ACMA][43] = 72, ++ [1][1][2][1][RTW89_CHILE][43] = 30, ++ [1][1][2][1][RTW89_UKRAINE][43] = 28, ++ [2][0][2][0][RTW89_FCC][3] = 64, ++ [2][0][2][0][RTW89_ETSI][3] = 64, ++ [2][0][2][0][RTW89_MKK][3] = 64, ++ [2][0][2][0][RTW89_IC][3] = 62, ++ [2][0][2][0][RTW89_KCC][3] = 64, ++ [2][0][2][0][RTW89_ACMA][3] = 64, ++ [2][0][2][0][RTW89_CHILE][3] = 30, ++ [2][0][2][0][RTW89_UKRAINE][3] = 52, ++ [2][0][2][0][RTW89_FCC][11] = 64, ++ [2][0][2][0][RTW89_ETSI][11] = 64, ++ [2][0][2][0][RTW89_MKK][11] = 64, ++ [2][0][2][0][RTW89_IC][11] = 62, ++ [2][0][2][0][RTW89_KCC][11] = 64, ++ [2][0][2][0][RTW89_ACMA][11] = 64, ++ [2][0][2][0][RTW89_CHILE][11] = 54, ++ [2][0][2][0][RTW89_UKRAINE][11] = 52, ++ [2][0][2][0][RTW89_FCC][18] = 62, ++ [2][0][2][0][RTW89_ETSI][18] = 64, ++ [2][0][2][0][RTW89_MKK][18] = 72, ++ [2][0][2][0][RTW89_IC][18] = 66, ++ [2][0][2][0][RTW89_KCC][18] = 64, ++ [2][0][2][0][RTW89_ACMA][18] = 64, ++ [2][0][2][0][RTW89_CHILE][18] = 54, ++ [2][0][2][0][RTW89_UKRAINE][18] = 52, ++ [2][0][2][0][RTW89_FCC][26] = 72, ++ [2][0][2][0][RTW89_ETSI][26] = 64, ++ [2][0][2][0][RTW89_MKK][26] = 72, ++ [2][0][2][0][RTW89_IC][26] = 127, ++ [2][0][2][0][RTW89_KCC][26] = 64, ++ [2][0][2][0][RTW89_ACMA][26] = 127, ++ [2][0][2][0][RTW89_CHILE][26] = 54, ++ [2][0][2][0][RTW89_UKRAINE][26] = 52, ++ [2][0][2][0][RTW89_FCC][34] = 72, ++ [2][0][2][0][RTW89_ETSI][34] = 127, ++ [2][0][2][0][RTW89_MKK][34] = 72, ++ [2][0][2][0][RTW89_IC][34] = 72, ++ [2][0][2][0][RTW89_KCC][34] = 64, ++ [2][0][2][0][RTW89_ACMA][34] = 72, ++ [2][0][2][0][RTW89_CHILE][34] = 54, ++ [2][0][2][0][RTW89_UKRAINE][34] = 127, ++ [2][0][2][0][RTW89_FCC][41] = 72, ++ [2][0][2][0][RTW89_ETSI][41] = 28, ++ [2][0][2][0][RTW89_MKK][41] = 127, ++ [2][0][2][0][RTW89_IC][41] = 72, ++ [2][0][2][0][RTW89_KCC][41] = 28, ++ [2][0][2][0][RTW89_ACMA][41] = 72, ++ [2][0][2][0][RTW89_CHILE][41] = 54, ++ [2][0][2][0][RTW89_UKRAINE][41] = 52, ++ [2][1][2][0][RTW89_FCC][3] = 56, ++ [2][1][2][0][RTW89_ETSI][3] = 52, ++ [2][1][2][0][RTW89_MKK][3] = 52, ++ [2][1][2][0][RTW89_IC][3] = 52, ++ [2][1][2][0][RTW89_KCC][3] = 52, ++ [2][1][2][0][RTW89_ACMA][3] = 52, ++ [2][1][2][0][RTW89_CHILE][3] = 18, ++ [2][1][2][0][RTW89_UKRAINE][3] = 40, ++ [2][1][2][0][RTW89_FCC][11] = 56, ++ [2][1][2][0][RTW89_ETSI][11] = 52, ++ [2][1][2][0][RTW89_MKK][11] = 52, ++ [2][1][2][0][RTW89_IC][11] = 52, ++ [2][1][2][0][RTW89_KCC][11] = 52, ++ [2][1][2][0][RTW89_ACMA][11] = 52, ++ [2][1][2][0][RTW89_CHILE][11] = 42, ++ [2][1][2][0][RTW89_UKRAINE][11] = 40, ++ [2][1][2][0][RTW89_FCC][18] = 56, ++ [2][1][2][0][RTW89_ETSI][18] = 52, ++ [2][1][2][0][RTW89_MKK][18] = 72, ++ [2][1][2][0][RTW89_IC][18] = 56, ++ [2][1][2][0][RTW89_KCC][18] = 52, ++ [2][1][2][0][RTW89_ACMA][18] = 52, ++ [2][1][2][0][RTW89_CHILE][18] = 42, ++ [2][1][2][0][RTW89_UKRAINE][18] = 40, ++ [2][1][2][0][RTW89_FCC][26] = 72, ++ [2][1][2][0][RTW89_ETSI][26] = 52, ++ [2][1][2][0][RTW89_MKK][26] = 72, ++ [2][1][2][0][RTW89_IC][26] = 127, ++ [2][1][2][0][RTW89_KCC][26] = 52, ++ [2][1][2][0][RTW89_ACMA][26] = 127, ++ [2][1][2][0][RTW89_CHILE][26] = 42, ++ [2][1][2][0][RTW89_UKRAINE][26] = 40, ++ [2][1][2][0][RTW89_FCC][34] = 72, ++ [2][1][2][0][RTW89_ETSI][34] = 127, ++ [2][1][2][0][RTW89_MKK][34] = 72, ++ [2][1][2][0][RTW89_IC][34] = 72, ++ [2][1][2][0][RTW89_KCC][34] = 52, ++ [2][1][2][0][RTW89_ACMA][34] = 72, ++ [2][1][2][0][RTW89_CHILE][34] = 42, ++ [2][1][2][0][RTW89_UKRAINE][34] = 127, ++ [2][1][2][0][RTW89_FCC][41] = 72, ++ [2][1][2][0][RTW89_ETSI][41] = 16, ++ [2][1][2][0][RTW89_MKK][41] = 127, ++ [2][1][2][0][RTW89_IC][41] = 72, ++ [2][1][2][0][RTW89_KCC][41] = 16, ++ [2][1][2][0][RTW89_ACMA][41] = 72, ++ [2][1][2][0][RTW89_CHILE][41] = 42, ++ [2][1][2][0][RTW89_UKRAINE][41] = 40, ++ [2][1][2][1][RTW89_FCC][3] = 56, ++ [2][1][2][1][RTW89_ETSI][3] = 40, ++ [2][1][2][1][RTW89_MKK][3] = 52, ++ [2][1][2][1][RTW89_IC][3] = 40, ++ [2][1][2][1][RTW89_KCC][3] = 40, ++ [2][1][2][1][RTW89_ACMA][3] = 40, ++ [2][1][2][1][RTW89_CHILE][3] = 6, ++ [2][1][2][1][RTW89_UKRAINE][3] = 28, ++ [2][1][2][1][RTW89_FCC][11] = 56, ++ [2][1][2][1][RTW89_ETSI][11] = 40, ++ [2][1][2][1][RTW89_MKK][11] = 52, ++ [2][1][2][1][RTW89_IC][11] = 40, ++ [2][1][2][1][RTW89_KCC][11] = 40, ++ [2][1][2][1][RTW89_ACMA][11] = 40, ++ [2][1][2][1][RTW89_CHILE][11] = 30, ++ [2][1][2][1][RTW89_UKRAINE][11] = 28, ++ [2][1][2][1][RTW89_FCC][18] = 56, ++ [2][1][2][1][RTW89_ETSI][18] = 40, ++ [2][1][2][1][RTW89_MKK][18] = 72, ++ [2][1][2][1][RTW89_IC][18] = 56, ++ [2][1][2][1][RTW89_KCC][18] = 40, ++ [2][1][2][1][RTW89_ACMA][18] = 40, ++ [2][1][2][1][RTW89_CHILE][18] = 30, ++ [2][1][2][1][RTW89_UKRAINE][18] = 28, ++ [2][1][2][1][RTW89_FCC][26] = 68, ++ [2][1][2][1][RTW89_ETSI][26] = 40, ++ [2][1][2][1][RTW89_MKK][26] = 72, ++ [2][1][2][1][RTW89_IC][26] = 127, ++ [2][1][2][1][RTW89_KCC][26] = 40, ++ [2][1][2][1][RTW89_ACMA][26] = 127, ++ [2][1][2][1][RTW89_CHILE][26] = 30, ++ [2][1][2][1][RTW89_UKRAINE][26] = 28, ++ [2][1][2][1][RTW89_FCC][34] = 68, ++ [2][1][2][1][RTW89_ETSI][34] = 127, ++ [2][1][2][1][RTW89_MKK][34] = 72, ++ [2][1][2][1][RTW89_IC][34] = 68, ++ [2][1][2][1][RTW89_KCC][34] = 40, ++ [2][1][2][1][RTW89_ACMA][34] = 68, ++ [2][1][2][1][RTW89_CHILE][34] = 30, ++ [2][1][2][1][RTW89_UKRAINE][34] = 127, ++ [2][1][2][1][RTW89_FCC][41] = 72, ++ [2][1][2][1][RTW89_ETSI][41] = 4, ++ [2][1][2][1][RTW89_MKK][41] = 127, ++ [2][1][2][1][RTW89_IC][41] = 72, ++ [2][1][2][1][RTW89_KCC][41] = 4, ++ [2][1][2][1][RTW89_ACMA][41] = 72, ++ [2][1][2][1][RTW89_CHILE][41] = 30, ++ [2][1][2][1][RTW89_UKRAINE][41] = 28, + }; + + const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [RTW89_REGD_NUM][RTW89_2G_CH_NUM] = { +- [0][0][0][0] = 32, +- [0][0][0][1] = 32, +- [0][0][0][2] = 32, +- [0][0][0][3] = 32, +- [0][0][0][4] = 32, +- [0][0][0][5] = 32, +- [0][0][0][6] = 32, +- [0][0][0][7] = 32, +- [0][0][0][8] = 32, +- [0][0][0][9] = 32, +- [0][0][0][10] = 32, +- [0][0][0][11] = 32, +- [0][0][0][12] = 32, +- [0][0][0][13] = 0, +- [0][1][0][0] = 20, +- [0][1][0][1] = 20, +- [0][1][0][2] = 20, +- [0][1][0][3] = 20, +- [0][1][0][4] = 20, +- [0][1][0][5] = 20, +- [0][1][0][6] = 20, +- [0][1][0][7] = 20, +- [0][1][0][8] = 20, +- [0][1][0][9] = 20, +- [0][1][0][10] = 20, +- [0][1][0][11] = 20, +- [0][1][0][12] = 20, +- [0][1][0][13] = 0, +- [1][0][0][0] = 42, +- [1][0][0][1] = 42, +- [1][0][0][2] = 42, +- [1][0][0][3] = 42, +- [1][0][0][4] = 42, +- [1][0][0][5] = 42, +- [1][0][0][6] = 42, +- [1][0][0][7] = 42, +- [1][0][0][8] = 42, +- [1][0][0][9] = 42, +- [1][0][0][10] = 42, +- [1][0][0][11] = 42, +- [1][0][0][12] = 36, +- [1][0][0][13] = 0, +- [1][1][0][0] = 30, +- [1][1][0][1] = 30, +- [1][1][0][2] = 30, +- [1][1][0][3] = 30, +- [1][1][0][4] = 30, +- [1][1][0][5] = 30, +- [1][1][0][6] = 30, +- [1][1][0][7] = 30, +- [1][1][0][8] = 30, +- [1][1][0][9] = 30, +- [1][1][0][10] = 30, +- [1][1][0][11] = 30, +- [1][1][0][12] = 30, +- [1][1][0][13] = 0, +- [2][0][0][0] = 52, +- [2][0][0][1] = 52, +- [2][0][0][2] = 52, +- [2][0][0][3] = 52, +- [2][0][0][4] = 52, +- [2][0][0][5] = 52, +- [2][0][0][6] = 52, +- [2][0][0][7] = 52, +- [2][0][0][8] = 52, +- [2][0][0][9] = 52, +- [2][0][0][10] = 52, +- [2][0][0][11] = 52, +- [2][0][0][12] = 40, +- [2][0][0][13] = 0, +- [2][1][0][0] = 40, +- [2][1][0][1] = 40, +- [2][1][0][2] = 40, +- [2][1][0][3] = 40, +- [2][1][0][4] = 40, +- [2][1][0][5] = 40, +- [2][1][0][6] = 40, +- [2][1][0][7] = 40, +- [2][1][0][8] = 40, +- [2][1][0][9] = 40, +- [2][1][0][10] = 40, +- [2][1][0][11] = 40, +- [2][1][0][12] = 26, +- [2][1][0][13] = 0, +- [0][0][2][0] = 70, +- [0][0][1][0] = 32, +- [0][0][3][0] = 40, +- [0][0][5][0] = 70, +- [0][0][6][0] = 32, +- [0][0][9][0] = 32, +- [0][0][8][0] = 60, +- [0][0][11][0] = 32, +- [0][0][2][1] = 70, +- [0][0][1][1] = 32, +- [0][0][3][1] = 40, +- [0][0][5][1] = 70, +- [0][0][6][1] = 32, +- [0][0][9][1] = 32, +- [0][0][8][1] = 60, +- [0][0][11][1] = 32, +- [0][0][2][2] = 74, +- [0][0][1][2] = 32, +- [0][0][3][2] = 40, +- [0][0][5][2] = 74, +- [0][0][6][2] = 32, +- [0][0][9][2] = 32, +- [0][0][8][2] = 60, +- [0][0][11][2] = 32, +- [0][0][2][3] = 78, +- [0][0][1][3] = 32, +- [0][0][3][3] = 40, +- [0][0][5][3] = 78, +- [0][0][6][3] = 32, +- [0][0][9][3] = 32, +- [0][0][8][3] = 60, +- [0][0][11][3] = 32, +- [0][0][2][4] = 78, +- [0][0][1][4] = 32, +- [0][0][3][4] = 40, +- [0][0][5][4] = 78, +- [0][0][6][4] = 32, +- [0][0][9][4] = 32, +- [0][0][8][4] = 60, +- [0][0][11][4] = 32, +- [0][0][2][5] = 78, +- [0][0][1][5] = 32, +- [0][0][3][5] = 40, +- [0][0][5][5] = 78, +- [0][0][6][5] = 32, +- [0][0][9][5] = 32, +- [0][0][8][5] = 60, +- [0][0][11][5] = 32, +- [0][0][2][6] = 78, +- [0][0][1][6] = 32, +- [0][0][3][6] = 40, +- [0][0][5][6] = 78, +- [0][0][6][6] = 32, +- [0][0][9][6] = 32, +- [0][0][8][6] = 60, +- [0][0][11][6] = 32, +- [0][0][2][7] = 78, +- [0][0][1][7] = 32, +- [0][0][3][7] = 40, +- [0][0][5][7] = 78, +- [0][0][6][7] = 32, +- [0][0][9][7] = 32, +- [0][0][8][7] = 60, +- [0][0][11][7] = 32, +- [0][0][2][8] = 74, +- [0][0][1][8] = 32, +- [0][0][3][8] = 40, +- [0][0][5][8] = 74, +- [0][0][6][8] = 32, +- [0][0][9][8] = 32, +- [0][0][8][8] = 60, +- [0][0][11][8] = 32, +- [0][0][2][9] = 70, +- [0][0][1][9] = 32, +- [0][0][3][9] = 40, +- [0][0][5][9] = 70, +- [0][0][6][9] = 32, +- [0][0][9][9] = 32, +- [0][0][8][9] = 60, +- [0][0][11][9] = 32, +- [0][0][2][10] = 70, +- [0][0][1][10] = 32, +- [0][0][3][10] = 40, +- [0][0][5][10] = 70, +- [0][0][6][10] = 32, +- [0][0][9][10] = 32, +- [0][0][8][10] = 60, +- [0][0][11][10] = 32, +- [0][0][2][11] = 58, +- [0][0][1][11] = 32, +- [0][0][3][11] = 40, +- [0][0][5][11] = 58, +- [0][0][6][11] = 32, +- [0][0][9][11] = 32, +- [0][0][8][11] = 60, +- [0][0][11][11] = 32, +- [0][0][2][12] = 34, +- [0][0][1][12] = 32, +- [0][0][3][12] = 40, +- [0][0][5][12] = 34, +- [0][0][6][12] = 32, +- [0][0][9][12] = 32, +- [0][0][8][12] = 60, +- [0][0][11][12] = 32, +- [0][0][2][13] = 127, +- [0][0][1][13] = 127, +- [0][0][3][13] = 127, +- [0][0][5][13] = 127, +- [0][0][6][13] = 127, +- [0][0][9][13] = 127, +- [0][0][8][13] = 127, +- [0][0][11][13] = 127, +- [0][1][2][0] = 64, +- [0][1][1][0] = 20, +- [0][1][3][0] = 28, +- [0][1][5][0] = 64, +- [0][1][6][0] = 20, +- [0][1][9][0] = 20, +- [0][1][8][0] = 48, +- [0][1][11][0] = 20, +- [0][1][2][1] = 64, +- [0][1][1][1] = 20, +- [0][1][3][1] = 28, +- [0][1][5][1] = 64, +- [0][1][6][1] = 20, +- [0][1][9][1] = 20, +- [0][1][8][1] = 48, +- [0][1][11][1] = 20, +- [0][1][2][2] = 68, +- [0][1][1][2] = 20, +- [0][1][3][2] = 28, +- [0][1][5][2] = 68, +- [0][1][6][2] = 20, +- [0][1][9][2] = 20, +- [0][1][8][2] = 48, +- [0][1][11][2] = 20, +- [0][1][2][3] = 72, +- [0][1][1][3] = 20, +- [0][1][3][3] = 28, +- [0][1][5][3] = 72, +- [0][1][6][3] = 20, +- [0][1][9][3] = 20, +- [0][1][8][3] = 48, +- [0][1][11][3] = 20, +- [0][1][2][4] = 76, +- [0][1][1][4] = 20, +- [0][1][3][4] = 28, +- [0][1][5][4] = 76, +- [0][1][6][4] = 20, +- [0][1][9][4] = 20, +- [0][1][8][4] = 48, +- [0][1][11][4] = 20, +- [0][1][2][5] = 78, +- [0][1][1][5] = 20, +- [0][1][3][5] = 28, +- [0][1][5][5] = 78, +- [0][1][6][5] = 20, +- [0][1][9][5] = 20, +- [0][1][8][5] = 48, +- [0][1][11][5] = 20, +- [0][1][2][6] = 76, +- [0][1][1][6] = 20, +- [0][1][3][6] = 28, +- [0][1][5][6] = 76, +- [0][1][6][6] = 20, +- [0][1][9][6] = 20, +- [0][1][8][6] = 48, +- [0][1][11][6] = 20, +- [0][1][2][7] = 72, +- [0][1][1][7] = 20, +- [0][1][3][7] = 28, +- [0][1][5][7] = 72, +- [0][1][6][7] = 20, +- [0][1][9][7] = 20, +- [0][1][8][7] = 48, +- [0][1][11][7] = 20, +- [0][1][2][8] = 68, +- [0][1][1][8] = 20, +- [0][1][3][8] = 28, +- [0][1][5][8] = 68, +- [0][1][6][8] = 20, +- [0][1][9][8] = 20, +- [0][1][8][8] = 48, +- [0][1][11][8] = 20, +- [0][1][2][9] = 64, +- [0][1][1][9] = 20, +- [0][1][3][9] = 28, +- [0][1][5][9] = 64, +- [0][1][6][9] = 20, +- [0][1][9][9] = 20, +- [0][1][8][9] = 48, +- [0][1][11][9] = 20, +- [0][1][2][10] = 64, +- [0][1][1][10] = 20, +- [0][1][3][10] = 28, +- [0][1][5][10] = 64, +- [0][1][6][10] = 20, +- [0][1][9][10] = 20, +- [0][1][8][10] = 48, +- [0][1][11][10] = 20, +- [0][1][2][11] = 54, +- [0][1][1][11] = 20, +- [0][1][3][11] = 28, +- [0][1][5][11] = 54, +- [0][1][6][11] = 20, +- [0][1][9][11] = 20, +- [0][1][8][11] = 48, +- [0][1][11][11] = 20, +- [0][1][2][12] = 32, +- [0][1][1][12] = 20, +- [0][1][3][12] = 28, +- [0][1][5][12] = 32, +- [0][1][6][12] = 20, +- [0][1][9][12] = 20, +- [0][1][8][12] = 48, +- [0][1][11][12] = 20, +- [0][1][2][13] = 127, +- [0][1][1][13] = 127, +- [0][1][3][13] = 127, +- [0][1][5][13] = 127, +- [0][1][6][13] = 127, +- [0][1][9][13] = 127, +- [0][1][8][13] = 127, +- [0][1][11][13] = 127, +- [1][0][2][0] = 72, +- [1][0][1][0] = 42, +- [1][0][3][0] = 50, +- [1][0][5][0] = 72, +- [1][0][6][0] = 42, +- [1][0][9][0] = 42, +- [1][0][8][0] = 60, +- [1][0][11][0] = 42, +- [1][0][2][1] = 72, +- [1][0][1][1] = 42, +- [1][0][3][1] = 50, +- [1][0][5][1] = 72, +- [1][0][6][1] = 42, +- [1][0][9][1] = 42, +- [1][0][8][1] = 60, +- [1][0][11][1] = 42, +- [1][0][2][2] = 76, +- [1][0][1][2] = 42, +- [1][0][3][2] = 50, +- [1][0][5][2] = 76, +- [1][0][6][2] = 42, +- [1][0][9][2] = 42, +- [1][0][8][2] = 60, +- [1][0][11][2] = 42, +- [1][0][2][3] = 78, +- [1][0][1][3] = 42, +- [1][0][3][3] = 50, +- [1][0][5][3] = 78, +- [1][0][6][3] = 42, +- [1][0][9][3] = 42, +- [1][0][8][3] = 60, +- [1][0][11][3] = 42, +- [1][0][2][4] = 78, +- [1][0][1][4] = 42, +- [1][0][3][4] = 50, +- [1][0][5][4] = 78, +- [1][0][6][4] = 42, +- [1][0][9][4] = 42, +- [1][0][8][4] = 60, +- [1][0][11][4] = 42, +- [1][0][2][5] = 78, +- [1][0][1][5] = 42, +- [1][0][3][5] = 50, +- [1][0][5][5] = 78, +- [1][0][6][5] = 42, +- [1][0][9][5] = 42, +- [1][0][8][5] = 60, +- [1][0][11][5] = 42, +- [1][0][2][6] = 78, +- [1][0][1][6] = 42, +- [1][0][3][6] = 50, +- [1][0][5][6] = 78, +- [1][0][6][6] = 42, +- [1][0][9][6] = 42, +- [1][0][8][6] = 60, +- [1][0][11][6] = 42, +- [1][0][2][7] = 78, +- [1][0][1][7] = 42, +- [1][0][3][7] = 50, +- [1][0][5][7] = 78, +- [1][0][6][7] = 42, +- [1][0][9][7] = 42, +- [1][0][8][7] = 60, +- [1][0][11][7] = 42, +- [1][0][2][8] = 78, +- [1][0][1][8] = 42, +- [1][0][3][8] = 50, +- [1][0][5][8] = 78, +- [1][0][6][8] = 42, +- [1][0][9][8] = 42, +- [1][0][8][8] = 60, +- [1][0][11][8] = 42, +- [1][0][2][9] = 74, +- [1][0][1][9] = 42, +- [1][0][3][9] = 50, +- [1][0][5][9] = 74, +- [1][0][6][9] = 42, +- [1][0][9][9] = 42, +- [1][0][8][9] = 60, +- [1][0][11][9] = 42, +- [1][0][2][10] = 74, +- [1][0][1][10] = 42, +- [1][0][3][10] = 50, +- [1][0][5][10] = 74, +- [1][0][6][10] = 42, +- [1][0][9][10] = 42, +- [1][0][8][10] = 60, +- [1][0][11][10] = 42, +- [1][0][2][11] = 64, +- [1][0][1][11] = 42, +- [1][0][3][11] = 50, +- [1][0][5][11] = 64, +- [1][0][6][11] = 42, +- [1][0][9][11] = 42, +- [1][0][8][11] = 60, +- [1][0][11][11] = 42, +- [1][0][2][12] = 36, +- [1][0][1][12] = 42, +- [1][0][3][12] = 50, +- [1][0][5][12] = 36, +- [1][0][6][12] = 42, +- [1][0][9][12] = 42, +- [1][0][8][12] = 60, +- [1][0][11][12] = 42, +- [1][0][2][13] = 127, +- [1][0][1][13] = 127, +- [1][0][3][13] = 127, +- [1][0][5][13] = 127, +- [1][0][6][13] = 127, +- [1][0][9][13] = 127, +- [1][0][8][13] = 127, +- [1][0][11][13] = 127, +- [1][1][2][0] = 66, +- [1][1][1][0] = 30, +- [1][1][3][0] = 38, +- [1][1][5][0] = 66, +- [1][1][6][0] = 30, +- [1][1][9][0] = 30, +- [1][1][8][0] = 48, +- [1][1][11][0] = 30, +- [1][1][2][1] = 66, +- [1][1][1][1] = 30, +- [1][1][3][1] = 38, +- [1][1][5][1] = 66, +- [1][1][6][1] = 30, +- [1][1][9][1] = 30, +- [1][1][8][1] = 48, +- [1][1][11][1] = 30, +- [1][1][2][2] = 70, +- [1][1][1][2] = 30, +- [1][1][3][2] = 38, +- [1][1][5][2] = 70, +- [1][1][6][2] = 30, +- [1][1][9][2] = 30, +- [1][1][8][2] = 48, +- [1][1][11][2] = 30, +- [1][1][2][3] = 74, +- [1][1][1][3] = 30, +- [1][1][3][3] = 38, +- [1][1][5][3] = 74, +- [1][1][6][3] = 30, +- [1][1][9][3] = 30, +- [1][1][8][3] = 48, +- [1][1][11][3] = 30, +- [1][1][2][4] = 78, +- [1][1][1][4] = 30, +- [1][1][3][4] = 38, +- [1][1][5][4] = 78, +- [1][1][6][4] = 30, +- [1][1][9][4] = 30, +- [1][1][8][4] = 48, +- [1][1][11][4] = 30, +- [1][1][2][5] = 78, +- [1][1][1][5] = 30, +- [1][1][3][5] = 38, +- [1][1][5][5] = 78, +- [1][1][6][5] = 30, +- [1][1][9][5] = 30, +- [1][1][8][5] = 48, +- [1][1][11][5] = 30, +- [1][1][2][6] = 78, +- [1][1][1][6] = 30, +- [1][1][3][6] = 38, +- [1][1][5][6] = 78, +- [1][1][6][6] = 30, +- [1][1][9][6] = 30, +- [1][1][8][6] = 48, +- [1][1][11][6] = 30, +- [1][1][2][7] = 74, +- [1][1][1][7] = 30, +- [1][1][3][7] = 38, +- [1][1][5][7] = 74, +- [1][1][6][7] = 30, +- [1][1][9][7] = 30, +- [1][1][8][7] = 48, +- [1][1][11][7] = 30, +- [1][1][2][8] = 70, +- [1][1][1][8] = 30, +- [1][1][3][8] = 38, +- [1][1][5][8] = 70, +- [1][1][6][8] = 30, +- [1][1][9][8] = 30, +- [1][1][8][8] = 48, +- [1][1][11][8] = 30, +- [1][1][2][9] = 66, +- [1][1][1][9] = 30, +- [1][1][3][9] = 38, +- [1][1][5][9] = 66, +- [1][1][6][9] = 30, +- [1][1][9][9] = 30, +- [1][1][8][9] = 48, +- [1][1][11][9] = 30, +- [1][1][2][10] = 66, +- [1][1][1][10] = 30, +- [1][1][3][10] = 38, +- [1][1][5][10] = 66, +- [1][1][6][10] = 30, +- [1][1][9][10] = 30, +- [1][1][8][10] = 48, +- [1][1][11][10] = 30, +- [1][1][2][11] = 60, +- [1][1][1][11] = 30, +- [1][1][3][11] = 38, +- [1][1][5][11] = 60, +- [1][1][6][11] = 30, +- [1][1][9][11] = 30, +- [1][1][8][11] = 48, +- [1][1][11][11] = 30, +- [1][1][2][12] = 32, +- [1][1][1][12] = 30, +- [1][1][3][12] = 38, +- [1][1][5][12] = 32, +- [1][1][6][12] = 30, +- [1][1][9][12] = 30, +- [1][1][8][12] = 48, +- [1][1][11][12] = 30, +- [1][1][2][13] = 127, +- [1][1][1][13] = 127, +- [1][1][3][13] = 127, +- [1][1][5][13] = 127, +- [1][1][6][13] = 127, +- [1][1][9][13] = 127, +- [1][1][8][13] = 127, +- [1][1][11][13] = 127, +- [2][0][2][0] = 76, +- [2][0][1][0] = 52, +- [2][0][3][0] = 64, +- [2][0][5][0] = 76, +- [2][0][6][0] = 52, +- [2][0][9][0] = 52, +- [2][0][8][0] = 60, +- [2][0][11][0] = 52, +- [2][0][2][1] = 76, +- [2][0][1][1] = 52, +- [2][0][3][1] = 64, +- [2][0][5][1] = 76, +- [2][0][6][1] = 52, +- [2][0][9][1] = 52, +- [2][0][8][1] = 60, +- [2][0][11][1] = 52, +- [2][0][2][2] = 78, +- [2][0][1][2] = 52, +- [2][0][3][2] = 64, +- [2][0][5][2] = 78, +- [2][0][6][2] = 52, +- [2][0][9][2] = 52, +- [2][0][8][2] = 60, +- [2][0][11][2] = 52, +- [2][0][2][3] = 78, +- [2][0][1][3] = 52, +- [2][0][3][3] = 64, +- [2][0][5][3] = 78, +- [2][0][6][3] = 52, +- [2][0][9][3] = 52, +- [2][0][8][3] = 60, +- [2][0][11][3] = 52, +- [2][0][2][4] = 78, +- [2][0][1][4] = 52, +- [2][0][3][4] = 64, +- [2][0][5][4] = 78, +- [2][0][6][4] = 52, +- [2][0][9][4] = 52, +- [2][0][8][4] = 60, +- [2][0][11][4] = 52, +- [2][0][2][5] = 78, +- [2][0][1][5] = 52, +- [2][0][3][5] = 64, +- [2][0][5][5] = 78, +- [2][0][6][5] = 52, +- [2][0][9][5] = 52, +- [2][0][8][5] = 60, +- [2][0][11][5] = 52, +- [2][0][2][6] = 78, +- [2][0][1][6] = 52, +- [2][0][3][6] = 64, +- [2][0][5][6] = 78, +- [2][0][6][6] = 52, +- [2][0][9][6] = 52, +- [2][0][8][6] = 60, +- [2][0][11][6] = 52, +- [2][0][2][7] = 78, +- [2][0][1][7] = 52, +- [2][0][3][7] = 64, +- [2][0][5][7] = 78, +- [2][0][6][7] = 52, +- [2][0][9][7] = 52, +- [2][0][8][7] = 60, +- [2][0][11][7] = 52, +- [2][0][2][8] = 78, +- [2][0][1][8] = 52, +- [2][0][3][8] = 64, +- [2][0][5][8] = 78, +- [2][0][6][8] = 52, +- [2][0][9][8] = 52, +- [2][0][8][8] = 60, +- [2][0][11][8] = 52, +- [2][0][2][9] = 76, +- [2][0][1][9] = 52, +- [2][0][3][9] = 64, +- [2][0][5][9] = 76, +- [2][0][6][9] = 52, +- [2][0][9][9] = 52, +- [2][0][8][9] = 60, +- [2][0][11][9] = 52, +- [2][0][2][10] = 76, +- [2][0][1][10] = 52, +- [2][0][3][10] = 64, +- [2][0][5][10] = 76, +- [2][0][6][10] = 52, +- [2][0][9][10] = 52, +- [2][0][8][10] = 60, +- [2][0][11][10] = 52, +- [2][0][2][11] = 68, +- [2][0][1][11] = 52, +- [2][0][3][11] = 64, +- [2][0][5][11] = 68, +- [2][0][6][11] = 52, +- [2][0][9][11] = 52, +- [2][0][8][11] = 60, +- [2][0][11][11] = 52, +- [2][0][2][12] = 40, +- [2][0][1][12] = 52, +- [2][0][3][12] = 64, +- [2][0][5][12] = 40, +- [2][0][6][12] = 52, +- [2][0][9][12] = 52, +- [2][0][8][12] = 60, +- [2][0][11][12] = 52, +- [2][0][2][13] = 127, +- [2][0][1][13] = 127, +- [2][0][3][13] = 127, +- [2][0][5][13] = 127, +- [2][0][6][13] = 127, +- [2][0][9][13] = 127, +- [2][0][8][13] = 127, +- [2][0][11][13] = 127, +- [2][1][2][0] = 68, +- [2][1][1][0] = 40, +- [2][1][3][0] = 52, +- [2][1][5][0] = 68, +- [2][1][6][0] = 40, +- [2][1][9][0] = 40, +- [2][1][8][0] = 48, +- [2][1][11][0] = 40, +- [2][1][2][1] = 68, +- [2][1][1][1] = 40, +- [2][1][3][1] = 52, +- [2][1][5][1] = 68, +- [2][1][6][1] = 40, +- [2][1][9][1] = 40, +- [2][1][8][1] = 48, +- [2][1][11][1] = 40, +- [2][1][2][2] = 72, +- [2][1][1][2] = 40, +- [2][1][3][2] = 52, +- [2][1][5][2] = 72, +- [2][1][6][2] = 40, +- [2][1][9][2] = 40, +- [2][1][8][2] = 48, +- [2][1][11][2] = 40, +- [2][1][2][3] = 76, +- [2][1][1][3] = 40, +- [2][1][3][3] = 52, +- [2][1][5][3] = 76, +- [2][1][6][3] = 40, +- [2][1][9][3] = 40, +- [2][1][8][3] = 48, +- [2][1][11][3] = 40, +- [2][1][2][4] = 78, +- [2][1][1][4] = 40, +- [2][1][3][4] = 52, +- [2][1][5][4] = 78, +- [2][1][6][4] = 40, +- [2][1][9][4] = 40, +- [2][1][8][4] = 48, +- [2][1][11][4] = 40, +- [2][1][2][5] = 78, +- [2][1][1][5] = 40, +- [2][1][3][5] = 52, +- [2][1][5][5] = 78, +- [2][1][6][5] = 40, +- [2][1][9][5] = 40, +- [2][1][8][5] = 48, +- [2][1][11][5] = 40, +- [2][1][2][6] = 78, +- [2][1][1][6] = 40, +- [2][1][3][6] = 52, +- [2][1][5][6] = 78, +- [2][1][6][6] = 40, +- [2][1][9][6] = 40, +- [2][1][8][6] = 48, +- [2][1][11][6] = 40, +- [2][1][2][7] = 78, +- [2][1][1][7] = 40, +- [2][1][3][7] = 52, +- [2][1][5][7] = 78, +- [2][1][6][7] = 40, +- [2][1][9][7] = 40, +- [2][1][8][7] = 48, +- [2][1][11][7] = 40, +- [2][1][2][8] = 74, +- [2][1][1][8] = 40, +- [2][1][3][8] = 52, +- [2][1][5][8] = 74, +- [2][1][6][8] = 40, +- [2][1][9][8] = 40, +- [2][1][8][8] = 48, +- [2][1][11][8] = 40, +- [2][1][2][9] = 70, +- [2][1][1][9] = 40, +- [2][1][3][9] = 52, +- [2][1][5][9] = 70, +- [2][1][6][9] = 40, +- [2][1][9][9] = 40, +- [2][1][8][9] = 48, +- [2][1][11][9] = 40, +- [2][1][2][10] = 70, +- [2][1][1][10] = 40, +- [2][1][3][10] = 52, +- [2][1][5][10] = 70, +- [2][1][6][10] = 40, +- [2][1][9][10] = 40, +- [2][1][8][10] = 48, +- [2][1][11][10] = 40, +- [2][1][2][11] = 48, +- [2][1][1][11] = 40, +- [2][1][3][11] = 52, +- [2][1][5][11] = 48, +- [2][1][6][11] = 40, +- [2][1][9][11] = 40, +- [2][1][8][11] = 48, +- [2][1][11][11] = 40, +- [2][1][2][12] = 26, +- [2][1][1][12] = 40, +- [2][1][3][12] = 52, +- [2][1][5][12] = 26, +- [2][1][6][12] = 40, +- [2][1][9][12] = 40, +- [2][1][8][12] = 48, +- [2][1][11][12] = 40, +- [2][1][2][13] = 127, +- [2][1][1][13] = 127, +- [2][1][3][13] = 127, +- [2][1][5][13] = 127, +- [2][1][6][13] = 127, +- [2][1][9][13] = 127, +- [2][1][8][13] = 127, +- [2][1][11][13] = 127, ++ [0][0][RTW89_WW][0] = 32, ++ [0][0][RTW89_WW][1] = 32, ++ [0][0][RTW89_WW][2] = 32, ++ [0][0][RTW89_WW][3] = 32, ++ [0][0][RTW89_WW][4] = 32, ++ [0][0][RTW89_WW][5] = 32, ++ [0][0][RTW89_WW][6] = 32, ++ [0][0][RTW89_WW][7] = 32, ++ [0][0][RTW89_WW][8] = 32, ++ [0][0][RTW89_WW][9] = 32, ++ [0][0][RTW89_WW][10] = 32, ++ [0][0][RTW89_WW][11] = 32, ++ [0][0][RTW89_WW][12] = 32, ++ [0][0][RTW89_WW][13] = 0, ++ [0][1][RTW89_WW][0] = 20, ++ [0][1][RTW89_WW][1] = 20, ++ [0][1][RTW89_WW][2] = 20, ++ [0][1][RTW89_WW][3] = 20, ++ [0][1][RTW89_WW][4] = 20, ++ [0][1][RTW89_WW][5] = 20, ++ [0][1][RTW89_WW][6] = 20, ++ [0][1][RTW89_WW][7] = 20, ++ [0][1][RTW89_WW][8] = 20, ++ [0][1][RTW89_WW][9] = 20, ++ [0][1][RTW89_WW][10] = 20, ++ [0][1][RTW89_WW][11] = 20, ++ [0][1][RTW89_WW][12] = 20, ++ [0][1][RTW89_WW][13] = 0, ++ [1][0][RTW89_WW][0] = 42, ++ [1][0][RTW89_WW][1] = 42, ++ [1][0][RTW89_WW][2] = 42, ++ [1][0][RTW89_WW][3] = 42, ++ [1][0][RTW89_WW][4] = 42, ++ [1][0][RTW89_WW][5] = 42, ++ [1][0][RTW89_WW][6] = 42, ++ [1][0][RTW89_WW][7] = 42, ++ [1][0][RTW89_WW][8] = 42, ++ [1][0][RTW89_WW][9] = 42, ++ [1][0][RTW89_WW][10] = 42, ++ [1][0][RTW89_WW][11] = 42, ++ [1][0][RTW89_WW][12] = 36, ++ [1][0][RTW89_WW][13] = 0, ++ [1][1][RTW89_WW][0] = 30, ++ [1][1][RTW89_WW][1] = 30, ++ [1][1][RTW89_WW][2] = 30, ++ [1][1][RTW89_WW][3] = 30, ++ [1][1][RTW89_WW][4] = 30, ++ [1][1][RTW89_WW][5] = 30, ++ [1][1][RTW89_WW][6] = 30, ++ [1][1][RTW89_WW][7] = 30, ++ [1][1][RTW89_WW][8] = 30, ++ [1][1][RTW89_WW][9] = 30, ++ [1][1][RTW89_WW][10] = 30, ++ [1][1][RTW89_WW][11] = 30, ++ [1][1][RTW89_WW][12] = 30, ++ [1][1][RTW89_WW][13] = 0, ++ [2][0][RTW89_WW][0] = 52, ++ [2][0][RTW89_WW][1] = 52, ++ [2][0][RTW89_WW][2] = 52, ++ [2][0][RTW89_WW][3] = 52, ++ [2][0][RTW89_WW][4] = 52, ++ [2][0][RTW89_WW][5] = 52, ++ [2][0][RTW89_WW][6] = 52, ++ [2][0][RTW89_WW][7] = 52, ++ [2][0][RTW89_WW][8] = 52, ++ [2][0][RTW89_WW][9] = 52, ++ [2][0][RTW89_WW][10] = 52, ++ [2][0][RTW89_WW][11] = 52, ++ [2][0][RTW89_WW][12] = 40, ++ [2][0][RTW89_WW][13] = 0, ++ [2][1][RTW89_WW][0] = 40, ++ [2][1][RTW89_WW][1] = 40, ++ [2][1][RTW89_WW][2] = 40, ++ [2][1][RTW89_WW][3] = 40, ++ [2][1][RTW89_WW][4] = 40, ++ [2][1][RTW89_WW][5] = 40, ++ [2][1][RTW89_WW][6] = 40, ++ [2][1][RTW89_WW][7] = 40, ++ [2][1][RTW89_WW][8] = 40, ++ [2][1][RTW89_WW][9] = 40, ++ [2][1][RTW89_WW][10] = 40, ++ [2][1][RTW89_WW][11] = 40, ++ [2][1][RTW89_WW][12] = 26, ++ [2][1][RTW89_WW][13] = 0, ++ [0][0][RTW89_FCC][0] = 70, ++ [0][0][RTW89_ETSI][0] = 32, ++ [0][0][RTW89_MKK][0] = 40, ++ [0][0][RTW89_IC][0] = 70, ++ [0][0][RTW89_KCC][0] = 32, ++ [0][0][RTW89_ACMA][0] = 32, ++ [0][0][RTW89_CHILE][0] = 60, ++ [0][0][RTW89_UKRAINE][0] = 32, ++ [0][0][RTW89_FCC][1] = 70, ++ [0][0][RTW89_ETSI][1] = 32, ++ [0][0][RTW89_MKK][1] = 40, ++ [0][0][RTW89_IC][1] = 70, ++ [0][0][RTW89_KCC][1] = 32, ++ [0][0][RTW89_ACMA][1] = 32, ++ [0][0][RTW89_CHILE][1] = 60, ++ [0][0][RTW89_UKRAINE][1] = 32, ++ [0][0][RTW89_FCC][2] = 74, ++ [0][0][RTW89_ETSI][2] = 32, ++ [0][0][RTW89_MKK][2] = 40, ++ [0][0][RTW89_IC][2] = 74, ++ [0][0][RTW89_KCC][2] = 32, ++ [0][0][RTW89_ACMA][2] = 32, ++ [0][0][RTW89_CHILE][2] = 60, ++ [0][0][RTW89_UKRAINE][2] = 32, ++ [0][0][RTW89_FCC][3] = 78, ++ [0][0][RTW89_ETSI][3] = 32, ++ [0][0][RTW89_MKK][3] = 40, ++ [0][0][RTW89_IC][3] = 78, ++ [0][0][RTW89_KCC][3] = 32, ++ [0][0][RTW89_ACMA][3] = 32, ++ [0][0][RTW89_CHILE][3] = 60, ++ [0][0][RTW89_UKRAINE][3] = 32, ++ [0][0][RTW89_FCC][4] = 78, ++ [0][0][RTW89_ETSI][4] = 32, ++ [0][0][RTW89_MKK][4] = 40, ++ [0][0][RTW89_IC][4] = 78, ++ [0][0][RTW89_KCC][4] = 32, ++ [0][0][RTW89_ACMA][4] = 32, ++ [0][0][RTW89_CHILE][4] = 60, ++ [0][0][RTW89_UKRAINE][4] = 32, ++ [0][0][RTW89_FCC][5] = 78, ++ [0][0][RTW89_ETSI][5] = 32, ++ [0][0][RTW89_MKK][5] = 40, ++ [0][0][RTW89_IC][5] = 78, ++ [0][0][RTW89_KCC][5] = 32, ++ [0][0][RTW89_ACMA][5] = 32, ++ [0][0][RTW89_CHILE][5] = 60, ++ [0][0][RTW89_UKRAINE][5] = 32, ++ [0][0][RTW89_FCC][6] = 78, ++ [0][0][RTW89_ETSI][6] = 32, ++ [0][0][RTW89_MKK][6] = 40, ++ [0][0][RTW89_IC][6] = 78, ++ [0][0][RTW89_KCC][6] = 32, ++ [0][0][RTW89_ACMA][6] = 32, ++ [0][0][RTW89_CHILE][6] = 60, ++ [0][0][RTW89_UKRAINE][6] = 32, ++ [0][0][RTW89_FCC][7] = 78, ++ [0][0][RTW89_ETSI][7] = 32, ++ [0][0][RTW89_MKK][7] = 40, ++ [0][0][RTW89_IC][7] = 78, ++ [0][0][RTW89_KCC][7] = 32, ++ [0][0][RTW89_ACMA][7] = 32, ++ [0][0][RTW89_CHILE][7] = 60, ++ [0][0][RTW89_UKRAINE][7] = 32, ++ [0][0][RTW89_FCC][8] = 74, ++ [0][0][RTW89_ETSI][8] = 32, ++ [0][0][RTW89_MKK][8] = 40, ++ [0][0][RTW89_IC][8] = 74, ++ [0][0][RTW89_KCC][8] = 32, ++ [0][0][RTW89_ACMA][8] = 32, ++ [0][0][RTW89_CHILE][8] = 60, ++ [0][0][RTW89_UKRAINE][8] = 32, ++ [0][0][RTW89_FCC][9] = 70, ++ [0][0][RTW89_ETSI][9] = 32, ++ [0][0][RTW89_MKK][9] = 40, ++ [0][0][RTW89_IC][9] = 70, ++ [0][0][RTW89_KCC][9] = 32, ++ [0][0][RTW89_ACMA][9] = 32, ++ [0][0][RTW89_CHILE][9] = 60, ++ [0][0][RTW89_UKRAINE][9] = 32, ++ [0][0][RTW89_FCC][10] = 70, ++ [0][0][RTW89_ETSI][10] = 32, ++ [0][0][RTW89_MKK][10] = 40, ++ [0][0][RTW89_IC][10] = 70, ++ [0][0][RTW89_KCC][10] = 32, ++ [0][0][RTW89_ACMA][10] = 32, ++ [0][0][RTW89_CHILE][10] = 60, ++ [0][0][RTW89_UKRAINE][10] = 32, ++ [0][0][RTW89_FCC][11] = 58, ++ [0][0][RTW89_ETSI][11] = 32, ++ [0][0][RTW89_MKK][11] = 40, ++ [0][0][RTW89_IC][11] = 58, ++ [0][0][RTW89_KCC][11] = 32, ++ [0][0][RTW89_ACMA][11] = 32, ++ [0][0][RTW89_CHILE][11] = 60, ++ [0][0][RTW89_UKRAINE][11] = 32, ++ [0][0][RTW89_FCC][12] = 34, ++ [0][0][RTW89_ETSI][12] = 32, ++ [0][0][RTW89_MKK][12] = 40, ++ [0][0][RTW89_IC][12] = 34, ++ [0][0][RTW89_KCC][12] = 32, ++ [0][0][RTW89_ACMA][12] = 32, ++ [0][0][RTW89_CHILE][12] = 60, ++ [0][0][RTW89_UKRAINE][12] = 32, ++ [0][0][RTW89_FCC][13] = 127, ++ [0][0][RTW89_ETSI][13] = 127, ++ [0][0][RTW89_MKK][13] = 127, ++ [0][0][RTW89_IC][13] = 127, ++ [0][0][RTW89_KCC][13] = 127, ++ [0][0][RTW89_ACMA][13] = 127, ++ [0][0][RTW89_CHILE][13] = 127, ++ [0][0][RTW89_UKRAINE][13] = 127, ++ [0][1][RTW89_FCC][0] = 64, ++ [0][1][RTW89_ETSI][0] = 20, ++ [0][1][RTW89_MKK][0] = 28, ++ [0][1][RTW89_IC][0] = 64, ++ [0][1][RTW89_KCC][0] = 20, ++ [0][1][RTW89_ACMA][0] = 20, ++ [0][1][RTW89_CHILE][0] = 48, ++ [0][1][RTW89_UKRAINE][0] = 20, ++ [0][1][RTW89_FCC][1] = 64, ++ [0][1][RTW89_ETSI][1] = 20, ++ [0][1][RTW89_MKK][1] = 28, ++ [0][1][RTW89_IC][1] = 64, ++ [0][1][RTW89_KCC][1] = 20, ++ [0][1][RTW89_ACMA][1] = 20, ++ [0][1][RTW89_CHILE][1] = 48, ++ [0][1][RTW89_UKRAINE][1] = 20, ++ [0][1][RTW89_FCC][2] = 68, ++ [0][1][RTW89_ETSI][2] = 20, ++ [0][1][RTW89_MKK][2] = 28, ++ [0][1][RTW89_IC][2] = 68, ++ [0][1][RTW89_KCC][2] = 20, ++ [0][1][RTW89_ACMA][2] = 20, ++ [0][1][RTW89_CHILE][2] = 48, ++ [0][1][RTW89_UKRAINE][2] = 20, ++ [0][1][RTW89_FCC][3] = 72, ++ [0][1][RTW89_ETSI][3] = 20, ++ [0][1][RTW89_MKK][3] = 28, ++ [0][1][RTW89_IC][3] = 72, ++ [0][1][RTW89_KCC][3] = 20, ++ [0][1][RTW89_ACMA][3] = 20, ++ [0][1][RTW89_CHILE][3] = 48, ++ [0][1][RTW89_UKRAINE][3] = 20, ++ [0][1][RTW89_FCC][4] = 76, ++ [0][1][RTW89_ETSI][4] = 20, ++ [0][1][RTW89_MKK][4] = 28, ++ [0][1][RTW89_IC][4] = 76, ++ [0][1][RTW89_KCC][4] = 20, ++ [0][1][RTW89_ACMA][4] = 20, ++ [0][1][RTW89_CHILE][4] = 48, ++ [0][1][RTW89_UKRAINE][4] = 20, ++ [0][1][RTW89_FCC][5] = 78, ++ [0][1][RTW89_ETSI][5] = 20, ++ [0][1][RTW89_MKK][5] = 28, ++ [0][1][RTW89_IC][5] = 78, ++ [0][1][RTW89_KCC][5] = 20, ++ [0][1][RTW89_ACMA][5] = 20, ++ [0][1][RTW89_CHILE][5] = 48, ++ [0][1][RTW89_UKRAINE][5] = 20, ++ [0][1][RTW89_FCC][6] = 76, ++ [0][1][RTW89_ETSI][6] = 20, ++ [0][1][RTW89_MKK][6] = 28, ++ [0][1][RTW89_IC][6] = 76, ++ [0][1][RTW89_KCC][6] = 20, ++ [0][1][RTW89_ACMA][6] = 20, ++ [0][1][RTW89_CHILE][6] = 48, ++ [0][1][RTW89_UKRAINE][6] = 20, ++ [0][1][RTW89_FCC][7] = 72, ++ [0][1][RTW89_ETSI][7] = 20, ++ [0][1][RTW89_MKK][7] = 28, ++ [0][1][RTW89_IC][7] = 72, ++ [0][1][RTW89_KCC][7] = 20, ++ [0][1][RTW89_ACMA][7] = 20, ++ [0][1][RTW89_CHILE][7] = 48, ++ [0][1][RTW89_UKRAINE][7] = 20, ++ [0][1][RTW89_FCC][8] = 68, ++ [0][1][RTW89_ETSI][8] = 20, ++ [0][1][RTW89_MKK][8] = 28, ++ [0][1][RTW89_IC][8] = 68, ++ [0][1][RTW89_KCC][8] = 20, ++ [0][1][RTW89_ACMA][8] = 20, ++ [0][1][RTW89_CHILE][8] = 48, ++ [0][1][RTW89_UKRAINE][8] = 20, ++ [0][1][RTW89_FCC][9] = 64, ++ [0][1][RTW89_ETSI][9] = 20, ++ [0][1][RTW89_MKK][9] = 28, ++ [0][1][RTW89_IC][9] = 64, ++ [0][1][RTW89_KCC][9] = 20, ++ [0][1][RTW89_ACMA][9] = 20, ++ [0][1][RTW89_CHILE][9] = 48, ++ [0][1][RTW89_UKRAINE][9] = 20, ++ [0][1][RTW89_FCC][10] = 64, ++ [0][1][RTW89_ETSI][10] = 20, ++ [0][1][RTW89_MKK][10] = 28, ++ [0][1][RTW89_IC][10] = 64, ++ [0][1][RTW89_KCC][10] = 20, ++ [0][1][RTW89_ACMA][10] = 20, ++ [0][1][RTW89_CHILE][10] = 48, ++ [0][1][RTW89_UKRAINE][10] = 20, ++ [0][1][RTW89_FCC][11] = 54, ++ [0][1][RTW89_ETSI][11] = 20, ++ [0][1][RTW89_MKK][11] = 28, ++ [0][1][RTW89_IC][11] = 54, ++ [0][1][RTW89_KCC][11] = 20, ++ [0][1][RTW89_ACMA][11] = 20, ++ [0][1][RTW89_CHILE][11] = 48, ++ [0][1][RTW89_UKRAINE][11] = 20, ++ [0][1][RTW89_FCC][12] = 32, ++ [0][1][RTW89_ETSI][12] = 20, ++ [0][1][RTW89_MKK][12] = 28, ++ [0][1][RTW89_IC][12] = 32, ++ [0][1][RTW89_KCC][12] = 20, ++ [0][1][RTW89_ACMA][12] = 20, ++ [0][1][RTW89_CHILE][12] = 48, ++ [0][1][RTW89_UKRAINE][12] = 20, ++ [0][1][RTW89_FCC][13] = 127, ++ [0][1][RTW89_ETSI][13] = 127, ++ [0][1][RTW89_MKK][13] = 127, ++ [0][1][RTW89_IC][13] = 127, ++ [0][1][RTW89_KCC][13] = 127, ++ [0][1][RTW89_ACMA][13] = 127, ++ [0][1][RTW89_CHILE][13] = 127, ++ [0][1][RTW89_UKRAINE][13] = 127, ++ [1][0][RTW89_FCC][0] = 72, ++ [1][0][RTW89_ETSI][0] = 42, ++ [1][0][RTW89_MKK][0] = 50, ++ [1][0][RTW89_IC][0] = 72, ++ [1][0][RTW89_KCC][0] = 42, ++ [1][0][RTW89_ACMA][0] = 42, ++ [1][0][RTW89_CHILE][0] = 60, ++ [1][0][RTW89_UKRAINE][0] = 42, ++ [1][0][RTW89_FCC][1] = 72, ++ [1][0][RTW89_ETSI][1] = 42, ++ [1][0][RTW89_MKK][1] = 50, ++ [1][0][RTW89_IC][1] = 72, ++ [1][0][RTW89_KCC][1] = 42, ++ [1][0][RTW89_ACMA][1] = 42, ++ [1][0][RTW89_CHILE][1] = 60, ++ [1][0][RTW89_UKRAINE][1] = 42, ++ [1][0][RTW89_FCC][2] = 76, ++ [1][0][RTW89_ETSI][2] = 42, ++ [1][0][RTW89_MKK][2] = 50, ++ [1][0][RTW89_IC][2] = 76, ++ [1][0][RTW89_KCC][2] = 42, ++ [1][0][RTW89_ACMA][2] = 42, ++ [1][0][RTW89_CHILE][2] = 60, ++ [1][0][RTW89_UKRAINE][2] = 42, ++ [1][0][RTW89_FCC][3] = 78, ++ [1][0][RTW89_ETSI][3] = 42, ++ [1][0][RTW89_MKK][3] = 50, ++ [1][0][RTW89_IC][3] = 78, ++ [1][0][RTW89_KCC][3] = 42, ++ [1][0][RTW89_ACMA][3] = 42, ++ [1][0][RTW89_CHILE][3] = 60, ++ [1][0][RTW89_UKRAINE][3] = 42, ++ [1][0][RTW89_FCC][4] = 78, ++ [1][0][RTW89_ETSI][4] = 42, ++ [1][0][RTW89_MKK][4] = 50, ++ [1][0][RTW89_IC][4] = 78, ++ [1][0][RTW89_KCC][4] = 42, ++ [1][0][RTW89_ACMA][4] = 42, ++ [1][0][RTW89_CHILE][4] = 60, ++ [1][0][RTW89_UKRAINE][4] = 42, ++ [1][0][RTW89_FCC][5] = 78, ++ [1][0][RTW89_ETSI][5] = 42, ++ [1][0][RTW89_MKK][5] = 50, ++ [1][0][RTW89_IC][5] = 78, ++ [1][0][RTW89_KCC][5] = 42, ++ [1][0][RTW89_ACMA][5] = 42, ++ [1][0][RTW89_CHILE][5] = 60, ++ [1][0][RTW89_UKRAINE][5] = 42, ++ [1][0][RTW89_FCC][6] = 78, ++ [1][0][RTW89_ETSI][6] = 42, ++ [1][0][RTW89_MKK][6] = 50, ++ [1][0][RTW89_IC][6] = 78, ++ [1][0][RTW89_KCC][6] = 42, ++ [1][0][RTW89_ACMA][6] = 42, ++ [1][0][RTW89_CHILE][6] = 60, ++ [1][0][RTW89_UKRAINE][6] = 42, ++ [1][0][RTW89_FCC][7] = 78, ++ [1][0][RTW89_ETSI][7] = 42, ++ [1][0][RTW89_MKK][7] = 50, ++ [1][0][RTW89_IC][7] = 78, ++ [1][0][RTW89_KCC][7] = 42, ++ [1][0][RTW89_ACMA][7] = 42, ++ [1][0][RTW89_CHILE][7] = 60, ++ [1][0][RTW89_UKRAINE][7] = 42, ++ [1][0][RTW89_FCC][8] = 78, ++ [1][0][RTW89_ETSI][8] = 42, ++ [1][0][RTW89_MKK][8] = 50, ++ [1][0][RTW89_IC][8] = 78, ++ [1][0][RTW89_KCC][8] = 42, ++ [1][0][RTW89_ACMA][8] = 42, ++ [1][0][RTW89_CHILE][8] = 60, ++ [1][0][RTW89_UKRAINE][8] = 42, ++ [1][0][RTW89_FCC][9] = 74, ++ [1][0][RTW89_ETSI][9] = 42, ++ [1][0][RTW89_MKK][9] = 50, ++ [1][0][RTW89_IC][9] = 74, ++ [1][0][RTW89_KCC][9] = 42, ++ [1][0][RTW89_ACMA][9] = 42, ++ [1][0][RTW89_CHILE][9] = 60, ++ [1][0][RTW89_UKRAINE][9] = 42, ++ [1][0][RTW89_FCC][10] = 74, ++ [1][0][RTW89_ETSI][10] = 42, ++ [1][0][RTW89_MKK][10] = 50, ++ [1][0][RTW89_IC][10] = 74, ++ [1][0][RTW89_KCC][10] = 42, ++ [1][0][RTW89_ACMA][10] = 42, ++ [1][0][RTW89_CHILE][10] = 60, ++ [1][0][RTW89_UKRAINE][10] = 42, ++ [1][0][RTW89_FCC][11] = 64, ++ [1][0][RTW89_ETSI][11] = 42, ++ [1][0][RTW89_MKK][11] = 50, ++ [1][0][RTW89_IC][11] = 64, ++ [1][0][RTW89_KCC][11] = 42, ++ [1][0][RTW89_ACMA][11] = 42, ++ [1][0][RTW89_CHILE][11] = 60, ++ [1][0][RTW89_UKRAINE][11] = 42, ++ [1][0][RTW89_FCC][12] = 36, ++ [1][0][RTW89_ETSI][12] = 42, ++ [1][0][RTW89_MKK][12] = 50, ++ [1][0][RTW89_IC][12] = 36, ++ [1][0][RTW89_KCC][12] = 42, ++ [1][0][RTW89_ACMA][12] = 42, ++ [1][0][RTW89_CHILE][12] = 60, ++ [1][0][RTW89_UKRAINE][12] = 42, ++ [1][0][RTW89_FCC][13] = 127, ++ [1][0][RTW89_ETSI][13] = 127, ++ [1][0][RTW89_MKK][13] = 127, ++ [1][0][RTW89_IC][13] = 127, ++ [1][0][RTW89_KCC][13] = 127, ++ [1][0][RTW89_ACMA][13] = 127, ++ [1][0][RTW89_CHILE][13] = 127, ++ [1][0][RTW89_UKRAINE][13] = 127, ++ [1][1][RTW89_FCC][0] = 66, ++ [1][1][RTW89_ETSI][0] = 30, ++ [1][1][RTW89_MKK][0] = 38, ++ [1][1][RTW89_IC][0] = 66, ++ [1][1][RTW89_KCC][0] = 30, ++ [1][1][RTW89_ACMA][0] = 30, ++ [1][1][RTW89_CHILE][0] = 48, ++ [1][1][RTW89_UKRAINE][0] = 30, ++ [1][1][RTW89_FCC][1] = 66, ++ [1][1][RTW89_ETSI][1] = 30, ++ [1][1][RTW89_MKK][1] = 38, ++ [1][1][RTW89_IC][1] = 66, ++ [1][1][RTW89_KCC][1] = 30, ++ [1][1][RTW89_ACMA][1] = 30, ++ [1][1][RTW89_CHILE][1] = 48, ++ [1][1][RTW89_UKRAINE][1] = 30, ++ [1][1][RTW89_FCC][2] = 70, ++ [1][1][RTW89_ETSI][2] = 30, ++ [1][1][RTW89_MKK][2] = 38, ++ [1][1][RTW89_IC][2] = 70, ++ [1][1][RTW89_KCC][2] = 30, ++ [1][1][RTW89_ACMA][2] = 30, ++ [1][1][RTW89_CHILE][2] = 48, ++ [1][1][RTW89_UKRAINE][2] = 30, ++ [1][1][RTW89_FCC][3] = 74, ++ [1][1][RTW89_ETSI][3] = 30, ++ [1][1][RTW89_MKK][3] = 38, ++ [1][1][RTW89_IC][3] = 74, ++ [1][1][RTW89_KCC][3] = 30, ++ [1][1][RTW89_ACMA][3] = 30, ++ [1][1][RTW89_CHILE][3] = 48, ++ [1][1][RTW89_UKRAINE][3] = 30, ++ [1][1][RTW89_FCC][4] = 78, ++ [1][1][RTW89_ETSI][4] = 30, ++ [1][1][RTW89_MKK][4] = 38, ++ [1][1][RTW89_IC][4] = 78, ++ [1][1][RTW89_KCC][4] = 30, ++ [1][1][RTW89_ACMA][4] = 30, ++ [1][1][RTW89_CHILE][4] = 48, ++ [1][1][RTW89_UKRAINE][4] = 30, ++ [1][1][RTW89_FCC][5] = 78, ++ [1][1][RTW89_ETSI][5] = 30, ++ [1][1][RTW89_MKK][5] = 38, ++ [1][1][RTW89_IC][5] = 78, ++ [1][1][RTW89_KCC][5] = 30, ++ [1][1][RTW89_ACMA][5] = 30, ++ [1][1][RTW89_CHILE][5] = 48, ++ [1][1][RTW89_UKRAINE][5] = 30, ++ [1][1][RTW89_FCC][6] = 78, ++ [1][1][RTW89_ETSI][6] = 30, ++ [1][1][RTW89_MKK][6] = 38, ++ [1][1][RTW89_IC][6] = 78, ++ [1][1][RTW89_KCC][6] = 30, ++ [1][1][RTW89_ACMA][6] = 30, ++ [1][1][RTW89_CHILE][6] = 48, ++ [1][1][RTW89_UKRAINE][6] = 30, ++ [1][1][RTW89_FCC][7] = 74, ++ [1][1][RTW89_ETSI][7] = 30, ++ [1][1][RTW89_MKK][7] = 38, ++ [1][1][RTW89_IC][7] = 74, ++ [1][1][RTW89_KCC][7] = 30, ++ [1][1][RTW89_ACMA][7] = 30, ++ [1][1][RTW89_CHILE][7] = 48, ++ [1][1][RTW89_UKRAINE][7] = 30, ++ [1][1][RTW89_FCC][8] = 70, ++ [1][1][RTW89_ETSI][8] = 30, ++ [1][1][RTW89_MKK][8] = 38, ++ [1][1][RTW89_IC][8] = 70, ++ [1][1][RTW89_KCC][8] = 30, ++ [1][1][RTW89_ACMA][8] = 30, ++ [1][1][RTW89_CHILE][8] = 48, ++ [1][1][RTW89_UKRAINE][8] = 30, ++ [1][1][RTW89_FCC][9] = 66, ++ [1][1][RTW89_ETSI][9] = 30, ++ [1][1][RTW89_MKK][9] = 38, ++ [1][1][RTW89_IC][9] = 66, ++ [1][1][RTW89_KCC][9] = 30, ++ [1][1][RTW89_ACMA][9] = 30, ++ [1][1][RTW89_CHILE][9] = 48, ++ [1][1][RTW89_UKRAINE][9] = 30, ++ [1][1][RTW89_FCC][10] = 66, ++ [1][1][RTW89_ETSI][10] = 30, ++ [1][1][RTW89_MKK][10] = 38, ++ [1][1][RTW89_IC][10] = 66, ++ [1][1][RTW89_KCC][10] = 30, ++ [1][1][RTW89_ACMA][10] = 30, ++ [1][1][RTW89_CHILE][10] = 48, ++ [1][1][RTW89_UKRAINE][10] = 30, ++ [1][1][RTW89_FCC][11] = 60, ++ [1][1][RTW89_ETSI][11] = 30, ++ [1][1][RTW89_MKK][11] = 38, ++ [1][1][RTW89_IC][11] = 60, ++ [1][1][RTW89_KCC][11] = 30, ++ [1][1][RTW89_ACMA][11] = 30, ++ [1][1][RTW89_CHILE][11] = 48, ++ [1][1][RTW89_UKRAINE][11] = 30, ++ [1][1][RTW89_FCC][12] = 32, ++ [1][1][RTW89_ETSI][12] = 30, ++ [1][1][RTW89_MKK][12] = 38, ++ [1][1][RTW89_IC][12] = 32, ++ [1][1][RTW89_KCC][12] = 30, ++ [1][1][RTW89_ACMA][12] = 30, ++ [1][1][RTW89_CHILE][12] = 48, ++ [1][1][RTW89_UKRAINE][12] = 30, ++ [1][1][RTW89_FCC][13] = 127, ++ [1][1][RTW89_ETSI][13] = 127, ++ [1][1][RTW89_MKK][13] = 127, ++ [1][1][RTW89_IC][13] = 127, ++ [1][1][RTW89_KCC][13] = 127, ++ [1][1][RTW89_ACMA][13] = 127, ++ [1][1][RTW89_CHILE][13] = 127, ++ [1][1][RTW89_UKRAINE][13] = 127, ++ [2][0][RTW89_FCC][0] = 76, ++ [2][0][RTW89_ETSI][0] = 52, ++ [2][0][RTW89_MKK][0] = 64, ++ [2][0][RTW89_IC][0] = 76, ++ [2][0][RTW89_KCC][0] = 52, ++ [2][0][RTW89_ACMA][0] = 52, ++ [2][0][RTW89_CHILE][0] = 60, ++ [2][0][RTW89_UKRAINE][0] = 52, ++ [2][0][RTW89_FCC][1] = 76, ++ [2][0][RTW89_ETSI][1] = 52, ++ [2][0][RTW89_MKK][1] = 64, ++ [2][0][RTW89_IC][1] = 76, ++ [2][0][RTW89_KCC][1] = 52, ++ [2][0][RTW89_ACMA][1] = 52, ++ [2][0][RTW89_CHILE][1] = 60, ++ [2][0][RTW89_UKRAINE][1] = 52, ++ [2][0][RTW89_FCC][2] = 78, ++ [2][0][RTW89_ETSI][2] = 52, ++ [2][0][RTW89_MKK][2] = 64, ++ [2][0][RTW89_IC][2] = 78, ++ [2][0][RTW89_KCC][2] = 52, ++ [2][0][RTW89_ACMA][2] = 52, ++ [2][0][RTW89_CHILE][2] = 60, ++ [2][0][RTW89_UKRAINE][2] = 52, ++ [2][0][RTW89_FCC][3] = 78, ++ [2][0][RTW89_ETSI][3] = 52, ++ [2][0][RTW89_MKK][3] = 64, ++ [2][0][RTW89_IC][3] = 78, ++ [2][0][RTW89_KCC][3] = 52, ++ [2][0][RTW89_ACMA][3] = 52, ++ [2][0][RTW89_CHILE][3] = 60, ++ [2][0][RTW89_UKRAINE][3] = 52, ++ [2][0][RTW89_FCC][4] = 78, ++ [2][0][RTW89_ETSI][4] = 52, ++ [2][0][RTW89_MKK][4] = 64, ++ [2][0][RTW89_IC][4] = 78, ++ [2][0][RTW89_KCC][4] = 52, ++ [2][0][RTW89_ACMA][4] = 52, ++ [2][0][RTW89_CHILE][4] = 60, ++ [2][0][RTW89_UKRAINE][4] = 52, ++ [2][0][RTW89_FCC][5] = 78, ++ [2][0][RTW89_ETSI][5] = 52, ++ [2][0][RTW89_MKK][5] = 64, ++ [2][0][RTW89_IC][5] = 78, ++ [2][0][RTW89_KCC][5] = 52, ++ [2][0][RTW89_ACMA][5] = 52, ++ [2][0][RTW89_CHILE][5] = 60, ++ [2][0][RTW89_UKRAINE][5] = 52, ++ [2][0][RTW89_FCC][6] = 78, ++ [2][0][RTW89_ETSI][6] = 52, ++ [2][0][RTW89_MKK][6] = 64, ++ [2][0][RTW89_IC][6] = 78, ++ [2][0][RTW89_KCC][6] = 52, ++ [2][0][RTW89_ACMA][6] = 52, ++ [2][0][RTW89_CHILE][6] = 60, ++ [2][0][RTW89_UKRAINE][6] = 52, ++ [2][0][RTW89_FCC][7] = 78, ++ [2][0][RTW89_ETSI][7] = 52, ++ [2][0][RTW89_MKK][7] = 64, ++ [2][0][RTW89_IC][7] = 78, ++ [2][0][RTW89_KCC][7] = 52, ++ [2][0][RTW89_ACMA][7] = 52, ++ [2][0][RTW89_CHILE][7] = 60, ++ [2][0][RTW89_UKRAINE][7] = 52, ++ [2][0][RTW89_FCC][8] = 78, ++ [2][0][RTW89_ETSI][8] = 52, ++ [2][0][RTW89_MKK][8] = 64, ++ [2][0][RTW89_IC][8] = 78, ++ [2][0][RTW89_KCC][8] = 52, ++ [2][0][RTW89_ACMA][8] = 52, ++ [2][0][RTW89_CHILE][8] = 60, ++ [2][0][RTW89_UKRAINE][8] = 52, ++ [2][0][RTW89_FCC][9] = 76, ++ [2][0][RTW89_ETSI][9] = 52, ++ [2][0][RTW89_MKK][9] = 64, ++ [2][0][RTW89_IC][9] = 76, ++ [2][0][RTW89_KCC][9] = 52, ++ [2][0][RTW89_ACMA][9] = 52, ++ [2][0][RTW89_CHILE][9] = 60, ++ [2][0][RTW89_UKRAINE][9] = 52, ++ [2][0][RTW89_FCC][10] = 76, ++ [2][0][RTW89_ETSI][10] = 52, ++ [2][0][RTW89_MKK][10] = 64, ++ [2][0][RTW89_IC][10] = 76, ++ [2][0][RTW89_KCC][10] = 52, ++ [2][0][RTW89_ACMA][10] = 52, ++ [2][0][RTW89_CHILE][10] = 60, ++ [2][0][RTW89_UKRAINE][10] = 52, ++ [2][0][RTW89_FCC][11] = 68, ++ [2][0][RTW89_ETSI][11] = 52, ++ [2][0][RTW89_MKK][11] = 64, ++ [2][0][RTW89_IC][11] = 68, ++ [2][0][RTW89_KCC][11] = 52, ++ [2][0][RTW89_ACMA][11] = 52, ++ [2][0][RTW89_CHILE][11] = 60, ++ [2][0][RTW89_UKRAINE][11] = 52, ++ [2][0][RTW89_FCC][12] = 40, ++ [2][0][RTW89_ETSI][12] = 52, ++ [2][0][RTW89_MKK][12] = 64, ++ [2][0][RTW89_IC][12] = 40, ++ [2][0][RTW89_KCC][12] = 52, ++ [2][0][RTW89_ACMA][12] = 52, ++ [2][0][RTW89_CHILE][12] = 60, ++ [2][0][RTW89_UKRAINE][12] = 52, ++ [2][0][RTW89_FCC][13] = 127, ++ [2][0][RTW89_ETSI][13] = 127, ++ [2][0][RTW89_MKK][13] = 127, ++ [2][0][RTW89_IC][13] = 127, ++ [2][0][RTW89_KCC][13] = 127, ++ [2][0][RTW89_ACMA][13] = 127, ++ [2][0][RTW89_CHILE][13] = 127, ++ [2][0][RTW89_UKRAINE][13] = 127, ++ [2][1][RTW89_FCC][0] = 68, ++ [2][1][RTW89_ETSI][0] = 40, ++ [2][1][RTW89_MKK][0] = 52, ++ [2][1][RTW89_IC][0] = 68, ++ [2][1][RTW89_KCC][0] = 40, ++ [2][1][RTW89_ACMA][0] = 40, ++ [2][1][RTW89_CHILE][0] = 48, ++ [2][1][RTW89_UKRAINE][0] = 40, ++ [2][1][RTW89_FCC][1] = 68, ++ [2][1][RTW89_ETSI][1] = 40, ++ [2][1][RTW89_MKK][1] = 52, ++ [2][1][RTW89_IC][1] = 68, ++ [2][1][RTW89_KCC][1] = 40, ++ [2][1][RTW89_ACMA][1] = 40, ++ [2][1][RTW89_CHILE][1] = 48, ++ [2][1][RTW89_UKRAINE][1] = 40, ++ [2][1][RTW89_FCC][2] = 72, ++ [2][1][RTW89_ETSI][2] = 40, ++ [2][1][RTW89_MKK][2] = 52, ++ [2][1][RTW89_IC][2] = 72, ++ [2][1][RTW89_KCC][2] = 40, ++ [2][1][RTW89_ACMA][2] = 40, ++ [2][1][RTW89_CHILE][2] = 48, ++ [2][1][RTW89_UKRAINE][2] = 40, ++ [2][1][RTW89_FCC][3] = 76, ++ [2][1][RTW89_ETSI][3] = 40, ++ [2][1][RTW89_MKK][3] = 52, ++ [2][1][RTW89_IC][3] = 76, ++ [2][1][RTW89_KCC][3] = 40, ++ [2][1][RTW89_ACMA][3] = 40, ++ [2][1][RTW89_CHILE][3] = 48, ++ [2][1][RTW89_UKRAINE][3] = 40, ++ [2][1][RTW89_FCC][4] = 78, ++ [2][1][RTW89_ETSI][4] = 40, ++ [2][1][RTW89_MKK][4] = 52, ++ [2][1][RTW89_IC][4] = 78, ++ [2][1][RTW89_KCC][4] = 40, ++ [2][1][RTW89_ACMA][4] = 40, ++ [2][1][RTW89_CHILE][4] = 48, ++ [2][1][RTW89_UKRAINE][4] = 40, ++ [2][1][RTW89_FCC][5] = 78, ++ [2][1][RTW89_ETSI][5] = 40, ++ [2][1][RTW89_MKK][5] = 52, ++ [2][1][RTW89_IC][5] = 78, ++ [2][1][RTW89_KCC][5] = 40, ++ [2][1][RTW89_ACMA][5] = 40, ++ [2][1][RTW89_CHILE][5] = 48, ++ [2][1][RTW89_UKRAINE][5] = 40, ++ [2][1][RTW89_FCC][6] = 78, ++ [2][1][RTW89_ETSI][6] = 40, ++ [2][1][RTW89_MKK][6] = 52, ++ [2][1][RTW89_IC][6] = 78, ++ [2][1][RTW89_KCC][6] = 40, ++ [2][1][RTW89_ACMA][6] = 40, ++ [2][1][RTW89_CHILE][6] = 48, ++ [2][1][RTW89_UKRAINE][6] = 40, ++ [2][1][RTW89_FCC][7] = 78, ++ [2][1][RTW89_ETSI][7] = 40, ++ [2][1][RTW89_MKK][7] = 52, ++ [2][1][RTW89_IC][7] = 78, ++ [2][1][RTW89_KCC][7] = 40, ++ [2][1][RTW89_ACMA][7] = 40, ++ [2][1][RTW89_CHILE][7] = 48, ++ [2][1][RTW89_UKRAINE][7] = 40, ++ [2][1][RTW89_FCC][8] = 74, ++ [2][1][RTW89_ETSI][8] = 40, ++ [2][1][RTW89_MKK][8] = 52, ++ [2][1][RTW89_IC][8] = 74, ++ [2][1][RTW89_KCC][8] = 40, ++ [2][1][RTW89_ACMA][8] = 40, ++ [2][1][RTW89_CHILE][8] = 48, ++ [2][1][RTW89_UKRAINE][8] = 40, ++ [2][1][RTW89_FCC][9] = 70, ++ [2][1][RTW89_ETSI][9] = 40, ++ [2][1][RTW89_MKK][9] = 52, ++ [2][1][RTW89_IC][9] = 70, ++ [2][1][RTW89_KCC][9] = 40, ++ [2][1][RTW89_ACMA][9] = 40, ++ [2][1][RTW89_CHILE][9] = 48, ++ [2][1][RTW89_UKRAINE][9] = 40, ++ [2][1][RTW89_FCC][10] = 70, ++ [2][1][RTW89_ETSI][10] = 40, ++ [2][1][RTW89_MKK][10] = 52, ++ [2][1][RTW89_IC][10] = 70, ++ [2][1][RTW89_KCC][10] = 40, ++ [2][1][RTW89_ACMA][10] = 40, ++ [2][1][RTW89_CHILE][10] = 48, ++ [2][1][RTW89_UKRAINE][10] = 40, ++ [2][1][RTW89_FCC][11] = 48, ++ [2][1][RTW89_ETSI][11] = 40, ++ [2][1][RTW89_MKK][11] = 52, ++ [2][1][RTW89_IC][11] = 48, ++ [2][1][RTW89_KCC][11] = 40, ++ [2][1][RTW89_ACMA][11] = 40, ++ [2][1][RTW89_CHILE][11] = 48, ++ [2][1][RTW89_UKRAINE][11] = 40, ++ [2][1][RTW89_FCC][12] = 26, ++ [2][1][RTW89_ETSI][12] = 40, ++ [2][1][RTW89_MKK][12] = 52, ++ [2][1][RTW89_IC][12] = 26, ++ [2][1][RTW89_KCC][12] = 40, ++ [2][1][RTW89_ACMA][12] = 40, ++ [2][1][RTW89_CHILE][12] = 48, ++ [2][1][RTW89_UKRAINE][12] = 40, ++ [2][1][RTW89_FCC][13] = 127, ++ [2][1][RTW89_ETSI][13] = 127, ++ [2][1][RTW89_MKK][13] = 127, ++ [2][1][RTW89_IC][13] = 127, ++ [2][1][RTW89_KCC][13] = 127, ++ [2][1][RTW89_ACMA][13] = 127, ++ [2][1][RTW89_CHILE][13] = 127, ++ [2][1][RTW89_UKRAINE][13] = 127, + }; + + const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [RTW89_REGD_NUM][RTW89_5G_CH_NUM] = { +- [0][0][0][0] = 22, +- [0][0][0][2] = 22, +- [0][0][0][4] = 22, +- [0][0][0][6] = 22, +- [0][0][0][8] = 24, +- [0][0][0][10] = 24, +- [0][0][0][12] = 24, +- [0][0][0][14] = 24, +- [0][0][0][15] = 24, +- [0][0][0][17] = 24, +- [0][0][0][19] = 24, +- [0][0][0][21] = 24, +- [0][0][0][23] = 24, +- [0][0][0][25] = 24, +- [0][0][0][27] = 24, +- [0][0][0][29] = 24, +- [0][0][0][31] = 24, +- [0][0][0][33] = 24, +- [0][0][0][35] = 24, +- [0][0][0][37] = 24, +- [0][0][0][38] = 28, +- [0][0][0][40] = 28, +- [0][0][0][42] = 28, +- [0][0][0][44] = 28, +- [0][0][0][46] = 28, +- [0][1][0][0] = 8, +- [0][1][0][2] = 8, +- [0][1][0][4] = 8, +- [0][1][0][6] = 8, +- [0][1][0][8] = 12, +- [0][1][0][10] = 12, +- [0][1][0][12] = 12, +- [0][1][0][14] = 12, +- [0][1][0][15] = 12, +- [0][1][0][17] = 12, +- [0][1][0][19] = 12, +- [0][1][0][21] = 12, +- [0][1][0][23] = 12, +- [0][1][0][25] = 12, +- [0][1][0][27] = 12, +- [0][1][0][29] = 12, +- [0][1][0][31] = 12, +- [0][1][0][33] = 12, +- [0][1][0][35] = 12, +- [0][1][0][37] = 12, +- [0][1][0][38] = 16, +- [0][1][0][40] = 16, +- [0][1][0][42] = 16, +- [0][1][0][44] = 16, +- [0][1][0][46] = 16, +- [1][0][0][0] = 30, +- [1][0][0][2] = 30, +- [1][0][0][4] = 30, +- [1][0][0][6] = 30, +- [1][0][0][8] = 36, +- [1][0][0][10] = 36, +- [1][0][0][12] = 36, +- [1][0][0][14] = 36, +- [1][0][0][15] = 36, +- [1][0][0][17] = 36, +- [1][0][0][19] = 36, +- [1][0][0][21] = 36, +- [1][0][0][23] = 36, +- [1][0][0][25] = 36, +- [1][0][0][27] = 36, +- [1][0][0][29] = 36, +- [1][0][0][31] = 36, +- [1][0][0][33] = 36, +- [1][0][0][35] = 36, +- [1][0][0][37] = 36, +- [1][0][0][38] = 28, +- [1][0][0][40] = 28, +- [1][0][0][42] = 28, +- [1][0][0][44] = 28, +- [1][0][0][46] = 28, +- [1][1][0][0] = 18, +- [1][1][0][2] = 18, +- [1][1][0][4] = 18, +- [1][1][0][6] = 18, +- [1][1][0][8] = 22, +- [1][1][0][10] = 22, +- [1][1][0][12] = 22, +- [1][1][0][14] = 22, +- [1][1][0][15] = 22, +- [1][1][0][17] = 22, +- [1][1][0][19] = 22, +- [1][1][0][21] = 22, +- [1][1][0][23] = 22, +- [1][1][0][25] = 22, +- [1][1][0][27] = 22, +- [1][1][0][29] = 22, +- [1][1][0][31] = 22, +- [1][1][0][33] = 22, +- [1][1][0][35] = 22, +- [1][1][0][37] = 22, +- [1][1][0][38] = 16, +- [1][1][0][40] = 16, +- [1][1][0][42] = 16, +- [1][1][0][44] = 16, +- [1][1][0][46] = 16, +- [2][0][0][0] = 30, +- [2][0][0][2] = 30, +- [2][0][0][4] = 30, +- [2][0][0][6] = 30, +- [2][0][0][8] = 46, +- [2][0][0][10] = 46, +- [2][0][0][12] = 46, +- [2][0][0][14] = 46, +- [2][0][0][15] = 46, +- [2][0][0][17] = 46, +- [2][0][0][19] = 46, +- [2][0][0][21] = 46, +- [2][0][0][23] = 46, +- [2][0][0][25] = 46, +- [2][0][0][27] = 46, +- [2][0][0][29] = 46, +- [2][0][0][31] = 46, +- [2][0][0][33] = 46, +- [2][0][0][35] = 46, +- [2][0][0][37] = 46, +- [2][0][0][38] = 28, +- [2][0][0][40] = 28, +- [2][0][0][42] = 28, +- [2][0][0][44] = 28, +- [2][0][0][46] = 28, +- [2][1][0][0] = 18, +- [2][1][0][2] = 18, +- [2][1][0][4] = 18, +- [2][1][0][6] = 18, +- [2][1][0][8] = 32, +- [2][1][0][10] = 32, +- [2][1][0][12] = 32, +- [2][1][0][14] = 32, +- [2][1][0][15] = 32, +- [2][1][0][17] = 32, +- [2][1][0][19] = 32, +- [2][1][0][21] = 32, +- [2][1][0][23] = 32, +- [2][1][0][25] = 32, +- [2][1][0][27] = 32, +- [2][1][0][29] = 32, +- [2][1][0][31] = 32, +- [2][1][0][33] = 32, +- [2][1][0][35] = 32, +- [2][1][0][37] = 32, +- [2][1][0][38] = 16, +- [2][1][0][40] = 16, +- [2][1][0][42] = 16, +- [2][1][0][44] = 16, +- [2][1][0][46] = 16, +- [0][0][2][0] = 48, +- [0][0][1][0] = 24, +- [0][0][3][0] = 26, +- [0][0][5][0] = 22, +- [0][0][6][0] = 24, +- [0][0][9][0] = 24, +- [0][0][8][0] = 30, +- [0][0][11][0] = 24, +- [0][0][2][2] = 48, +- [0][0][1][2] = 24, +- [0][0][3][2] = 26, +- [0][0][5][2] = 22, +- [0][0][6][2] = 24, +- [0][0][9][2] = 24, +- [0][0][8][2] = 30, +- [0][0][11][2] = 24, +- [0][0][2][4] = 48, +- [0][0][1][4] = 24, +- [0][0][3][4] = 26, +- [0][0][5][4] = 22, +- [0][0][6][4] = 24, +- [0][0][9][4] = 24, +- [0][0][8][4] = 30, +- [0][0][11][4] = 24, +- [0][0][2][6] = 48, +- [0][0][1][6] = 24, +- [0][0][3][6] = 26, +- [0][0][5][6] = 22, +- [0][0][6][6] = 24, +- [0][0][9][6] = 24, +- [0][0][8][6] = 30, +- [0][0][11][6] = 24, +- [0][0][2][8] = 48, +- [0][0][1][8] = 24, +- [0][0][3][8] = 26, +- [0][0][5][8] = 48, +- [0][0][6][8] = 24, +- [0][0][9][8] = 24, +- [0][0][8][8] = 54, +- [0][0][11][8] = 24, +- [0][0][2][10] = 48, +- [0][0][1][10] = 24, +- [0][0][3][10] = 26, +- [0][0][5][10] = 48, +- [0][0][6][10] = 24, +- [0][0][9][10] = 24, +- [0][0][8][10] = 54, +- [0][0][11][10] = 24, +- [0][0][2][12] = 48, +- [0][0][1][12] = 24, +- [0][0][3][12] = 26, +- [0][0][5][12] = 48, +- [0][0][6][12] = 24, +- [0][0][9][12] = 24, +- [0][0][8][12] = 54, +- [0][0][11][12] = 24, +- [0][0][2][14] = 48, +- [0][0][1][14] = 24, +- [0][0][3][14] = 26, +- [0][0][5][14] = 48, +- [0][0][6][14] = 24, +- [0][0][9][14] = 24, +- [0][0][8][14] = 54, +- [0][0][11][14] = 24, +- [0][0][2][15] = 48, +- [0][0][1][15] = 24, +- [0][0][3][15] = 44, +- [0][0][5][15] = 48, +- [0][0][6][15] = 24, +- [0][0][9][15] = 24, +- [0][0][8][15] = 54, +- [0][0][11][15] = 24, +- [0][0][2][17] = 48, +- [0][0][1][17] = 24, +- [0][0][3][17] = 44, +- [0][0][5][17] = 48, +- [0][0][6][17] = 24, +- [0][0][9][17] = 24, +- [0][0][8][17] = 54, +- [0][0][11][17] = 24, +- [0][0][2][19] = 48, +- [0][0][1][19] = 24, +- [0][0][3][19] = 44, +- [0][0][5][19] = 48, +- [0][0][6][19] = 24, +- [0][0][9][19] = 24, +- [0][0][8][19] = 54, +- [0][0][11][19] = 24, +- [0][0][2][21] = 48, +- [0][0][1][21] = 24, +- [0][0][3][21] = 44, +- [0][0][5][21] = 48, +- [0][0][6][21] = 24, +- [0][0][9][21] = 24, +- [0][0][8][21] = 54, +- [0][0][11][21] = 24, +- [0][0][2][23] = 48, +- [0][0][1][23] = 24, +- [0][0][3][23] = 44, +- [0][0][5][23] = 48, +- [0][0][6][23] = 24, +- [0][0][9][23] = 24, +- [0][0][8][23] = 54, +- [0][0][11][23] = 24, +- [0][0][2][25] = 48, +- [0][0][1][25] = 24, +- [0][0][3][25] = 44, +- [0][0][5][25] = 127, +- [0][0][6][25] = 24, +- [0][0][9][25] = 127, +- [0][0][8][25] = 54, +- [0][0][11][25] = 24, +- [0][0][2][27] = 48, +- [0][0][1][27] = 24, +- [0][0][3][27] = 44, +- [0][0][5][27] = 127, +- [0][0][6][27] = 24, +- [0][0][9][27] = 127, +- [0][0][8][27] = 54, +- [0][0][11][27] = 24, +- [0][0][2][29] = 48, +- [0][0][1][29] = 24, +- [0][0][3][29] = 44, +- [0][0][5][29] = 127, +- [0][0][6][29] = 24, +- [0][0][9][29] = 127, +- [0][0][8][29] = 54, +- [0][0][11][29] = 24, +- [0][0][2][31] = 48, +- [0][0][1][31] = 24, +- [0][0][3][31] = 44, +- [0][0][5][31] = 48, +- [0][0][6][31] = 24, +- [0][0][9][31] = 24, +- [0][0][8][31] = 54, +- [0][0][11][31] = 24, +- [0][0][2][33] = 48, +- [0][0][1][33] = 24, +- [0][0][3][33] = 44, +- [0][0][5][33] = 48, +- [0][0][6][33] = 24, +- [0][0][9][33] = 24, +- [0][0][8][33] = 54, +- [0][0][11][33] = 24, +- [0][0][2][35] = 48, +- [0][0][1][35] = 24, +- [0][0][3][35] = 44, +- [0][0][5][35] = 48, +- [0][0][6][35] = 24, +- [0][0][9][35] = 24, +- [0][0][8][35] = 54, +- [0][0][11][35] = 24, +- [0][0][2][37] = 48, +- [0][0][1][37] = 127, +- [0][0][3][37] = 44, +- [0][0][5][37] = 48, +- [0][0][6][37] = 24, +- [0][0][9][37] = 48, +- [0][0][8][37] = 54, +- [0][0][11][37] = 127, +- [0][0][2][38] = 76, +- [0][0][1][38] = 28, +- [0][0][3][38] = 127, +- [0][0][5][38] = 76, +- [0][0][6][38] = 28, +- [0][0][9][38] = 76, +- [0][0][8][38] = 54, +- [0][0][11][38] = 28, +- [0][0][2][40] = 76, +- [0][0][1][40] = 28, +- [0][0][3][40] = 127, +- [0][0][5][40] = 76, +- [0][0][6][40] = 28, +- [0][0][9][40] = 76, +- [0][0][8][40] = 54, +- [0][0][11][40] = 28, +- [0][0][2][42] = 76, +- [0][0][1][42] = 28, +- [0][0][3][42] = 127, +- [0][0][5][42] = 76, +- [0][0][6][42] = 28, +- [0][0][9][42] = 76, +- [0][0][8][42] = 54, +- [0][0][11][42] = 28, +- [0][0][2][44] = 76, +- [0][0][1][44] = 28, +- [0][0][3][44] = 127, +- [0][0][5][44] = 76, +- [0][0][6][44] = 28, +- [0][0][9][44] = 76, +- [0][0][8][44] = 54, +- [0][0][11][44] = 28, +- [0][0][2][46] = 76, +- [0][0][1][46] = 28, +- [0][0][3][46] = 127, +- [0][0][5][46] = 76, +- [0][0][6][46] = 28, +- [0][0][9][46] = 76, +- [0][0][8][46] = 54, +- [0][0][11][46] = 28, +- [0][1][2][0] = 36, +- [0][1][1][0] = 12, +- [0][1][3][0] = 14, +- [0][1][5][0] = 8, +- [0][1][6][0] = 12, +- [0][1][9][0] = 12, +- [0][1][8][0] = 18, +- [0][1][11][0] = 12, +- [0][1][2][2] = 36, +- [0][1][1][2] = 12, +- [0][1][3][2] = 14, +- [0][1][5][2] = 8, +- [0][1][6][2] = 12, +- [0][1][9][2] = 12, +- [0][1][8][2] = 18, +- [0][1][11][2] = 12, +- [0][1][2][4] = 36, +- [0][1][1][4] = 12, +- [0][1][3][4] = 14, +- [0][1][5][4] = 8, +- [0][1][6][4] = 12, +- [0][1][9][4] = 12, +- [0][1][8][4] = 18, +- [0][1][11][4] = 12, +- [0][1][2][6] = 36, +- [0][1][1][6] = 12, +- [0][1][3][6] = 14, +- [0][1][5][6] = 8, +- [0][1][6][6] = 12, +- [0][1][9][6] = 12, +- [0][1][8][6] = 18, +- [0][1][11][6] = 12, +- [0][1][2][8] = 36, +- [0][1][1][8] = 12, +- [0][1][3][8] = 14, +- [0][1][5][8] = 36, +- [0][1][6][8] = 12, +- [0][1][9][8] = 12, +- [0][1][8][8] = 42, +- [0][1][11][8] = 12, +- [0][1][2][10] = 36, +- [0][1][1][10] = 12, +- [0][1][3][10] = 14, +- [0][1][5][10] = 36, +- [0][1][6][10] = 12, +- [0][1][9][10] = 12, +- [0][1][8][10] = 42, +- [0][1][11][10] = 12, +- [0][1][2][12] = 36, +- [0][1][1][12] = 12, +- [0][1][3][12] = 14, +- [0][1][5][12] = 36, +- [0][1][6][12] = 12, +- [0][1][9][12] = 12, +- [0][1][8][12] = 42, +- [0][1][11][12] = 12, +- [0][1][2][14] = 36, +- [0][1][1][14] = 12, +- [0][1][3][14] = 14, +- [0][1][5][14] = 36, +- [0][1][6][14] = 12, +- [0][1][9][14] = 12, +- [0][1][8][14] = 42, +- [0][1][11][14] = 12, +- [0][1][2][15] = 36, +- [0][1][1][15] = 12, +- [0][1][3][15] = 32, +- [0][1][5][15] = 36, +- [0][1][6][15] = 12, +- [0][1][9][15] = 12, +- [0][1][8][15] = 42, +- [0][1][11][15] = 12, +- [0][1][2][17] = 36, +- [0][1][1][17] = 12, +- [0][1][3][17] = 32, +- [0][1][5][17] = 36, +- [0][1][6][17] = 12, +- [0][1][9][17] = 12, +- [0][1][8][17] = 42, +- [0][1][11][17] = 12, +- [0][1][2][19] = 36, +- [0][1][1][19] = 12, +- [0][1][3][19] = 32, +- [0][1][5][19] = 36, +- [0][1][6][19] = 12, +- [0][1][9][19] = 12, +- [0][1][8][19] = 42, +- [0][1][11][19] = 12, +- [0][1][2][21] = 36, +- [0][1][1][21] = 12, +- [0][1][3][21] = 32, +- [0][1][5][21] = 36, +- [0][1][6][21] = 12, +- [0][1][9][21] = 12, +- [0][1][8][21] = 42, +- [0][1][11][21] = 12, +- [0][1][2][23] = 36, +- [0][1][1][23] = 12, +- [0][1][3][23] = 32, +- [0][1][5][23] = 36, +- [0][1][6][23] = 12, +- [0][1][9][23] = 12, +- [0][1][8][23] = 42, +- [0][1][11][23] = 12, +- [0][1][2][25] = 36, +- [0][1][1][25] = 12, +- [0][1][3][25] = 32, +- [0][1][5][25] = 127, +- [0][1][6][25] = 12, +- [0][1][9][25] = 127, +- [0][1][8][25] = 42, +- [0][1][11][25] = 12, +- [0][1][2][27] = 36, +- [0][1][1][27] = 12, +- [0][1][3][27] = 32, +- [0][1][5][27] = 127, +- [0][1][6][27] = 12, +- [0][1][9][27] = 127, +- [0][1][8][27] = 42, +- [0][1][11][27] = 12, +- [0][1][2][29] = 36, +- [0][1][1][29] = 12, +- [0][1][3][29] = 32, +- [0][1][5][29] = 127, +- [0][1][6][29] = 12, +- [0][1][9][29] = 127, +- [0][1][8][29] = 42, +- [0][1][11][29] = 12, +- [0][1][2][31] = 36, +- [0][1][1][31] = 12, +- [0][1][3][31] = 32, +- [0][1][5][31] = 36, +- [0][1][6][31] = 12, +- [0][1][9][31] = 12, +- [0][1][8][31] = 42, +- [0][1][11][31] = 12, +- [0][1][2][33] = 36, +- [0][1][1][33] = 12, +- [0][1][3][33] = 32, +- [0][1][5][33] = 36, +- [0][1][6][33] = 12, +- [0][1][9][33] = 12, +- [0][1][8][33] = 42, +- [0][1][11][33] = 12, +- [0][1][2][35] = 36, +- [0][1][1][35] = 12, +- [0][1][3][35] = 32, +- [0][1][5][35] = 36, +- [0][1][6][35] = 12, +- [0][1][9][35] = 12, +- [0][1][8][35] = 42, +- [0][1][11][35] = 12, +- [0][1][2][37] = 36, +- [0][1][1][37] = 127, +- [0][1][3][37] = 32, +- [0][1][5][37] = 36, +- [0][1][6][37] = 12, +- [0][1][9][37] = 36, +- [0][1][8][37] = 42, +- [0][1][11][37] = 127, +- [0][1][2][38] = 72, +- [0][1][1][38] = 16, +- [0][1][3][38] = 127, +- [0][1][5][38] = 72, +- [0][1][6][38] = 16, +- [0][1][9][38] = 76, +- [0][1][8][38] = 42, +- [0][1][11][38] = 16, +- [0][1][2][40] = 76, +- [0][1][1][40] = 16, +- [0][1][3][40] = 127, +- [0][1][5][40] = 76, +- [0][1][6][40] = 16, +- [0][1][9][40] = 76, +- [0][1][8][40] = 42, +- [0][1][11][40] = 16, +- [0][1][2][42] = 76, +- [0][1][1][42] = 16, +- [0][1][3][42] = 127, +- [0][1][5][42] = 76, +- [0][1][6][42] = 16, +- [0][1][9][42] = 76, +- [0][1][8][42] = 42, +- [0][1][11][42] = 16, +- [0][1][2][44] = 76, +- [0][1][1][44] = 16, +- [0][1][3][44] = 127, +- [0][1][5][44] = 76, +- [0][1][6][44] = 16, +- [0][1][9][44] = 76, +- [0][1][8][44] = 42, +- [0][1][11][44] = 16, +- [0][1][2][46] = 76, +- [0][1][1][46] = 16, +- [0][1][3][46] = 127, +- [0][1][5][46] = 76, +- [0][1][6][46] = 16, +- [0][1][9][46] = 76, +- [0][1][8][46] = 42, +- [0][1][11][46] = 16, +- [1][0][2][0] = 62, +- [1][0][1][0] = 36, +- [1][0][3][0] = 36, +- [1][0][5][0] = 34, +- [1][0][6][0] = 36, +- [1][0][9][0] = 36, +- [1][0][8][0] = 30, +- [1][0][11][0] = 36, +- [1][0][2][2] = 62, +- [1][0][1][2] = 36, +- [1][0][3][2] = 36, +- [1][0][5][2] = 34, +- [1][0][6][2] = 36, +- [1][0][9][2] = 36, +- [1][0][8][2] = 30, +- [1][0][11][2] = 36, +- [1][0][2][4] = 62, +- [1][0][1][4] = 36, +- [1][0][3][4] = 36, +- [1][0][5][4] = 34, +- [1][0][6][4] = 36, +- [1][0][9][4] = 36, +- [1][0][8][4] = 30, +- [1][0][11][4] = 36, +- [1][0][2][6] = 62, +- [1][0][1][6] = 36, +- [1][0][3][6] = 36, +- [1][0][5][6] = 34, +- [1][0][6][6] = 36, +- [1][0][9][6] = 36, +- [1][0][8][6] = 30, +- [1][0][11][6] = 36, +- [1][0][2][8] = 62, +- [1][0][1][8] = 36, +- [1][0][3][8] = 36, +- [1][0][5][8] = 62, +- [1][0][6][8] = 36, +- [1][0][9][8] = 36, +- [1][0][8][8] = 54, +- [1][0][11][8] = 36, +- [1][0][2][10] = 62, +- [1][0][1][10] = 36, +- [1][0][3][10] = 36, +- [1][0][5][10] = 62, +- [1][0][6][10] = 36, +- [1][0][9][10] = 36, +- [1][0][8][10] = 54, +- [1][0][11][10] = 36, +- [1][0][2][12] = 62, +- [1][0][1][12] = 36, +- [1][0][3][12] = 36, +- [1][0][5][12] = 62, +- [1][0][6][12] = 36, +- [1][0][9][12] = 36, +- [1][0][8][12] = 54, +- [1][0][11][12] = 36, +- [1][0][2][14] = 62, +- [1][0][1][14] = 36, +- [1][0][3][14] = 36, +- [1][0][5][14] = 62, +- [1][0][6][14] = 36, +- [1][0][9][14] = 36, +- [1][0][8][14] = 54, +- [1][0][11][14] = 36, +- [1][0][2][15] = 62, +- [1][0][1][15] = 36, +- [1][0][3][15] = 58, +- [1][0][5][15] = 62, +- [1][0][6][15] = 36, +- [1][0][9][15] = 36, +- [1][0][8][15] = 54, +- [1][0][11][15] = 36, +- [1][0][2][17] = 62, +- [1][0][1][17] = 36, +- [1][0][3][17] = 58, +- [1][0][5][17] = 62, +- [1][0][6][17] = 36, +- [1][0][9][17] = 36, +- [1][0][8][17] = 54, +- [1][0][11][17] = 36, +- [1][0][2][19] = 62, +- [1][0][1][19] = 36, +- [1][0][3][19] = 58, +- [1][0][5][19] = 62, +- [1][0][6][19] = 36, +- [1][0][9][19] = 36, +- [1][0][8][19] = 54, +- [1][0][11][19] = 36, +- [1][0][2][21] = 62, +- [1][0][1][21] = 36, +- [1][0][3][21] = 58, +- [1][0][5][21] = 62, +- [1][0][6][21] = 36, +- [1][0][9][21] = 36, +- [1][0][8][21] = 54, +- [1][0][11][21] = 36, +- [1][0][2][23] = 62, +- [1][0][1][23] = 36, +- [1][0][3][23] = 58, +- [1][0][5][23] = 62, +- [1][0][6][23] = 36, +- [1][0][9][23] = 36, +- [1][0][8][23] = 54, +- [1][0][11][23] = 36, +- [1][0][2][25] = 62, +- [1][0][1][25] = 36, +- [1][0][3][25] = 58, +- [1][0][5][25] = 127, +- [1][0][6][25] = 36, +- [1][0][9][25] = 127, +- [1][0][8][25] = 54, +- [1][0][11][25] = 36, +- [1][0][2][27] = 62, +- [1][0][1][27] = 36, +- [1][0][3][27] = 58, +- [1][0][5][27] = 127, +- [1][0][6][27] = 36, +- [1][0][9][27] = 127, +- [1][0][8][27] = 54, +- [1][0][11][27] = 36, +- [1][0][2][29] = 62, +- [1][0][1][29] = 36, +- [1][0][3][29] = 58, +- [1][0][5][29] = 127, +- [1][0][6][29] = 36, +- [1][0][9][29] = 127, +- [1][0][8][29] = 54, +- [1][0][11][29] = 36, +- [1][0][2][31] = 62, +- [1][0][1][31] = 36, +- [1][0][3][31] = 58, +- [1][0][5][31] = 62, +- [1][0][6][31] = 36, +- [1][0][9][31] = 36, +- [1][0][8][31] = 54, +- [1][0][11][31] = 36, +- [1][0][2][33] = 62, +- [1][0][1][33] = 36, +- [1][0][3][33] = 58, +- [1][0][5][33] = 62, +- [1][0][6][33] = 36, +- [1][0][9][33] = 36, +- [1][0][8][33] = 54, +- [1][0][11][33] = 36, +- [1][0][2][35] = 62, +- [1][0][1][35] = 36, +- [1][0][3][35] = 58, +- [1][0][5][35] = 62, +- [1][0][6][35] = 36, +- [1][0][9][35] = 36, +- [1][0][8][35] = 54, +- [1][0][11][35] = 36, +- [1][0][2][37] = 56, +- [1][0][1][37] = 62, +- [1][0][3][37] = 127, +- [1][0][5][37] = 58, +- [1][0][6][37] = 62, +- [1][0][9][37] = 36, +- [1][0][8][37] = 62, +- [1][0][11][37] = 54, +- [1][0][2][38] = 76, +- [1][0][1][38] = 28, +- [1][0][3][38] = 127, +- [1][0][5][38] = 76, +- [1][0][6][38] = 28, +- [1][0][9][38] = 76, +- [1][0][8][38] = 54, +- [1][0][11][38] = 28, +- [1][0][2][40] = 76, +- [1][0][1][40] = 28, +- [1][0][3][40] = 127, +- [1][0][5][40] = 76, +- [1][0][6][40] = 28, +- [1][0][9][40] = 76, +- [1][0][8][40] = 54, +- [1][0][11][40] = 28, +- [1][0][2][42] = 76, +- [1][0][1][42] = 28, +- [1][0][3][42] = 127, +- [1][0][5][42] = 76, +- [1][0][6][42] = 28, +- [1][0][9][42] = 76, +- [1][0][8][42] = 54, +- [1][0][11][42] = 28, +- [1][0][2][44] = 76, +- [1][0][1][44] = 28, +- [1][0][3][44] = 127, +- [1][0][5][44] = 76, +- [1][0][6][44] = 28, +- [1][0][9][44] = 76, +- [1][0][8][44] = 54, +- [1][0][11][44] = 28, +- [1][0][2][46] = 76, +- [1][0][1][46] = 28, +- [1][0][3][46] = 127, +- [1][0][5][46] = 76, +- [1][0][6][46] = 28, +- [1][0][9][46] = 76, +- [1][0][8][46] = 54, +- [1][0][11][46] = 28, +- [1][1][2][0] = 46, +- [1][1][1][0] = 22, +- [1][1][3][0] = 24, +- [1][1][5][0] = 18, +- [1][1][6][0] = 22, +- [1][1][9][0] = 22, +- [1][1][8][0] = 18, +- [1][1][11][0] = 22, +- [1][1][2][2] = 46, +- [1][1][1][2] = 22, +- [1][1][3][2] = 24, +- [1][1][5][2] = 18, +- [1][1][6][2] = 22, +- [1][1][9][2] = 22, +- [1][1][8][2] = 18, +- [1][1][11][2] = 22, +- [1][1][2][4] = 46, +- [1][1][1][4] = 22, +- [1][1][3][4] = 24, +- [1][1][5][4] = 18, +- [1][1][6][4] = 22, +- [1][1][9][4] = 22, +- [1][1][8][4] = 18, +- [1][1][11][4] = 22, +- [1][1][2][6] = 46, +- [1][1][1][6] = 22, +- [1][1][3][6] = 24, +- [1][1][5][6] = 18, +- [1][1][6][6] = 22, +- [1][1][9][6] = 22, +- [1][1][8][6] = 18, +- [1][1][11][6] = 22, +- [1][1][2][8] = 46, +- [1][1][1][8] = 22, +- [1][1][3][8] = 24, +- [1][1][5][8] = 46, +- [1][1][6][8] = 22, +- [1][1][9][8] = 22, +- [1][1][8][8] = 42, +- [1][1][11][8] = 22, +- [1][1][2][10] = 46, +- [1][1][1][10] = 22, +- [1][1][3][10] = 24, +- [1][1][5][10] = 46, +- [1][1][6][10] = 22, +- [1][1][9][10] = 22, +- [1][1][8][10] = 42, +- [1][1][11][10] = 22, +- [1][1][2][12] = 46, +- [1][1][1][12] = 22, +- [1][1][3][12] = 24, +- [1][1][5][12] = 46, +- [1][1][6][12] = 22, +- [1][1][9][12] = 22, +- [1][1][8][12] = 42, +- [1][1][11][12] = 22, +- [1][1][2][14] = 46, +- [1][1][1][14] = 22, +- [1][1][3][14] = 24, +- [1][1][5][14] = 46, +- [1][1][6][14] = 22, +- [1][1][9][14] = 22, +- [1][1][8][14] = 42, +- [1][1][11][14] = 22, +- [1][1][2][15] = 46, +- [1][1][1][15] = 22, +- [1][1][3][15] = 46, +- [1][1][5][15] = 46, +- [1][1][6][15] = 22, +- [1][1][9][15] = 22, +- [1][1][8][15] = 42, +- [1][1][11][15] = 22, +- [1][1][2][17] = 46, +- [1][1][1][17] = 22, +- [1][1][3][17] = 46, +- [1][1][5][17] = 46, +- [1][1][6][17] = 22, +- [1][1][9][17] = 22, +- [1][1][8][17] = 42, +- [1][1][11][17] = 22, +- [1][1][2][19] = 46, +- [1][1][1][19] = 22, +- [1][1][3][19] = 46, +- [1][1][5][19] = 46, +- [1][1][6][19] = 22, +- [1][1][9][19] = 22, +- [1][1][8][19] = 42, +- [1][1][11][19] = 22, +- [1][1][2][21] = 46, +- [1][1][1][21] = 22, +- [1][1][3][21] = 46, +- [1][1][5][21] = 46, +- [1][1][6][21] = 22, +- [1][1][9][21] = 22, +- [1][1][8][21] = 42, +- [1][1][11][21] = 22, +- [1][1][2][23] = 46, +- [1][1][1][23] = 22, +- [1][1][3][23] = 46, +- [1][1][5][23] = 46, +- [1][1][6][23] = 22, +- [1][1][9][23] = 22, +- [1][1][8][23] = 42, +- [1][1][11][23] = 22, +- [1][1][2][25] = 46, +- [1][1][1][25] = 22, +- [1][1][3][25] = 46, +- [1][1][5][25] = 127, +- [1][1][6][25] = 22, +- [1][1][9][25] = 127, +- [1][1][8][25] = 42, +- [1][1][11][25] = 22, +- [1][1][2][27] = 46, +- [1][1][1][27] = 22, +- [1][1][3][27] = 46, +- [1][1][5][27] = 127, +- [1][1][6][27] = 22, +- [1][1][9][27] = 127, +- [1][1][8][27] = 42, +- [1][1][11][27] = 22, +- [1][1][2][29] = 46, +- [1][1][1][29] = 22, +- [1][1][3][29] = 46, +- [1][1][5][29] = 127, +- [1][1][6][29] = 22, +- [1][1][9][29] = 127, +- [1][1][8][29] = 42, +- [1][1][11][29] = 22, +- [1][1][2][31] = 46, +- [1][1][1][31] = 22, +- [1][1][3][31] = 46, +- [1][1][5][31] = 46, +- [1][1][6][31] = 22, +- [1][1][9][31] = 22, +- [1][1][8][31] = 42, +- [1][1][11][31] = 22, +- [1][1][2][33] = 46, +- [1][1][1][33] = 22, +- [1][1][3][33] = 46, +- [1][1][5][33] = 46, +- [1][1][6][33] = 22, +- [1][1][9][33] = 22, +- [1][1][8][33] = 42, +- [1][1][11][33] = 22, +- [1][1][2][35] = 46, +- [1][1][1][35] = 22, +- [1][1][3][35] = 46, +- [1][1][5][35] = 46, +- [1][1][6][35] = 22, +- [1][1][9][35] = 22, +- [1][1][8][35] = 42, +- [1][1][11][35] = 22, +- [1][1][2][37] = 46, +- [1][1][1][37] = 127, +- [1][1][3][37] = 46, +- [1][1][5][37] = 46, +- [1][1][6][37] = 22, +- [1][1][9][37] = 50, +- [1][1][8][37] = 42, +- [1][1][11][37] = 127, +- [1][1][2][38] = 74, +- [1][1][1][38] = 16, +- [1][1][3][38] = 127, +- [1][1][5][38] = 74, +- [1][1][6][38] = 16, +- [1][1][9][38] = 76, +- [1][1][8][38] = 42, +- [1][1][11][38] = 16, +- [1][1][2][40] = 76, +- [1][1][1][40] = 16, +- [1][1][3][40] = 127, +- [1][1][5][40] = 76, +- [1][1][6][40] = 16, +- [1][1][9][40] = 76, +- [1][1][8][40] = 42, +- [1][1][11][40] = 16, +- [1][1][2][42] = 76, +- [1][1][1][42] = 16, +- [1][1][3][42] = 127, +- [1][1][5][42] = 76, +- [1][1][6][42] = 16, +- [1][1][9][42] = 76, +- [1][1][8][42] = 42, +- [1][1][11][42] = 16, +- [1][1][2][44] = 76, +- [1][1][1][44] = 16, +- [1][1][3][44] = 127, +- [1][1][5][44] = 76, +- [1][1][6][44] = 16, +- [1][1][9][44] = 76, +- [1][1][8][44] = 42, +- [1][1][11][44] = 16, +- [1][1][2][46] = 76, +- [1][1][1][46] = 16, +- [1][1][3][46] = 127, +- [1][1][5][46] = 76, +- [1][1][6][46] = 16, +- [1][1][9][46] = 76, +- [1][1][8][46] = 42, +- [1][1][11][46] = 16, +- [2][0][2][0] = 74, +- [2][0][1][0] = 46, +- [2][0][3][0] = 50, +- [2][0][5][0] = 46, +- [2][0][6][0] = 46, +- [2][0][9][0] = 46, +- [2][0][8][0] = 30, +- [2][0][11][0] = 46, +- [2][0][2][2] = 74, +- [2][0][1][2] = 46, +- [2][0][3][2] = 50, +- [2][0][5][2] = 46, +- [2][0][6][2] = 46, +- [2][0][9][2] = 46, +- [2][0][8][2] = 30, +- [2][0][11][2] = 46, +- [2][0][2][4] = 74, +- [2][0][1][4] = 46, +- [2][0][3][4] = 50, +- [2][0][5][4] = 46, +- [2][0][6][4] = 46, +- [2][0][9][4] = 46, +- [2][0][8][4] = 30, +- [2][0][11][4] = 46, +- [2][0][2][6] = 74, +- [2][0][1][6] = 46, +- [2][0][3][6] = 50, +- [2][0][5][6] = 46, +- [2][0][6][6] = 46, +- [2][0][9][6] = 46, +- [2][0][8][6] = 30, +- [2][0][11][6] = 46, +- [2][0][2][8] = 74, +- [2][0][1][8] = 46, +- [2][0][3][8] = 50, +- [2][0][5][8] = 66, +- [2][0][6][8] = 46, +- [2][0][9][8] = 46, +- [2][0][8][8] = 54, +- [2][0][11][8] = 46, +- [2][0][2][10] = 74, +- [2][0][1][10] = 46, +- [2][0][3][10] = 50, +- [2][0][5][10] = 66, +- [2][0][6][10] = 46, +- [2][0][9][10] = 46, +- [2][0][8][10] = 54, +- [2][0][11][10] = 46, +- [2][0][2][12] = 74, +- [2][0][1][12] = 46, +- [2][0][3][12] = 50, +- [2][0][5][12] = 66, +- [2][0][6][12] = 46, +- [2][0][9][12] = 46, +- [2][0][8][12] = 54, +- [2][0][11][12] = 46, +- [2][0][2][14] = 74, +- [2][0][1][14] = 46, +- [2][0][3][14] = 50, +- [2][0][5][14] = 66, +- [2][0][6][14] = 46, +- [2][0][9][14] = 46, +- [2][0][8][14] = 54, +- [2][0][11][14] = 46, +- [2][0][2][15] = 74, +- [2][0][1][15] = 46, +- [2][0][3][15] = 70, +- [2][0][5][15] = 74, +- [2][0][6][15] = 46, +- [2][0][9][15] = 46, +- [2][0][8][15] = 54, +- [2][0][11][15] = 46, +- [2][0][2][17] = 74, +- [2][0][1][17] = 46, +- [2][0][3][17] = 70, +- [2][0][5][17] = 74, +- [2][0][6][17] = 46, +- [2][0][9][17] = 46, +- [2][0][8][17] = 54, +- [2][0][11][17] = 46, +- [2][0][2][19] = 74, +- [2][0][1][19] = 46, +- [2][0][3][19] = 70, +- [2][0][5][19] = 74, +- [2][0][6][19] = 46, +- [2][0][9][19] = 46, +- [2][0][8][19] = 54, +- [2][0][11][19] = 46, +- [2][0][2][21] = 74, +- [2][0][1][21] = 46, +- [2][0][3][21] = 70, +- [2][0][5][21] = 74, +- [2][0][6][21] = 46, +- [2][0][9][21] = 46, +- [2][0][8][21] = 54, +- [2][0][11][21] = 46, +- [2][0][2][23] = 74, +- [2][0][1][23] = 46, +- [2][0][3][23] = 70, +- [2][0][5][23] = 74, +- [2][0][6][23] = 46, +- [2][0][9][23] = 46, +- [2][0][8][23] = 54, +- [2][0][11][23] = 46, +- [2][0][2][25] = 74, +- [2][0][1][25] = 46, +- [2][0][3][25] = 70, +- [2][0][5][25] = 127, +- [2][0][6][25] = 46, +- [2][0][9][25] = 127, +- [2][0][8][25] = 54, +- [2][0][11][25] = 46, +- [2][0][2][27] = 74, +- [2][0][1][27] = 46, +- [2][0][3][27] = 70, +- [2][0][5][27] = 127, +- [2][0][6][27] = 46, +- [2][0][9][27] = 127, +- [2][0][8][27] = 54, +- [2][0][11][27] = 46, +- [2][0][2][29] = 74, +- [2][0][1][29] = 46, +- [2][0][3][29] = 70, +- [2][0][5][29] = 127, +- [2][0][6][29] = 46, +- [2][0][9][29] = 127, +- [2][0][8][29] = 54, +- [2][0][11][29] = 46, +- [2][0][2][31] = 74, +- [2][0][1][31] = 46, +- [2][0][3][31] = 70, +- [2][0][5][31] = 74, +- [2][0][6][31] = 46, +- [2][0][9][31] = 46, +- [2][0][8][31] = 54, +- [2][0][11][31] = 46, +- [2][0][2][33] = 74, +- [2][0][1][33] = 46, +- [2][0][3][33] = 70, +- [2][0][5][33] = 74, +- [2][0][6][33] = 46, +- [2][0][9][33] = 46, +- [2][0][8][33] = 54, +- [2][0][11][33] = 46, +- [2][0][2][35] = 74, +- [2][0][1][35] = 46, +- [2][0][3][35] = 70, +- [2][0][5][35] = 74, +- [2][0][6][35] = 46, +- [2][0][9][35] = 46, +- [2][0][8][35] = 54, +- [2][0][11][35] = 46, +- [2][0][2][37] = 74, +- [2][0][1][37] = 127, +- [2][0][3][37] = 70, +- [2][0][5][37] = 74, +- [2][0][6][37] = 46, +- [2][0][9][37] = 74, +- [2][0][8][37] = 54, +- [2][0][11][37] = 127, +- [2][0][2][38] = 76, +- [2][0][1][38] = 28, +- [2][0][3][38] = 127, +- [2][0][5][38] = 76, +- [2][0][6][38] = 28, +- [2][0][9][38] = 76, +- [2][0][8][38] = 54, +- [2][0][11][38] = 28, +- [2][0][2][40] = 76, +- [2][0][1][40] = 28, +- [2][0][3][40] = 127, +- [2][0][5][40] = 76, +- [2][0][6][40] = 28, +- [2][0][9][40] = 76, +- [2][0][8][40] = 54, +- [2][0][11][40] = 28, +- [2][0][2][42] = 76, +- [2][0][1][42] = 28, +- [2][0][3][42] = 127, +- [2][0][5][42] = 76, +- [2][0][6][42] = 28, +- [2][0][9][42] = 76, +- [2][0][8][42] = 54, +- [2][0][11][42] = 28, +- [2][0][2][44] = 76, +- [2][0][1][44] = 28, +- [2][0][3][44] = 127, +- [2][0][5][44] = 76, +- [2][0][6][44] = 28, +- [2][0][9][44] = 76, +- [2][0][8][44] = 54, +- [2][0][11][44] = 28, +- [2][0][2][46] = 76, +- [2][0][1][46] = 28, +- [2][0][3][46] = 127, +- [2][0][5][46] = 76, +- [2][0][6][46] = 28, +- [2][0][9][46] = 76, +- [2][0][8][46] = 54, +- [2][0][11][46] = 28, +- [2][1][2][0] = 58, +- [2][1][1][0] = 32, +- [2][1][3][0] = 38, +- [2][1][5][0] = 30, +- [2][1][6][0] = 32, +- [2][1][9][0] = 32, +- [2][1][8][0] = 18, +- [2][1][11][0] = 32, +- [2][1][2][2] = 58, +- [2][1][1][2] = 32, +- [2][1][3][2] = 38, +- [2][1][5][2] = 30, +- [2][1][6][2] = 32, +- [2][1][9][2] = 32, +- [2][1][8][2] = 18, +- [2][1][11][2] = 32, +- [2][1][2][4] = 58, +- [2][1][1][4] = 32, +- [2][1][3][4] = 38, +- [2][1][5][4] = 30, +- [2][1][6][4] = 32, +- [2][1][9][4] = 32, +- [2][1][8][4] = 18, +- [2][1][11][4] = 32, +- [2][1][2][6] = 58, +- [2][1][1][6] = 32, +- [2][1][3][6] = 38, +- [2][1][5][6] = 30, +- [2][1][6][6] = 32, +- [2][1][9][6] = 32, +- [2][1][8][6] = 18, +- [2][1][11][6] = 32, +- [2][1][2][8] = 58, +- [2][1][1][8] = 32, +- [2][1][3][8] = 38, +- [2][1][5][8] = 52, +- [2][1][6][8] = 32, +- [2][1][9][8] = 32, +- [2][1][8][8] = 42, +- [2][1][11][8] = 32, +- [2][1][2][10] = 58, +- [2][1][1][10] = 32, +- [2][1][3][10] = 38, +- [2][1][5][10] = 52, +- [2][1][6][10] = 32, +- [2][1][9][10] = 32, +- [2][1][8][10] = 42, +- [2][1][11][10] = 32, +- [2][1][2][12] = 58, +- [2][1][1][12] = 32, +- [2][1][3][12] = 38, +- [2][1][5][12] = 52, +- [2][1][6][12] = 32, +- [2][1][9][12] = 32, +- [2][1][8][12] = 42, +- [2][1][11][12] = 32, +- [2][1][2][14] = 58, +- [2][1][1][14] = 32, +- [2][1][3][14] = 38, +- [2][1][5][14] = 52, +- [2][1][6][14] = 32, +- [2][1][9][14] = 32, +- [2][1][8][14] = 42, +- [2][1][11][14] = 32, +- [2][1][2][15] = 58, +- [2][1][1][15] = 32, +- [2][1][3][15] = 58, +- [2][1][5][15] = 58, +- [2][1][6][15] = 32, +- [2][1][9][15] = 32, +- [2][1][8][15] = 42, +- [2][1][11][15] = 32, +- [2][1][2][17] = 58, +- [2][1][1][17] = 32, +- [2][1][3][17] = 58, +- [2][1][5][17] = 58, +- [2][1][6][17] = 32, +- [2][1][9][17] = 32, +- [2][1][8][17] = 42, +- [2][1][11][17] = 32, +- [2][1][2][19] = 58, +- [2][1][1][19] = 32, +- [2][1][3][19] = 58, +- [2][1][5][19] = 58, +- [2][1][6][19] = 32, +- [2][1][9][19] = 32, +- [2][1][8][19] = 42, +- [2][1][11][19] = 32, +- [2][1][2][21] = 58, +- [2][1][1][21] = 32, +- [2][1][3][21] = 58, +- [2][1][5][21] = 58, +- [2][1][6][21] = 32, +- [2][1][9][21] = 32, +- [2][1][8][21] = 42, +- [2][1][11][21] = 32, +- [2][1][2][23] = 58, +- [2][1][1][23] = 32, +- [2][1][3][23] = 58, +- [2][1][5][23] = 58, +- [2][1][6][23] = 32, +- [2][1][9][23] = 32, +- [2][1][8][23] = 42, +- [2][1][11][23] = 32, +- [2][1][2][25] = 58, +- [2][1][1][25] = 32, +- [2][1][3][25] = 58, +- [2][1][5][25] = 127, +- [2][1][6][25] = 32, +- [2][1][9][25] = 127, +- [2][1][8][25] = 42, +- [2][1][11][25] = 32, +- [2][1][2][27] = 58, +- [2][1][1][27] = 32, +- [2][1][3][27] = 58, +- [2][1][5][27] = 127, +- [2][1][6][27] = 32, +- [2][1][9][27] = 127, +- [2][1][8][27] = 42, +- [2][1][11][27] = 32, +- [2][1][2][29] = 58, +- [2][1][1][29] = 32, +- [2][1][3][29] = 58, +- [2][1][5][29] = 127, +- [2][1][6][29] = 32, +- [2][1][9][29] = 127, +- [2][1][8][29] = 42, +- [2][1][11][29] = 32, +- [2][1][2][31] = 58, +- [2][1][1][31] = 32, +- [2][1][3][31] = 58, +- [2][1][5][31] = 58, +- [2][1][6][31] = 32, +- [2][1][9][31] = 32, +- [2][1][8][31] = 42, +- [2][1][11][31] = 32, +- [2][1][2][33] = 58, +- [2][1][1][33] = 32, +- [2][1][3][33] = 58, +- [2][1][5][33] = 58, +- [2][1][6][33] = 32, +- [2][1][9][33] = 32, +- [2][1][8][33] = 42, +- [2][1][11][33] = 32, +- [2][1][2][35] = 58, +- [2][1][1][35] = 32, +- [2][1][3][35] = 58, +- [2][1][5][35] = 58, +- [2][1][6][35] = 32, +- [2][1][9][35] = 32, +- [2][1][8][35] = 42, +- [2][1][11][35] = 32, +- [2][1][2][37] = 58, +- [2][1][1][37] = 127, +- [2][1][3][37] = 58, +- [2][1][5][37] = 58, +- [2][1][6][37] = 32, +- [2][1][9][37] = 62, +- [2][1][8][37] = 42, +- [2][1][11][37] = 127, +- [2][1][2][38] = 76, +- [2][1][1][38] = 16, +- [2][1][3][38] = 127, +- [2][1][5][38] = 76, +- [2][1][6][38] = 16, +- [2][1][9][38] = 76, +- [2][1][8][38] = 42, +- [2][1][11][38] = 16, +- [2][1][2][40] = 76, +- [2][1][1][40] = 16, +- [2][1][3][40] = 127, +- [2][1][5][40] = 76, +- [2][1][6][40] = 16, +- [2][1][9][40] = 76, +- [2][1][8][40] = 42, +- [2][1][11][40] = 16, +- [2][1][2][42] = 76, +- [2][1][1][42] = 16, +- [2][1][3][42] = 127, +- [2][1][5][42] = 76, +- [2][1][6][42] = 16, +- [2][1][9][42] = 76, +- [2][1][8][42] = 42, +- [2][1][11][42] = 16, +- [2][1][2][44] = 76, +- [2][1][1][44] = 16, +- [2][1][3][44] = 127, +- [2][1][5][44] = 76, +- [2][1][6][44] = 16, +- [2][1][9][44] = 76, +- [2][1][8][44] = 42, +- [2][1][11][44] = 16, +- [2][1][2][46] = 76, +- [2][1][1][46] = 16, +- [2][1][3][46] = 127, +- [2][1][5][46] = 76, +- [2][1][6][46] = 16, +- [2][1][9][46] = 76, +- [2][1][8][46] = 42, +- [2][1][11][46] = 16, ++ [0][0][RTW89_WW][0] = 22, ++ [0][0][RTW89_WW][2] = 22, ++ [0][0][RTW89_WW][4] = 22, ++ [0][0][RTW89_WW][6] = 22, ++ [0][0][RTW89_WW][8] = 24, ++ [0][0][RTW89_WW][10] = 24, ++ [0][0][RTW89_WW][12] = 24, ++ [0][0][RTW89_WW][14] = 24, ++ [0][0][RTW89_WW][15] = 24, ++ [0][0][RTW89_WW][17] = 24, ++ [0][0][RTW89_WW][19] = 24, ++ [0][0][RTW89_WW][21] = 24, ++ [0][0][RTW89_WW][23] = 24, ++ [0][0][RTW89_WW][25] = 24, ++ [0][0][RTW89_WW][27] = 24, ++ [0][0][RTW89_WW][29] = 24, ++ [0][0][RTW89_WW][31] = 24, ++ [0][0][RTW89_WW][33] = 24, ++ [0][0][RTW89_WW][35] = 24, ++ [0][0][RTW89_WW][37] = 24, ++ [0][0][RTW89_WW][38] = 28, ++ [0][0][RTW89_WW][40] = 28, ++ [0][0][RTW89_WW][42] = 28, ++ [0][0][RTW89_WW][44] = 28, ++ [0][0][RTW89_WW][46] = 28, ++ [0][1][RTW89_WW][0] = 8, ++ [0][1][RTW89_WW][2] = 8, ++ [0][1][RTW89_WW][4] = 8, ++ [0][1][RTW89_WW][6] = 8, ++ [0][1][RTW89_WW][8] = 12, ++ [0][1][RTW89_WW][10] = 12, ++ [0][1][RTW89_WW][12] = 12, ++ [0][1][RTW89_WW][14] = 12, ++ [0][1][RTW89_WW][15] = 12, ++ [0][1][RTW89_WW][17] = 12, ++ [0][1][RTW89_WW][19] = 12, ++ [0][1][RTW89_WW][21] = 12, ++ [0][1][RTW89_WW][23] = 12, ++ [0][1][RTW89_WW][25] = 12, ++ [0][1][RTW89_WW][27] = 12, ++ [0][1][RTW89_WW][29] = 12, ++ [0][1][RTW89_WW][31] = 12, ++ [0][1][RTW89_WW][33] = 12, ++ [0][1][RTW89_WW][35] = 12, ++ [0][1][RTW89_WW][37] = 12, ++ [0][1][RTW89_WW][38] = 16, ++ [0][1][RTW89_WW][40] = 16, ++ [0][1][RTW89_WW][42] = 16, ++ [0][1][RTW89_WW][44] = 16, ++ [0][1][RTW89_WW][46] = 16, ++ [1][0][RTW89_WW][0] = 30, ++ [1][0][RTW89_WW][2] = 30, ++ [1][0][RTW89_WW][4] = 30, ++ [1][0][RTW89_WW][6] = 30, ++ [1][0][RTW89_WW][8] = 36, ++ [1][0][RTW89_WW][10] = 36, ++ [1][0][RTW89_WW][12] = 36, ++ [1][0][RTW89_WW][14] = 36, ++ [1][0][RTW89_WW][15] = 36, ++ [1][0][RTW89_WW][17] = 36, ++ [1][0][RTW89_WW][19] = 36, ++ [1][0][RTW89_WW][21] = 36, ++ [1][0][RTW89_WW][23] = 36, ++ [1][0][RTW89_WW][25] = 36, ++ [1][0][RTW89_WW][27] = 36, ++ [1][0][RTW89_WW][29] = 36, ++ [1][0][RTW89_WW][31] = 36, ++ [1][0][RTW89_WW][33] = 36, ++ [1][0][RTW89_WW][35] = 36, ++ [1][0][RTW89_WW][37] = 36, ++ [1][0][RTW89_WW][38] = 28, ++ [1][0][RTW89_WW][40] = 28, ++ [1][0][RTW89_WW][42] = 28, ++ [1][0][RTW89_WW][44] = 28, ++ [1][0][RTW89_WW][46] = 28, ++ [1][1][RTW89_WW][0] = 18, ++ [1][1][RTW89_WW][2] = 18, ++ [1][1][RTW89_WW][4] = 18, ++ [1][1][RTW89_WW][6] = 18, ++ [1][1][RTW89_WW][8] = 22, ++ [1][1][RTW89_WW][10] = 22, ++ [1][1][RTW89_WW][12] = 22, ++ [1][1][RTW89_WW][14] = 22, ++ [1][1][RTW89_WW][15] = 22, ++ [1][1][RTW89_WW][17] = 22, ++ [1][1][RTW89_WW][19] = 22, ++ [1][1][RTW89_WW][21] = 22, ++ [1][1][RTW89_WW][23] = 22, ++ [1][1][RTW89_WW][25] = 22, ++ [1][1][RTW89_WW][27] = 22, ++ [1][1][RTW89_WW][29] = 22, ++ [1][1][RTW89_WW][31] = 22, ++ [1][1][RTW89_WW][33] = 22, ++ [1][1][RTW89_WW][35] = 22, ++ [1][1][RTW89_WW][37] = 22, ++ [1][1][RTW89_WW][38] = 16, ++ [1][1][RTW89_WW][40] = 16, ++ [1][1][RTW89_WW][42] = 16, ++ [1][1][RTW89_WW][44] = 16, ++ [1][1][RTW89_WW][46] = 16, ++ [2][0][RTW89_WW][0] = 30, ++ [2][0][RTW89_WW][2] = 30, ++ [2][0][RTW89_WW][4] = 30, ++ [2][0][RTW89_WW][6] = 30, ++ [2][0][RTW89_WW][8] = 46, ++ [2][0][RTW89_WW][10] = 46, ++ [2][0][RTW89_WW][12] = 46, ++ [2][0][RTW89_WW][14] = 46, ++ [2][0][RTW89_WW][15] = 46, ++ [2][0][RTW89_WW][17] = 46, ++ [2][0][RTW89_WW][19] = 46, ++ [2][0][RTW89_WW][21] = 46, ++ [2][0][RTW89_WW][23] = 46, ++ [2][0][RTW89_WW][25] = 46, ++ [2][0][RTW89_WW][27] = 46, ++ [2][0][RTW89_WW][29] = 46, ++ [2][0][RTW89_WW][31] = 46, ++ [2][0][RTW89_WW][33] = 46, ++ [2][0][RTW89_WW][35] = 46, ++ [2][0][RTW89_WW][37] = 46, ++ [2][0][RTW89_WW][38] = 28, ++ [2][0][RTW89_WW][40] = 28, ++ [2][0][RTW89_WW][42] = 28, ++ [2][0][RTW89_WW][44] = 28, ++ [2][0][RTW89_WW][46] = 28, ++ [2][1][RTW89_WW][0] = 18, ++ [2][1][RTW89_WW][2] = 18, ++ [2][1][RTW89_WW][4] = 18, ++ [2][1][RTW89_WW][6] = 18, ++ [2][1][RTW89_WW][8] = 32, ++ [2][1][RTW89_WW][10] = 32, ++ [2][1][RTW89_WW][12] = 32, ++ [2][1][RTW89_WW][14] = 32, ++ [2][1][RTW89_WW][15] = 32, ++ [2][1][RTW89_WW][17] = 32, ++ [2][1][RTW89_WW][19] = 32, ++ [2][1][RTW89_WW][21] = 32, ++ [2][1][RTW89_WW][23] = 32, ++ [2][1][RTW89_WW][25] = 32, ++ [2][1][RTW89_WW][27] = 32, ++ [2][1][RTW89_WW][29] = 32, ++ [2][1][RTW89_WW][31] = 32, ++ [2][1][RTW89_WW][33] = 32, ++ [2][1][RTW89_WW][35] = 32, ++ [2][1][RTW89_WW][37] = 32, ++ [2][1][RTW89_WW][38] = 16, ++ [2][1][RTW89_WW][40] = 16, ++ [2][1][RTW89_WW][42] = 16, ++ [2][1][RTW89_WW][44] = 16, ++ [2][1][RTW89_WW][46] = 16, ++ [0][0][RTW89_FCC][0] = 48, ++ [0][0][RTW89_ETSI][0] = 24, ++ [0][0][RTW89_MKK][0] = 26, ++ [0][0][RTW89_IC][0] = 22, ++ [0][0][RTW89_KCC][0] = 24, ++ [0][0][RTW89_ACMA][0] = 24, ++ [0][0][RTW89_CHILE][0] = 30, ++ [0][0][RTW89_UKRAINE][0] = 24, ++ [0][0][RTW89_FCC][2] = 48, ++ [0][0][RTW89_ETSI][2] = 24, ++ [0][0][RTW89_MKK][2] = 26, ++ [0][0][RTW89_IC][2] = 22, ++ [0][0][RTW89_KCC][2] = 24, ++ [0][0][RTW89_ACMA][2] = 24, ++ [0][0][RTW89_CHILE][2] = 30, ++ [0][0][RTW89_UKRAINE][2] = 24, ++ [0][0][RTW89_FCC][4] = 48, ++ [0][0][RTW89_ETSI][4] = 24, ++ [0][0][RTW89_MKK][4] = 26, ++ [0][0][RTW89_IC][4] = 22, ++ [0][0][RTW89_KCC][4] = 24, ++ [0][0][RTW89_ACMA][4] = 24, ++ [0][0][RTW89_CHILE][4] = 30, ++ [0][0][RTW89_UKRAINE][4] = 24, ++ [0][0][RTW89_FCC][6] = 48, ++ [0][0][RTW89_ETSI][6] = 24, ++ [0][0][RTW89_MKK][6] = 26, ++ [0][0][RTW89_IC][6] = 22, ++ [0][0][RTW89_KCC][6] = 24, ++ [0][0][RTW89_ACMA][6] = 24, ++ [0][0][RTW89_CHILE][6] = 30, ++ [0][0][RTW89_UKRAINE][6] = 24, ++ [0][0][RTW89_FCC][8] = 48, ++ [0][0][RTW89_ETSI][8] = 24, ++ [0][0][RTW89_MKK][8] = 26, ++ [0][0][RTW89_IC][8] = 48, ++ [0][0][RTW89_KCC][8] = 24, ++ [0][0][RTW89_ACMA][8] = 24, ++ [0][0][RTW89_CHILE][8] = 54, ++ [0][0][RTW89_UKRAINE][8] = 24, ++ [0][0][RTW89_FCC][10] = 48, ++ [0][0][RTW89_ETSI][10] = 24, ++ [0][0][RTW89_MKK][10] = 26, ++ [0][0][RTW89_IC][10] = 48, ++ [0][0][RTW89_KCC][10] = 24, ++ [0][0][RTW89_ACMA][10] = 24, ++ [0][0][RTW89_CHILE][10] = 54, ++ [0][0][RTW89_UKRAINE][10] = 24, ++ [0][0][RTW89_FCC][12] = 48, ++ [0][0][RTW89_ETSI][12] = 24, ++ [0][0][RTW89_MKK][12] = 26, ++ [0][0][RTW89_IC][12] = 48, ++ [0][0][RTW89_KCC][12] = 24, ++ [0][0][RTW89_ACMA][12] = 24, ++ [0][0][RTW89_CHILE][12] = 54, ++ [0][0][RTW89_UKRAINE][12] = 24, ++ [0][0][RTW89_FCC][14] = 48, ++ [0][0][RTW89_ETSI][14] = 24, ++ [0][0][RTW89_MKK][14] = 26, ++ [0][0][RTW89_IC][14] = 48, ++ [0][0][RTW89_KCC][14] = 24, ++ [0][0][RTW89_ACMA][14] = 24, ++ [0][0][RTW89_CHILE][14] = 54, ++ [0][0][RTW89_UKRAINE][14] = 24, ++ [0][0][RTW89_FCC][15] = 48, ++ [0][0][RTW89_ETSI][15] = 24, ++ [0][0][RTW89_MKK][15] = 44, ++ [0][0][RTW89_IC][15] = 48, ++ [0][0][RTW89_KCC][15] = 24, ++ [0][0][RTW89_ACMA][15] = 24, ++ [0][0][RTW89_CHILE][15] = 54, ++ [0][0][RTW89_UKRAINE][15] = 24, ++ [0][0][RTW89_FCC][17] = 48, ++ [0][0][RTW89_ETSI][17] = 24, ++ [0][0][RTW89_MKK][17] = 44, ++ [0][0][RTW89_IC][17] = 48, ++ [0][0][RTW89_KCC][17] = 24, ++ [0][0][RTW89_ACMA][17] = 24, ++ [0][0][RTW89_CHILE][17] = 54, ++ [0][0][RTW89_UKRAINE][17] = 24, ++ [0][0][RTW89_FCC][19] = 48, ++ [0][0][RTW89_ETSI][19] = 24, ++ [0][0][RTW89_MKK][19] = 44, ++ [0][0][RTW89_IC][19] = 48, ++ [0][0][RTW89_KCC][19] = 24, ++ [0][0][RTW89_ACMA][19] = 24, ++ [0][0][RTW89_CHILE][19] = 54, ++ [0][0][RTW89_UKRAINE][19] = 24, ++ [0][0][RTW89_FCC][21] = 48, ++ [0][0][RTW89_ETSI][21] = 24, ++ [0][0][RTW89_MKK][21] = 44, ++ [0][0][RTW89_IC][21] = 48, ++ [0][0][RTW89_KCC][21] = 24, ++ [0][0][RTW89_ACMA][21] = 24, ++ [0][0][RTW89_CHILE][21] = 54, ++ [0][0][RTW89_UKRAINE][21] = 24, ++ [0][0][RTW89_FCC][23] = 48, ++ [0][0][RTW89_ETSI][23] = 24, ++ [0][0][RTW89_MKK][23] = 44, ++ [0][0][RTW89_IC][23] = 48, ++ [0][0][RTW89_KCC][23] = 24, ++ [0][0][RTW89_ACMA][23] = 24, ++ [0][0][RTW89_CHILE][23] = 54, ++ [0][0][RTW89_UKRAINE][23] = 24, ++ [0][0][RTW89_FCC][25] = 48, ++ [0][0][RTW89_ETSI][25] = 24, ++ [0][0][RTW89_MKK][25] = 44, ++ [0][0][RTW89_IC][25] = 127, ++ [0][0][RTW89_KCC][25] = 24, ++ [0][0][RTW89_ACMA][25] = 127, ++ [0][0][RTW89_CHILE][25] = 54, ++ [0][0][RTW89_UKRAINE][25] = 24, ++ [0][0][RTW89_FCC][27] = 48, ++ [0][0][RTW89_ETSI][27] = 24, ++ [0][0][RTW89_MKK][27] = 44, ++ [0][0][RTW89_IC][27] = 127, ++ [0][0][RTW89_KCC][27] = 24, ++ [0][0][RTW89_ACMA][27] = 127, ++ [0][0][RTW89_CHILE][27] = 54, ++ [0][0][RTW89_UKRAINE][27] = 24, ++ [0][0][RTW89_FCC][29] = 48, ++ [0][0][RTW89_ETSI][29] = 24, ++ [0][0][RTW89_MKK][29] = 44, ++ [0][0][RTW89_IC][29] = 127, ++ [0][0][RTW89_KCC][29] = 24, ++ [0][0][RTW89_ACMA][29] = 127, ++ [0][0][RTW89_CHILE][29] = 54, ++ [0][0][RTW89_UKRAINE][29] = 24, ++ [0][0][RTW89_FCC][31] = 48, ++ [0][0][RTW89_ETSI][31] = 24, ++ [0][0][RTW89_MKK][31] = 44, ++ [0][0][RTW89_IC][31] = 48, ++ [0][0][RTW89_KCC][31] = 24, ++ [0][0][RTW89_ACMA][31] = 24, ++ [0][0][RTW89_CHILE][31] = 54, ++ [0][0][RTW89_UKRAINE][31] = 24, ++ [0][0][RTW89_FCC][33] = 48, ++ [0][0][RTW89_ETSI][33] = 24, ++ [0][0][RTW89_MKK][33] = 44, ++ [0][0][RTW89_IC][33] = 48, ++ [0][0][RTW89_KCC][33] = 24, ++ [0][0][RTW89_ACMA][33] = 24, ++ [0][0][RTW89_CHILE][33] = 54, ++ [0][0][RTW89_UKRAINE][33] = 24, ++ [0][0][RTW89_FCC][35] = 48, ++ [0][0][RTW89_ETSI][35] = 24, ++ [0][0][RTW89_MKK][35] = 44, ++ [0][0][RTW89_IC][35] = 48, ++ [0][0][RTW89_KCC][35] = 24, ++ [0][0][RTW89_ACMA][35] = 24, ++ [0][0][RTW89_CHILE][35] = 54, ++ [0][0][RTW89_UKRAINE][35] = 24, ++ [0][0][RTW89_FCC][37] = 48, ++ [0][0][RTW89_ETSI][37] = 127, ++ [0][0][RTW89_MKK][37] = 44, ++ [0][0][RTW89_IC][37] = 48, ++ [0][0][RTW89_KCC][37] = 24, ++ [0][0][RTW89_ACMA][37] = 48, ++ [0][0][RTW89_CHILE][37] = 54, ++ [0][0][RTW89_UKRAINE][37] = 127, ++ [0][0][RTW89_FCC][38] = 76, ++ [0][0][RTW89_ETSI][38] = 28, ++ [0][0][RTW89_MKK][38] = 127, ++ [0][0][RTW89_IC][38] = 76, ++ [0][0][RTW89_KCC][38] = 28, ++ [0][0][RTW89_ACMA][38] = 76, ++ [0][0][RTW89_CHILE][38] = 54, ++ [0][0][RTW89_UKRAINE][38] = 28, ++ [0][0][RTW89_FCC][40] = 76, ++ [0][0][RTW89_ETSI][40] = 28, ++ [0][0][RTW89_MKK][40] = 127, ++ [0][0][RTW89_IC][40] = 76, ++ [0][0][RTW89_KCC][40] = 28, ++ [0][0][RTW89_ACMA][40] = 76, ++ [0][0][RTW89_CHILE][40] = 54, ++ [0][0][RTW89_UKRAINE][40] = 28, ++ [0][0][RTW89_FCC][42] = 76, ++ [0][0][RTW89_ETSI][42] = 28, ++ [0][0][RTW89_MKK][42] = 127, ++ [0][0][RTW89_IC][42] = 76, ++ [0][0][RTW89_KCC][42] = 28, ++ [0][0][RTW89_ACMA][42] = 76, ++ [0][0][RTW89_CHILE][42] = 54, ++ [0][0][RTW89_UKRAINE][42] = 28, ++ [0][0][RTW89_FCC][44] = 76, ++ [0][0][RTW89_ETSI][44] = 28, ++ [0][0][RTW89_MKK][44] = 127, ++ [0][0][RTW89_IC][44] = 76, ++ [0][0][RTW89_KCC][44] = 28, ++ [0][0][RTW89_ACMA][44] = 76, ++ [0][0][RTW89_CHILE][44] = 54, ++ [0][0][RTW89_UKRAINE][44] = 28, ++ [0][0][RTW89_FCC][46] = 76, ++ [0][0][RTW89_ETSI][46] = 28, ++ [0][0][RTW89_MKK][46] = 127, ++ [0][0][RTW89_IC][46] = 76, ++ [0][0][RTW89_KCC][46] = 28, ++ [0][0][RTW89_ACMA][46] = 76, ++ [0][0][RTW89_CHILE][46] = 54, ++ [0][0][RTW89_UKRAINE][46] = 28, ++ [0][1][RTW89_FCC][0] = 36, ++ [0][1][RTW89_ETSI][0] = 12, ++ [0][1][RTW89_MKK][0] = 14, ++ [0][1][RTW89_IC][0] = 8, ++ [0][1][RTW89_KCC][0] = 12, ++ [0][1][RTW89_ACMA][0] = 12, ++ [0][1][RTW89_CHILE][0] = 18, ++ [0][1][RTW89_UKRAINE][0] = 12, ++ [0][1][RTW89_FCC][2] = 36, ++ [0][1][RTW89_ETSI][2] = 12, ++ [0][1][RTW89_MKK][2] = 14, ++ [0][1][RTW89_IC][2] = 8, ++ [0][1][RTW89_KCC][2] = 12, ++ [0][1][RTW89_ACMA][2] = 12, ++ [0][1][RTW89_CHILE][2] = 18, ++ [0][1][RTW89_UKRAINE][2] = 12, ++ [0][1][RTW89_FCC][4] = 36, ++ [0][1][RTW89_ETSI][4] = 12, ++ [0][1][RTW89_MKK][4] = 14, ++ [0][1][RTW89_IC][4] = 8, ++ [0][1][RTW89_KCC][4] = 12, ++ [0][1][RTW89_ACMA][4] = 12, ++ [0][1][RTW89_CHILE][4] = 18, ++ [0][1][RTW89_UKRAINE][4] = 12, ++ [0][1][RTW89_FCC][6] = 36, ++ [0][1][RTW89_ETSI][6] = 12, ++ [0][1][RTW89_MKK][6] = 14, ++ [0][1][RTW89_IC][6] = 8, ++ [0][1][RTW89_KCC][6] = 12, ++ [0][1][RTW89_ACMA][6] = 12, ++ [0][1][RTW89_CHILE][6] = 18, ++ [0][1][RTW89_UKRAINE][6] = 12, ++ [0][1][RTW89_FCC][8] = 36, ++ [0][1][RTW89_ETSI][8] = 12, ++ [0][1][RTW89_MKK][8] = 14, ++ [0][1][RTW89_IC][8] = 36, ++ [0][1][RTW89_KCC][8] = 12, ++ [0][1][RTW89_ACMA][8] = 12, ++ [0][1][RTW89_CHILE][8] = 42, ++ [0][1][RTW89_UKRAINE][8] = 12, ++ [0][1][RTW89_FCC][10] = 36, ++ [0][1][RTW89_ETSI][10] = 12, ++ [0][1][RTW89_MKK][10] = 14, ++ [0][1][RTW89_IC][10] = 36, ++ [0][1][RTW89_KCC][10] = 12, ++ [0][1][RTW89_ACMA][10] = 12, ++ [0][1][RTW89_CHILE][10] = 42, ++ [0][1][RTW89_UKRAINE][10] = 12, ++ [0][1][RTW89_FCC][12] = 36, ++ [0][1][RTW89_ETSI][12] = 12, ++ [0][1][RTW89_MKK][12] = 14, ++ [0][1][RTW89_IC][12] = 36, ++ [0][1][RTW89_KCC][12] = 12, ++ [0][1][RTW89_ACMA][12] = 12, ++ [0][1][RTW89_CHILE][12] = 42, ++ [0][1][RTW89_UKRAINE][12] = 12, ++ [0][1][RTW89_FCC][14] = 36, ++ [0][1][RTW89_ETSI][14] = 12, ++ [0][1][RTW89_MKK][14] = 14, ++ [0][1][RTW89_IC][14] = 36, ++ [0][1][RTW89_KCC][14] = 12, ++ [0][1][RTW89_ACMA][14] = 12, ++ [0][1][RTW89_CHILE][14] = 42, ++ [0][1][RTW89_UKRAINE][14] = 12, ++ [0][1][RTW89_FCC][15] = 36, ++ [0][1][RTW89_ETSI][15] = 12, ++ [0][1][RTW89_MKK][15] = 32, ++ [0][1][RTW89_IC][15] = 36, ++ [0][1][RTW89_KCC][15] = 12, ++ [0][1][RTW89_ACMA][15] = 12, ++ [0][1][RTW89_CHILE][15] = 42, ++ [0][1][RTW89_UKRAINE][15] = 12, ++ [0][1][RTW89_FCC][17] = 36, ++ [0][1][RTW89_ETSI][17] = 12, ++ [0][1][RTW89_MKK][17] = 32, ++ [0][1][RTW89_IC][17] = 36, ++ [0][1][RTW89_KCC][17] = 12, ++ [0][1][RTW89_ACMA][17] = 12, ++ [0][1][RTW89_CHILE][17] = 42, ++ [0][1][RTW89_UKRAINE][17] = 12, ++ [0][1][RTW89_FCC][19] = 36, ++ [0][1][RTW89_ETSI][19] = 12, ++ [0][1][RTW89_MKK][19] = 32, ++ [0][1][RTW89_IC][19] = 36, ++ [0][1][RTW89_KCC][19] = 12, ++ [0][1][RTW89_ACMA][19] = 12, ++ [0][1][RTW89_CHILE][19] = 42, ++ [0][1][RTW89_UKRAINE][19] = 12, ++ [0][1][RTW89_FCC][21] = 36, ++ [0][1][RTW89_ETSI][21] = 12, ++ [0][1][RTW89_MKK][21] = 32, ++ [0][1][RTW89_IC][21] = 36, ++ [0][1][RTW89_KCC][21] = 12, ++ [0][1][RTW89_ACMA][21] = 12, ++ [0][1][RTW89_CHILE][21] = 42, ++ [0][1][RTW89_UKRAINE][21] = 12, ++ [0][1][RTW89_FCC][23] = 36, ++ [0][1][RTW89_ETSI][23] = 12, ++ [0][1][RTW89_MKK][23] = 32, ++ [0][1][RTW89_IC][23] = 36, ++ [0][1][RTW89_KCC][23] = 12, ++ [0][1][RTW89_ACMA][23] = 12, ++ [0][1][RTW89_CHILE][23] = 42, ++ [0][1][RTW89_UKRAINE][23] = 12, ++ [0][1][RTW89_FCC][25] = 36, ++ [0][1][RTW89_ETSI][25] = 12, ++ [0][1][RTW89_MKK][25] = 32, ++ [0][1][RTW89_IC][25] = 127, ++ [0][1][RTW89_KCC][25] = 12, ++ [0][1][RTW89_ACMA][25] = 127, ++ [0][1][RTW89_CHILE][25] = 42, ++ [0][1][RTW89_UKRAINE][25] = 12, ++ [0][1][RTW89_FCC][27] = 36, ++ [0][1][RTW89_ETSI][27] = 12, ++ [0][1][RTW89_MKK][27] = 32, ++ [0][1][RTW89_IC][27] = 127, ++ [0][1][RTW89_KCC][27] = 12, ++ [0][1][RTW89_ACMA][27] = 127, ++ [0][1][RTW89_CHILE][27] = 42, ++ [0][1][RTW89_UKRAINE][27] = 12, ++ [0][1][RTW89_FCC][29] = 36, ++ [0][1][RTW89_ETSI][29] = 12, ++ [0][1][RTW89_MKK][29] = 32, ++ [0][1][RTW89_IC][29] = 127, ++ [0][1][RTW89_KCC][29] = 12, ++ [0][1][RTW89_ACMA][29] = 127, ++ [0][1][RTW89_CHILE][29] = 42, ++ [0][1][RTW89_UKRAINE][29] = 12, ++ [0][1][RTW89_FCC][31] = 36, ++ [0][1][RTW89_ETSI][31] = 12, ++ [0][1][RTW89_MKK][31] = 32, ++ [0][1][RTW89_IC][31] = 36, ++ [0][1][RTW89_KCC][31] = 12, ++ [0][1][RTW89_ACMA][31] = 12, ++ [0][1][RTW89_CHILE][31] = 42, ++ [0][1][RTW89_UKRAINE][31] = 12, ++ [0][1][RTW89_FCC][33] = 36, ++ [0][1][RTW89_ETSI][33] = 12, ++ [0][1][RTW89_MKK][33] = 32, ++ [0][1][RTW89_IC][33] = 36, ++ [0][1][RTW89_KCC][33] = 12, ++ [0][1][RTW89_ACMA][33] = 12, ++ [0][1][RTW89_CHILE][33] = 42, ++ [0][1][RTW89_UKRAINE][33] = 12, ++ [0][1][RTW89_FCC][35] = 36, ++ [0][1][RTW89_ETSI][35] = 12, ++ [0][1][RTW89_MKK][35] = 32, ++ [0][1][RTW89_IC][35] = 36, ++ [0][1][RTW89_KCC][35] = 12, ++ [0][1][RTW89_ACMA][35] = 12, ++ [0][1][RTW89_CHILE][35] = 42, ++ [0][1][RTW89_UKRAINE][35] = 12, ++ [0][1][RTW89_FCC][37] = 36, ++ [0][1][RTW89_ETSI][37] = 127, ++ [0][1][RTW89_MKK][37] = 32, ++ [0][1][RTW89_IC][37] = 36, ++ [0][1][RTW89_KCC][37] = 12, ++ [0][1][RTW89_ACMA][37] = 36, ++ [0][1][RTW89_CHILE][37] = 42, ++ [0][1][RTW89_UKRAINE][37] = 127, ++ [0][1][RTW89_FCC][38] = 72, ++ [0][1][RTW89_ETSI][38] = 16, ++ [0][1][RTW89_MKK][38] = 127, ++ [0][1][RTW89_IC][38] = 72, ++ [0][1][RTW89_KCC][38] = 16, ++ [0][1][RTW89_ACMA][38] = 76, ++ [0][1][RTW89_CHILE][38] = 42, ++ [0][1][RTW89_UKRAINE][38] = 16, ++ [0][1][RTW89_FCC][40] = 76, ++ [0][1][RTW89_ETSI][40] = 16, ++ [0][1][RTW89_MKK][40] = 127, ++ [0][1][RTW89_IC][40] = 76, ++ [0][1][RTW89_KCC][40] = 16, ++ [0][1][RTW89_ACMA][40] = 76, ++ [0][1][RTW89_CHILE][40] = 42, ++ [0][1][RTW89_UKRAINE][40] = 16, ++ [0][1][RTW89_FCC][42] = 76, ++ [0][1][RTW89_ETSI][42] = 16, ++ [0][1][RTW89_MKK][42] = 127, ++ [0][1][RTW89_IC][42] = 76, ++ [0][1][RTW89_KCC][42] = 16, ++ [0][1][RTW89_ACMA][42] = 76, ++ [0][1][RTW89_CHILE][42] = 42, ++ [0][1][RTW89_UKRAINE][42] = 16, ++ [0][1][RTW89_FCC][44] = 76, ++ [0][1][RTW89_ETSI][44] = 16, ++ [0][1][RTW89_MKK][44] = 127, ++ [0][1][RTW89_IC][44] = 76, ++ [0][1][RTW89_KCC][44] = 16, ++ [0][1][RTW89_ACMA][44] = 76, ++ [0][1][RTW89_CHILE][44] = 42, ++ [0][1][RTW89_UKRAINE][44] = 16, ++ [0][1][RTW89_FCC][46] = 76, ++ [0][1][RTW89_ETSI][46] = 16, ++ [0][1][RTW89_MKK][46] = 127, ++ [0][1][RTW89_IC][46] = 76, ++ [0][1][RTW89_KCC][46] = 16, ++ [0][1][RTW89_ACMA][46] = 76, ++ [0][1][RTW89_CHILE][46] = 42, ++ [0][1][RTW89_UKRAINE][46] = 16, ++ [1][0][RTW89_FCC][0] = 62, ++ [1][0][RTW89_ETSI][0] = 36, ++ [1][0][RTW89_MKK][0] = 36, ++ [1][0][RTW89_IC][0] = 34, ++ [1][0][RTW89_KCC][0] = 36, ++ [1][0][RTW89_ACMA][0] = 36, ++ [1][0][RTW89_CHILE][0] = 30, ++ [1][0][RTW89_UKRAINE][0] = 36, ++ [1][0][RTW89_FCC][2] = 62, ++ [1][0][RTW89_ETSI][2] = 36, ++ [1][0][RTW89_MKK][2] = 36, ++ [1][0][RTW89_IC][2] = 34, ++ [1][0][RTW89_KCC][2] = 36, ++ [1][0][RTW89_ACMA][2] = 36, ++ [1][0][RTW89_CHILE][2] = 30, ++ [1][0][RTW89_UKRAINE][2] = 36, ++ [1][0][RTW89_FCC][4] = 62, ++ [1][0][RTW89_ETSI][4] = 36, ++ [1][0][RTW89_MKK][4] = 36, ++ [1][0][RTW89_IC][4] = 34, ++ [1][0][RTW89_KCC][4] = 36, ++ [1][0][RTW89_ACMA][4] = 36, ++ [1][0][RTW89_CHILE][4] = 30, ++ [1][0][RTW89_UKRAINE][4] = 36, ++ [1][0][RTW89_FCC][6] = 62, ++ [1][0][RTW89_ETSI][6] = 36, ++ [1][0][RTW89_MKK][6] = 36, ++ [1][0][RTW89_IC][6] = 34, ++ [1][0][RTW89_KCC][6] = 36, ++ [1][0][RTW89_ACMA][6] = 36, ++ [1][0][RTW89_CHILE][6] = 30, ++ [1][0][RTW89_UKRAINE][6] = 36, ++ [1][0][RTW89_FCC][8] = 62, ++ [1][0][RTW89_ETSI][8] = 36, ++ [1][0][RTW89_MKK][8] = 36, ++ [1][0][RTW89_IC][8] = 62, ++ [1][0][RTW89_KCC][8] = 36, ++ [1][0][RTW89_ACMA][8] = 36, ++ [1][0][RTW89_CHILE][8] = 54, ++ [1][0][RTW89_UKRAINE][8] = 36, ++ [1][0][RTW89_FCC][10] = 62, ++ [1][0][RTW89_ETSI][10] = 36, ++ [1][0][RTW89_MKK][10] = 36, ++ [1][0][RTW89_IC][10] = 62, ++ [1][0][RTW89_KCC][10] = 36, ++ [1][0][RTW89_ACMA][10] = 36, ++ [1][0][RTW89_CHILE][10] = 54, ++ [1][0][RTW89_UKRAINE][10] = 36, ++ [1][0][RTW89_FCC][12] = 62, ++ [1][0][RTW89_ETSI][12] = 36, ++ [1][0][RTW89_MKK][12] = 36, ++ [1][0][RTW89_IC][12] = 62, ++ [1][0][RTW89_KCC][12] = 36, ++ [1][0][RTW89_ACMA][12] = 36, ++ [1][0][RTW89_CHILE][12] = 54, ++ [1][0][RTW89_UKRAINE][12] = 36, ++ [1][0][RTW89_FCC][14] = 62, ++ [1][0][RTW89_ETSI][14] = 36, ++ [1][0][RTW89_MKK][14] = 36, ++ [1][0][RTW89_IC][14] = 62, ++ [1][0][RTW89_KCC][14] = 36, ++ [1][0][RTW89_ACMA][14] = 36, ++ [1][0][RTW89_CHILE][14] = 54, ++ [1][0][RTW89_UKRAINE][14] = 36, ++ [1][0][RTW89_FCC][15] = 62, ++ [1][0][RTW89_ETSI][15] = 36, ++ [1][0][RTW89_MKK][15] = 58, ++ [1][0][RTW89_IC][15] = 62, ++ [1][0][RTW89_KCC][15] = 36, ++ [1][0][RTW89_ACMA][15] = 36, ++ [1][0][RTW89_CHILE][15] = 54, ++ [1][0][RTW89_UKRAINE][15] = 36, ++ [1][0][RTW89_FCC][17] = 62, ++ [1][0][RTW89_ETSI][17] = 36, ++ [1][0][RTW89_MKK][17] = 58, ++ [1][0][RTW89_IC][17] = 62, ++ [1][0][RTW89_KCC][17] = 36, ++ [1][0][RTW89_ACMA][17] = 36, ++ [1][0][RTW89_CHILE][17] = 54, ++ [1][0][RTW89_UKRAINE][17] = 36, ++ [1][0][RTW89_FCC][19] = 62, ++ [1][0][RTW89_ETSI][19] = 36, ++ [1][0][RTW89_MKK][19] = 58, ++ [1][0][RTW89_IC][19] = 62, ++ [1][0][RTW89_KCC][19] = 36, ++ [1][0][RTW89_ACMA][19] = 36, ++ [1][0][RTW89_CHILE][19] = 54, ++ [1][0][RTW89_UKRAINE][19] = 36, ++ [1][0][RTW89_FCC][21] = 62, ++ [1][0][RTW89_ETSI][21] = 36, ++ [1][0][RTW89_MKK][21] = 58, ++ [1][0][RTW89_IC][21] = 62, ++ [1][0][RTW89_KCC][21] = 36, ++ [1][0][RTW89_ACMA][21] = 36, ++ [1][0][RTW89_CHILE][21] = 54, ++ [1][0][RTW89_UKRAINE][21] = 36, ++ [1][0][RTW89_FCC][23] = 62, ++ [1][0][RTW89_ETSI][23] = 36, ++ [1][0][RTW89_MKK][23] = 58, ++ [1][0][RTW89_IC][23] = 62, ++ [1][0][RTW89_KCC][23] = 36, ++ [1][0][RTW89_ACMA][23] = 36, ++ [1][0][RTW89_CHILE][23] = 54, ++ [1][0][RTW89_UKRAINE][23] = 36, ++ [1][0][RTW89_FCC][25] = 62, ++ [1][0][RTW89_ETSI][25] = 36, ++ [1][0][RTW89_MKK][25] = 58, ++ [1][0][RTW89_IC][25] = 127, ++ [1][0][RTW89_KCC][25] = 36, ++ [1][0][RTW89_ACMA][25] = 127, ++ [1][0][RTW89_CHILE][25] = 54, ++ [1][0][RTW89_UKRAINE][25] = 36, ++ [1][0][RTW89_FCC][27] = 62, ++ [1][0][RTW89_ETSI][27] = 36, ++ [1][0][RTW89_MKK][27] = 58, ++ [1][0][RTW89_IC][27] = 127, ++ [1][0][RTW89_KCC][27] = 36, ++ [1][0][RTW89_ACMA][27] = 127, ++ [1][0][RTW89_CHILE][27] = 54, ++ [1][0][RTW89_UKRAINE][27] = 36, ++ [1][0][RTW89_FCC][29] = 62, ++ [1][0][RTW89_ETSI][29] = 36, ++ [1][0][RTW89_MKK][29] = 58, ++ [1][0][RTW89_IC][29] = 127, ++ [1][0][RTW89_KCC][29] = 36, ++ [1][0][RTW89_ACMA][29] = 127, ++ [1][0][RTW89_CHILE][29] = 54, ++ [1][0][RTW89_UKRAINE][29] = 36, ++ [1][0][RTW89_FCC][31] = 62, ++ [1][0][RTW89_ETSI][31] = 36, ++ [1][0][RTW89_MKK][31] = 58, ++ [1][0][RTW89_IC][31] = 62, ++ [1][0][RTW89_KCC][31] = 36, ++ [1][0][RTW89_ACMA][31] = 36, ++ [1][0][RTW89_CHILE][31] = 54, ++ [1][0][RTW89_UKRAINE][31] = 36, ++ [1][0][RTW89_FCC][33] = 62, ++ [1][0][RTW89_ETSI][33] = 36, ++ [1][0][RTW89_MKK][33] = 58, ++ [1][0][RTW89_IC][33] = 62, ++ [1][0][RTW89_KCC][33] = 36, ++ [1][0][RTW89_ACMA][33] = 36, ++ [1][0][RTW89_CHILE][33] = 54, ++ [1][0][RTW89_UKRAINE][33] = 36, ++ [1][0][RTW89_FCC][35] = 62, ++ [1][0][RTW89_ETSI][35] = 36, ++ [1][0][RTW89_MKK][35] = 58, ++ [1][0][RTW89_IC][35] = 62, ++ [1][0][RTW89_KCC][35] = 36, ++ [1][0][RTW89_ACMA][35] = 36, ++ [1][0][RTW89_CHILE][35] = 54, ++ [1][0][RTW89_UKRAINE][35] = 36, ++ [1][0][RTW89_FCC][37] = 56, ++ [1][0][RTW89_ETSI][37] = 62, ++ [1][0][RTW89_MKK][37] = 127, ++ [1][0][RTW89_IC][37] = 58, ++ [1][0][RTW89_KCC][37] = 62, ++ [1][0][RTW89_ACMA][37] = 36, ++ [1][0][RTW89_CHILE][37] = 62, ++ [1][0][RTW89_UKRAINE][37] = 54, ++ [1][0][RTW89_FCC][38] = 76, ++ [1][0][RTW89_ETSI][38] = 28, ++ [1][0][RTW89_MKK][38] = 127, ++ [1][0][RTW89_IC][38] = 76, ++ [1][0][RTW89_KCC][38] = 28, ++ [1][0][RTW89_ACMA][38] = 76, ++ [1][0][RTW89_CHILE][38] = 54, ++ [1][0][RTW89_UKRAINE][38] = 28, ++ [1][0][RTW89_FCC][40] = 76, ++ [1][0][RTW89_ETSI][40] = 28, ++ [1][0][RTW89_MKK][40] = 127, ++ [1][0][RTW89_IC][40] = 76, ++ [1][0][RTW89_KCC][40] = 28, ++ [1][0][RTW89_ACMA][40] = 76, ++ [1][0][RTW89_CHILE][40] = 54, ++ [1][0][RTW89_UKRAINE][40] = 28, ++ [1][0][RTW89_FCC][42] = 76, ++ [1][0][RTW89_ETSI][42] = 28, ++ [1][0][RTW89_MKK][42] = 127, ++ [1][0][RTW89_IC][42] = 76, ++ [1][0][RTW89_KCC][42] = 28, ++ [1][0][RTW89_ACMA][42] = 76, ++ [1][0][RTW89_CHILE][42] = 54, ++ [1][0][RTW89_UKRAINE][42] = 28, ++ [1][0][RTW89_FCC][44] = 76, ++ [1][0][RTW89_ETSI][44] = 28, ++ [1][0][RTW89_MKK][44] = 127, ++ [1][0][RTW89_IC][44] = 76, ++ [1][0][RTW89_KCC][44] = 28, ++ [1][0][RTW89_ACMA][44] = 76, ++ [1][0][RTW89_CHILE][44] = 54, ++ [1][0][RTW89_UKRAINE][44] = 28, ++ [1][0][RTW89_FCC][46] = 76, ++ [1][0][RTW89_ETSI][46] = 28, ++ [1][0][RTW89_MKK][46] = 127, ++ [1][0][RTW89_IC][46] = 76, ++ [1][0][RTW89_KCC][46] = 28, ++ [1][0][RTW89_ACMA][46] = 76, ++ [1][0][RTW89_CHILE][46] = 54, ++ [1][0][RTW89_UKRAINE][46] = 28, ++ [1][1][RTW89_FCC][0] = 46, ++ [1][1][RTW89_ETSI][0] = 22, ++ [1][1][RTW89_MKK][0] = 24, ++ [1][1][RTW89_IC][0] = 18, ++ [1][1][RTW89_KCC][0] = 22, ++ [1][1][RTW89_ACMA][0] = 22, ++ [1][1][RTW89_CHILE][0] = 18, ++ [1][1][RTW89_UKRAINE][0] = 22, ++ [1][1][RTW89_FCC][2] = 46, ++ [1][1][RTW89_ETSI][2] = 22, ++ [1][1][RTW89_MKK][2] = 24, ++ [1][1][RTW89_IC][2] = 18, ++ [1][1][RTW89_KCC][2] = 22, ++ [1][1][RTW89_ACMA][2] = 22, ++ [1][1][RTW89_CHILE][2] = 18, ++ [1][1][RTW89_UKRAINE][2] = 22, ++ [1][1][RTW89_FCC][4] = 46, ++ [1][1][RTW89_ETSI][4] = 22, ++ [1][1][RTW89_MKK][4] = 24, ++ [1][1][RTW89_IC][4] = 18, ++ [1][1][RTW89_KCC][4] = 22, ++ [1][1][RTW89_ACMA][4] = 22, ++ [1][1][RTW89_CHILE][4] = 18, ++ [1][1][RTW89_UKRAINE][4] = 22, ++ [1][1][RTW89_FCC][6] = 46, ++ [1][1][RTW89_ETSI][6] = 22, ++ [1][1][RTW89_MKK][6] = 24, ++ [1][1][RTW89_IC][6] = 18, ++ [1][1][RTW89_KCC][6] = 22, ++ [1][1][RTW89_ACMA][6] = 22, ++ [1][1][RTW89_CHILE][6] = 18, ++ [1][1][RTW89_UKRAINE][6] = 22, ++ [1][1][RTW89_FCC][8] = 46, ++ [1][1][RTW89_ETSI][8] = 22, ++ [1][1][RTW89_MKK][8] = 24, ++ [1][1][RTW89_IC][8] = 46, ++ [1][1][RTW89_KCC][8] = 22, ++ [1][1][RTW89_ACMA][8] = 22, ++ [1][1][RTW89_CHILE][8] = 42, ++ [1][1][RTW89_UKRAINE][8] = 22, ++ [1][1][RTW89_FCC][10] = 46, ++ [1][1][RTW89_ETSI][10] = 22, ++ [1][1][RTW89_MKK][10] = 24, ++ [1][1][RTW89_IC][10] = 46, ++ [1][1][RTW89_KCC][10] = 22, ++ [1][1][RTW89_ACMA][10] = 22, ++ [1][1][RTW89_CHILE][10] = 42, ++ [1][1][RTW89_UKRAINE][10] = 22, ++ [1][1][RTW89_FCC][12] = 46, ++ [1][1][RTW89_ETSI][12] = 22, ++ [1][1][RTW89_MKK][12] = 24, ++ [1][1][RTW89_IC][12] = 46, ++ [1][1][RTW89_KCC][12] = 22, ++ [1][1][RTW89_ACMA][12] = 22, ++ [1][1][RTW89_CHILE][12] = 42, ++ [1][1][RTW89_UKRAINE][12] = 22, ++ [1][1][RTW89_FCC][14] = 46, ++ [1][1][RTW89_ETSI][14] = 22, ++ [1][1][RTW89_MKK][14] = 24, ++ [1][1][RTW89_IC][14] = 46, ++ [1][1][RTW89_KCC][14] = 22, ++ [1][1][RTW89_ACMA][14] = 22, ++ [1][1][RTW89_CHILE][14] = 42, ++ [1][1][RTW89_UKRAINE][14] = 22, ++ [1][1][RTW89_FCC][15] = 46, ++ [1][1][RTW89_ETSI][15] = 22, ++ [1][1][RTW89_MKK][15] = 46, ++ [1][1][RTW89_IC][15] = 46, ++ [1][1][RTW89_KCC][15] = 22, ++ [1][1][RTW89_ACMA][15] = 22, ++ [1][1][RTW89_CHILE][15] = 42, ++ [1][1][RTW89_UKRAINE][15] = 22, ++ [1][1][RTW89_FCC][17] = 46, ++ [1][1][RTW89_ETSI][17] = 22, ++ [1][1][RTW89_MKK][17] = 46, ++ [1][1][RTW89_IC][17] = 46, ++ [1][1][RTW89_KCC][17] = 22, ++ [1][1][RTW89_ACMA][17] = 22, ++ [1][1][RTW89_CHILE][17] = 42, ++ [1][1][RTW89_UKRAINE][17] = 22, ++ [1][1][RTW89_FCC][19] = 46, ++ [1][1][RTW89_ETSI][19] = 22, ++ [1][1][RTW89_MKK][19] = 46, ++ [1][1][RTW89_IC][19] = 46, ++ [1][1][RTW89_KCC][19] = 22, ++ [1][1][RTW89_ACMA][19] = 22, ++ [1][1][RTW89_CHILE][19] = 42, ++ [1][1][RTW89_UKRAINE][19] = 22, ++ [1][1][RTW89_FCC][21] = 46, ++ [1][1][RTW89_ETSI][21] = 22, ++ [1][1][RTW89_MKK][21] = 46, ++ [1][1][RTW89_IC][21] = 46, ++ [1][1][RTW89_KCC][21] = 22, ++ [1][1][RTW89_ACMA][21] = 22, ++ [1][1][RTW89_CHILE][21] = 42, ++ [1][1][RTW89_UKRAINE][21] = 22, ++ [1][1][RTW89_FCC][23] = 46, ++ [1][1][RTW89_ETSI][23] = 22, ++ [1][1][RTW89_MKK][23] = 46, ++ [1][1][RTW89_IC][23] = 46, ++ [1][1][RTW89_KCC][23] = 22, ++ [1][1][RTW89_ACMA][23] = 22, ++ [1][1][RTW89_CHILE][23] = 42, ++ [1][1][RTW89_UKRAINE][23] = 22, ++ [1][1][RTW89_FCC][25] = 46, ++ [1][1][RTW89_ETSI][25] = 22, ++ [1][1][RTW89_MKK][25] = 46, ++ [1][1][RTW89_IC][25] = 127, ++ [1][1][RTW89_KCC][25] = 22, ++ [1][1][RTW89_ACMA][25] = 127, ++ [1][1][RTW89_CHILE][25] = 42, ++ [1][1][RTW89_UKRAINE][25] = 22, ++ [1][1][RTW89_FCC][27] = 46, ++ [1][1][RTW89_ETSI][27] = 22, ++ [1][1][RTW89_MKK][27] = 46, ++ [1][1][RTW89_IC][27] = 127, ++ [1][1][RTW89_KCC][27] = 22, ++ [1][1][RTW89_ACMA][27] = 127, ++ [1][1][RTW89_CHILE][27] = 42, ++ [1][1][RTW89_UKRAINE][27] = 22, ++ [1][1][RTW89_FCC][29] = 46, ++ [1][1][RTW89_ETSI][29] = 22, ++ [1][1][RTW89_MKK][29] = 46, ++ [1][1][RTW89_IC][29] = 127, ++ [1][1][RTW89_KCC][29] = 22, ++ [1][1][RTW89_ACMA][29] = 127, ++ [1][1][RTW89_CHILE][29] = 42, ++ [1][1][RTW89_UKRAINE][29] = 22, ++ [1][1][RTW89_FCC][31] = 46, ++ [1][1][RTW89_ETSI][31] = 22, ++ [1][1][RTW89_MKK][31] = 46, ++ [1][1][RTW89_IC][31] = 46, ++ [1][1][RTW89_KCC][31] = 22, ++ [1][1][RTW89_ACMA][31] = 22, ++ [1][1][RTW89_CHILE][31] = 42, ++ [1][1][RTW89_UKRAINE][31] = 22, ++ [1][1][RTW89_FCC][33] = 46, ++ [1][1][RTW89_ETSI][33] = 22, ++ [1][1][RTW89_MKK][33] = 46, ++ [1][1][RTW89_IC][33] = 46, ++ [1][1][RTW89_KCC][33] = 22, ++ [1][1][RTW89_ACMA][33] = 22, ++ [1][1][RTW89_CHILE][33] = 42, ++ [1][1][RTW89_UKRAINE][33] = 22, ++ [1][1][RTW89_FCC][35] = 46, ++ [1][1][RTW89_ETSI][35] = 22, ++ [1][1][RTW89_MKK][35] = 46, ++ [1][1][RTW89_IC][35] = 46, ++ [1][1][RTW89_KCC][35] = 22, ++ [1][1][RTW89_ACMA][35] = 22, ++ [1][1][RTW89_CHILE][35] = 42, ++ [1][1][RTW89_UKRAINE][35] = 22, ++ [1][1][RTW89_FCC][37] = 46, ++ [1][1][RTW89_ETSI][37] = 127, ++ [1][1][RTW89_MKK][37] = 46, ++ [1][1][RTW89_IC][37] = 46, ++ [1][1][RTW89_KCC][37] = 22, ++ [1][1][RTW89_ACMA][37] = 50, ++ [1][1][RTW89_CHILE][37] = 42, ++ [1][1][RTW89_UKRAINE][37] = 127, ++ [1][1][RTW89_FCC][38] = 74, ++ [1][1][RTW89_ETSI][38] = 16, ++ [1][1][RTW89_MKK][38] = 127, ++ [1][1][RTW89_IC][38] = 74, ++ [1][1][RTW89_KCC][38] = 16, ++ [1][1][RTW89_ACMA][38] = 76, ++ [1][1][RTW89_CHILE][38] = 42, ++ [1][1][RTW89_UKRAINE][38] = 16, ++ [1][1][RTW89_FCC][40] = 76, ++ [1][1][RTW89_ETSI][40] = 16, ++ [1][1][RTW89_MKK][40] = 127, ++ [1][1][RTW89_IC][40] = 76, ++ [1][1][RTW89_KCC][40] = 16, ++ [1][1][RTW89_ACMA][40] = 76, ++ [1][1][RTW89_CHILE][40] = 42, ++ [1][1][RTW89_UKRAINE][40] = 16, ++ [1][1][RTW89_FCC][42] = 76, ++ [1][1][RTW89_ETSI][42] = 16, ++ [1][1][RTW89_MKK][42] = 127, ++ [1][1][RTW89_IC][42] = 76, ++ [1][1][RTW89_KCC][42] = 16, ++ [1][1][RTW89_ACMA][42] = 76, ++ [1][1][RTW89_CHILE][42] = 42, ++ [1][1][RTW89_UKRAINE][42] = 16, ++ [1][1][RTW89_FCC][44] = 76, ++ [1][1][RTW89_ETSI][44] = 16, ++ [1][1][RTW89_MKK][44] = 127, ++ [1][1][RTW89_IC][44] = 76, ++ [1][1][RTW89_KCC][44] = 16, ++ [1][1][RTW89_ACMA][44] = 76, ++ [1][1][RTW89_CHILE][44] = 42, ++ [1][1][RTW89_UKRAINE][44] = 16, ++ [1][1][RTW89_FCC][46] = 76, ++ [1][1][RTW89_ETSI][46] = 16, ++ [1][1][RTW89_MKK][46] = 127, ++ [1][1][RTW89_IC][46] = 76, ++ [1][1][RTW89_KCC][46] = 16, ++ [1][1][RTW89_ACMA][46] = 76, ++ [1][1][RTW89_CHILE][46] = 42, ++ [1][1][RTW89_UKRAINE][46] = 16, ++ [2][0][RTW89_FCC][0] = 74, ++ [2][0][RTW89_ETSI][0] = 46, ++ [2][0][RTW89_MKK][0] = 50, ++ [2][0][RTW89_IC][0] = 46, ++ [2][0][RTW89_KCC][0] = 46, ++ [2][0][RTW89_ACMA][0] = 46, ++ [2][0][RTW89_CHILE][0] = 30, ++ [2][0][RTW89_UKRAINE][0] = 46, ++ [2][0][RTW89_FCC][2] = 74, ++ [2][0][RTW89_ETSI][2] = 46, ++ [2][0][RTW89_MKK][2] = 50, ++ [2][0][RTW89_IC][2] = 46, ++ [2][0][RTW89_KCC][2] = 46, ++ [2][0][RTW89_ACMA][2] = 46, ++ [2][0][RTW89_CHILE][2] = 30, ++ [2][0][RTW89_UKRAINE][2] = 46, ++ [2][0][RTW89_FCC][4] = 74, ++ [2][0][RTW89_ETSI][4] = 46, ++ [2][0][RTW89_MKK][4] = 50, ++ [2][0][RTW89_IC][4] = 46, ++ [2][0][RTW89_KCC][4] = 46, ++ [2][0][RTW89_ACMA][4] = 46, ++ [2][0][RTW89_CHILE][4] = 30, ++ [2][0][RTW89_UKRAINE][4] = 46, ++ [2][0][RTW89_FCC][6] = 74, ++ [2][0][RTW89_ETSI][6] = 46, ++ [2][0][RTW89_MKK][6] = 50, ++ [2][0][RTW89_IC][6] = 46, ++ [2][0][RTW89_KCC][6] = 46, ++ [2][0][RTW89_ACMA][6] = 46, ++ [2][0][RTW89_CHILE][6] = 30, ++ [2][0][RTW89_UKRAINE][6] = 46, ++ [2][0][RTW89_FCC][8] = 74, ++ [2][0][RTW89_ETSI][8] = 46, ++ [2][0][RTW89_MKK][8] = 50, ++ [2][0][RTW89_IC][8] = 66, ++ [2][0][RTW89_KCC][8] = 46, ++ [2][0][RTW89_ACMA][8] = 46, ++ [2][0][RTW89_CHILE][8] = 54, ++ [2][0][RTW89_UKRAINE][8] = 46, ++ [2][0][RTW89_FCC][10] = 74, ++ [2][0][RTW89_ETSI][10] = 46, ++ [2][0][RTW89_MKK][10] = 50, ++ [2][0][RTW89_IC][10] = 66, ++ [2][0][RTW89_KCC][10] = 46, ++ [2][0][RTW89_ACMA][10] = 46, ++ [2][0][RTW89_CHILE][10] = 54, ++ [2][0][RTW89_UKRAINE][10] = 46, ++ [2][0][RTW89_FCC][12] = 74, ++ [2][0][RTW89_ETSI][12] = 46, ++ [2][0][RTW89_MKK][12] = 50, ++ [2][0][RTW89_IC][12] = 66, ++ [2][0][RTW89_KCC][12] = 46, ++ [2][0][RTW89_ACMA][12] = 46, ++ [2][0][RTW89_CHILE][12] = 54, ++ [2][0][RTW89_UKRAINE][12] = 46, ++ [2][0][RTW89_FCC][14] = 74, ++ [2][0][RTW89_ETSI][14] = 46, ++ [2][0][RTW89_MKK][14] = 50, ++ [2][0][RTW89_IC][14] = 66, ++ [2][0][RTW89_KCC][14] = 46, ++ [2][0][RTW89_ACMA][14] = 46, ++ [2][0][RTW89_CHILE][14] = 54, ++ [2][0][RTW89_UKRAINE][14] = 46, ++ [2][0][RTW89_FCC][15] = 74, ++ [2][0][RTW89_ETSI][15] = 46, ++ [2][0][RTW89_MKK][15] = 70, ++ [2][0][RTW89_IC][15] = 74, ++ [2][0][RTW89_KCC][15] = 46, ++ [2][0][RTW89_ACMA][15] = 46, ++ [2][0][RTW89_CHILE][15] = 54, ++ [2][0][RTW89_UKRAINE][15] = 46, ++ [2][0][RTW89_FCC][17] = 74, ++ [2][0][RTW89_ETSI][17] = 46, ++ [2][0][RTW89_MKK][17] = 70, ++ [2][0][RTW89_IC][17] = 74, ++ [2][0][RTW89_KCC][17] = 46, ++ [2][0][RTW89_ACMA][17] = 46, ++ [2][0][RTW89_CHILE][17] = 54, ++ [2][0][RTW89_UKRAINE][17] = 46, ++ [2][0][RTW89_FCC][19] = 74, ++ [2][0][RTW89_ETSI][19] = 46, ++ [2][0][RTW89_MKK][19] = 70, ++ [2][0][RTW89_IC][19] = 74, ++ [2][0][RTW89_KCC][19] = 46, ++ [2][0][RTW89_ACMA][19] = 46, ++ [2][0][RTW89_CHILE][19] = 54, ++ [2][0][RTW89_UKRAINE][19] = 46, ++ [2][0][RTW89_FCC][21] = 74, ++ [2][0][RTW89_ETSI][21] = 46, ++ [2][0][RTW89_MKK][21] = 70, ++ [2][0][RTW89_IC][21] = 74, ++ [2][0][RTW89_KCC][21] = 46, ++ [2][0][RTW89_ACMA][21] = 46, ++ [2][0][RTW89_CHILE][21] = 54, ++ [2][0][RTW89_UKRAINE][21] = 46, ++ [2][0][RTW89_FCC][23] = 74, ++ [2][0][RTW89_ETSI][23] = 46, ++ [2][0][RTW89_MKK][23] = 70, ++ [2][0][RTW89_IC][23] = 74, ++ [2][0][RTW89_KCC][23] = 46, ++ [2][0][RTW89_ACMA][23] = 46, ++ [2][0][RTW89_CHILE][23] = 54, ++ [2][0][RTW89_UKRAINE][23] = 46, ++ [2][0][RTW89_FCC][25] = 74, ++ [2][0][RTW89_ETSI][25] = 46, ++ [2][0][RTW89_MKK][25] = 70, ++ [2][0][RTW89_IC][25] = 127, ++ [2][0][RTW89_KCC][25] = 46, ++ [2][0][RTW89_ACMA][25] = 127, ++ [2][0][RTW89_CHILE][25] = 54, ++ [2][0][RTW89_UKRAINE][25] = 46, ++ [2][0][RTW89_FCC][27] = 74, ++ [2][0][RTW89_ETSI][27] = 46, ++ [2][0][RTW89_MKK][27] = 70, ++ [2][0][RTW89_IC][27] = 127, ++ [2][0][RTW89_KCC][27] = 46, ++ [2][0][RTW89_ACMA][27] = 127, ++ [2][0][RTW89_CHILE][27] = 54, ++ [2][0][RTW89_UKRAINE][27] = 46, ++ [2][0][RTW89_FCC][29] = 74, ++ [2][0][RTW89_ETSI][29] = 46, ++ [2][0][RTW89_MKK][29] = 70, ++ [2][0][RTW89_IC][29] = 127, ++ [2][0][RTW89_KCC][29] = 46, ++ [2][0][RTW89_ACMA][29] = 127, ++ [2][0][RTW89_CHILE][29] = 54, ++ [2][0][RTW89_UKRAINE][29] = 46, ++ [2][0][RTW89_FCC][31] = 74, ++ [2][0][RTW89_ETSI][31] = 46, ++ [2][0][RTW89_MKK][31] = 70, ++ [2][0][RTW89_IC][31] = 74, ++ [2][0][RTW89_KCC][31] = 46, ++ [2][0][RTW89_ACMA][31] = 46, ++ [2][0][RTW89_CHILE][31] = 54, ++ [2][0][RTW89_UKRAINE][31] = 46, ++ [2][0][RTW89_FCC][33] = 74, ++ [2][0][RTW89_ETSI][33] = 46, ++ [2][0][RTW89_MKK][33] = 70, ++ [2][0][RTW89_IC][33] = 74, ++ [2][0][RTW89_KCC][33] = 46, ++ [2][0][RTW89_ACMA][33] = 46, ++ [2][0][RTW89_CHILE][33] = 54, ++ [2][0][RTW89_UKRAINE][33] = 46, ++ [2][0][RTW89_FCC][35] = 74, ++ [2][0][RTW89_ETSI][35] = 46, ++ [2][0][RTW89_MKK][35] = 70, ++ [2][0][RTW89_IC][35] = 74, ++ [2][0][RTW89_KCC][35] = 46, ++ [2][0][RTW89_ACMA][35] = 46, ++ [2][0][RTW89_CHILE][35] = 54, ++ [2][0][RTW89_UKRAINE][35] = 46, ++ [2][0][RTW89_FCC][37] = 74, ++ [2][0][RTW89_ETSI][37] = 127, ++ [2][0][RTW89_MKK][37] = 70, ++ [2][0][RTW89_IC][37] = 74, ++ [2][0][RTW89_KCC][37] = 46, ++ [2][0][RTW89_ACMA][37] = 74, ++ [2][0][RTW89_CHILE][37] = 54, ++ [2][0][RTW89_UKRAINE][37] = 127, ++ [2][0][RTW89_FCC][38] = 76, ++ [2][0][RTW89_ETSI][38] = 28, ++ [2][0][RTW89_MKK][38] = 127, ++ [2][0][RTW89_IC][38] = 76, ++ [2][0][RTW89_KCC][38] = 28, ++ [2][0][RTW89_ACMA][38] = 76, ++ [2][0][RTW89_CHILE][38] = 54, ++ [2][0][RTW89_UKRAINE][38] = 28, ++ [2][0][RTW89_FCC][40] = 76, ++ [2][0][RTW89_ETSI][40] = 28, ++ [2][0][RTW89_MKK][40] = 127, ++ [2][0][RTW89_IC][40] = 76, ++ [2][0][RTW89_KCC][40] = 28, ++ [2][0][RTW89_ACMA][40] = 76, ++ [2][0][RTW89_CHILE][40] = 54, ++ [2][0][RTW89_UKRAINE][40] = 28, ++ [2][0][RTW89_FCC][42] = 76, ++ [2][0][RTW89_ETSI][42] = 28, ++ [2][0][RTW89_MKK][42] = 127, ++ [2][0][RTW89_IC][42] = 76, ++ [2][0][RTW89_KCC][42] = 28, ++ [2][0][RTW89_ACMA][42] = 76, ++ [2][0][RTW89_CHILE][42] = 54, ++ [2][0][RTW89_UKRAINE][42] = 28, ++ [2][0][RTW89_FCC][44] = 76, ++ [2][0][RTW89_ETSI][44] = 28, ++ [2][0][RTW89_MKK][44] = 127, ++ [2][0][RTW89_IC][44] = 76, ++ [2][0][RTW89_KCC][44] = 28, ++ [2][0][RTW89_ACMA][44] = 76, ++ [2][0][RTW89_CHILE][44] = 54, ++ [2][0][RTW89_UKRAINE][44] = 28, ++ [2][0][RTW89_FCC][46] = 76, ++ [2][0][RTW89_ETSI][46] = 28, ++ [2][0][RTW89_MKK][46] = 127, ++ [2][0][RTW89_IC][46] = 76, ++ [2][0][RTW89_KCC][46] = 28, ++ [2][0][RTW89_ACMA][46] = 76, ++ [2][0][RTW89_CHILE][46] = 54, ++ [2][0][RTW89_UKRAINE][46] = 28, ++ [2][1][RTW89_FCC][0] = 58, ++ [2][1][RTW89_ETSI][0] = 32, ++ [2][1][RTW89_MKK][0] = 38, ++ [2][1][RTW89_IC][0] = 30, ++ [2][1][RTW89_KCC][0] = 32, ++ [2][1][RTW89_ACMA][0] = 32, ++ [2][1][RTW89_CHILE][0] = 18, ++ [2][1][RTW89_UKRAINE][0] = 32, ++ [2][1][RTW89_FCC][2] = 58, ++ [2][1][RTW89_ETSI][2] = 32, ++ [2][1][RTW89_MKK][2] = 38, ++ [2][1][RTW89_IC][2] = 30, ++ [2][1][RTW89_KCC][2] = 32, ++ [2][1][RTW89_ACMA][2] = 32, ++ [2][1][RTW89_CHILE][2] = 18, ++ [2][1][RTW89_UKRAINE][2] = 32, ++ [2][1][RTW89_FCC][4] = 58, ++ [2][1][RTW89_ETSI][4] = 32, ++ [2][1][RTW89_MKK][4] = 38, ++ [2][1][RTW89_IC][4] = 30, ++ [2][1][RTW89_KCC][4] = 32, ++ [2][1][RTW89_ACMA][4] = 32, ++ [2][1][RTW89_CHILE][4] = 18, ++ [2][1][RTW89_UKRAINE][4] = 32, ++ [2][1][RTW89_FCC][6] = 58, ++ [2][1][RTW89_ETSI][6] = 32, ++ [2][1][RTW89_MKK][6] = 38, ++ [2][1][RTW89_IC][6] = 30, ++ [2][1][RTW89_KCC][6] = 32, ++ [2][1][RTW89_ACMA][6] = 32, ++ [2][1][RTW89_CHILE][6] = 18, ++ [2][1][RTW89_UKRAINE][6] = 32, ++ [2][1][RTW89_FCC][8] = 58, ++ [2][1][RTW89_ETSI][8] = 32, ++ [2][1][RTW89_MKK][8] = 38, ++ [2][1][RTW89_IC][8] = 52, ++ [2][1][RTW89_KCC][8] = 32, ++ [2][1][RTW89_ACMA][8] = 32, ++ [2][1][RTW89_CHILE][8] = 42, ++ [2][1][RTW89_UKRAINE][8] = 32, ++ [2][1][RTW89_FCC][10] = 58, ++ [2][1][RTW89_ETSI][10] = 32, ++ [2][1][RTW89_MKK][10] = 38, ++ [2][1][RTW89_IC][10] = 52, ++ [2][1][RTW89_KCC][10] = 32, ++ [2][1][RTW89_ACMA][10] = 32, ++ [2][1][RTW89_CHILE][10] = 42, ++ [2][1][RTW89_UKRAINE][10] = 32, ++ [2][1][RTW89_FCC][12] = 58, ++ [2][1][RTW89_ETSI][12] = 32, ++ [2][1][RTW89_MKK][12] = 38, ++ [2][1][RTW89_IC][12] = 52, ++ [2][1][RTW89_KCC][12] = 32, ++ [2][1][RTW89_ACMA][12] = 32, ++ [2][1][RTW89_CHILE][12] = 42, ++ [2][1][RTW89_UKRAINE][12] = 32, ++ [2][1][RTW89_FCC][14] = 58, ++ [2][1][RTW89_ETSI][14] = 32, ++ [2][1][RTW89_MKK][14] = 38, ++ [2][1][RTW89_IC][14] = 52, ++ [2][1][RTW89_KCC][14] = 32, ++ [2][1][RTW89_ACMA][14] = 32, ++ [2][1][RTW89_CHILE][14] = 42, ++ [2][1][RTW89_UKRAINE][14] = 32, ++ [2][1][RTW89_FCC][15] = 58, ++ [2][1][RTW89_ETSI][15] = 32, ++ [2][1][RTW89_MKK][15] = 58, ++ [2][1][RTW89_IC][15] = 58, ++ [2][1][RTW89_KCC][15] = 32, ++ [2][1][RTW89_ACMA][15] = 32, ++ [2][1][RTW89_CHILE][15] = 42, ++ [2][1][RTW89_UKRAINE][15] = 32, ++ [2][1][RTW89_FCC][17] = 58, ++ [2][1][RTW89_ETSI][17] = 32, ++ [2][1][RTW89_MKK][17] = 58, ++ [2][1][RTW89_IC][17] = 58, ++ [2][1][RTW89_KCC][17] = 32, ++ [2][1][RTW89_ACMA][17] = 32, ++ [2][1][RTW89_CHILE][17] = 42, ++ [2][1][RTW89_UKRAINE][17] = 32, ++ [2][1][RTW89_FCC][19] = 58, ++ [2][1][RTW89_ETSI][19] = 32, ++ [2][1][RTW89_MKK][19] = 58, ++ [2][1][RTW89_IC][19] = 58, ++ [2][1][RTW89_KCC][19] = 32, ++ [2][1][RTW89_ACMA][19] = 32, ++ [2][1][RTW89_CHILE][19] = 42, ++ [2][1][RTW89_UKRAINE][19] = 32, ++ [2][1][RTW89_FCC][21] = 58, ++ [2][1][RTW89_ETSI][21] = 32, ++ [2][1][RTW89_MKK][21] = 58, ++ [2][1][RTW89_IC][21] = 58, ++ [2][1][RTW89_KCC][21] = 32, ++ [2][1][RTW89_ACMA][21] = 32, ++ [2][1][RTW89_CHILE][21] = 42, ++ [2][1][RTW89_UKRAINE][21] = 32, ++ [2][1][RTW89_FCC][23] = 58, ++ [2][1][RTW89_ETSI][23] = 32, ++ [2][1][RTW89_MKK][23] = 58, ++ [2][1][RTW89_IC][23] = 58, ++ [2][1][RTW89_KCC][23] = 32, ++ [2][1][RTW89_ACMA][23] = 32, ++ [2][1][RTW89_CHILE][23] = 42, ++ [2][1][RTW89_UKRAINE][23] = 32, ++ [2][1][RTW89_FCC][25] = 58, ++ [2][1][RTW89_ETSI][25] = 32, ++ [2][1][RTW89_MKK][25] = 58, ++ [2][1][RTW89_IC][25] = 127, ++ [2][1][RTW89_KCC][25] = 32, ++ [2][1][RTW89_ACMA][25] = 127, ++ [2][1][RTW89_CHILE][25] = 42, ++ [2][1][RTW89_UKRAINE][25] = 32, ++ [2][1][RTW89_FCC][27] = 58, ++ [2][1][RTW89_ETSI][27] = 32, ++ [2][1][RTW89_MKK][27] = 58, ++ [2][1][RTW89_IC][27] = 127, ++ [2][1][RTW89_KCC][27] = 32, ++ [2][1][RTW89_ACMA][27] = 127, ++ [2][1][RTW89_CHILE][27] = 42, ++ [2][1][RTW89_UKRAINE][27] = 32, ++ [2][1][RTW89_FCC][29] = 58, ++ [2][1][RTW89_ETSI][29] = 32, ++ [2][1][RTW89_MKK][29] = 58, ++ [2][1][RTW89_IC][29] = 127, ++ [2][1][RTW89_KCC][29] = 32, ++ [2][1][RTW89_ACMA][29] = 127, ++ [2][1][RTW89_CHILE][29] = 42, ++ [2][1][RTW89_UKRAINE][29] = 32, ++ [2][1][RTW89_FCC][31] = 58, ++ [2][1][RTW89_ETSI][31] = 32, ++ [2][1][RTW89_MKK][31] = 58, ++ [2][1][RTW89_IC][31] = 58, ++ [2][1][RTW89_KCC][31] = 32, ++ [2][1][RTW89_ACMA][31] = 32, ++ [2][1][RTW89_CHILE][31] = 42, ++ [2][1][RTW89_UKRAINE][31] = 32, ++ [2][1][RTW89_FCC][33] = 58, ++ [2][1][RTW89_ETSI][33] = 32, ++ [2][1][RTW89_MKK][33] = 58, ++ [2][1][RTW89_IC][33] = 58, ++ [2][1][RTW89_KCC][33] = 32, ++ [2][1][RTW89_ACMA][33] = 32, ++ [2][1][RTW89_CHILE][33] = 42, ++ [2][1][RTW89_UKRAINE][33] = 32, ++ [2][1][RTW89_FCC][35] = 58, ++ [2][1][RTW89_ETSI][35] = 32, ++ [2][1][RTW89_MKK][35] = 58, ++ [2][1][RTW89_IC][35] = 58, ++ [2][1][RTW89_KCC][35] = 32, ++ [2][1][RTW89_ACMA][35] = 32, ++ [2][1][RTW89_CHILE][35] = 42, ++ [2][1][RTW89_UKRAINE][35] = 32, ++ [2][1][RTW89_FCC][37] = 58, ++ [2][1][RTW89_ETSI][37] = 127, ++ [2][1][RTW89_MKK][37] = 58, ++ [2][1][RTW89_IC][37] = 58, ++ [2][1][RTW89_KCC][37] = 32, ++ [2][1][RTW89_ACMA][37] = 62, ++ [2][1][RTW89_CHILE][37] = 42, ++ [2][1][RTW89_UKRAINE][37] = 127, ++ [2][1][RTW89_FCC][38] = 76, ++ [2][1][RTW89_ETSI][38] = 16, ++ [2][1][RTW89_MKK][38] = 127, ++ [2][1][RTW89_IC][38] = 76, ++ [2][1][RTW89_KCC][38] = 16, ++ [2][1][RTW89_ACMA][38] = 76, ++ [2][1][RTW89_CHILE][38] = 42, ++ [2][1][RTW89_UKRAINE][38] = 16, ++ [2][1][RTW89_FCC][40] = 76, ++ [2][1][RTW89_ETSI][40] = 16, ++ [2][1][RTW89_MKK][40] = 127, ++ [2][1][RTW89_IC][40] = 76, ++ [2][1][RTW89_KCC][40] = 16, ++ [2][1][RTW89_ACMA][40] = 76, ++ [2][1][RTW89_CHILE][40] = 42, ++ [2][1][RTW89_UKRAINE][40] = 16, ++ [2][1][RTW89_FCC][42] = 76, ++ [2][1][RTW89_ETSI][42] = 16, ++ [2][1][RTW89_MKK][42] = 127, ++ [2][1][RTW89_IC][42] = 76, ++ [2][1][RTW89_KCC][42] = 16, ++ [2][1][RTW89_ACMA][42] = 76, ++ [2][1][RTW89_CHILE][42] = 42, ++ [2][1][RTW89_UKRAINE][42] = 16, ++ [2][1][RTW89_FCC][44] = 76, ++ [2][1][RTW89_ETSI][44] = 16, ++ [2][1][RTW89_MKK][44] = 127, ++ [2][1][RTW89_IC][44] = 76, ++ [2][1][RTW89_KCC][44] = 16, ++ [2][1][RTW89_ACMA][44] = 76, ++ [2][1][RTW89_CHILE][44] = 42, ++ [2][1][RTW89_UKRAINE][44] = 16, ++ [2][1][RTW89_FCC][46] = 76, ++ [2][1][RTW89_ETSI][46] = 16, ++ [2][1][RTW89_MKK][46] = 127, ++ [2][1][RTW89_IC][46] = 76, ++ [2][1][RTW89_KCC][46] = 16, ++ [2][1][RTW89_ACMA][46] = 76, ++ [2][1][RTW89_CHILE][46] = 42, ++ [2][1][RTW89_UKRAINE][46] = 16, + }; + + #define DECLARE_DIG_TABLE(name) \ +-- +2.13.6 + diff --git a/SOURCES/0012-rtw89-update-rtw89-regulation-definition-to-R58-R31.patch b/SOURCES/0012-rtw89-update-rtw89-regulation-definition-to-R58-R31.patch new file mode 100644 index 0000000..1100127 --- /dev/null +++ b/SOURCES/0012-rtw89-update-rtw89-regulation-definition-to-R58-R31.patch @@ -0,0 +1,93 @@ +From 7613345d117cb43c93176775f2fd7cc06cdc8006 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 12/36] rtw89: update rtw89 regulation definition to R58-R31 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 542577149794b9c8638f6f2cb90b35b137b44156 +Author: Zong-Zhe Yang +Date: Mon Nov 1 17:31:04 2021 +0800 + + rtw89: update rtw89 regulation definition to R58-R31 + + Support QATAR in rtw89_regulation_type and reorder the enum to align + realtek R58-R31 regulation definition. Besides, if an unassigned entry + of limit/limit_ru tables is read, return the corresponding WW value for + the unconfigured case. + + Signed-off-by: Zong-Zhe Yang + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211101093106.28848-3-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/core.h | 9 +++++---- + drivers/net/wireless/realtek/rtw89/phy.c | 12 ++++++++++++ + 2 files changed, 17 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +index c2885e4dd882..3729abda04f9 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.h ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -411,12 +411,13 @@ enum rtw89_regulation_type { + RTW89_NA = 4, + RTW89_IC = 5, + RTW89_KCC = 6, +- RTW89_NCC = 7, +- RTW89_CHILE = 8, +- RTW89_ACMA = 9, +- RTW89_MEXICO = 10, ++ RTW89_ACMA = 7, ++ RTW89_NCC = 8, ++ RTW89_MEXICO = 9, ++ RTW89_CHILE = 10, + RTW89_UKRAINE = 11, + RTW89_CN = 12, ++ RTW89_QATAR = 13, + RTW89_REGD_NUM, + }; + +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +index ab134856baac..0620ef02e275 100644 +--- a/drivers/net/wireless/realtek/rtw89/phy.c ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -1099,9 +1099,15 @@ s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, + switch (band) { + case RTW89_BAND_2G: + lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; ++ if (!lmt) ++ lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] ++ [RTW89_WW][ch_idx]; + break; + case RTW89_BAND_5G: + lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; ++ if (!lmt) ++ lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] ++ [RTW89_WW][ch_idx]; + break; + default: + rtw89_warn(rtwdev, "unknown band type: %d\n", band); +@@ -1224,9 +1230,15 @@ static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, + switch (band) { + case RTW89_BAND_2G: + lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; ++ if (!lmt_ru) ++ lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] ++ [RTW89_WW][ch_idx]; + break; + case RTW89_BAND_5G: + lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; ++ if (!lmt_ru) ++ lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] ++ [RTW89_WW][ch_idx]; + break; + default: + rtw89_warn(rtwdev, "unknown band type: %d\n", band); +-- +2.13.6 + diff --git a/SOURCES/0013-rtw89-update-tx-power-limit-limit_ru-tables-to-R54.patch b/SOURCES/0013-rtw89-update-tx-power-limit-limit_ru-tables-to-R54.patch new file mode 100644 index 0000000..f1c80dd --- /dev/null +++ b/SOURCES/0013-rtw89-update-tx-power-limit-limit_ru-tables-to-R54.patch @@ -0,0 +1,7144 @@ +From 9d6bbdb6b26a2f7f0f8c64dd64af1aa69b3261d3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 13/36] rtw89: update tx power limit/limit_ru tables to R54 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit ebaae2c2c3bd5a6b15ed4a4f7a8a35b1989e24af +Author: Zong-Zhe Yang +Date: Mon Nov 1 17:31:05 2021 +0800 + + rtw89: update tx power limit/limit_ru tables to R54 + + Update tx power limit table and tx power limit_ru table to R54. + Configure entries for MEXICO, CN, QATAR, and adjust some values + of original entries. + + Signed-off-by: Zong-Zhe Yang + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211101093106.28848-4-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + .../net/wireless/realtek/rtw89/rtw8852a_table.c | 3083 +++++++++++++++----- + 1 file changed, 2413 insertions(+), 670 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +index c7ebeed043c5..253b5f8fc4f9 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a_table.c +@@ -43556,106 +43556,145 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][0][0][0][RTW89_ETSI][0] = 56, + [0][0][0][0][RTW89_MKK][0] = 68, + [0][0][0][0][RTW89_IC][0] = 76, +- [0][0][0][0][RTW89_KCC][0] = 56, ++ [0][0][0][0][RTW89_KCC][0] = 76, + [0][0][0][0][RTW89_ACMA][0] = 56, + [0][0][0][0][RTW89_CHILE][0] = 60, + [0][0][0][0][RTW89_UKRAINE][0] = 56, ++ [0][0][0][0][RTW89_MEXICO][0] = 76, ++ [0][0][0][0][RTW89_CN][0] = 56, ++ [0][0][0][0][RTW89_QATAR][0] = 56, + [0][0][0][0][RTW89_FCC][1] = 76, + [0][0][0][0][RTW89_ETSI][1] = 56, + [0][0][0][0][RTW89_MKK][1] = 68, + [0][0][0][0][RTW89_IC][1] = 76, +- [0][0][0][0][RTW89_KCC][1] = 56, ++ [0][0][0][0][RTW89_KCC][1] = 76, + [0][0][0][0][RTW89_ACMA][1] = 56, + [0][0][0][0][RTW89_CHILE][1] = 60, + [0][0][0][0][RTW89_UKRAINE][1] = 56, ++ [0][0][0][0][RTW89_MEXICO][1] = 76, ++ [0][0][0][0][RTW89_CN][1] = 56, ++ [0][0][0][0][RTW89_QATAR][1] = 56, + [0][0][0][0][RTW89_FCC][2] = 76, + [0][0][0][0][RTW89_ETSI][2] = 56, + [0][0][0][0][RTW89_MKK][2] = 68, + [0][0][0][0][RTW89_IC][2] = 76, +- [0][0][0][0][RTW89_KCC][2] = 56, ++ [0][0][0][0][RTW89_KCC][2] = 76, + [0][0][0][0][RTW89_ACMA][2] = 56, + [0][0][0][0][RTW89_CHILE][2] = 60, + [0][0][0][0][RTW89_UKRAINE][2] = 56, ++ [0][0][0][0][RTW89_MEXICO][2] = 76, ++ [0][0][0][0][RTW89_CN][2] = 56, ++ [0][0][0][0][RTW89_QATAR][2] = 56, + [0][0][0][0][RTW89_FCC][3] = 76, + [0][0][0][0][RTW89_ETSI][3] = 56, + [0][0][0][0][RTW89_MKK][3] = 68, + [0][0][0][0][RTW89_IC][3] = 76, +- [0][0][0][0][RTW89_KCC][3] = 56, ++ [0][0][0][0][RTW89_KCC][3] = 76, + [0][0][0][0][RTW89_ACMA][3] = 56, + [0][0][0][0][RTW89_CHILE][3] = 60, + [0][0][0][0][RTW89_UKRAINE][3] = 56, ++ [0][0][0][0][RTW89_MEXICO][3] = 76, ++ [0][0][0][0][RTW89_CN][3] = 56, ++ [0][0][0][0][RTW89_QATAR][3] = 56, + [0][0][0][0][RTW89_FCC][4] = 76, + [0][0][0][0][RTW89_ETSI][4] = 56, + [0][0][0][0][RTW89_MKK][4] = 68, + [0][0][0][0][RTW89_IC][4] = 76, +- [0][0][0][0][RTW89_KCC][4] = 56, ++ [0][0][0][0][RTW89_KCC][4] = 76, + [0][0][0][0][RTW89_ACMA][4] = 56, + [0][0][0][0][RTW89_CHILE][4] = 60, + [0][0][0][0][RTW89_UKRAINE][4] = 56, ++ [0][0][0][0][RTW89_MEXICO][4] = 76, ++ [0][0][0][0][RTW89_CN][4] = 56, ++ [0][0][0][0][RTW89_QATAR][4] = 56, + [0][0][0][0][RTW89_FCC][5] = 76, + [0][0][0][0][RTW89_ETSI][5] = 56, + [0][0][0][0][RTW89_MKK][5] = 68, + [0][0][0][0][RTW89_IC][5] = 76, +- [0][0][0][0][RTW89_KCC][5] = 56, ++ [0][0][0][0][RTW89_KCC][5] = 76, + [0][0][0][0][RTW89_ACMA][5] = 56, + [0][0][0][0][RTW89_CHILE][5] = 60, + [0][0][0][0][RTW89_UKRAINE][5] = 56, ++ [0][0][0][0][RTW89_MEXICO][5] = 76, ++ [0][0][0][0][RTW89_CN][5] = 56, ++ [0][0][0][0][RTW89_QATAR][5] = 56, + [0][0][0][0][RTW89_FCC][6] = 76, + [0][0][0][0][RTW89_ETSI][6] = 56, + [0][0][0][0][RTW89_MKK][6] = 68, + [0][0][0][0][RTW89_IC][6] = 76, +- [0][0][0][0][RTW89_KCC][6] = 56, ++ [0][0][0][0][RTW89_KCC][6] = 76, + [0][0][0][0][RTW89_ACMA][6] = 56, + [0][0][0][0][RTW89_CHILE][6] = 60, + [0][0][0][0][RTW89_UKRAINE][6] = 56, ++ [0][0][0][0][RTW89_MEXICO][6] = 76, ++ [0][0][0][0][RTW89_CN][6] = 56, ++ [0][0][0][0][RTW89_QATAR][6] = 56, + [0][0][0][0][RTW89_FCC][7] = 76, + [0][0][0][0][RTW89_ETSI][7] = 56, + [0][0][0][0][RTW89_MKK][7] = 68, + [0][0][0][0][RTW89_IC][7] = 76, +- [0][0][0][0][RTW89_KCC][7] = 56, ++ [0][0][0][0][RTW89_KCC][7] = 76, + [0][0][0][0][RTW89_ACMA][7] = 56, + [0][0][0][0][RTW89_CHILE][7] = 60, + [0][0][0][0][RTW89_UKRAINE][7] = 56, ++ [0][0][0][0][RTW89_MEXICO][7] = 76, ++ [0][0][0][0][RTW89_CN][7] = 56, ++ [0][0][0][0][RTW89_QATAR][7] = 56, + [0][0][0][0][RTW89_FCC][8] = 76, + [0][0][0][0][RTW89_ETSI][8] = 56, + [0][0][0][0][RTW89_MKK][8] = 68, + [0][0][0][0][RTW89_IC][8] = 76, +- [0][0][0][0][RTW89_KCC][8] = 56, ++ [0][0][0][0][RTW89_KCC][8] = 76, + [0][0][0][0][RTW89_ACMA][8] = 56, + [0][0][0][0][RTW89_CHILE][8] = 60, + [0][0][0][0][RTW89_UKRAINE][8] = 56, ++ [0][0][0][0][RTW89_MEXICO][8] = 76, ++ [0][0][0][0][RTW89_CN][8] = 56, ++ [0][0][0][0][RTW89_QATAR][8] = 56, + [0][0][0][0][RTW89_FCC][9] = 76, + [0][0][0][0][RTW89_ETSI][9] = 56, + [0][0][0][0][RTW89_MKK][9] = 68, + [0][0][0][0][RTW89_IC][9] = 76, +- [0][0][0][0][RTW89_KCC][9] = 56, ++ [0][0][0][0][RTW89_KCC][9] = 76, + [0][0][0][0][RTW89_ACMA][9] = 56, + [0][0][0][0][RTW89_CHILE][9] = 60, + [0][0][0][0][RTW89_UKRAINE][9] = 56, ++ [0][0][0][0][RTW89_MEXICO][9] = 76, ++ [0][0][0][0][RTW89_CN][9] = 56, ++ [0][0][0][0][RTW89_QATAR][9] = 56, + [0][0][0][0][RTW89_FCC][10] = 76, + [0][0][0][0][RTW89_ETSI][10] = 56, + [0][0][0][0][RTW89_MKK][10] = 68, + [0][0][0][0][RTW89_IC][10] = 76, +- [0][0][0][0][RTW89_KCC][10] = 56, ++ [0][0][0][0][RTW89_KCC][10] = 76, + [0][0][0][0][RTW89_ACMA][10] = 56, + [0][0][0][0][RTW89_CHILE][10] = 60, + [0][0][0][0][RTW89_UKRAINE][10] = 56, ++ [0][0][0][0][RTW89_MEXICO][10] = 76, ++ [0][0][0][0][RTW89_CN][10] = 56, ++ [0][0][0][0][RTW89_QATAR][10] = 56, + [0][0][0][0][RTW89_FCC][11] = 68, + [0][0][0][0][RTW89_ETSI][11] = 56, + [0][0][0][0][RTW89_MKK][11] = 68, + [0][0][0][0][RTW89_IC][11] = 68, +- [0][0][0][0][RTW89_KCC][11] = 56, ++ [0][0][0][0][RTW89_KCC][11] = 76, + [0][0][0][0][RTW89_ACMA][11] = 56, + [0][0][0][0][RTW89_CHILE][11] = 60, + [0][0][0][0][RTW89_UKRAINE][11] = 56, ++ [0][0][0][0][RTW89_MEXICO][11] = 68, ++ [0][0][0][0][RTW89_CN][11] = 56, ++ [0][0][0][0][RTW89_QATAR][11] = 56, + [0][0][0][0][RTW89_FCC][12] = 48, + [0][0][0][0][RTW89_ETSI][12] = 56, + [0][0][0][0][RTW89_MKK][12] = 68, + [0][0][0][0][RTW89_IC][12] = 48, +- [0][0][0][0][RTW89_KCC][12] = 56, ++ [0][0][0][0][RTW89_KCC][12] = 76, + [0][0][0][0][RTW89_ACMA][12] = 56, +- [0][0][0][0][RTW89_CHILE][12] = 60, ++ [0][0][0][0][RTW89_CHILE][12] = 48, + [0][0][0][0][RTW89_UKRAINE][12] = 56, ++ [0][0][0][0][RTW89_MEXICO][12] = 48, ++ [0][0][0][0][RTW89_CN][12] = 56, ++ [0][0][0][0][RTW89_QATAR][12] = 56, + [0][0][0][0][RTW89_FCC][13] = 127, + [0][0][0][0][RTW89_ETSI][13] = 127, + [0][0][0][0][RTW89_MKK][13] = 76, +@@ -43664,110 +43703,152 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][0][0][0][RTW89_ACMA][13] = 127, + [0][0][0][0][RTW89_CHILE][13] = 127, + [0][0][0][0][RTW89_UKRAINE][13] = 127, ++ [0][0][0][0][RTW89_MEXICO][13] = 127, ++ [0][0][0][0][RTW89_CN][13] = 127, ++ [0][0][0][0][RTW89_QATAR][13] = 127, + [0][1][0][0][RTW89_FCC][0] = 74, + [0][1][0][0][RTW89_ETSI][0] = 44, + [0][1][0][0][RTW89_MKK][0] = 56, + [0][1][0][0][RTW89_IC][0] = 74, +- [0][1][0][0][RTW89_KCC][0] = 44, ++ [0][1][0][0][RTW89_KCC][0] = 68, + [0][1][0][0][RTW89_ACMA][0] = 44, + [0][1][0][0][RTW89_CHILE][0] = 48, + [0][1][0][0][RTW89_UKRAINE][0] = 44, ++ [0][1][0][0][RTW89_MEXICO][0] = 74, ++ [0][1][0][0][RTW89_CN][0] = 44, ++ [0][1][0][0][RTW89_QATAR][0] = 44, + [0][1][0][0][RTW89_FCC][1] = 76, + [0][1][0][0][RTW89_ETSI][1] = 44, + [0][1][0][0][RTW89_MKK][1] = 56, + [0][1][0][0][RTW89_IC][1] = 76, +- [0][1][0][0][RTW89_KCC][1] = 44, ++ [0][1][0][0][RTW89_KCC][1] = 68, + [0][1][0][0][RTW89_ACMA][1] = 44, + [0][1][0][0][RTW89_CHILE][1] = 48, + [0][1][0][0][RTW89_UKRAINE][1] = 44, ++ [0][1][0][0][RTW89_MEXICO][1] = 76, ++ [0][1][0][0][RTW89_CN][1] = 44, ++ [0][1][0][0][RTW89_QATAR][1] = 44, + [0][1][0][0][RTW89_FCC][2] = 76, + [0][1][0][0][RTW89_ETSI][2] = 44, + [0][1][0][0][RTW89_MKK][2] = 56, + [0][1][0][0][RTW89_IC][2] = 76, +- [0][1][0][0][RTW89_KCC][2] = 44, ++ [0][1][0][0][RTW89_KCC][2] = 68, + [0][1][0][0][RTW89_ACMA][2] = 44, + [0][1][0][0][RTW89_CHILE][2] = 48, + [0][1][0][0][RTW89_UKRAINE][2] = 44, ++ [0][1][0][0][RTW89_MEXICO][2] = 76, ++ [0][1][0][0][RTW89_CN][2] = 44, ++ [0][1][0][0][RTW89_QATAR][2] = 44, + [0][1][0][0][RTW89_FCC][3] = 76, + [0][1][0][0][RTW89_ETSI][3] = 44, + [0][1][0][0][RTW89_MKK][3] = 56, + [0][1][0][0][RTW89_IC][3] = 76, +- [0][1][0][0][RTW89_KCC][3] = 44, ++ [0][1][0][0][RTW89_KCC][3] = 68, + [0][1][0][0][RTW89_ACMA][3] = 44, + [0][1][0][0][RTW89_CHILE][3] = 48, + [0][1][0][0][RTW89_UKRAINE][3] = 44, ++ [0][1][0][0][RTW89_MEXICO][3] = 76, ++ [0][1][0][0][RTW89_CN][3] = 44, ++ [0][1][0][0][RTW89_QATAR][3] = 44, + [0][1][0][0][RTW89_FCC][4] = 76, + [0][1][0][0][RTW89_ETSI][4] = 44, + [0][1][0][0][RTW89_MKK][4] = 56, + [0][1][0][0][RTW89_IC][4] = 76, +- [0][1][0][0][RTW89_KCC][4] = 44, ++ [0][1][0][0][RTW89_KCC][4] = 68, + [0][1][0][0][RTW89_ACMA][4] = 44, + [0][1][0][0][RTW89_CHILE][4] = 48, + [0][1][0][0][RTW89_UKRAINE][4] = 44, ++ [0][1][0][0][RTW89_MEXICO][4] = 76, ++ [0][1][0][0][RTW89_CN][4] = 44, ++ [0][1][0][0][RTW89_QATAR][4] = 44, + [0][1][0][0][RTW89_FCC][5] = 76, + [0][1][0][0][RTW89_ETSI][5] = 44, + [0][1][0][0][RTW89_MKK][5] = 56, + [0][1][0][0][RTW89_IC][5] = 76, +- [0][1][0][0][RTW89_KCC][5] = 44, ++ [0][1][0][0][RTW89_KCC][5] = 68, + [0][1][0][0][RTW89_ACMA][5] = 44, + [0][1][0][0][RTW89_CHILE][5] = 48, + [0][1][0][0][RTW89_UKRAINE][5] = 44, ++ [0][1][0][0][RTW89_MEXICO][5] = 76, ++ [0][1][0][0][RTW89_CN][5] = 44, ++ [0][1][0][0][RTW89_QATAR][5] = 44, + [0][1][0][0][RTW89_FCC][6] = 76, + [0][1][0][0][RTW89_ETSI][6] = 44, + [0][1][0][0][RTW89_MKK][6] = 56, + [0][1][0][0][RTW89_IC][6] = 76, +- [0][1][0][0][RTW89_KCC][6] = 44, ++ [0][1][0][0][RTW89_KCC][6] = 68, + [0][1][0][0][RTW89_ACMA][6] = 44, + [0][1][0][0][RTW89_CHILE][6] = 48, + [0][1][0][0][RTW89_UKRAINE][6] = 44, ++ [0][1][0][0][RTW89_MEXICO][6] = 76, ++ [0][1][0][0][RTW89_CN][6] = 44, ++ [0][1][0][0][RTW89_QATAR][6] = 44, + [0][1][0][0][RTW89_FCC][7] = 76, + [0][1][0][0][RTW89_ETSI][7] = 44, + [0][1][0][0][RTW89_MKK][7] = 56, + [0][1][0][0][RTW89_IC][7] = 76, +- [0][1][0][0][RTW89_KCC][7] = 44, ++ [0][1][0][0][RTW89_KCC][7] = 68, + [0][1][0][0][RTW89_ACMA][7] = 44, + [0][1][0][0][RTW89_CHILE][7] = 48, + [0][1][0][0][RTW89_UKRAINE][7] = 44, ++ [0][1][0][0][RTW89_MEXICO][7] = 76, ++ [0][1][0][0][RTW89_CN][7] = 44, ++ [0][1][0][0][RTW89_QATAR][7] = 44, + [0][1][0][0][RTW89_FCC][8] = 76, + [0][1][0][0][RTW89_ETSI][8] = 44, + [0][1][0][0][RTW89_MKK][8] = 56, + [0][1][0][0][RTW89_IC][8] = 76, +- [0][1][0][0][RTW89_KCC][8] = 44, ++ [0][1][0][0][RTW89_KCC][8] = 68, + [0][1][0][0][RTW89_ACMA][8] = 44, + [0][1][0][0][RTW89_CHILE][8] = 48, + [0][1][0][0][RTW89_UKRAINE][8] = 44, ++ [0][1][0][0][RTW89_MEXICO][8] = 76, ++ [0][1][0][0][RTW89_CN][8] = 44, ++ [0][1][0][0][RTW89_QATAR][8] = 44, + [0][1][0][0][RTW89_FCC][9] = 76, + [0][1][0][0][RTW89_ETSI][9] = 44, + [0][1][0][0][RTW89_MKK][9] = 56, + [0][1][0][0][RTW89_IC][9] = 76, +- [0][1][0][0][RTW89_KCC][9] = 44, ++ [0][1][0][0][RTW89_KCC][9] = 68, + [0][1][0][0][RTW89_ACMA][9] = 44, + [0][1][0][0][RTW89_CHILE][9] = 48, + [0][1][0][0][RTW89_UKRAINE][9] = 44, ++ [0][1][0][0][RTW89_MEXICO][9] = 76, ++ [0][1][0][0][RTW89_CN][9] = 44, ++ [0][1][0][0][RTW89_QATAR][9] = 44, + [0][1][0][0][RTW89_FCC][10] = 62, + [0][1][0][0][RTW89_ETSI][10] = 44, + [0][1][0][0][RTW89_MKK][10] = 56, + [0][1][0][0][RTW89_IC][10] = 62, +- [0][1][0][0][RTW89_KCC][10] = 44, ++ [0][1][0][0][RTW89_KCC][10] = 68, + [0][1][0][0][RTW89_ACMA][10] = 44, + [0][1][0][0][RTW89_CHILE][10] = 48, + [0][1][0][0][RTW89_UKRAINE][10] = 44, ++ [0][1][0][0][RTW89_MEXICO][10] = 62, ++ [0][1][0][0][RTW89_CN][10] = 44, ++ [0][1][0][0][RTW89_QATAR][10] = 44, + [0][1][0][0][RTW89_FCC][11] = 52, + [0][1][0][0][RTW89_ETSI][11] = 44, + [0][1][0][0][RTW89_MKK][11] = 56, + [0][1][0][0][RTW89_IC][11] = 52, +- [0][1][0][0][RTW89_KCC][11] = 44, ++ [0][1][0][0][RTW89_KCC][11] = 68, + [0][1][0][0][RTW89_ACMA][11] = 44, + [0][1][0][0][RTW89_CHILE][11] = 48, + [0][1][0][0][RTW89_UKRAINE][11] = 44, ++ [0][1][0][0][RTW89_MEXICO][11] = 52, ++ [0][1][0][0][RTW89_CN][11] = 44, ++ [0][1][0][0][RTW89_QATAR][11] = 44, + [0][1][0][0][RTW89_FCC][12] = 38, + [0][1][0][0][RTW89_ETSI][12] = 44, + [0][1][0][0][RTW89_MKK][12] = 56, + [0][1][0][0][RTW89_IC][12] = 38, +- [0][1][0][0][RTW89_KCC][12] = 44, ++ [0][1][0][0][RTW89_KCC][12] = 68, + [0][1][0][0][RTW89_ACMA][12] = 44, +- [0][1][0][0][RTW89_CHILE][12] = 48, ++ [0][1][0][0][RTW89_CHILE][12] = 38, + [0][1][0][0][RTW89_UKRAINE][12] = 44, ++ [0][1][0][0][RTW89_MEXICO][12] = 38, ++ [0][1][0][0][RTW89_CN][12] = 44, ++ [0][1][0][0][RTW89_QATAR][12] = 44, + [0][1][0][0][RTW89_FCC][13] = 127, + [0][1][0][0][RTW89_ETSI][13] = 127, + [0][1][0][0][RTW89_MKK][13] = 64, +@@ -43776,6 +43857,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][1][0][0][RTW89_ACMA][13] = 127, + [0][1][0][0][RTW89_CHILE][13] = 127, + [0][1][0][0][RTW89_UKRAINE][13] = 127, ++ [0][1][0][0][RTW89_MEXICO][13] = 127, ++ [0][1][0][0][RTW89_CN][13] = 127, ++ [0][1][0][0][RTW89_QATAR][13] = 127, + [1][0][0][0][RTW89_FCC][0] = 127, + [1][0][0][0][RTW89_ETSI][0] = 127, + [1][0][0][0][RTW89_MKK][0] = 127, +@@ -43784,6 +43868,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][0][0][RTW89_ACMA][0] = 127, + [1][0][0][0][RTW89_CHILE][0] = 127, + [1][0][0][0][RTW89_UKRAINE][0] = 127, ++ [1][0][0][0][RTW89_MEXICO][0] = 127, ++ [1][0][0][0][RTW89_CN][0] = 127, ++ [1][0][0][0][RTW89_QATAR][0] = 127, + [1][0][0][0][RTW89_FCC][1] = 127, + [1][0][0][0][RTW89_ETSI][1] = 127, + [1][0][0][0][RTW89_MKK][1] = 127, +@@ -43792,78 +43879,108 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][0][0][RTW89_ACMA][1] = 127, + [1][0][0][0][RTW89_CHILE][1] = 127, + [1][0][0][0][RTW89_UKRAINE][1] = 127, ++ [1][0][0][0][RTW89_MEXICO][1] = 127, ++ [1][0][0][0][RTW89_CN][1] = 127, ++ [1][0][0][0][RTW89_QATAR][1] = 127, + [1][0][0][0][RTW89_FCC][2] = 60, + [1][0][0][0][RTW89_ETSI][2] = 58, + [1][0][0][0][RTW89_MKK][2] = 68, + [1][0][0][0][RTW89_IC][2] = 60, +- [1][0][0][0][RTW89_KCC][2] = 58, ++ [1][0][0][0][RTW89_KCC][2] = 70, + [1][0][0][0][RTW89_ACMA][2] = 58, + [1][0][0][0][RTW89_CHILE][2] = 60, + [1][0][0][0][RTW89_UKRAINE][2] = 58, ++ [1][0][0][0][RTW89_MEXICO][2] = 60, ++ [1][0][0][0][RTW89_CN][2] = 58, ++ [1][0][0][0][RTW89_QATAR][2] = 58, + [1][0][0][0][RTW89_FCC][3] = 60, + [1][0][0][0][RTW89_ETSI][3] = 58, + [1][0][0][0][RTW89_MKK][3] = 68, + [1][0][0][0][RTW89_IC][3] = 60, +- [1][0][0][0][RTW89_KCC][3] = 58, ++ [1][0][0][0][RTW89_KCC][3] = 70, + [1][0][0][0][RTW89_ACMA][3] = 58, + [1][0][0][0][RTW89_CHILE][3] = 60, + [1][0][0][0][RTW89_UKRAINE][3] = 58, ++ [1][0][0][0][RTW89_MEXICO][3] = 60, ++ [1][0][0][0][RTW89_CN][3] = 58, ++ [1][0][0][0][RTW89_QATAR][3] = 58, + [1][0][0][0][RTW89_FCC][4] = 60, + [1][0][0][0][RTW89_ETSI][4] = 58, + [1][0][0][0][RTW89_MKK][4] = 68, + [1][0][0][0][RTW89_IC][4] = 60, +- [1][0][0][0][RTW89_KCC][4] = 58, ++ [1][0][0][0][RTW89_KCC][4] = 70, + [1][0][0][0][RTW89_ACMA][4] = 58, + [1][0][0][0][RTW89_CHILE][4] = 60, + [1][0][0][0][RTW89_UKRAINE][4] = 58, ++ [1][0][0][0][RTW89_MEXICO][4] = 60, ++ [1][0][0][0][RTW89_CN][4] = 58, ++ [1][0][0][0][RTW89_QATAR][4] = 58, + [1][0][0][0][RTW89_FCC][5] = 60, + [1][0][0][0][RTW89_ETSI][5] = 58, + [1][0][0][0][RTW89_MKK][5] = 68, + [1][0][0][0][RTW89_IC][5] = 60, +- [1][0][0][0][RTW89_KCC][5] = 58, ++ [1][0][0][0][RTW89_KCC][5] = 70, + [1][0][0][0][RTW89_ACMA][5] = 58, + [1][0][0][0][RTW89_CHILE][5] = 60, + [1][0][0][0][RTW89_UKRAINE][5] = 58, ++ [1][0][0][0][RTW89_MEXICO][5] = 60, ++ [1][0][0][0][RTW89_CN][5] = 58, ++ [1][0][0][0][RTW89_QATAR][5] = 58, + [1][0][0][0][RTW89_FCC][6] = 46, + [1][0][0][0][RTW89_ETSI][6] = 58, + [1][0][0][0][RTW89_MKK][6] = 68, + [1][0][0][0][RTW89_IC][6] = 46, +- [1][0][0][0][RTW89_KCC][6] = 58, ++ [1][0][0][0][RTW89_KCC][6] = 70, + [1][0][0][0][RTW89_ACMA][6] = 58, +- [1][0][0][0][RTW89_CHILE][6] = 60, ++ [1][0][0][0][RTW89_CHILE][6] = 46, + [1][0][0][0][RTW89_UKRAINE][6] = 58, ++ [1][0][0][0][RTW89_MEXICO][6] = 46, ++ [1][0][0][0][RTW89_CN][6] = 58, ++ [1][0][0][0][RTW89_QATAR][6] = 58, + [1][0][0][0][RTW89_FCC][7] = 46, + [1][0][0][0][RTW89_ETSI][7] = 58, + [1][0][0][0][RTW89_MKK][7] = 68, + [1][0][0][0][RTW89_IC][7] = 46, +- [1][0][0][0][RTW89_KCC][7] = 58, ++ [1][0][0][0][RTW89_KCC][7] = 70, + [1][0][0][0][RTW89_ACMA][7] = 58, +- [1][0][0][0][RTW89_CHILE][7] = 60, ++ [1][0][0][0][RTW89_CHILE][7] = 46, + [1][0][0][0][RTW89_UKRAINE][7] = 58, ++ [1][0][0][0][RTW89_MEXICO][7] = 46, ++ [1][0][0][0][RTW89_CN][7] = 58, ++ [1][0][0][0][RTW89_QATAR][7] = 58, + [1][0][0][0][RTW89_FCC][8] = 46, + [1][0][0][0][RTW89_ETSI][8] = 58, + [1][0][0][0][RTW89_MKK][8] = 68, + [1][0][0][0][RTW89_IC][8] = 46, +- [1][0][0][0][RTW89_KCC][8] = 58, ++ [1][0][0][0][RTW89_KCC][8] = 70, + [1][0][0][0][RTW89_ACMA][8] = 58, +- [1][0][0][0][RTW89_CHILE][8] = 60, ++ [1][0][0][0][RTW89_CHILE][8] = 46, + [1][0][0][0][RTW89_UKRAINE][8] = 58, ++ [1][0][0][0][RTW89_MEXICO][8] = 46, ++ [1][0][0][0][RTW89_CN][8] = 58, ++ [1][0][0][0][RTW89_QATAR][8] = 58, + [1][0][0][0][RTW89_FCC][9] = 32, + [1][0][0][0][RTW89_ETSI][9] = 58, + [1][0][0][0][RTW89_MKK][9] = 68, + [1][0][0][0][RTW89_IC][9] = 32, +- [1][0][0][0][RTW89_KCC][9] = 58, ++ [1][0][0][0][RTW89_KCC][9] = 70, + [1][0][0][0][RTW89_ACMA][9] = 58, +- [1][0][0][0][RTW89_CHILE][9] = 60, ++ [1][0][0][0][RTW89_CHILE][9] = 32, + [1][0][0][0][RTW89_UKRAINE][9] = 58, ++ [1][0][0][0][RTW89_MEXICO][9] = 32, ++ [1][0][0][0][RTW89_CN][9] = 58, ++ [1][0][0][0][RTW89_QATAR][9] = 58, + [1][0][0][0][RTW89_FCC][10] = 32, + [1][0][0][0][RTW89_ETSI][10] = 58, + [1][0][0][0][RTW89_MKK][10] = 68, + [1][0][0][0][RTW89_IC][10] = 32, +- [1][0][0][0][RTW89_KCC][10] = 58, ++ [1][0][0][0][RTW89_KCC][10] = 70, + [1][0][0][0][RTW89_ACMA][10] = 58, +- [1][0][0][0][RTW89_CHILE][10] = 60, ++ [1][0][0][0][RTW89_CHILE][10] = 32, + [1][0][0][0][RTW89_UKRAINE][10] = 58, ++ [1][0][0][0][RTW89_MEXICO][10] = 32, ++ [1][0][0][0][RTW89_CN][10] = 58, ++ [1][0][0][0][RTW89_QATAR][10] = 58, + [1][0][0][0][RTW89_FCC][11] = 127, + [1][0][0][0][RTW89_ETSI][11] = 127, + [1][0][0][0][RTW89_MKK][11] = 127, +@@ -43872,6 +43989,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][0][0][RTW89_ACMA][11] = 127, + [1][0][0][0][RTW89_CHILE][11] = 127, + [1][0][0][0][RTW89_UKRAINE][11] = 127, ++ [1][0][0][0][RTW89_MEXICO][11] = 127, ++ [1][0][0][0][RTW89_CN][11] = 127, ++ [1][0][0][0][RTW89_QATAR][11] = 127, + [1][0][0][0][RTW89_FCC][12] = 127, + [1][0][0][0][RTW89_ETSI][12] = 127, + [1][0][0][0][RTW89_MKK][12] = 127, +@@ -43880,6 +44000,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][0][0][RTW89_ACMA][12] = 127, + [1][0][0][0][RTW89_CHILE][12] = 127, + [1][0][0][0][RTW89_UKRAINE][12] = 127, ++ [1][0][0][0][RTW89_MEXICO][12] = 127, ++ [1][0][0][0][RTW89_CN][12] = 127, ++ [1][0][0][0][RTW89_QATAR][12] = 127, + [1][0][0][0][RTW89_FCC][13] = 127, + [1][0][0][0][RTW89_ETSI][13] = 127, + [1][0][0][0][RTW89_MKK][13] = 127, +@@ -43888,6 +44011,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][0][0][RTW89_ACMA][13] = 127, + [1][0][0][0][RTW89_CHILE][13] = 127, + [1][0][0][0][RTW89_UKRAINE][13] = 127, ++ [1][0][0][0][RTW89_MEXICO][13] = 127, ++ [1][0][0][0][RTW89_CN][13] = 127, ++ [1][0][0][0][RTW89_QATAR][13] = 127, + [1][1][0][0][RTW89_FCC][0] = 127, + [1][1][0][0][RTW89_ETSI][0] = 127, + [1][1][0][0][RTW89_MKK][0] = 127, +@@ -43896,6 +44022,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][0][0][RTW89_ACMA][0] = 127, + [1][1][0][0][RTW89_CHILE][0] = 127, + [1][1][0][0][RTW89_UKRAINE][0] = 127, ++ [1][1][0][0][RTW89_MEXICO][0] = 127, ++ [1][1][0][0][RTW89_CN][0] = 127, ++ [1][1][0][0][RTW89_QATAR][0] = 127, + [1][1][0][0][RTW89_FCC][1] = 127, + [1][1][0][0][RTW89_ETSI][1] = 127, + [1][1][0][0][RTW89_MKK][1] = 127, +@@ -43904,78 +44033,108 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][0][0][RTW89_ACMA][1] = 127, + [1][1][0][0][RTW89_CHILE][1] = 127, + [1][1][0][0][RTW89_UKRAINE][1] = 127, ++ [1][1][0][0][RTW89_MEXICO][1] = 127, ++ [1][1][0][0][RTW89_CN][1] = 127, ++ [1][1][0][0][RTW89_QATAR][1] = 127, + [1][1][0][0][RTW89_FCC][2] = 48, + [1][1][0][0][RTW89_ETSI][2] = 46, + [1][1][0][0][RTW89_MKK][2] = 56, + [1][1][0][0][RTW89_IC][2] = 48, +- [1][1][0][0][RTW89_KCC][2] = 46, ++ [1][1][0][0][RTW89_KCC][2] = 58, + [1][1][0][0][RTW89_ACMA][2] = 46, + [1][1][0][0][RTW89_CHILE][2] = 48, + [1][1][0][0][RTW89_UKRAINE][2] = 46, ++ [1][1][0][0][RTW89_MEXICO][2] = 48, ++ [1][1][0][0][RTW89_CN][2] = 46, ++ [1][1][0][0][RTW89_QATAR][2] = 46, + [1][1][0][0][RTW89_FCC][3] = 48, + [1][1][0][0][RTW89_ETSI][3] = 46, + [1][1][0][0][RTW89_MKK][3] = 56, + [1][1][0][0][RTW89_IC][3] = 48, +- [1][1][0][0][RTW89_KCC][3] = 46, ++ [1][1][0][0][RTW89_KCC][3] = 58, + [1][1][0][0][RTW89_ACMA][3] = 46, + [1][1][0][0][RTW89_CHILE][3] = 48, + [1][1][0][0][RTW89_UKRAINE][3] = 46, ++ [1][1][0][0][RTW89_MEXICO][3] = 48, ++ [1][1][0][0][RTW89_CN][3] = 46, ++ [1][1][0][0][RTW89_QATAR][3] = 46, + [1][1][0][0][RTW89_FCC][4] = 48, + [1][1][0][0][RTW89_ETSI][4] = 46, + [1][1][0][0][RTW89_MKK][4] = 56, + [1][1][0][0][RTW89_IC][4] = 48, +- [1][1][0][0][RTW89_KCC][4] = 46, ++ [1][1][0][0][RTW89_KCC][4] = 58, + [1][1][0][0][RTW89_ACMA][4] = 46, + [1][1][0][0][RTW89_CHILE][4] = 48, + [1][1][0][0][RTW89_UKRAINE][4] = 46, ++ [1][1][0][0][RTW89_MEXICO][4] = 48, ++ [1][1][0][0][RTW89_CN][4] = 46, ++ [1][1][0][0][RTW89_QATAR][4] = 46, + [1][1][0][0][RTW89_FCC][5] = 58, + [1][1][0][0][RTW89_ETSI][5] = 46, + [1][1][0][0][RTW89_MKK][5] = 56, + [1][1][0][0][RTW89_IC][5] = 58, +- [1][1][0][0][RTW89_KCC][5] = 46, ++ [1][1][0][0][RTW89_KCC][5] = 58, + [1][1][0][0][RTW89_ACMA][5] = 46, + [1][1][0][0][RTW89_CHILE][5] = 48, + [1][1][0][0][RTW89_UKRAINE][5] = 46, ++ [1][1][0][0][RTW89_MEXICO][5] = 58, ++ [1][1][0][0][RTW89_CN][5] = 46, ++ [1][1][0][0][RTW89_QATAR][5] = 46, + [1][1][0][0][RTW89_FCC][6] = 46, + [1][1][0][0][RTW89_ETSI][6] = 46, + [1][1][0][0][RTW89_MKK][6] = 56, + [1][1][0][0][RTW89_IC][6] = 46, +- [1][1][0][0][RTW89_KCC][6] = 46, ++ [1][1][0][0][RTW89_KCC][6] = 58, + [1][1][0][0][RTW89_ACMA][6] = 46, +- [1][1][0][0][RTW89_CHILE][6] = 48, ++ [1][1][0][0][RTW89_CHILE][6] = 46, + [1][1][0][0][RTW89_UKRAINE][6] = 46, ++ [1][1][0][0][RTW89_MEXICO][6] = 46, ++ [1][1][0][0][RTW89_CN][6] = 46, ++ [1][1][0][0][RTW89_QATAR][6] = 46, + [1][1][0][0][RTW89_FCC][7] = 46, + [1][1][0][0][RTW89_ETSI][7] = 46, + [1][1][0][0][RTW89_MKK][7] = 56, + [1][1][0][0][RTW89_IC][7] = 46, +- [1][1][0][0][RTW89_KCC][7] = 46, ++ [1][1][0][0][RTW89_KCC][7] = 58, + [1][1][0][0][RTW89_ACMA][7] = 46, +- [1][1][0][0][RTW89_CHILE][7] = 48, ++ [1][1][0][0][RTW89_CHILE][7] = 46, + [1][1][0][0][RTW89_UKRAINE][7] = 46, ++ [1][1][0][0][RTW89_MEXICO][7] = 46, ++ [1][1][0][0][RTW89_CN][7] = 46, ++ [1][1][0][0][RTW89_QATAR][7] = 46, + [1][1][0][0][RTW89_FCC][8] = 46, + [1][1][0][0][RTW89_ETSI][8] = 46, + [1][1][0][0][RTW89_MKK][8] = 56, + [1][1][0][0][RTW89_IC][8] = 46, +- [1][1][0][0][RTW89_KCC][8] = 46, ++ [1][1][0][0][RTW89_KCC][8] = 58, + [1][1][0][0][RTW89_ACMA][8] = 46, +- [1][1][0][0][RTW89_CHILE][8] = 48, ++ [1][1][0][0][RTW89_CHILE][8] = 46, + [1][1][0][0][RTW89_UKRAINE][8] = 46, ++ [1][1][0][0][RTW89_MEXICO][8] = 46, ++ [1][1][0][0][RTW89_CN][8] = 46, ++ [1][1][0][0][RTW89_QATAR][8] = 46, + [1][1][0][0][RTW89_FCC][9] = 24, + [1][1][0][0][RTW89_ETSI][9] = 46, + [1][1][0][0][RTW89_MKK][9] = 56, + [1][1][0][0][RTW89_IC][9] = 24, +- [1][1][0][0][RTW89_KCC][9] = 46, ++ [1][1][0][0][RTW89_KCC][9] = 58, + [1][1][0][0][RTW89_ACMA][9] = 46, +- [1][1][0][0][RTW89_CHILE][9] = 48, ++ [1][1][0][0][RTW89_CHILE][9] = 24, + [1][1][0][0][RTW89_UKRAINE][9] = 46, ++ [1][1][0][0][RTW89_MEXICO][9] = 24, ++ [1][1][0][0][RTW89_CN][9] = 46, ++ [1][1][0][0][RTW89_QATAR][9] = 46, + [1][1][0][0][RTW89_FCC][10] = 24, + [1][1][0][0][RTW89_ETSI][10] = 46, + [1][1][0][0][RTW89_MKK][10] = 56, + [1][1][0][0][RTW89_IC][10] = 24, +- [1][1][0][0][RTW89_KCC][10] = 46, ++ [1][1][0][0][RTW89_KCC][10] = 58, + [1][1][0][0][RTW89_ACMA][10] = 46, +- [1][1][0][0][RTW89_CHILE][10] = 48, ++ [1][1][0][0][RTW89_CHILE][10] = 24, + [1][1][0][0][RTW89_UKRAINE][10] = 46, ++ [1][1][0][0][RTW89_MEXICO][10] = 24, ++ [1][1][0][0][RTW89_CN][10] = 46, ++ [1][1][0][0][RTW89_QATAR][10] = 46, + [1][1][0][0][RTW89_FCC][11] = 127, + [1][1][0][0][RTW89_ETSI][11] = 127, + [1][1][0][0][RTW89_MKK][11] = 127, +@@ -43984,6 +44143,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][0][0][RTW89_ACMA][11] = 127, + [1][1][0][0][RTW89_CHILE][11] = 127, + [1][1][0][0][RTW89_UKRAINE][11] = 127, ++ [1][1][0][0][RTW89_MEXICO][11] = 127, ++ [1][1][0][0][RTW89_CN][11] = 127, ++ [1][1][0][0][RTW89_QATAR][11] = 127, + [1][1][0][0][RTW89_FCC][12] = 127, + [1][1][0][0][RTW89_ETSI][12] = 127, + [1][1][0][0][RTW89_MKK][12] = 127, +@@ -43992,6 +44154,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][0][0][RTW89_ACMA][12] = 127, + [1][1][0][0][RTW89_CHILE][12] = 127, + [1][1][0][0][RTW89_UKRAINE][12] = 127, ++ [1][1][0][0][RTW89_MEXICO][12] = 127, ++ [1][1][0][0][RTW89_CN][12] = 127, ++ [1][1][0][0][RTW89_QATAR][12] = 127, + [1][1][0][0][RTW89_FCC][13] = 127, + [1][1][0][0][RTW89_ETSI][13] = 127, + [1][1][0][0][RTW89_MKK][13] = 127, +@@ -44000,110 +44165,152 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][0][0][RTW89_ACMA][13] = 127, + [1][1][0][0][RTW89_CHILE][13] = 127, + [1][1][0][0][RTW89_UKRAINE][13] = 127, ++ [1][1][0][0][RTW89_MEXICO][13] = 127, ++ [1][1][0][0][RTW89_CN][13] = 127, ++ [1][1][0][0][RTW89_QATAR][13] = 127, + [0][0][1][0][RTW89_FCC][0] = 66, + [0][0][1][0][RTW89_ETSI][0] = 58, + [0][0][1][0][RTW89_MKK][0] = 76, + [0][0][1][0][RTW89_IC][0] = 66, +- [0][0][1][0][RTW89_KCC][0] = 58, ++ [0][0][1][0][RTW89_KCC][0] = 76, + [0][0][1][0][RTW89_ACMA][0] = 58, + [0][0][1][0][RTW89_CHILE][0] = 60, + [0][0][1][0][RTW89_UKRAINE][0] = 58, ++ [0][0][1][0][RTW89_MEXICO][0] = 66, ++ [0][0][1][0][RTW89_CN][0] = 58, ++ [0][0][1][0][RTW89_QATAR][0] = 58, + [0][0][1][0][RTW89_FCC][1] = 66, + [0][0][1][0][RTW89_ETSI][1] = 58, + [0][0][1][0][RTW89_MKK][1] = 76, + [0][0][1][0][RTW89_IC][1] = 66, +- [0][0][1][0][RTW89_KCC][1] = 58, ++ [0][0][1][0][RTW89_KCC][1] = 76, + [0][0][1][0][RTW89_ACMA][1] = 58, + [0][0][1][0][RTW89_CHILE][1] = 60, + [0][0][1][0][RTW89_UKRAINE][1] = 58, ++ [0][0][1][0][RTW89_MEXICO][1] = 66, ++ [0][0][1][0][RTW89_CN][1] = 58, ++ [0][0][1][0][RTW89_QATAR][1] = 58, + [0][0][1][0][RTW89_FCC][2] = 70, + [0][0][1][0][RTW89_ETSI][2] = 58, + [0][0][1][0][RTW89_MKK][2] = 76, + [0][0][1][0][RTW89_IC][2] = 70, +- [0][0][1][0][RTW89_KCC][2] = 58, ++ [0][0][1][0][RTW89_KCC][2] = 76, + [0][0][1][0][RTW89_ACMA][2] = 58, + [0][0][1][0][RTW89_CHILE][2] = 60, + [0][0][1][0][RTW89_UKRAINE][2] = 58, ++ [0][0][1][0][RTW89_MEXICO][2] = 70, ++ [0][0][1][0][RTW89_CN][2] = 58, ++ [0][0][1][0][RTW89_QATAR][2] = 58, + [0][0][1][0][RTW89_FCC][3] = 74, + [0][0][1][0][RTW89_ETSI][3] = 58, + [0][0][1][0][RTW89_MKK][3] = 76, + [0][0][1][0][RTW89_IC][3] = 74, +- [0][0][1][0][RTW89_KCC][3] = 58, ++ [0][0][1][0][RTW89_KCC][3] = 76, + [0][0][1][0][RTW89_ACMA][3] = 58, + [0][0][1][0][RTW89_CHILE][3] = 60, + [0][0][1][0][RTW89_UKRAINE][3] = 58, ++ [0][0][1][0][RTW89_MEXICO][3] = 74, ++ [0][0][1][0][RTW89_CN][3] = 58, ++ [0][0][1][0][RTW89_QATAR][3] = 58, + [0][0][1][0][RTW89_FCC][4] = 78, + [0][0][1][0][RTW89_ETSI][4] = 58, + [0][0][1][0][RTW89_MKK][4] = 76, + [0][0][1][0][RTW89_IC][4] = 78, +- [0][0][1][0][RTW89_KCC][4] = 58, ++ [0][0][1][0][RTW89_KCC][4] = 76, + [0][0][1][0][RTW89_ACMA][4] = 58, + [0][0][1][0][RTW89_CHILE][4] = 60, + [0][0][1][0][RTW89_UKRAINE][4] = 58, ++ [0][0][1][0][RTW89_MEXICO][4] = 78, ++ [0][0][1][0][RTW89_CN][4] = 58, ++ [0][0][1][0][RTW89_QATAR][4] = 58, + [0][0][1][0][RTW89_FCC][5] = 78, + [0][0][1][0][RTW89_ETSI][5] = 58, + [0][0][1][0][RTW89_MKK][5] = 76, + [0][0][1][0][RTW89_IC][5] = 78, +- [0][0][1][0][RTW89_KCC][5] = 58, ++ [0][0][1][0][RTW89_KCC][5] = 76, + [0][0][1][0][RTW89_ACMA][5] = 58, + [0][0][1][0][RTW89_CHILE][5] = 60, + [0][0][1][0][RTW89_UKRAINE][5] = 58, ++ [0][0][1][0][RTW89_MEXICO][5] = 78, ++ [0][0][1][0][RTW89_CN][5] = 58, ++ [0][0][1][0][RTW89_QATAR][5] = 58, + [0][0][1][0][RTW89_FCC][6] = 78, + [0][0][1][0][RTW89_ETSI][6] = 58, + [0][0][1][0][RTW89_MKK][6] = 76, + [0][0][1][0][RTW89_IC][6] = 78, +- [0][0][1][0][RTW89_KCC][6] = 58, ++ [0][0][1][0][RTW89_KCC][6] = 76, + [0][0][1][0][RTW89_ACMA][6] = 58, + [0][0][1][0][RTW89_CHILE][6] = 60, + [0][0][1][0][RTW89_UKRAINE][6] = 58, ++ [0][0][1][0][RTW89_MEXICO][6] = 78, ++ [0][0][1][0][RTW89_CN][6] = 58, ++ [0][0][1][0][RTW89_QATAR][6] = 58, + [0][0][1][0][RTW89_FCC][7] = 74, + [0][0][1][0][RTW89_ETSI][7] = 58, + [0][0][1][0][RTW89_MKK][7] = 76, + [0][0][1][0][RTW89_IC][7] = 74, +- [0][0][1][0][RTW89_KCC][7] = 58, ++ [0][0][1][0][RTW89_KCC][7] = 76, + [0][0][1][0][RTW89_ACMA][7] = 58, + [0][0][1][0][RTW89_CHILE][7] = 60, + [0][0][1][0][RTW89_UKRAINE][7] = 58, ++ [0][0][1][0][RTW89_MEXICO][7] = 74, ++ [0][0][1][0][RTW89_CN][7] = 58, ++ [0][0][1][0][RTW89_QATAR][7] = 58, + [0][0][1][0][RTW89_FCC][8] = 70, + [0][0][1][0][RTW89_ETSI][8] = 58, + [0][0][1][0][RTW89_MKK][8] = 76, + [0][0][1][0][RTW89_IC][8] = 70, +- [0][0][1][0][RTW89_KCC][8] = 58, ++ [0][0][1][0][RTW89_KCC][8] = 76, + [0][0][1][0][RTW89_ACMA][8] = 58, + [0][0][1][0][RTW89_CHILE][8] = 60, + [0][0][1][0][RTW89_UKRAINE][8] = 58, ++ [0][0][1][0][RTW89_MEXICO][8] = 70, ++ [0][0][1][0][RTW89_CN][8] = 58, ++ [0][0][1][0][RTW89_QATAR][8] = 58, + [0][0][1][0][RTW89_FCC][9] = 66, + [0][0][1][0][RTW89_ETSI][9] = 58, + [0][0][1][0][RTW89_MKK][9] = 76, + [0][0][1][0][RTW89_IC][9] = 66, +- [0][0][1][0][RTW89_KCC][9] = 58, ++ [0][0][1][0][RTW89_KCC][9] = 76, + [0][0][1][0][RTW89_ACMA][9] = 58, + [0][0][1][0][RTW89_CHILE][9] = 60, + [0][0][1][0][RTW89_UKRAINE][9] = 58, ++ [0][0][1][0][RTW89_MEXICO][9] = 66, ++ [0][0][1][0][RTW89_CN][9] = 58, ++ [0][0][1][0][RTW89_QATAR][9] = 58, + [0][0][1][0][RTW89_FCC][10] = 66, + [0][0][1][0][RTW89_ETSI][10] = 58, + [0][0][1][0][RTW89_MKK][10] = 76, + [0][0][1][0][RTW89_IC][10] = 66, +- [0][0][1][0][RTW89_KCC][10] = 58, ++ [0][0][1][0][RTW89_KCC][10] = 76, + [0][0][1][0][RTW89_ACMA][10] = 58, + [0][0][1][0][RTW89_CHILE][10] = 60, + [0][0][1][0][RTW89_UKRAINE][10] = 58, ++ [0][0][1][0][RTW89_MEXICO][10] = 66, ++ [0][0][1][0][RTW89_CN][10] = 58, ++ [0][0][1][0][RTW89_QATAR][10] = 58, + [0][0][1][0][RTW89_FCC][11] = 56, + [0][0][1][0][RTW89_ETSI][11] = 58, + [0][0][1][0][RTW89_MKK][11] = 76, + [0][0][1][0][RTW89_IC][11] = 56, +- [0][0][1][0][RTW89_KCC][11] = 58, ++ [0][0][1][0][RTW89_KCC][11] = 76, + [0][0][1][0][RTW89_ACMA][11] = 58, +- [0][0][1][0][RTW89_CHILE][11] = 60, ++ [0][0][1][0][RTW89_CHILE][11] = 56, + [0][0][1][0][RTW89_UKRAINE][11] = 58, ++ [0][0][1][0][RTW89_MEXICO][11] = 56, ++ [0][0][1][0][RTW89_CN][11] = 58, ++ [0][0][1][0][RTW89_QATAR][11] = 58, + [0][0][1][0][RTW89_FCC][12] = 52, + [0][0][1][0][RTW89_ETSI][12] = 58, + [0][0][1][0][RTW89_MKK][12] = 76, + [0][0][1][0][RTW89_IC][12] = 52, +- [0][0][1][0][RTW89_KCC][12] = 58, ++ [0][0][1][0][RTW89_KCC][12] = 76, + [0][0][1][0][RTW89_ACMA][12] = 58, +- [0][0][1][0][RTW89_CHILE][12] = 60, ++ [0][0][1][0][RTW89_CHILE][12] = 52, + [0][0][1][0][RTW89_UKRAINE][12] = 58, ++ [0][0][1][0][RTW89_MEXICO][12] = 52, ++ [0][0][1][0][RTW89_CN][12] = 58, ++ [0][0][1][0][RTW89_QATAR][12] = 58, + [0][0][1][0][RTW89_FCC][13] = 127, + [0][0][1][0][RTW89_ETSI][13] = 127, + [0][0][1][0][RTW89_MKK][13] = 127, +@@ -44112,110 +44319,152 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][0][1][0][RTW89_ACMA][13] = 127, + [0][0][1][0][RTW89_CHILE][13] = 127, + [0][0][1][0][RTW89_UKRAINE][13] = 127, ++ [0][0][1][0][RTW89_MEXICO][13] = 127, ++ [0][0][1][0][RTW89_CN][13] = 127, ++ [0][0][1][0][RTW89_QATAR][13] = 127, + [0][1][1][0][RTW89_FCC][0] = 62, + [0][1][1][0][RTW89_ETSI][0] = 46, + [0][1][1][0][RTW89_MKK][0] = 64, + [0][1][1][0][RTW89_IC][0] = 62, +- [0][1][1][0][RTW89_KCC][0] = 46, ++ [0][1][1][0][RTW89_KCC][0] = 70, + [0][1][1][0][RTW89_ACMA][0] = 46, + [0][1][1][0][RTW89_CHILE][0] = 48, + [0][1][1][0][RTW89_UKRAINE][0] = 46, ++ [0][1][1][0][RTW89_MEXICO][0] = 62, ++ [0][1][1][0][RTW89_CN][0] = 46, ++ [0][1][1][0][RTW89_QATAR][0] = 46, + [0][1][1][0][RTW89_FCC][1] = 62, + [0][1][1][0][RTW89_ETSI][1] = 46, + [0][1][1][0][RTW89_MKK][1] = 64, + [0][1][1][0][RTW89_IC][1] = 62, +- [0][1][1][0][RTW89_KCC][1] = 46, ++ [0][1][1][0][RTW89_KCC][1] = 70, + [0][1][1][0][RTW89_ACMA][1] = 46, + [0][1][1][0][RTW89_CHILE][1] = 48, + [0][1][1][0][RTW89_UKRAINE][1] = 46, ++ [0][1][1][0][RTW89_MEXICO][1] = 62, ++ [0][1][1][0][RTW89_CN][1] = 46, ++ [0][1][1][0][RTW89_QATAR][1] = 46, + [0][1][1][0][RTW89_FCC][2] = 66, + [0][1][1][0][RTW89_ETSI][2] = 46, + [0][1][1][0][RTW89_MKK][2] = 64, + [0][1][1][0][RTW89_IC][2] = 66, +- [0][1][1][0][RTW89_KCC][2] = 46, ++ [0][1][1][0][RTW89_KCC][2] = 70, + [0][1][1][0][RTW89_ACMA][2] = 46, + [0][1][1][0][RTW89_CHILE][2] = 48, + [0][1][1][0][RTW89_UKRAINE][2] = 46, ++ [0][1][1][0][RTW89_MEXICO][2] = 66, ++ [0][1][1][0][RTW89_CN][2] = 46, ++ [0][1][1][0][RTW89_QATAR][2] = 46, + [0][1][1][0][RTW89_FCC][3] = 70, + [0][1][1][0][RTW89_ETSI][3] = 46, + [0][1][1][0][RTW89_MKK][3] = 64, + [0][1][1][0][RTW89_IC][3] = 70, +- [0][1][1][0][RTW89_KCC][3] = 46, ++ [0][1][1][0][RTW89_KCC][3] = 70, + [0][1][1][0][RTW89_ACMA][3] = 46, + [0][1][1][0][RTW89_CHILE][3] = 48, + [0][1][1][0][RTW89_UKRAINE][3] = 46, ++ [0][1][1][0][RTW89_MEXICO][3] = 70, ++ [0][1][1][0][RTW89_CN][3] = 46, ++ [0][1][1][0][RTW89_QATAR][3] = 46, + [0][1][1][0][RTW89_FCC][4] = 78, + [0][1][1][0][RTW89_ETSI][4] = 46, + [0][1][1][0][RTW89_MKK][4] = 64, + [0][1][1][0][RTW89_IC][4] = 78, +- [0][1][1][0][RTW89_KCC][4] = 46, ++ [0][1][1][0][RTW89_KCC][4] = 70, + [0][1][1][0][RTW89_ACMA][4] = 46, + [0][1][1][0][RTW89_CHILE][4] = 48, + [0][1][1][0][RTW89_UKRAINE][4] = 46, ++ [0][1][1][0][RTW89_MEXICO][4] = 78, ++ [0][1][1][0][RTW89_CN][4] = 46, ++ [0][1][1][0][RTW89_QATAR][4] = 46, + [0][1][1][0][RTW89_FCC][5] = 78, + [0][1][1][0][RTW89_ETSI][5] = 46, + [0][1][1][0][RTW89_MKK][5] = 64, + [0][1][1][0][RTW89_IC][5] = 78, +- [0][1][1][0][RTW89_KCC][5] = 46, ++ [0][1][1][0][RTW89_KCC][5] = 70, + [0][1][1][0][RTW89_ACMA][5] = 46, + [0][1][1][0][RTW89_CHILE][5] = 48, + [0][1][1][0][RTW89_UKRAINE][5] = 46, ++ [0][1][1][0][RTW89_MEXICO][5] = 78, ++ [0][1][1][0][RTW89_CN][5] = 46, ++ [0][1][1][0][RTW89_QATAR][5] = 46, + [0][1][1][0][RTW89_FCC][6] = 78, + [0][1][1][0][RTW89_ETSI][6] = 46, + [0][1][1][0][RTW89_MKK][6] = 64, + [0][1][1][0][RTW89_IC][6] = 78, +- [0][1][1][0][RTW89_KCC][6] = 46, ++ [0][1][1][0][RTW89_KCC][6] = 70, + [0][1][1][0][RTW89_ACMA][6] = 46, + [0][1][1][0][RTW89_CHILE][6] = 48, + [0][1][1][0][RTW89_UKRAINE][6] = 46, ++ [0][1][1][0][RTW89_MEXICO][6] = 78, ++ [0][1][1][0][RTW89_CN][6] = 46, ++ [0][1][1][0][RTW89_QATAR][6] = 46, + [0][1][1][0][RTW89_FCC][7] = 70, + [0][1][1][0][RTW89_ETSI][7] = 46, + [0][1][1][0][RTW89_MKK][7] = 64, + [0][1][1][0][RTW89_IC][7] = 70, +- [0][1][1][0][RTW89_KCC][7] = 46, ++ [0][1][1][0][RTW89_KCC][7] = 70, + [0][1][1][0][RTW89_ACMA][7] = 46, + [0][1][1][0][RTW89_CHILE][7] = 48, + [0][1][1][0][RTW89_UKRAINE][7] = 46, ++ [0][1][1][0][RTW89_MEXICO][7] = 70, ++ [0][1][1][0][RTW89_CN][7] = 46, ++ [0][1][1][0][RTW89_QATAR][7] = 46, + [0][1][1][0][RTW89_FCC][8] = 66, + [0][1][1][0][RTW89_ETSI][8] = 46, + [0][1][1][0][RTW89_MKK][8] = 64, + [0][1][1][0][RTW89_IC][8] = 66, +- [0][1][1][0][RTW89_KCC][8] = 46, ++ [0][1][1][0][RTW89_KCC][8] = 70, + [0][1][1][0][RTW89_ACMA][8] = 46, + [0][1][1][0][RTW89_CHILE][8] = 48, + [0][1][1][0][RTW89_UKRAINE][8] = 46, ++ [0][1][1][0][RTW89_MEXICO][8] = 66, ++ [0][1][1][0][RTW89_CN][8] = 46, ++ [0][1][1][0][RTW89_QATAR][8] = 46, + [0][1][1][0][RTW89_FCC][9] = 62, + [0][1][1][0][RTW89_ETSI][9] = 46, + [0][1][1][0][RTW89_MKK][9] = 64, + [0][1][1][0][RTW89_IC][9] = 62, +- [0][1][1][0][RTW89_KCC][9] = 46, ++ [0][1][1][0][RTW89_KCC][9] = 70, + [0][1][1][0][RTW89_ACMA][9] = 46, + [0][1][1][0][RTW89_CHILE][9] = 48, + [0][1][1][0][RTW89_UKRAINE][9] = 46, ++ [0][1][1][0][RTW89_MEXICO][9] = 62, ++ [0][1][1][0][RTW89_CN][9] = 46, ++ [0][1][1][0][RTW89_QATAR][9] = 46, + [0][1][1][0][RTW89_FCC][10] = 62, + [0][1][1][0][RTW89_ETSI][10] = 46, + [0][1][1][0][RTW89_MKK][10] = 64, + [0][1][1][0][RTW89_IC][10] = 62, +- [0][1][1][0][RTW89_KCC][10] = 46, ++ [0][1][1][0][RTW89_KCC][10] = 70, + [0][1][1][0][RTW89_ACMA][10] = 46, + [0][1][1][0][RTW89_CHILE][10] = 48, + [0][1][1][0][RTW89_UKRAINE][10] = 46, ++ [0][1][1][0][RTW89_MEXICO][10] = 62, ++ [0][1][1][0][RTW89_CN][10] = 46, ++ [0][1][1][0][RTW89_QATAR][10] = 46, + [0][1][1][0][RTW89_FCC][11] = 42, + [0][1][1][0][RTW89_ETSI][11] = 46, + [0][1][1][0][RTW89_MKK][11] = 64, + [0][1][1][0][RTW89_IC][11] = 42, +- [0][1][1][0][RTW89_KCC][11] = 46, ++ [0][1][1][0][RTW89_KCC][11] = 70, + [0][1][1][0][RTW89_ACMA][11] = 46, +- [0][1][1][0][RTW89_CHILE][11] = 48, ++ [0][1][1][0][RTW89_CHILE][11] = 42, + [0][1][1][0][RTW89_UKRAINE][11] = 46, ++ [0][1][1][0][RTW89_MEXICO][11] = 42, ++ [0][1][1][0][RTW89_CN][11] = 46, ++ [0][1][1][0][RTW89_QATAR][11] = 46, + [0][1][1][0][RTW89_FCC][12] = 40, + [0][1][1][0][RTW89_ETSI][12] = 46, + [0][1][1][0][RTW89_MKK][12] = 64, + [0][1][1][0][RTW89_IC][12] = 40, +- [0][1][1][0][RTW89_KCC][12] = 46, ++ [0][1][1][0][RTW89_KCC][12] = 70, + [0][1][1][0][RTW89_ACMA][12] = 46, +- [0][1][1][0][RTW89_CHILE][12] = 48, ++ [0][1][1][0][RTW89_CHILE][12] = 40, + [0][1][1][0][RTW89_UKRAINE][12] = 46, ++ [0][1][1][0][RTW89_MEXICO][12] = 40, ++ [0][1][1][0][RTW89_CN][12] = 46, ++ [0][1][1][0][RTW89_QATAR][12] = 46, + [0][1][1][0][RTW89_FCC][13] = 127, + [0][1][1][0][RTW89_ETSI][13] = 127, + [0][1][1][0][RTW89_MKK][13] = 127, +@@ -44224,110 +44473,152 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][1][1][0][RTW89_ACMA][13] = 127, + [0][1][1][0][RTW89_CHILE][13] = 127, + [0][1][1][0][RTW89_UKRAINE][13] = 127, ++ [0][1][1][0][RTW89_MEXICO][13] = 127, ++ [0][1][1][0][RTW89_CN][13] = 127, ++ [0][1][1][0][RTW89_QATAR][13] = 127, + [0][0][2][0][RTW89_FCC][0] = 66, + [0][0][2][0][RTW89_ETSI][0] = 58, + [0][0][2][0][RTW89_MKK][0] = 76, + [0][0][2][0][RTW89_IC][0] = 66, +- [0][0][2][0][RTW89_KCC][0] = 58, ++ [0][0][2][0][RTW89_KCC][0] = 76, + [0][0][2][0][RTW89_ACMA][0] = 58, + [0][0][2][0][RTW89_CHILE][0] = 60, + [0][0][2][0][RTW89_UKRAINE][0] = 58, ++ [0][0][2][0][RTW89_MEXICO][0] = 66, ++ [0][0][2][0][RTW89_CN][0] = 58, ++ [0][0][2][0][RTW89_QATAR][0] = 58, + [0][0][2][0][RTW89_FCC][1] = 66, + [0][0][2][0][RTW89_ETSI][1] = 58, + [0][0][2][0][RTW89_MKK][1] = 76, + [0][0][2][0][RTW89_IC][1] = 66, +- [0][0][2][0][RTW89_KCC][1] = 58, ++ [0][0][2][0][RTW89_KCC][1] = 76, + [0][0][2][0][RTW89_ACMA][1] = 58, + [0][0][2][0][RTW89_CHILE][1] = 60, + [0][0][2][0][RTW89_UKRAINE][1] = 58, ++ [0][0][2][0][RTW89_MEXICO][1] = 66, ++ [0][0][2][0][RTW89_CN][1] = 58, ++ [0][0][2][0][RTW89_QATAR][1] = 58, + [0][0][2][0][RTW89_FCC][2] = 70, + [0][0][2][0][RTW89_ETSI][2] = 58, + [0][0][2][0][RTW89_MKK][2] = 76, + [0][0][2][0][RTW89_IC][2] = 70, +- [0][0][2][0][RTW89_KCC][2] = 58, ++ [0][0][2][0][RTW89_KCC][2] = 76, + [0][0][2][0][RTW89_ACMA][2] = 58, + [0][0][2][0][RTW89_CHILE][2] = 60, + [0][0][2][0][RTW89_UKRAINE][2] = 58, ++ [0][0][2][0][RTW89_MEXICO][2] = 70, ++ [0][0][2][0][RTW89_CN][2] = 58, ++ [0][0][2][0][RTW89_QATAR][2] = 58, + [0][0][2][0][RTW89_FCC][3] = 74, + [0][0][2][0][RTW89_ETSI][3] = 58, + [0][0][2][0][RTW89_MKK][3] = 76, + [0][0][2][0][RTW89_IC][3] = 74, +- [0][0][2][0][RTW89_KCC][3] = 58, ++ [0][0][2][0][RTW89_KCC][3] = 76, + [0][0][2][0][RTW89_ACMA][3] = 58, + [0][0][2][0][RTW89_CHILE][3] = 60, + [0][0][2][0][RTW89_UKRAINE][3] = 58, ++ [0][0][2][0][RTW89_MEXICO][3] = 74, ++ [0][0][2][0][RTW89_CN][3] = 58, ++ [0][0][2][0][RTW89_QATAR][3] = 58, + [0][0][2][0][RTW89_FCC][4] = 76, + [0][0][2][0][RTW89_ETSI][4] = 58, + [0][0][2][0][RTW89_MKK][4] = 76, + [0][0][2][0][RTW89_IC][4] = 76, +- [0][0][2][0][RTW89_KCC][4] = 58, ++ [0][0][2][0][RTW89_KCC][4] = 76, + [0][0][2][0][RTW89_ACMA][4] = 58, + [0][0][2][0][RTW89_CHILE][4] = 60, + [0][0][2][0][RTW89_UKRAINE][4] = 58, ++ [0][0][2][0][RTW89_MEXICO][4] = 76, ++ [0][0][2][0][RTW89_CN][4] = 58, ++ [0][0][2][0][RTW89_QATAR][4] = 58, + [0][0][2][0][RTW89_FCC][5] = 76, + [0][0][2][0][RTW89_ETSI][5] = 58, + [0][0][2][0][RTW89_MKK][5] = 76, + [0][0][2][0][RTW89_IC][5] = 76, +- [0][0][2][0][RTW89_KCC][5] = 58, ++ [0][0][2][0][RTW89_KCC][5] = 76, + [0][0][2][0][RTW89_ACMA][5] = 58, + [0][0][2][0][RTW89_CHILE][5] = 60, + [0][0][2][0][RTW89_UKRAINE][5] = 58, ++ [0][0][2][0][RTW89_MEXICO][5] = 76, ++ [0][0][2][0][RTW89_CN][5] = 58, ++ [0][0][2][0][RTW89_QATAR][5] = 58, + [0][0][2][0][RTW89_FCC][6] = 76, + [0][0][2][0][RTW89_ETSI][6] = 58, + [0][0][2][0][RTW89_MKK][6] = 76, + [0][0][2][0][RTW89_IC][6] = 76, +- [0][0][2][0][RTW89_KCC][6] = 58, ++ [0][0][2][0][RTW89_KCC][6] = 76, + [0][0][2][0][RTW89_ACMA][6] = 58, + [0][0][2][0][RTW89_CHILE][6] = 60, + [0][0][2][0][RTW89_UKRAINE][6] = 58, ++ [0][0][2][0][RTW89_MEXICO][6] = 76, ++ [0][0][2][0][RTW89_CN][6] = 58, ++ [0][0][2][0][RTW89_QATAR][6] = 58, + [0][0][2][0][RTW89_FCC][7] = 74, + [0][0][2][0][RTW89_ETSI][7] = 58, + [0][0][2][0][RTW89_MKK][7] = 76, + [0][0][2][0][RTW89_IC][7] = 74, +- [0][0][2][0][RTW89_KCC][7] = 58, ++ [0][0][2][0][RTW89_KCC][7] = 76, + [0][0][2][0][RTW89_ACMA][7] = 58, + [0][0][2][0][RTW89_CHILE][7] = 60, + [0][0][2][0][RTW89_UKRAINE][7] = 58, ++ [0][0][2][0][RTW89_MEXICO][7] = 74, ++ [0][0][2][0][RTW89_CN][7] = 58, ++ [0][0][2][0][RTW89_QATAR][7] = 58, + [0][0][2][0][RTW89_FCC][8] = 70, + [0][0][2][0][RTW89_ETSI][8] = 58, + [0][0][2][0][RTW89_MKK][8] = 76, + [0][0][2][0][RTW89_IC][8] = 70, +- [0][0][2][0][RTW89_KCC][8] = 58, ++ [0][0][2][0][RTW89_KCC][8] = 76, + [0][0][2][0][RTW89_ACMA][8] = 58, + [0][0][2][0][RTW89_CHILE][8] = 60, + [0][0][2][0][RTW89_UKRAINE][8] = 58, ++ [0][0][2][0][RTW89_MEXICO][8] = 70, ++ [0][0][2][0][RTW89_CN][8] = 58, ++ [0][0][2][0][RTW89_QATAR][8] = 58, + [0][0][2][0][RTW89_FCC][9] = 66, + [0][0][2][0][RTW89_ETSI][9] = 58, + [0][0][2][0][RTW89_MKK][9] = 76, + [0][0][2][0][RTW89_IC][9] = 66, +- [0][0][2][0][RTW89_KCC][9] = 58, ++ [0][0][2][0][RTW89_KCC][9] = 76, + [0][0][2][0][RTW89_ACMA][9] = 58, + [0][0][2][0][RTW89_CHILE][9] = 60, + [0][0][2][0][RTW89_UKRAINE][9] = 58, ++ [0][0][2][0][RTW89_MEXICO][9] = 66, ++ [0][0][2][0][RTW89_CN][9] = 58, ++ [0][0][2][0][RTW89_QATAR][9] = 58, + [0][0][2][0][RTW89_FCC][10] = 66, + [0][0][2][0][RTW89_ETSI][10] = 58, + [0][0][2][0][RTW89_MKK][10] = 76, + [0][0][2][0][RTW89_IC][10] = 66, +- [0][0][2][0][RTW89_KCC][10] = 58, ++ [0][0][2][0][RTW89_KCC][10] = 76, + [0][0][2][0][RTW89_ACMA][10] = 58, + [0][0][2][0][RTW89_CHILE][10] = 60, + [0][0][2][0][RTW89_UKRAINE][10] = 58, ++ [0][0][2][0][RTW89_MEXICO][10] = 66, ++ [0][0][2][0][RTW89_CN][10] = 58, ++ [0][0][2][0][RTW89_QATAR][10] = 58, + [0][0][2][0][RTW89_FCC][11] = 54, + [0][0][2][0][RTW89_ETSI][11] = 58, + [0][0][2][0][RTW89_MKK][11] = 76, + [0][0][2][0][RTW89_IC][11] = 54, +- [0][0][2][0][RTW89_KCC][11] = 58, ++ [0][0][2][0][RTW89_KCC][11] = 76, + [0][0][2][0][RTW89_ACMA][11] = 58, +- [0][0][2][0][RTW89_CHILE][11] = 60, ++ [0][0][2][0][RTW89_CHILE][11] = 54, + [0][0][2][0][RTW89_UKRAINE][11] = 58, ++ [0][0][2][0][RTW89_MEXICO][11] = 54, ++ [0][0][2][0][RTW89_CN][11] = 58, ++ [0][0][2][0][RTW89_QATAR][11] = 58, + [0][0][2][0][RTW89_FCC][12] = 50, + [0][0][2][0][RTW89_ETSI][12] = 58, + [0][0][2][0][RTW89_MKK][12] = 76, + [0][0][2][0][RTW89_IC][12] = 50, +- [0][0][2][0][RTW89_KCC][12] = 58, ++ [0][0][2][0][RTW89_KCC][12] = 74, + [0][0][2][0][RTW89_ACMA][12] = 58, +- [0][0][2][0][RTW89_CHILE][12] = 60, ++ [0][0][2][0][RTW89_CHILE][12] = 50, + [0][0][2][0][RTW89_UKRAINE][12] = 58, ++ [0][0][2][0][RTW89_MEXICO][12] = 50, ++ [0][0][2][0][RTW89_CN][12] = 58, ++ [0][0][2][0][RTW89_QATAR][12] = 58, + [0][0][2][0][RTW89_FCC][13] = 127, + [0][0][2][0][RTW89_ETSI][13] = 127, + [0][0][2][0][RTW89_MKK][13] = 127, +@@ -44336,110 +44627,152 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][0][2][0][RTW89_ACMA][13] = 127, + [0][0][2][0][RTW89_CHILE][13] = 127, + [0][0][2][0][RTW89_UKRAINE][13] = 127, ++ [0][0][2][0][RTW89_MEXICO][13] = 127, ++ [0][0][2][0][RTW89_CN][13] = 127, ++ [0][0][2][0][RTW89_QATAR][13] = 127, + [0][1][2][0][RTW89_FCC][0] = 62, + [0][1][2][0][RTW89_ETSI][0] = 46, + [0][1][2][0][RTW89_MKK][0] = 64, + [0][1][2][0][RTW89_IC][0] = 62, +- [0][1][2][0][RTW89_KCC][0] = 46, ++ [0][1][2][0][RTW89_KCC][0] = 68, + [0][1][2][0][RTW89_ACMA][0] = 46, + [0][1][2][0][RTW89_CHILE][0] = 48, + [0][1][2][0][RTW89_UKRAINE][0] = 46, ++ [0][1][2][0][RTW89_MEXICO][0] = 62, ++ [0][1][2][0][RTW89_CN][0] = 46, ++ [0][1][2][0][RTW89_QATAR][0] = 46, + [0][1][2][0][RTW89_FCC][1] = 62, + [0][1][2][0][RTW89_ETSI][1] = 46, + [0][1][2][0][RTW89_MKK][1] = 64, + [0][1][2][0][RTW89_IC][1] = 62, +- [0][1][2][0][RTW89_KCC][1] = 46, ++ [0][1][2][0][RTW89_KCC][1] = 70, + [0][1][2][0][RTW89_ACMA][1] = 46, + [0][1][2][0][RTW89_CHILE][1] = 48, + [0][1][2][0][RTW89_UKRAINE][1] = 46, ++ [0][1][2][0][RTW89_MEXICO][1] = 62, ++ [0][1][2][0][RTW89_CN][1] = 46, ++ [0][1][2][0][RTW89_QATAR][1] = 46, + [0][1][2][0][RTW89_FCC][2] = 66, + [0][1][2][0][RTW89_ETSI][2] = 46, + [0][1][2][0][RTW89_MKK][2] = 64, + [0][1][2][0][RTW89_IC][2] = 66, +- [0][1][2][0][RTW89_KCC][2] = 46, ++ [0][1][2][0][RTW89_KCC][2] = 70, + [0][1][2][0][RTW89_ACMA][2] = 46, + [0][1][2][0][RTW89_CHILE][2] = 48, + [0][1][2][0][RTW89_UKRAINE][2] = 46, ++ [0][1][2][0][RTW89_MEXICO][2] = 66, ++ [0][1][2][0][RTW89_CN][2] = 46, ++ [0][1][2][0][RTW89_QATAR][2] = 46, + [0][1][2][0][RTW89_FCC][3] = 70, + [0][1][2][0][RTW89_ETSI][3] = 46, + [0][1][2][0][RTW89_MKK][3] = 64, + [0][1][2][0][RTW89_IC][3] = 70, +- [0][1][2][0][RTW89_KCC][3] = 46, ++ [0][1][2][0][RTW89_KCC][3] = 70, + [0][1][2][0][RTW89_ACMA][3] = 46, + [0][1][2][0][RTW89_CHILE][3] = 48, + [0][1][2][0][RTW89_UKRAINE][3] = 46, ++ [0][1][2][0][RTW89_MEXICO][3] = 70, ++ [0][1][2][0][RTW89_CN][3] = 46, ++ [0][1][2][0][RTW89_QATAR][3] = 46, + [0][1][2][0][RTW89_FCC][4] = 76, + [0][1][2][0][RTW89_ETSI][4] = 46, + [0][1][2][0][RTW89_MKK][4] = 64, + [0][1][2][0][RTW89_IC][4] = 76, +- [0][1][2][0][RTW89_KCC][4] = 46, ++ [0][1][2][0][RTW89_KCC][4] = 70, + [0][1][2][0][RTW89_ACMA][4] = 46, + [0][1][2][0][RTW89_CHILE][4] = 48, + [0][1][2][0][RTW89_UKRAINE][4] = 46, ++ [0][1][2][0][RTW89_MEXICO][4] = 76, ++ [0][1][2][0][RTW89_CN][4] = 46, ++ [0][1][2][0][RTW89_QATAR][4] = 46, + [0][1][2][0][RTW89_FCC][5] = 76, + [0][1][2][0][RTW89_ETSI][5] = 46, + [0][1][2][0][RTW89_MKK][5] = 64, + [0][1][2][0][RTW89_IC][5] = 76, +- [0][1][2][0][RTW89_KCC][5] = 46, ++ [0][1][2][0][RTW89_KCC][5] = 70, + [0][1][2][0][RTW89_ACMA][5] = 46, + [0][1][2][0][RTW89_CHILE][5] = 48, + [0][1][2][0][RTW89_UKRAINE][5] = 46, ++ [0][1][2][0][RTW89_MEXICO][5] = 76, ++ [0][1][2][0][RTW89_CN][5] = 46, ++ [0][1][2][0][RTW89_QATAR][5] = 46, + [0][1][2][0][RTW89_FCC][6] = 76, + [0][1][2][0][RTW89_ETSI][6] = 46, + [0][1][2][0][RTW89_MKK][6] = 64, + [0][1][2][0][RTW89_IC][6] = 76, +- [0][1][2][0][RTW89_KCC][6] = 46, ++ [0][1][2][0][RTW89_KCC][6] = 70, + [0][1][2][0][RTW89_ACMA][6] = 46, + [0][1][2][0][RTW89_CHILE][6] = 48, + [0][1][2][0][RTW89_UKRAINE][6] = 46, ++ [0][1][2][0][RTW89_MEXICO][6] = 76, ++ [0][1][2][0][RTW89_CN][6] = 46, ++ [0][1][2][0][RTW89_QATAR][6] = 46, + [0][1][2][0][RTW89_FCC][7] = 68, + [0][1][2][0][RTW89_ETSI][7] = 46, + [0][1][2][0][RTW89_MKK][7] = 64, + [0][1][2][0][RTW89_IC][7] = 68, +- [0][1][2][0][RTW89_KCC][7] = 46, ++ [0][1][2][0][RTW89_KCC][7] = 70, + [0][1][2][0][RTW89_ACMA][7] = 46, + [0][1][2][0][RTW89_CHILE][7] = 48, + [0][1][2][0][RTW89_UKRAINE][7] = 46, ++ [0][1][2][0][RTW89_MEXICO][7] = 68, ++ [0][1][2][0][RTW89_CN][7] = 46, ++ [0][1][2][0][RTW89_QATAR][7] = 46, + [0][1][2][0][RTW89_FCC][8] = 64, + [0][1][2][0][RTW89_ETSI][8] = 46, + [0][1][2][0][RTW89_MKK][8] = 64, + [0][1][2][0][RTW89_IC][8] = 64, +- [0][1][2][0][RTW89_KCC][8] = 46, ++ [0][1][2][0][RTW89_KCC][8] = 70, + [0][1][2][0][RTW89_ACMA][8] = 46, + [0][1][2][0][RTW89_CHILE][8] = 48, + [0][1][2][0][RTW89_UKRAINE][8] = 46, ++ [0][1][2][0][RTW89_MEXICO][8] = 64, ++ [0][1][2][0][RTW89_CN][8] = 46, ++ [0][1][2][0][RTW89_QATAR][8] = 46, + [0][1][2][0][RTW89_FCC][9] = 60, + [0][1][2][0][RTW89_ETSI][9] = 46, + [0][1][2][0][RTW89_MKK][9] = 64, + [0][1][2][0][RTW89_IC][9] = 60, +- [0][1][2][0][RTW89_KCC][9] = 46, ++ [0][1][2][0][RTW89_KCC][9] = 70, + [0][1][2][0][RTW89_ACMA][9] = 46, + [0][1][2][0][RTW89_CHILE][9] = 48, + [0][1][2][0][RTW89_UKRAINE][9] = 46, ++ [0][1][2][0][RTW89_MEXICO][9] = 60, ++ [0][1][2][0][RTW89_CN][9] = 46, ++ [0][1][2][0][RTW89_QATAR][9] = 46, + [0][1][2][0][RTW89_FCC][10] = 60, + [0][1][2][0][RTW89_ETSI][10] = 46, + [0][1][2][0][RTW89_MKK][10] = 64, + [0][1][2][0][RTW89_IC][10] = 60, +- [0][1][2][0][RTW89_KCC][10] = 46, ++ [0][1][2][0][RTW89_KCC][10] = 70, + [0][1][2][0][RTW89_ACMA][10] = 46, + [0][1][2][0][RTW89_CHILE][10] = 48, + [0][1][2][0][RTW89_UKRAINE][10] = 46, ++ [0][1][2][0][RTW89_MEXICO][10] = 60, ++ [0][1][2][0][RTW89_CN][10] = 46, ++ [0][1][2][0][RTW89_QATAR][10] = 46, + [0][1][2][0][RTW89_FCC][11] = 42, + [0][1][2][0][RTW89_ETSI][11] = 46, + [0][1][2][0][RTW89_MKK][11] = 64, + [0][1][2][0][RTW89_IC][11] = 42, +- [0][1][2][0][RTW89_KCC][11] = 46, ++ [0][1][2][0][RTW89_KCC][11] = 70, + [0][1][2][0][RTW89_ACMA][11] = 46, +- [0][1][2][0][RTW89_CHILE][11] = 48, ++ [0][1][2][0][RTW89_CHILE][11] = 42, + [0][1][2][0][RTW89_UKRAINE][11] = 46, ++ [0][1][2][0][RTW89_MEXICO][11] = 42, ++ [0][1][2][0][RTW89_CN][11] = 46, ++ [0][1][2][0][RTW89_QATAR][11] = 46, + [0][1][2][0][RTW89_FCC][12] = 40, + [0][1][2][0][RTW89_ETSI][12] = 46, + [0][1][2][0][RTW89_MKK][12] = 64, + [0][1][2][0][RTW89_IC][12] = 40, +- [0][1][2][0][RTW89_KCC][12] = 46, ++ [0][1][2][0][RTW89_KCC][12] = 68, + [0][1][2][0][RTW89_ACMA][12] = 46, +- [0][1][2][0][RTW89_CHILE][12] = 48, ++ [0][1][2][0][RTW89_CHILE][12] = 40, + [0][1][2][0][RTW89_UKRAINE][12] = 46, ++ [0][1][2][0][RTW89_MEXICO][12] = 40, ++ [0][1][2][0][RTW89_CN][12] = 46, ++ [0][1][2][0][RTW89_QATAR][12] = 46, + [0][1][2][0][RTW89_FCC][13] = 127, + [0][1][2][0][RTW89_ETSI][13] = 127, + [0][1][2][0][RTW89_MKK][13] = 127, +@@ -44448,110 +44781,152 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][1][2][0][RTW89_ACMA][13] = 127, + [0][1][2][0][RTW89_CHILE][13] = 127, + [0][1][2][0][RTW89_UKRAINE][13] = 127, ++ [0][1][2][0][RTW89_MEXICO][13] = 127, ++ [0][1][2][0][RTW89_CN][13] = 127, ++ [0][1][2][0][RTW89_QATAR][13] = 127, + [0][1][2][1][RTW89_FCC][0] = 62, + [0][1][2][1][RTW89_ETSI][0] = 34, + [0][1][2][1][RTW89_MKK][0] = 64, + [0][1][2][1][RTW89_IC][0] = 62, +- [0][1][2][1][RTW89_KCC][0] = 34, ++ [0][1][2][1][RTW89_KCC][0] = 68, + [0][1][2][1][RTW89_ACMA][0] = 34, + [0][1][2][1][RTW89_CHILE][0] = 36, + [0][1][2][1][RTW89_UKRAINE][0] = 34, ++ [0][1][2][1][RTW89_MEXICO][0] = 62, ++ [0][1][2][1][RTW89_CN][0] = 34, ++ [0][1][2][1][RTW89_QATAR][0] = 34, + [0][1][2][1][RTW89_FCC][1] = 62, + [0][1][2][1][RTW89_ETSI][1] = 34, + [0][1][2][1][RTW89_MKK][1] = 64, + [0][1][2][1][RTW89_IC][1] = 62, +- [0][1][2][1][RTW89_KCC][1] = 34, ++ [0][1][2][1][RTW89_KCC][1] = 70, + [0][1][2][1][RTW89_ACMA][1] = 34, + [0][1][2][1][RTW89_CHILE][1] = 36, + [0][1][2][1][RTW89_UKRAINE][1] = 34, ++ [0][1][2][1][RTW89_MEXICO][1] = 62, ++ [0][1][2][1][RTW89_CN][1] = 34, ++ [0][1][2][1][RTW89_QATAR][1] = 34, + [0][1][2][1][RTW89_FCC][2] = 66, + [0][1][2][1][RTW89_ETSI][2] = 34, + [0][1][2][1][RTW89_MKK][2] = 64, + [0][1][2][1][RTW89_IC][2] = 66, +- [0][1][2][1][RTW89_KCC][2] = 34, ++ [0][1][2][1][RTW89_KCC][2] = 70, + [0][1][2][1][RTW89_ACMA][2] = 34, + [0][1][2][1][RTW89_CHILE][2] = 36, + [0][1][2][1][RTW89_UKRAINE][2] = 34, ++ [0][1][2][1][RTW89_MEXICO][2] = 66, ++ [0][1][2][1][RTW89_CN][2] = 34, ++ [0][1][2][1][RTW89_QATAR][2] = 34, + [0][1][2][1][RTW89_FCC][3] = 70, + [0][1][2][1][RTW89_ETSI][3] = 34, + [0][1][2][1][RTW89_MKK][3] = 64, + [0][1][2][1][RTW89_IC][3] = 70, +- [0][1][2][1][RTW89_KCC][3] = 34, ++ [0][1][2][1][RTW89_KCC][3] = 70, + [0][1][2][1][RTW89_ACMA][3] = 34, + [0][1][2][1][RTW89_CHILE][3] = 36, + [0][1][2][1][RTW89_UKRAINE][3] = 34, ++ [0][1][2][1][RTW89_MEXICO][3] = 70, ++ [0][1][2][1][RTW89_CN][3] = 34, ++ [0][1][2][1][RTW89_QATAR][3] = 34, + [0][1][2][1][RTW89_FCC][4] = 76, + [0][1][2][1][RTW89_ETSI][4] = 34, + [0][1][2][1][RTW89_MKK][4] = 64, + [0][1][2][1][RTW89_IC][4] = 76, +- [0][1][2][1][RTW89_KCC][4] = 34, ++ [0][1][2][1][RTW89_KCC][4] = 70, + [0][1][2][1][RTW89_ACMA][4] = 34, + [0][1][2][1][RTW89_CHILE][4] = 36, + [0][1][2][1][RTW89_UKRAINE][4] = 34, ++ [0][1][2][1][RTW89_MEXICO][4] = 76, ++ [0][1][2][1][RTW89_CN][4] = 34, ++ [0][1][2][1][RTW89_QATAR][4] = 34, + [0][1][2][1][RTW89_FCC][5] = 76, + [0][1][2][1][RTW89_ETSI][5] = 34, + [0][1][2][1][RTW89_MKK][5] = 64, + [0][1][2][1][RTW89_IC][5] = 76, +- [0][1][2][1][RTW89_KCC][5] = 34, ++ [0][1][2][1][RTW89_KCC][5] = 70, + [0][1][2][1][RTW89_ACMA][5] = 34, + [0][1][2][1][RTW89_CHILE][5] = 36, + [0][1][2][1][RTW89_UKRAINE][5] = 34, ++ [0][1][2][1][RTW89_MEXICO][5] = 76, ++ [0][1][2][1][RTW89_CN][5] = 34, ++ [0][1][2][1][RTW89_QATAR][5] = 34, + [0][1][2][1][RTW89_FCC][6] = 76, + [0][1][2][1][RTW89_ETSI][6] = 34, + [0][1][2][1][RTW89_MKK][6] = 64, + [0][1][2][1][RTW89_IC][6] = 76, +- [0][1][2][1][RTW89_KCC][6] = 34, ++ [0][1][2][1][RTW89_KCC][6] = 70, + [0][1][2][1][RTW89_ACMA][6] = 34, + [0][1][2][1][RTW89_CHILE][6] = 36, + [0][1][2][1][RTW89_UKRAINE][6] = 34, ++ [0][1][2][1][RTW89_MEXICO][6] = 76, ++ [0][1][2][1][RTW89_CN][6] = 34, ++ [0][1][2][1][RTW89_QATAR][6] = 34, + [0][1][2][1][RTW89_FCC][7] = 68, + [0][1][2][1][RTW89_ETSI][7] = 34, + [0][1][2][1][RTW89_MKK][7] = 64, + [0][1][2][1][RTW89_IC][7] = 68, +- [0][1][2][1][RTW89_KCC][7] = 34, ++ [0][1][2][1][RTW89_KCC][7] = 70, + [0][1][2][1][RTW89_ACMA][7] = 34, + [0][1][2][1][RTW89_CHILE][7] = 36, + [0][1][2][1][RTW89_UKRAINE][7] = 34, ++ [0][1][2][1][RTW89_MEXICO][7] = 68, ++ [0][1][2][1][RTW89_CN][7] = 34, ++ [0][1][2][1][RTW89_QATAR][7] = 34, + [0][1][2][1][RTW89_FCC][8] = 64, + [0][1][2][1][RTW89_ETSI][8] = 34, + [0][1][2][1][RTW89_MKK][8] = 64, + [0][1][2][1][RTW89_IC][8] = 64, +- [0][1][2][1][RTW89_KCC][8] = 34, ++ [0][1][2][1][RTW89_KCC][8] = 70, + [0][1][2][1][RTW89_ACMA][8] = 34, + [0][1][2][1][RTW89_CHILE][8] = 36, + [0][1][2][1][RTW89_UKRAINE][8] = 34, ++ [0][1][2][1][RTW89_MEXICO][8] = 64, ++ [0][1][2][1][RTW89_CN][8] = 34, ++ [0][1][2][1][RTW89_QATAR][8] = 34, + [0][1][2][1][RTW89_FCC][9] = 60, + [0][1][2][1][RTW89_ETSI][9] = 34, + [0][1][2][1][RTW89_MKK][9] = 64, + [0][1][2][1][RTW89_IC][9] = 60, +- [0][1][2][1][RTW89_KCC][9] = 34, ++ [0][1][2][1][RTW89_KCC][9] = 70, + [0][1][2][1][RTW89_ACMA][9] = 34, + [0][1][2][1][RTW89_CHILE][9] = 36, + [0][1][2][1][RTW89_UKRAINE][9] = 34, ++ [0][1][2][1][RTW89_MEXICO][9] = 60, ++ [0][1][2][1][RTW89_CN][9] = 34, ++ [0][1][2][1][RTW89_QATAR][9] = 34, + [0][1][2][1][RTW89_FCC][10] = 60, + [0][1][2][1][RTW89_ETSI][10] = 34, + [0][1][2][1][RTW89_MKK][10] = 64, + [0][1][2][1][RTW89_IC][10] = 60, +- [0][1][2][1][RTW89_KCC][10] = 34, ++ [0][1][2][1][RTW89_KCC][10] = 70, + [0][1][2][1][RTW89_ACMA][10] = 34, + [0][1][2][1][RTW89_CHILE][10] = 36, + [0][1][2][1][RTW89_UKRAINE][10] = 34, ++ [0][1][2][1][RTW89_MEXICO][10] = 60, ++ [0][1][2][1][RTW89_CN][10] = 34, ++ [0][1][2][1][RTW89_QATAR][10] = 34, + [0][1][2][1][RTW89_FCC][11] = 42, + [0][1][2][1][RTW89_ETSI][11] = 34, + [0][1][2][1][RTW89_MKK][11] = 64, + [0][1][2][1][RTW89_IC][11] = 42, +- [0][1][2][1][RTW89_KCC][11] = 34, ++ [0][1][2][1][RTW89_KCC][11] = 70, + [0][1][2][1][RTW89_ACMA][11] = 34, + [0][1][2][1][RTW89_CHILE][11] = 36, + [0][1][2][1][RTW89_UKRAINE][11] = 34, ++ [0][1][2][1][RTW89_MEXICO][11] = 42, ++ [0][1][2][1][RTW89_CN][11] = 34, ++ [0][1][2][1][RTW89_QATAR][11] = 34, + [0][1][2][1][RTW89_FCC][12] = 40, + [0][1][2][1][RTW89_ETSI][12] = 34, + [0][1][2][1][RTW89_MKK][12] = 64, + [0][1][2][1][RTW89_IC][12] = 40, +- [0][1][2][1][RTW89_KCC][12] = 34, ++ [0][1][2][1][RTW89_KCC][12] = 68, + [0][1][2][1][RTW89_ACMA][12] = 34, + [0][1][2][1][RTW89_CHILE][12] = 36, + [0][1][2][1][RTW89_UKRAINE][12] = 34, ++ [0][1][2][1][RTW89_MEXICO][12] = 40, ++ [0][1][2][1][RTW89_CN][12] = 34, ++ [0][1][2][1][RTW89_QATAR][12] = 34, + [0][1][2][1][RTW89_FCC][13] = 127, + [0][1][2][1][RTW89_ETSI][13] = 127, + [0][1][2][1][RTW89_MKK][13] = 127, +@@ -44560,6 +44935,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [0][1][2][1][RTW89_ACMA][13] = 127, + [0][1][2][1][RTW89_CHILE][13] = 127, + [0][1][2][1][RTW89_UKRAINE][13] = 127, ++ [0][1][2][1][RTW89_MEXICO][13] = 127, ++ [0][1][2][1][RTW89_CN][13] = 127, ++ [0][1][2][1][RTW89_QATAR][13] = 127, + [1][0][2][0][RTW89_FCC][0] = 127, + [1][0][2][0][RTW89_ETSI][0] = 127, + [1][0][2][0][RTW89_MKK][0] = 127, +@@ -44568,6 +44946,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][2][0][RTW89_ACMA][0] = 127, + [1][0][2][0][RTW89_CHILE][0] = 127, + [1][0][2][0][RTW89_UKRAINE][0] = 127, ++ [1][0][2][0][RTW89_MEXICO][0] = 127, ++ [1][0][2][0][RTW89_CN][0] = 127, ++ [1][0][2][0][RTW89_QATAR][0] = 127, + [1][0][2][0][RTW89_FCC][1] = 127, + [1][0][2][0][RTW89_ETSI][1] = 127, + [1][0][2][0][RTW89_MKK][1] = 127, +@@ -44576,78 +44957,108 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][2][0][RTW89_ACMA][1] = 127, + [1][0][2][0][RTW89_CHILE][1] = 127, + [1][0][2][0][RTW89_UKRAINE][1] = 127, ++ [1][0][2][0][RTW89_MEXICO][1] = 127, ++ [1][0][2][0][RTW89_CN][1] = 127, ++ [1][0][2][0][RTW89_QATAR][1] = 127, + [1][0][2][0][RTW89_FCC][2] = 56, + [1][0][2][0][RTW89_ETSI][2] = 58, +- [1][0][2][0][RTW89_MKK][2] = 76, ++ [1][0][2][0][RTW89_MKK][2] = 68, + [1][0][2][0][RTW89_IC][2] = 56, +- [1][0][2][0][RTW89_KCC][2] = 58, ++ [1][0][2][0][RTW89_KCC][2] = 68, + [1][0][2][0][RTW89_ACMA][2] = 58, +- [1][0][2][0][RTW89_CHILE][2] = 60, ++ [1][0][2][0][RTW89_CHILE][2] = 56, + [1][0][2][0][RTW89_UKRAINE][2] = 58, ++ [1][0][2][0][RTW89_MEXICO][2] = 56, ++ [1][0][2][0][RTW89_CN][2] = 58, ++ [1][0][2][0][RTW89_QATAR][2] = 58, + [1][0][2][0][RTW89_FCC][3] = 56, + [1][0][2][0][RTW89_ETSI][3] = 58, +- [1][0][2][0][RTW89_MKK][3] = 76, ++ [1][0][2][0][RTW89_MKK][3] = 68, + [1][0][2][0][RTW89_IC][3] = 56, +- [1][0][2][0][RTW89_KCC][3] = 58, ++ [1][0][2][0][RTW89_KCC][3] = 68, + [1][0][2][0][RTW89_ACMA][3] = 58, +- [1][0][2][0][RTW89_CHILE][3] = 60, ++ [1][0][2][0][RTW89_CHILE][3] = 56, + [1][0][2][0][RTW89_UKRAINE][3] = 58, ++ [1][0][2][0][RTW89_MEXICO][3] = 56, ++ [1][0][2][0][RTW89_CN][3] = 58, ++ [1][0][2][0][RTW89_QATAR][3] = 58, + [1][0][2][0][RTW89_FCC][4] = 60, + [1][0][2][0][RTW89_ETSI][4] = 58, +- [1][0][2][0][RTW89_MKK][4] = 76, ++ [1][0][2][0][RTW89_MKK][4] = 68, + [1][0][2][0][RTW89_IC][4] = 60, +- [1][0][2][0][RTW89_KCC][4] = 58, ++ [1][0][2][0][RTW89_KCC][4] = 68, + [1][0][2][0][RTW89_ACMA][4] = 58, + [1][0][2][0][RTW89_CHILE][4] = 60, + [1][0][2][0][RTW89_UKRAINE][4] = 58, ++ [1][0][2][0][RTW89_MEXICO][4] = 60, ++ [1][0][2][0][RTW89_CN][4] = 58, ++ [1][0][2][0][RTW89_QATAR][4] = 58, + [1][0][2][0][RTW89_FCC][5] = 64, + [1][0][2][0][RTW89_ETSI][5] = 58, +- [1][0][2][0][RTW89_MKK][5] = 76, ++ [1][0][2][0][RTW89_MKK][5] = 68, + [1][0][2][0][RTW89_IC][5] = 64, +- [1][0][2][0][RTW89_KCC][5] = 58, ++ [1][0][2][0][RTW89_KCC][5] = 68, + [1][0][2][0][RTW89_ACMA][5] = 58, + [1][0][2][0][RTW89_CHILE][5] = 60, + [1][0][2][0][RTW89_UKRAINE][5] = 58, ++ [1][0][2][0][RTW89_MEXICO][5] = 64, ++ [1][0][2][0][RTW89_CN][5] = 58, ++ [1][0][2][0][RTW89_QATAR][5] = 58, + [1][0][2][0][RTW89_FCC][6] = 54, + [1][0][2][0][RTW89_ETSI][6] = 58, +- [1][0][2][0][RTW89_MKK][6] = 76, ++ [1][0][2][0][RTW89_MKK][6] = 68, + [1][0][2][0][RTW89_IC][6] = 54, +- [1][0][2][0][RTW89_KCC][6] = 58, ++ [1][0][2][0][RTW89_KCC][6] = 68, + [1][0][2][0][RTW89_ACMA][6] = 58, +- [1][0][2][0][RTW89_CHILE][6] = 60, ++ [1][0][2][0][RTW89_CHILE][6] = 54, + [1][0][2][0][RTW89_UKRAINE][6] = 58, ++ [1][0][2][0][RTW89_MEXICO][6] = 54, ++ [1][0][2][0][RTW89_CN][6] = 58, ++ [1][0][2][0][RTW89_QATAR][6] = 58, + [1][0][2][0][RTW89_FCC][7] = 50, + [1][0][2][0][RTW89_ETSI][7] = 58, +- [1][0][2][0][RTW89_MKK][7] = 76, ++ [1][0][2][0][RTW89_MKK][7] = 68, + [1][0][2][0][RTW89_IC][7] = 50, +- [1][0][2][0][RTW89_KCC][7] = 58, ++ [1][0][2][0][RTW89_KCC][7] = 68, + [1][0][2][0][RTW89_ACMA][7] = 58, +- [1][0][2][0][RTW89_CHILE][7] = 60, ++ [1][0][2][0][RTW89_CHILE][7] = 50, + [1][0][2][0][RTW89_UKRAINE][7] = 58, ++ [1][0][2][0][RTW89_MEXICO][7] = 50, ++ [1][0][2][0][RTW89_CN][7] = 58, ++ [1][0][2][0][RTW89_QATAR][7] = 58, + [1][0][2][0][RTW89_FCC][8] = 50, + [1][0][2][0][RTW89_ETSI][8] = 58, +- [1][0][2][0][RTW89_MKK][8] = 76, ++ [1][0][2][0][RTW89_MKK][8] = 68, + [1][0][2][0][RTW89_IC][8] = 50, +- [1][0][2][0][RTW89_KCC][8] = 58, ++ [1][0][2][0][RTW89_KCC][8] = 68, + [1][0][2][0][RTW89_ACMA][8] = 58, +- [1][0][2][0][RTW89_CHILE][8] = 60, ++ [1][0][2][0][RTW89_CHILE][8] = 50, + [1][0][2][0][RTW89_UKRAINE][8] = 58, ++ [1][0][2][0][RTW89_MEXICO][8] = 50, ++ [1][0][2][0][RTW89_CN][8] = 58, ++ [1][0][2][0][RTW89_QATAR][8] = 58, + [1][0][2][0][RTW89_FCC][9] = 42, + [1][0][2][0][RTW89_ETSI][9] = 58, +- [1][0][2][0][RTW89_MKK][9] = 76, ++ [1][0][2][0][RTW89_MKK][9] = 68, + [1][0][2][0][RTW89_IC][9] = 42, +- [1][0][2][0][RTW89_KCC][9] = 58, ++ [1][0][2][0][RTW89_KCC][9] = 68, + [1][0][2][0][RTW89_ACMA][9] = 58, +- [1][0][2][0][RTW89_CHILE][9] = 60, ++ [1][0][2][0][RTW89_CHILE][9] = 42, + [1][0][2][0][RTW89_UKRAINE][9] = 58, ++ [1][0][2][0][RTW89_MEXICO][9] = 42, ++ [1][0][2][0][RTW89_CN][9] = 58, ++ [1][0][2][0][RTW89_QATAR][9] = 58, + [1][0][2][0][RTW89_FCC][10] = 40, + [1][0][2][0][RTW89_ETSI][10] = 58, +- [1][0][2][0][RTW89_MKK][10] = 76, ++ [1][0][2][0][RTW89_MKK][10] = 68, + [1][0][2][0][RTW89_IC][10] = 40, +- [1][0][2][0][RTW89_KCC][10] = 58, ++ [1][0][2][0][RTW89_KCC][10] = 68, + [1][0][2][0][RTW89_ACMA][10] = 58, +- [1][0][2][0][RTW89_CHILE][10] = 60, ++ [1][0][2][0][RTW89_CHILE][10] = 40, + [1][0][2][0][RTW89_UKRAINE][10] = 58, ++ [1][0][2][0][RTW89_MEXICO][10] = 40, ++ [1][0][2][0][RTW89_CN][10] = 58, ++ [1][0][2][0][RTW89_QATAR][10] = 58, + [1][0][2][0][RTW89_FCC][11] = 127, + [1][0][2][0][RTW89_ETSI][11] = 127, + [1][0][2][0][RTW89_MKK][11] = 127, +@@ -44656,6 +45067,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][2][0][RTW89_ACMA][11] = 127, + [1][0][2][0][RTW89_CHILE][11] = 127, + [1][0][2][0][RTW89_UKRAINE][11] = 127, ++ [1][0][2][0][RTW89_MEXICO][11] = 127, ++ [1][0][2][0][RTW89_CN][11] = 127, ++ [1][0][2][0][RTW89_QATAR][11] = 127, + [1][0][2][0][RTW89_FCC][12] = 127, + [1][0][2][0][RTW89_ETSI][12] = 127, + [1][0][2][0][RTW89_MKK][12] = 127, +@@ -44664,6 +45078,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][2][0][RTW89_ACMA][12] = 127, + [1][0][2][0][RTW89_CHILE][12] = 127, + [1][0][2][0][RTW89_UKRAINE][12] = 127, ++ [1][0][2][0][RTW89_MEXICO][12] = 127, ++ [1][0][2][0][RTW89_CN][12] = 127, ++ [1][0][2][0][RTW89_QATAR][12] = 127, + [1][0][2][0][RTW89_FCC][13] = 127, + [1][0][2][0][RTW89_ETSI][13] = 127, + [1][0][2][0][RTW89_MKK][13] = 127, +@@ -44672,6 +45089,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][0][2][0][RTW89_ACMA][13] = 127, + [1][0][2][0][RTW89_CHILE][13] = 127, + [1][0][2][0][RTW89_UKRAINE][13] = 127, ++ [1][0][2][0][RTW89_MEXICO][13] = 127, ++ [1][0][2][0][RTW89_CN][13] = 127, ++ [1][0][2][0][RTW89_QATAR][13] = 127, + [1][1][2][0][RTW89_FCC][0] = 127, + [1][1][2][0][RTW89_ETSI][0] = 127, + [1][1][2][0][RTW89_MKK][0] = 127, +@@ -44680,6 +45100,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][0][RTW89_ACMA][0] = 127, + [1][1][2][0][RTW89_CHILE][0] = 127, + [1][1][2][0][RTW89_UKRAINE][0] = 127, ++ [1][1][2][0][RTW89_MEXICO][0] = 127, ++ [1][1][2][0][RTW89_CN][0] = 127, ++ [1][1][2][0][RTW89_QATAR][0] = 127, + [1][1][2][0][RTW89_FCC][1] = 127, + [1][1][2][0][RTW89_ETSI][1] = 127, + [1][1][2][0][RTW89_MKK][1] = 127, +@@ -44688,78 +45111,108 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][0][RTW89_ACMA][1] = 127, + [1][1][2][0][RTW89_CHILE][1] = 127, + [1][1][2][0][RTW89_UKRAINE][1] = 127, ++ [1][1][2][0][RTW89_MEXICO][1] = 127, ++ [1][1][2][0][RTW89_CN][1] = 127, ++ [1][1][2][0][RTW89_QATAR][1] = 127, + [1][1][2][0][RTW89_FCC][2] = 52, + [1][1][2][0][RTW89_ETSI][2] = 46, + [1][1][2][0][RTW89_MKK][2] = 64, + [1][1][2][0][RTW89_IC][2] = 52, +- [1][1][2][0][RTW89_KCC][2] = 46, ++ [1][1][2][0][RTW89_KCC][2] = 66, + [1][1][2][0][RTW89_ACMA][2] = 46, + [1][1][2][0][RTW89_CHILE][2] = 48, + [1][1][2][0][RTW89_UKRAINE][2] = 46, ++ [1][1][2][0][RTW89_MEXICO][2] = 52, ++ [1][1][2][0][RTW89_CN][2] = 46, ++ [1][1][2][0][RTW89_QATAR][2] = 46, + [1][1][2][0][RTW89_FCC][3] = 52, + [1][1][2][0][RTW89_ETSI][3] = 46, + [1][1][2][0][RTW89_MKK][3] = 64, + [1][1][2][0][RTW89_IC][3] = 52, +- [1][1][2][0][RTW89_KCC][3] = 46, ++ [1][1][2][0][RTW89_KCC][3] = 68, + [1][1][2][0][RTW89_ACMA][3] = 46, + [1][1][2][0][RTW89_CHILE][3] = 48, + [1][1][2][0][RTW89_UKRAINE][3] = 46, ++ [1][1][2][0][RTW89_MEXICO][3] = 52, ++ [1][1][2][0][RTW89_CN][3] = 46, ++ [1][1][2][0][RTW89_QATAR][3] = 46, + [1][1][2][0][RTW89_FCC][4] = 56, + [1][1][2][0][RTW89_ETSI][4] = 46, + [1][1][2][0][RTW89_MKK][4] = 64, + [1][1][2][0][RTW89_IC][4] = 56, +- [1][1][2][0][RTW89_KCC][4] = 46, ++ [1][1][2][0][RTW89_KCC][4] = 68, + [1][1][2][0][RTW89_ACMA][4] = 46, + [1][1][2][0][RTW89_CHILE][4] = 48, + [1][1][2][0][RTW89_UKRAINE][4] = 46, ++ [1][1][2][0][RTW89_MEXICO][4] = 56, ++ [1][1][2][0][RTW89_CN][4] = 46, ++ [1][1][2][0][RTW89_QATAR][4] = 46, + [1][1][2][0][RTW89_FCC][5] = 60, + [1][1][2][0][RTW89_ETSI][5] = 46, + [1][1][2][0][RTW89_MKK][5] = 64, + [1][1][2][0][RTW89_IC][5] = 60, +- [1][1][2][0][RTW89_KCC][5] = 46, ++ [1][1][2][0][RTW89_KCC][5] = 68, + [1][1][2][0][RTW89_ACMA][5] = 46, + [1][1][2][0][RTW89_CHILE][5] = 48, + [1][1][2][0][RTW89_UKRAINE][5] = 46, ++ [1][1][2][0][RTW89_MEXICO][5] = 60, ++ [1][1][2][0][RTW89_CN][5] = 46, ++ [1][1][2][0][RTW89_QATAR][5] = 46, + [1][1][2][0][RTW89_FCC][6] = 54, + [1][1][2][0][RTW89_ETSI][6] = 46, + [1][1][2][0][RTW89_MKK][6] = 64, + [1][1][2][0][RTW89_IC][6] = 52, +- [1][1][2][0][RTW89_KCC][6] = 46, ++ [1][1][2][0][RTW89_KCC][6] = 68, + [1][1][2][0][RTW89_ACMA][6] = 46, + [1][1][2][0][RTW89_CHILE][6] = 48, + [1][1][2][0][RTW89_UKRAINE][6] = 46, ++ [1][1][2][0][RTW89_MEXICO][6] = 54, ++ [1][1][2][0][RTW89_CN][6] = 46, ++ [1][1][2][0][RTW89_QATAR][6] = 46, + [1][1][2][0][RTW89_FCC][7] = 50, + [1][1][2][0][RTW89_ETSI][7] = 46, + [1][1][2][0][RTW89_MKK][7] = 64, + [1][1][2][0][RTW89_IC][7] = 48, +- [1][1][2][0][RTW89_KCC][7] = 46, ++ [1][1][2][0][RTW89_KCC][7] = 68, + [1][1][2][0][RTW89_ACMA][7] = 46, + [1][1][2][0][RTW89_CHILE][7] = 48, + [1][1][2][0][RTW89_UKRAINE][7] = 46, ++ [1][1][2][0][RTW89_MEXICO][7] = 50, ++ [1][1][2][0][RTW89_CN][7] = 46, ++ [1][1][2][0][RTW89_QATAR][7] = 46, + [1][1][2][0][RTW89_FCC][8] = 50, + [1][1][2][0][RTW89_ETSI][8] = 46, + [1][1][2][0][RTW89_MKK][8] = 64, + [1][1][2][0][RTW89_IC][8] = 48, +- [1][1][2][0][RTW89_KCC][8] = 46, ++ [1][1][2][0][RTW89_KCC][8] = 68, + [1][1][2][0][RTW89_ACMA][8] = 46, + [1][1][2][0][RTW89_CHILE][8] = 48, + [1][1][2][0][RTW89_UKRAINE][8] = 46, ++ [1][1][2][0][RTW89_MEXICO][8] = 50, ++ [1][1][2][0][RTW89_CN][8] = 46, ++ [1][1][2][0][RTW89_QATAR][8] = 46, + [1][1][2][0][RTW89_FCC][9] = 38, + [1][1][2][0][RTW89_ETSI][9] = 46, + [1][1][2][0][RTW89_MKK][9] = 64, + [1][1][2][0][RTW89_IC][9] = 38, +- [1][1][2][0][RTW89_KCC][9] = 46, ++ [1][1][2][0][RTW89_KCC][9] = 68, + [1][1][2][0][RTW89_ACMA][9] = 46, +- [1][1][2][0][RTW89_CHILE][9] = 48, ++ [1][1][2][0][RTW89_CHILE][9] = 38, + [1][1][2][0][RTW89_UKRAINE][9] = 46, ++ [1][1][2][0][RTW89_MEXICO][9] = 38, ++ [1][1][2][0][RTW89_CN][9] = 46, ++ [1][1][2][0][RTW89_QATAR][9] = 46, + [1][1][2][0][RTW89_FCC][10] = 36, + [1][1][2][0][RTW89_ETSI][10] = 46, + [1][1][2][0][RTW89_MKK][10] = 64, + [1][1][2][0][RTW89_IC][10] = 36, +- [1][1][2][0][RTW89_KCC][10] = 46, ++ [1][1][2][0][RTW89_KCC][10] = 66, + [1][1][2][0][RTW89_ACMA][10] = 46, +- [1][1][2][0][RTW89_CHILE][10] = 48, ++ [1][1][2][0][RTW89_CHILE][10] = 36, + [1][1][2][0][RTW89_UKRAINE][10] = 46, ++ [1][1][2][0][RTW89_MEXICO][10] = 36, ++ [1][1][2][0][RTW89_CN][10] = 46, ++ [1][1][2][0][RTW89_QATAR][10] = 46, + [1][1][2][0][RTW89_FCC][11] = 127, + [1][1][2][0][RTW89_ETSI][11] = 127, + [1][1][2][0][RTW89_MKK][11] = 127, +@@ -44768,6 +45221,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][0][RTW89_ACMA][11] = 127, + [1][1][2][0][RTW89_CHILE][11] = 127, + [1][1][2][0][RTW89_UKRAINE][11] = 127, ++ [1][1][2][0][RTW89_MEXICO][11] = 127, ++ [1][1][2][0][RTW89_CN][11] = 127, ++ [1][1][2][0][RTW89_QATAR][11] = 127, + [1][1][2][0][RTW89_FCC][12] = 127, + [1][1][2][0][RTW89_ETSI][12] = 127, + [1][1][2][0][RTW89_MKK][12] = 127, +@@ -44776,6 +45232,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][0][RTW89_ACMA][12] = 127, + [1][1][2][0][RTW89_CHILE][12] = 127, + [1][1][2][0][RTW89_UKRAINE][12] = 127, ++ [1][1][2][0][RTW89_MEXICO][12] = 127, ++ [1][1][2][0][RTW89_CN][12] = 127, ++ [1][1][2][0][RTW89_QATAR][12] = 127, + [1][1][2][0][RTW89_FCC][13] = 127, + [1][1][2][0][RTW89_ETSI][13] = 127, + [1][1][2][0][RTW89_MKK][13] = 127, +@@ -44784,6 +45243,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][0][RTW89_ACMA][13] = 127, + [1][1][2][0][RTW89_CHILE][13] = 127, + [1][1][2][0][RTW89_UKRAINE][13] = 127, ++ [1][1][2][0][RTW89_MEXICO][13] = 127, ++ [1][1][2][0][RTW89_CN][13] = 127, ++ [1][1][2][0][RTW89_QATAR][13] = 127, + [1][1][2][1][RTW89_FCC][0] = 127, + [1][1][2][1][RTW89_ETSI][0] = 127, + [1][1][2][1][RTW89_MKK][0] = 127, +@@ -44792,6 +45254,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][1][RTW89_ACMA][0] = 127, + [1][1][2][1][RTW89_CHILE][0] = 127, + [1][1][2][1][RTW89_UKRAINE][0] = 127, ++ [1][1][2][1][RTW89_MEXICO][0] = 127, ++ [1][1][2][1][RTW89_CN][0] = 127, ++ [1][1][2][1][RTW89_QATAR][0] = 127, + [1][1][2][1][RTW89_FCC][1] = 127, + [1][1][2][1][RTW89_ETSI][1] = 127, + [1][1][2][1][RTW89_MKK][1] = 127, +@@ -44800,78 +45265,108 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][1][RTW89_ACMA][1] = 127, + [1][1][2][1][RTW89_CHILE][1] = 127, + [1][1][2][1][RTW89_UKRAINE][1] = 127, ++ [1][1][2][1][RTW89_MEXICO][1] = 127, ++ [1][1][2][1][RTW89_CN][1] = 127, ++ [1][1][2][1][RTW89_QATAR][1] = 127, + [1][1][2][1][RTW89_FCC][2] = 52, + [1][1][2][1][RTW89_ETSI][2] = 34, + [1][1][2][1][RTW89_MKK][2] = 64, + [1][1][2][1][RTW89_IC][2] = 52, +- [1][1][2][1][RTW89_KCC][2] = 34, ++ [1][1][2][1][RTW89_KCC][2] = 66, + [1][1][2][1][RTW89_ACMA][2] = 34, + [1][1][2][1][RTW89_CHILE][2] = 36, + [1][1][2][1][RTW89_UKRAINE][2] = 34, ++ [1][1][2][1][RTW89_MEXICO][2] = 52, ++ [1][1][2][1][RTW89_CN][2] = 34, ++ [1][1][2][1][RTW89_QATAR][2] = 34, + [1][1][2][1][RTW89_FCC][3] = 52, + [1][1][2][1][RTW89_ETSI][3] = 34, + [1][1][2][1][RTW89_MKK][3] = 64, + [1][1][2][1][RTW89_IC][3] = 52, +- [1][1][2][1][RTW89_KCC][3] = 34, ++ [1][1][2][1][RTW89_KCC][3] = 68, + [1][1][2][1][RTW89_ACMA][3] = 34, + [1][1][2][1][RTW89_CHILE][3] = 36, + [1][1][2][1][RTW89_UKRAINE][3] = 34, ++ [1][1][2][1][RTW89_MEXICO][3] = 52, ++ [1][1][2][1][RTW89_CN][3] = 34, ++ [1][1][2][1][RTW89_QATAR][3] = 34, + [1][1][2][1][RTW89_FCC][4] = 56, + [1][1][2][1][RTW89_ETSI][4] = 34, + [1][1][2][1][RTW89_MKK][4] = 64, + [1][1][2][1][RTW89_IC][4] = 56, +- [1][1][2][1][RTW89_KCC][4] = 34, ++ [1][1][2][1][RTW89_KCC][4] = 68, + [1][1][2][1][RTW89_ACMA][4] = 34, + [1][1][2][1][RTW89_CHILE][4] = 36, + [1][1][2][1][RTW89_UKRAINE][4] = 34, ++ [1][1][2][1][RTW89_MEXICO][4] = 56, ++ [1][1][2][1][RTW89_CN][4] = 34, ++ [1][1][2][1][RTW89_QATAR][4] = 34, + [1][1][2][1][RTW89_FCC][5] = 60, + [1][1][2][1][RTW89_ETSI][5] = 34, + [1][1][2][1][RTW89_MKK][5] = 64, + [1][1][2][1][RTW89_IC][5] = 60, +- [1][1][2][1][RTW89_KCC][5] = 34, ++ [1][1][2][1][RTW89_KCC][5] = 68, + [1][1][2][1][RTW89_ACMA][5] = 34, + [1][1][2][1][RTW89_CHILE][5] = 36, + [1][1][2][1][RTW89_UKRAINE][5] = 34, ++ [1][1][2][1][RTW89_MEXICO][5] = 60, ++ [1][1][2][1][RTW89_CN][5] = 34, ++ [1][1][2][1][RTW89_QATAR][5] = 34, + [1][1][2][1][RTW89_FCC][6] = 54, + [1][1][2][1][RTW89_ETSI][6] = 34, + [1][1][2][1][RTW89_MKK][6] = 64, + [1][1][2][1][RTW89_IC][6] = 52, +- [1][1][2][1][RTW89_KCC][6] = 34, ++ [1][1][2][1][RTW89_KCC][6] = 68, + [1][1][2][1][RTW89_ACMA][6] = 34, + [1][1][2][1][RTW89_CHILE][6] = 36, + [1][1][2][1][RTW89_UKRAINE][6] = 34, ++ [1][1][2][1][RTW89_MEXICO][6] = 54, ++ [1][1][2][1][RTW89_CN][6] = 34, ++ [1][1][2][1][RTW89_QATAR][6] = 34, + [1][1][2][1][RTW89_FCC][7] = 50, + [1][1][2][1][RTW89_ETSI][7] = 34, + [1][1][2][1][RTW89_MKK][7] = 64, + [1][1][2][1][RTW89_IC][7] = 48, +- [1][1][2][1][RTW89_KCC][7] = 34, ++ [1][1][2][1][RTW89_KCC][7] = 68, + [1][1][2][1][RTW89_ACMA][7] = 34, + [1][1][2][1][RTW89_CHILE][7] = 36, + [1][1][2][1][RTW89_UKRAINE][7] = 34, ++ [1][1][2][1][RTW89_MEXICO][7] = 50, ++ [1][1][2][1][RTW89_CN][7] = 34, ++ [1][1][2][1][RTW89_QATAR][7] = 34, + [1][1][2][1][RTW89_FCC][8] = 50, + [1][1][2][1][RTW89_ETSI][8] = 34, + [1][1][2][1][RTW89_MKK][8] = 64, + [1][1][2][1][RTW89_IC][8] = 48, +- [1][1][2][1][RTW89_KCC][8] = 34, ++ [1][1][2][1][RTW89_KCC][8] = 68, + [1][1][2][1][RTW89_ACMA][8] = 34, + [1][1][2][1][RTW89_CHILE][8] = 36, + [1][1][2][1][RTW89_UKRAINE][8] = 34, ++ [1][1][2][1][RTW89_MEXICO][8] = 50, ++ [1][1][2][1][RTW89_CN][8] = 34, ++ [1][1][2][1][RTW89_QATAR][8] = 34, + [1][1][2][1][RTW89_FCC][9] = 38, + [1][1][2][1][RTW89_ETSI][9] = 34, + [1][1][2][1][RTW89_MKK][9] = 64, + [1][1][2][1][RTW89_IC][9] = 38, +- [1][1][2][1][RTW89_KCC][9] = 34, ++ [1][1][2][1][RTW89_KCC][9] = 68, + [1][1][2][1][RTW89_ACMA][9] = 34, + [1][1][2][1][RTW89_CHILE][9] = 36, + [1][1][2][1][RTW89_UKRAINE][9] = 34, ++ [1][1][2][1][RTW89_MEXICO][9] = 38, ++ [1][1][2][1][RTW89_CN][9] = 34, ++ [1][1][2][1][RTW89_QATAR][9] = 34, + [1][1][2][1][RTW89_FCC][10] = 36, + [1][1][2][1][RTW89_ETSI][10] = 34, + [1][1][2][1][RTW89_MKK][10] = 64, + [1][1][2][1][RTW89_IC][10] = 36, +- [1][1][2][1][RTW89_KCC][10] = 34, ++ [1][1][2][1][RTW89_KCC][10] = 66, + [1][1][2][1][RTW89_ACMA][10] = 34, + [1][1][2][1][RTW89_CHILE][10] = 36, + [1][1][2][1][RTW89_UKRAINE][10] = 34, ++ [1][1][2][1][RTW89_MEXICO][10] = 36, ++ [1][1][2][1][RTW89_CN][10] = 34, ++ [1][1][2][1][RTW89_QATAR][10] = 34, + [1][1][2][1][RTW89_FCC][11] = 127, + [1][1][2][1][RTW89_ETSI][11] = 127, + [1][1][2][1][RTW89_MKK][11] = 127, +@@ -44880,6 +45375,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][1][RTW89_ACMA][11] = 127, + [1][1][2][1][RTW89_CHILE][11] = 127, + [1][1][2][1][RTW89_UKRAINE][11] = 127, ++ [1][1][2][1][RTW89_MEXICO][11] = 127, ++ [1][1][2][1][RTW89_CN][11] = 127, ++ [1][1][2][1][RTW89_QATAR][11] = 127, + [1][1][2][1][RTW89_FCC][12] = 127, + [1][1][2][1][RTW89_ETSI][12] = 127, + [1][1][2][1][RTW89_MKK][12] = 127, +@@ -44888,6 +45386,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][1][RTW89_ACMA][12] = 127, + [1][1][2][1][RTW89_CHILE][12] = 127, + [1][1][2][1][RTW89_UKRAINE][12] = 127, ++ [1][1][2][1][RTW89_MEXICO][12] = 127, ++ [1][1][2][1][RTW89_CN][12] = 127, ++ [1][1][2][1][RTW89_QATAR][12] = 127, + [1][1][2][1][RTW89_FCC][13] = 127, + [1][1][2][1][RTW89_ETSI][13] = 127, + [1][1][2][1][RTW89_MKK][13] = 127, +@@ -44896,6 +45397,9 @@ const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM] + [1][1][2][1][RTW89_ACMA][13] = 127, + [1][1][2][1][RTW89_CHILE][13] = 127, + [1][1][2][1][RTW89_UKRAINE][13] = 127, ++ [1][1][2][1][RTW89_MEXICO][13] = 127, ++ [1][1][2][1][RTW89_CN][13] = 127, ++ [1][1][2][1][RTW89_QATAR][13] = 127, + }; + + const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] +@@ -45084,1434 +45588,1971 @@ const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM] + [0][0][1][0][RTW89_ETSI][0] = 58, + [0][0][1][0][RTW89_MKK][0] = 62, + [0][0][1][0][RTW89_IC][0] = 62, +- [0][0][1][0][RTW89_KCC][0] = 58, ++ [0][0][1][0][RTW89_KCC][0] = 76, + [0][0][1][0][RTW89_ACMA][0] = 58, + [0][0][1][0][RTW89_CHILE][0] = 30, + [0][0][1][0][RTW89_UKRAINE][0] = 52, ++ [0][0][1][0][RTW89_MEXICO][0] = 62, ++ [0][0][1][0][RTW89_CN][0] = 58, ++ [0][0][1][0][RTW89_QATAR][0] = 58, + [0][0][1][0][RTW89_FCC][2] = 76, + [0][0][1][0][RTW89_ETSI][2] = 58, + [0][0][1][0][RTW89_MKK][2] = 62, + [0][0][1][0][RTW89_IC][2] = 62, +- [0][0][1][0][RTW89_KCC][2] = 58, ++ [0][0][1][0][RTW89_KCC][2] = 76, + [0][0][1][0][RTW89_ACMA][2] = 58, + [0][0][1][0][RTW89_CHILE][2] = 30, + [0][0][1][0][RTW89_UKRAINE][2] = 52, ++ [0][0][1][0][RTW89_MEXICO][2] = 62, ++ [0][0][1][0][RTW89_CN][2] = 58, ++ [0][0][1][0][RTW89_QATAR][2] = 58, + [0][0][1][0][RTW89_FCC][4] = 76, + [0][0][1][0][RTW89_ETSI][4] = 58, + [0][0][1][0][RTW89_MKK][4] = 62, + [0][0][1][0][RTW89_IC][4] = 62, +- [0][0][1][0][RTW89_KCC][4] = 58, ++ [0][0][1][0][RTW89_KCC][4] = 76, + [0][0][1][0][RTW89_ACMA][4] = 58, + [0][0][1][0][RTW89_CHILE][4] = 30, + [0][0][1][0][RTW89_UKRAINE][4] = 52, ++ [0][0][1][0][RTW89_MEXICO][4] = 62, ++ [0][0][1][0][RTW89_CN][4] = 58, ++ [0][0][1][0][RTW89_QATAR][4] = 58, + [0][0][1][0][RTW89_FCC][6] = 76, + [0][0][1][0][RTW89_ETSI][6] = 58, + [0][0][1][0][RTW89_MKK][6] = 62, + [0][0][1][0][RTW89_IC][6] = 62, +- [0][0][1][0][RTW89_KCC][6] = 54, ++ [0][0][1][0][RTW89_KCC][6] = 58, + [0][0][1][0][RTW89_ACMA][6] = 58, + [0][0][1][0][RTW89_CHILE][6] = 30, + [0][0][1][0][RTW89_UKRAINE][6] = 52, ++ [0][0][1][0][RTW89_MEXICO][6] = 62, ++ [0][0][1][0][RTW89_CN][6] = 58, ++ [0][0][1][0][RTW89_QATAR][6] = 58, + [0][0][1][0][RTW89_FCC][8] = 76, + [0][0][1][0][RTW89_ETSI][8] = 58, + [0][0][1][0][RTW89_MKK][8] = 62, + [0][0][1][0][RTW89_IC][8] = 64, +- [0][0][1][0][RTW89_KCC][8] = 58, ++ [0][0][1][0][RTW89_KCC][8] = 76, + [0][0][1][0][RTW89_ACMA][8] = 58, + [0][0][1][0][RTW89_CHILE][8] = 54, + [0][0][1][0][RTW89_UKRAINE][8] = 52, ++ [0][0][1][0][RTW89_MEXICO][8] = 76, ++ [0][0][1][0][RTW89_CN][8] = 58, ++ [0][0][1][0][RTW89_QATAR][8] = 58, + [0][0][1][0][RTW89_FCC][10] = 76, + [0][0][1][0][RTW89_ETSI][10] = 58, + [0][0][1][0][RTW89_MKK][10] = 62, + [0][0][1][0][RTW89_IC][10] = 64, +- [0][0][1][0][RTW89_KCC][10] = 58, ++ [0][0][1][0][RTW89_KCC][10] = 76, + [0][0][1][0][RTW89_ACMA][10] = 58, + [0][0][1][0][RTW89_CHILE][10] = 54, + [0][0][1][0][RTW89_UKRAINE][10] = 52, ++ [0][0][1][0][RTW89_MEXICO][10] = 76, ++ [0][0][1][0][RTW89_CN][10] = 58, ++ [0][0][1][0][RTW89_QATAR][10] = 58, + [0][0][1][0][RTW89_FCC][12] = 76, + [0][0][1][0][RTW89_ETSI][12] = 58, + [0][0][1][0][RTW89_MKK][12] = 62, + [0][0][1][0][RTW89_IC][12] = 64, +- [0][0][1][0][RTW89_KCC][12] = 58, ++ [0][0][1][0][RTW89_KCC][12] = 76, + [0][0][1][0][RTW89_ACMA][12] = 58, + [0][0][1][0][RTW89_CHILE][12] = 54, + [0][0][1][0][RTW89_UKRAINE][12] = 52, ++ [0][0][1][0][RTW89_MEXICO][12] = 76, ++ [0][0][1][0][RTW89_CN][12] = 58, ++ [0][0][1][0][RTW89_QATAR][12] = 58, + [0][0][1][0][RTW89_FCC][14] = 76, + [0][0][1][0][RTW89_ETSI][14] = 58, + [0][0][1][0][RTW89_MKK][14] = 62, + [0][0][1][0][RTW89_IC][14] = 64, +- [0][0][1][0][RTW89_KCC][14] = 58, ++ [0][0][1][0][RTW89_KCC][14] = 76, + [0][0][1][0][RTW89_ACMA][14] = 58, + [0][0][1][0][RTW89_CHILE][14] = 54, + [0][0][1][0][RTW89_UKRAINE][14] = 52, ++ [0][0][1][0][RTW89_MEXICO][14] = 76, ++ [0][0][1][0][RTW89_CN][14] = 58, ++ [0][0][1][0][RTW89_QATAR][14] = 58, + [0][0][1][0][RTW89_FCC][15] = 76, + [0][0][1][0][RTW89_ETSI][15] = 58, + [0][0][1][0][RTW89_MKK][15] = 76, + [0][0][1][0][RTW89_IC][15] = 76, +- [0][0][1][0][RTW89_KCC][15] = 58, ++ [0][0][1][0][RTW89_KCC][15] = 76, + [0][0][1][0][RTW89_ACMA][15] = 58, + [0][0][1][0][RTW89_CHILE][15] = 54, + [0][0][1][0][RTW89_UKRAINE][15] = 52, ++ [0][0][1][0][RTW89_MEXICO][15] = 76, ++ [0][0][1][0][RTW89_CN][15] = 127, ++ [0][0][1][0][RTW89_QATAR][15] = 52, + [0][0][1][0][RTW89_FCC][17] = 76, + [0][0][1][0][RTW89_ETSI][17] = 58, + [0][0][1][0][RTW89_MKK][17] = 76, + [0][0][1][0][RTW89_IC][17] = 76, +- [0][0][1][0][RTW89_KCC][17] = 58, ++ [0][0][1][0][RTW89_KCC][17] = 76, + [0][0][1][0][RTW89_ACMA][17] = 58, + [0][0][1][0][RTW89_CHILE][17] = 54, + [0][0][1][0][RTW89_UKRAINE][17] = 52, ++ [0][0][1][0][RTW89_MEXICO][17] = 76, ++ [0][0][1][0][RTW89_CN][17] = 127, ++ [0][0][1][0][RTW89_QATAR][17] = 52, + [0][0][1][0][RTW89_FCC][19] = 76, + [0][0][1][0][RTW89_ETSI][19] = 58, + [0][0][1][0][RTW89_MKK][19] = 76, + [0][0][1][0][RTW89_IC][19] = 76, +- [0][0][1][0][RTW89_KCC][19] = 58, ++ [0][0][1][0][RTW89_KCC][19] = 76, + [0][0][1][0][RTW89_ACMA][19] = 58, + [0][0][1][0][RTW89_CHILE][19] = 54, + [0][0][1][0][RTW89_UKRAINE][19] = 52, ++ [0][0][1][0][RTW89_MEXICO][19] = 76, ++ [0][0][1][0][RTW89_CN][19] = 127, ++ [0][0][1][0][RTW89_QATAR][19] = 52, + [0][0][1][0][RTW89_FCC][21] = 76, + [0][0][1][0][RTW89_ETSI][21] = 58, + [0][0][1][0][RTW89_MKK][21] = 76, + [0][0][1][0][RTW89_IC][21] = 76, +- [0][0][1][0][RTW89_KCC][21] = 58, ++ [0][0][1][0][RTW89_KCC][21] = 76, + [0][0][1][0][RTW89_ACMA][21] = 58, + [0][0][1][0][RTW89_CHILE][21] = 54, + [0][0][1][0][RTW89_UKRAINE][21] = 52, ++ [0][0][1][0][RTW89_MEXICO][21] = 76, ++ [0][0][1][0][RTW89_CN][21] = 127, ++ [0][0][1][0][RTW89_QATAR][21] = 52, + [0][0][1][0][RTW89_FCC][23] = 76, + [0][0][1][0][RTW89_ETSI][23] = 58, + [0][0][1][0][RTW89_MKK][23] = 76, + [0][0][1][0][RTW89_IC][23] = 76, +- [0][0][1][0][RTW89_KCC][23] = 58, ++ [0][0][1][0][RTW89_KCC][23] = 76, + [0][0][1][0][RTW89_ACMA][23] = 58, + [0][0][1][0][RTW89_CHILE][23] = 54, + [0][0][1][0][RTW89_UKRAINE][23] = 52, ++ [0][0][1][0][RTW89_MEXICO][23] = 76, ++ [0][0][1][0][RTW89_CN][23] = 127, ++ [0][0][1][0][RTW89_QATAR][23] = 52, + [0][0][1][0][RTW89_FCC][25] = 76, + [0][0][1][0][RTW89_ETSI][25] = 58, + [0][0][1][0][RTW89_MKK][25] = 76, + [0][0][1][0][RTW89_IC][25] = 127, +- [0][0][1][0][RTW89_KCC][25] = 58, ++ [0][0][1][0][RTW89_KCC][25] = 76, + [0][0][1][0][RTW89_ACMA][25] = 127, + [0][0][1][0][RTW89_CHILE][25] = 54, + [0][0][1][0][RTW89_UKRAINE][25] = 52, ++ [0][0][1][0][RTW89_MEXICO][25] = 76, ++ [0][0][1][0][RTW89_CN][25] = 127, ++ [0][0][1][0][RTW89_QATAR][25] = 52, + [0][0][1][0][RTW89_FCC][27] = 76, + [0][0][1][0][RTW89_ETSI][27] = 58, + [0][0][1][0][RTW89_MKK][27] = 76, + [0][0][1][0][RTW89_IC][27] = 127, +- [0][0][1][0][RTW89_KCC][27] = 58, ++ [0][0][1][0][RTW89_KCC][27] = 76, + [0][0][1][0][RTW89_ACMA][27] = 127, + [0][0][1][0][RTW89_CHILE][27] = 54, + [0][0][1][0][RTW89_UKRAINE][27] = 52, ++ [0][0][1][0][RTW89_MEXICO][27] = 76, ++ [0][0][1][0][RTW89_CN][27] = 127, ++ [0][0][1][0][RTW89_QATAR][27] = 52, + [0][0][1][0][RTW89_FCC][29] = 76, + [0][0][1][0][RTW89_ETSI][29] = 58, + [0][0][1][0][RTW89_MKK][29] = 76, + [0][0][1][0][RTW89_IC][29] = 127, +- [0][0][1][0][RTW89_KCC][29] = 58, ++ [0][0][1][0][RTW89_KCC][29] = 76, + [0][0][1][0][RTW89_ACMA][29] = 127, + [0][0][1][0][RTW89_CHILE][29] = 54, + [0][0][1][0][RTW89_UKRAINE][29] = 52, ++ [0][0][1][0][RTW89_MEXICO][29] = 76, ++ [0][0][1][0][RTW89_CN][29] = 127, ++ [0][0][1][0][RTW89_QATAR][29] = 52, + [0][0][1][0][RTW89_FCC][31] = 76, + [0][0][1][0][RTW89_ETSI][31] = 58, + [0][0][1][0][RTW89_MKK][31] = 76, + [0][0][1][0][RTW89_IC][31] = 76, +- [0][0][1][0][RTW89_KCC][31] = 58, ++ [0][0][1][0][RTW89_KCC][31] = 76, + [0][0][1][0][RTW89_ACMA][31] = 58, + [0][0][1][0][RTW89_CHILE][31] = 54, + [0][0][1][0][RTW89_UKRAINE][31] = 52, ++ [0][0][1][0][RTW89_MEXICO][31] = 76, ++ [0][0][1][0][RTW89_CN][31] = 127, ++ [0][0][1][0][RTW89_QATAR][31] = 52, + [0][0][1][0][RTW89_FCC][33] = 76, + [0][0][1][0][RTW89_ETSI][33] = 58, + [0][0][1][0][RTW89_MKK][33] = 76, + [0][0][1][0][RTW89_IC][33] = 76, +- [0][0][1][0][RTW89_KCC][33] = 58, ++ [0][0][1][0][RTW89_KCC][33] = 76, + [0][0][1][0][RTW89_ACMA][33] = 58, + [0][0][1][0][RTW89_CHILE][33] = 54, + [0][0][1][0][RTW89_UKRAINE][33] = 52, ++ [0][0][1][0][RTW89_MEXICO][33] = 76, ++ [0][0][1][0][RTW89_CN][33] = 127, ++ [0][0][1][0][RTW89_QATAR][33] = 52, + [0][0][1][0][RTW89_FCC][35] = 74, + [0][0][1][0][RTW89_ETSI][35] = 58, + [0][0][1][0][RTW89_MKK][35] = 76, + [0][0][1][0][RTW89_IC][35] = 74, +- [0][0][1][0][RTW89_KCC][35] = 58, ++ [0][0][1][0][RTW89_KCC][35] = 76, + [0][0][1][0][RTW89_ACMA][35] = 58, + [0][0][1][0][RTW89_CHILE][35] = 54, + [0][0][1][0][RTW89_UKRAINE][35] = 52, ++ [0][0][1][0][RTW89_MEXICO][35] = 74, ++ [0][0][1][0][RTW89_CN][35] = 127, ++ [0][0][1][0][RTW89_QATAR][35] = 52, + [0][0][1][0][RTW89_FCC][37] = 76, + [0][0][1][0][RTW89_ETSI][37] = 127, + [0][0][1][0][RTW89_MKK][37] = 76, + [0][0][1][0][RTW89_IC][37] = 76, +- [0][0][1][0][RTW89_KCC][37] = 58, ++ [0][0][1][0][RTW89_KCC][37] = 76, + [0][0][1][0][RTW89_ACMA][37] = 76, + [0][0][1][0][RTW89_CHILE][37] = 54, + [0][0][1][0][RTW89_UKRAINE][37] = 127, ++ [0][0][1][0][RTW89_MEXICO][37] = 76, ++ [0][0][1][0][RTW89_CN][37] = 127, ++ [0][0][1][0][RTW89_QATAR][37] = 127, + [0][0][1][0][RTW89_FCC][38] = 76, + [0][0][1][0][RTW89_ETSI][38] = 28, + [0][0][1][0][RTW89_MKK][38] = 127, + [0][0][1][0][RTW89_IC][38] = 76, +- [0][0][1][0][RTW89_KCC][38] = 28, ++ [0][0][1][0][RTW89_KCC][38] = 76, + [0][0][1][0][RTW89_ACMA][38] = 76, + [0][0][1][0][RTW89_CHILE][38] = 54, +- [0][0][1][0][RTW89_UKRAINE][38] = 52, ++ [0][0][1][0][RTW89_UKRAINE][38] = 28, ++ [0][0][1][0][RTW89_MEXICO][38] = 76, ++ [0][0][1][0][RTW89_CN][38] = 72, ++ [0][0][1][0][RTW89_QATAR][38] = 28, + [0][0][1][0][RTW89_FCC][40] = 76, + [0][0][1][0][RTW89_ETSI][40] = 28, + [0][0][1][0][RTW89_MKK][40] = 127, + [0][0][1][0][RTW89_IC][40] = 76, +- [0][0][1][0][RTW89_KCC][40] = 28, ++ [0][0][1][0][RTW89_KCC][40] = 76, + [0][0][1][0][RTW89_ACMA][40] = 76, + [0][0][1][0][RTW89_CHILE][40] = 54, +- [0][0][1][0][RTW89_UKRAINE][40] = 52, ++ [0][0][1][0][RTW89_UKRAINE][40] = 28, ++ [0][0][1][0][RTW89_MEXICO][40] = 76, ++ [0][0][1][0][RTW89_CN][40] = 76, ++ [0][0][1][0][RTW89_QATAR][40] = 28, + [0][0][1][0][RTW89_FCC][42] = 76, + [0][0][1][0][RTW89_ETSI][42] = 28, + [0][0][1][0][RTW89_MKK][42] = 127, + [0][0][1][0][RTW89_IC][42] = 76, +- [0][0][1][0][RTW89_KCC][42] = 28, ++ [0][0][1][0][RTW89_KCC][42] = 76, + [0][0][1][0][RTW89_ACMA][42] = 76, + [0][0][1][0][RTW89_CHILE][42] = 54, +- [0][0][1][0][RTW89_UKRAINE][42] = 52, ++ [0][0][1][0][RTW89_UKRAINE][42] = 28, ++ [0][0][1][0][RTW89_MEXICO][42] = 76, ++ [0][0][1][0][RTW89_CN][42] = 76, ++ [0][0][1][0][RTW89_QATAR][42] = 28, + [0][0][1][0][RTW89_FCC][44] = 76, + [0][0][1][0][RTW89_ETSI][44] = 28, + [0][0][1][0][RTW89_MKK][44] = 127, + [0][0][1][0][RTW89_IC][44] = 76, +- [0][0][1][0][RTW89_KCC][44] = 28, ++ [0][0][1][0][RTW89_KCC][44] = 76, + [0][0][1][0][RTW89_ACMA][44] = 76, + [0][0][1][0][RTW89_CHILE][44] = 54, +- [0][0][1][0][RTW89_UKRAINE][44] = 52, ++ [0][0][1][0][RTW89_UKRAINE][44] = 28, ++ [0][0][1][0][RTW89_MEXICO][44] = 76, ++ [0][0][1][0][RTW89_CN][44] = 76, ++ [0][0][1][0][RTW89_QATAR][44] = 28, + [0][0][1][0][RTW89_FCC][46] = 76, + [0][0][1][0][RTW89_ETSI][46] = 28, + [0][0][1][0][RTW89_MKK][46] = 127, + [0][0][1][0][RTW89_IC][46] = 76, +- [0][0][1][0][RTW89_KCC][46] = 28, ++ [0][0][1][0][RTW89_KCC][46] = 76, + [0][0][1][0][RTW89_ACMA][46] = 76, + [0][0][1][0][RTW89_CHILE][46] = 54, +- [0][0][1][0][RTW89_UKRAINE][46] = 52, ++ [0][0][1][0][RTW89_UKRAINE][46] = 28, ++ [0][0][1][0][RTW89_MEXICO][46] = 76, ++ [0][0][1][0][RTW89_CN][46] = 76, ++ [0][0][1][0][RTW89_QATAR][46] = 28, + [0][1][1][0][RTW89_FCC][0] = 68, + [0][1][1][0][RTW89_ETSI][0] = 46, + [0][1][1][0][RTW89_MKK][0] = 50, + [0][1][1][0][RTW89_IC][0] = 40, +- [0][1][1][0][RTW89_KCC][0] = 46, ++ [0][1][1][0][RTW89_KCC][0] = 72, + [0][1][1][0][RTW89_ACMA][0] = 46, + [0][1][1][0][RTW89_CHILE][0] = 18, + [0][1][1][0][RTW89_UKRAINE][0] = 40, ++ [0][1][1][0][RTW89_MEXICO][0] = 50, ++ [0][1][1][0][RTW89_CN][0] = 46, ++ [0][1][1][0][RTW89_QATAR][0] = 46, + [0][1][1][0][RTW89_FCC][2] = 68, + [0][1][1][0][RTW89_ETSI][2] = 46, + [0][1][1][0][RTW89_MKK][2] = 50, + [0][1][1][0][RTW89_IC][2] = 40, +- [0][1][1][0][RTW89_KCC][2] = 46, ++ [0][1][1][0][RTW89_KCC][2] = 72, + [0][1][1][0][RTW89_ACMA][2] = 46, + [0][1][1][0][RTW89_CHILE][2] = 18, + [0][1][1][0][RTW89_UKRAINE][2] = 40, ++ [0][1][1][0][RTW89_MEXICO][2] = 50, ++ [0][1][1][0][RTW89_CN][2] = 46, ++ [0][1][1][0][RTW89_QATAR][2] = 46, + [0][1][1][0][RTW89_FCC][4] = 68, + [0][1][1][0][RTW89_ETSI][4] = 46, + [0][1][1][0][RTW89_MKK][4] = 50, + [0][1][1][0][RTW89_IC][4] = 40, +- [0][1][1][0][RTW89_KCC][4] = 46, ++ [0][1][1][0][RTW89_KCC][4] = 72, + [0][1][1][0][RTW89_ACMA][4] = 46, + [0][1][1][0][RTW89_CHILE][4] = 18, + [0][1][1][0][RTW89_UKRAINE][4] = 40, ++ [0][1][1][0][RTW89_MEXICO][4] = 50, ++ [0][1][1][0][RTW89_CN][4] = 46, ++ [0][1][1][0][RTW89_QATAR][4] = 46, + [0][1][1][0][RTW89_FCC][6] = 68, + [0][1][1][0][RTW89_ETSI][6] = 46, + [0][1][1][0][RTW89_MKK][6] = 50, + [0][1][1][0][RTW89_IC][6] = 40, +- [0][1][1][0][RTW89_KCC][6] = 36, ++ [0][1][1][0][RTW89_KCC][6] = 44, + [0][1][1][0][RTW89_ACMA][6] = 46, + [0][1][1][0][RTW89_CHILE][6] = 18, + [0][1][1][0][RTW89_UKRAINE][6] = 40, ++ [0][1][1][0][RTW89_MEXICO][6] = 50, ++ [0][1][1][0][RTW89_CN][6] = 46, ++ [0][1][1][0][RTW89_QATAR][6] = 46, + [0][1][1][0][RTW89_FCC][8] = 68, + [0][1][1][0][RTW89_ETSI][8] = 46, + [0][1][1][0][RTW89_MKK][8] = 50, + [0][1][1][0][RTW89_IC][8] = 52, +- [0][1][1][0][RTW89_KCC][8] = 46, ++ [0][1][1][0][RTW89_KCC][8] = 72, + [0][1][1][0][RTW89_ACMA][8] = 46, + [0][1][1][0][RTW89_CHILE][8] = 42, + [0][1][1][0][RTW89_UKRAINE][8] = 40, ++ [0][1][1][0][RTW89_MEXICO][8] = 68, ++ [0][1][1][0][RTW89_CN][8] = 46, ++ [0][1][1][0][RTW89_QATAR][8] = 46, + [0][1][1][0][RTW89_FCC][10] = 68, + [0][1][1][0][RTW89_ETSI][10] = 46, + [0][1][1][0][RTW89_MKK][10] = 50, + [0][1][1][0][RTW89_IC][10] = 52, +- [0][1][1][0][RTW89_KCC][10] = 46, ++ [0][1][1][0][RTW89_KCC][10] = 72, + [0][1][1][0][RTW89_ACMA][10] = 46, + [0][1][1][0][RTW89_CHILE][10] = 42, + [0][1][1][0][RTW89_UKRAINE][10] = 40, ++ [0][1][1][0][RTW89_MEXICO][10] = 68, ++ [0][1][1][0][RTW89_CN][10] = 46, ++ [0][1][1][0][RTW89_QATAR][10] = 46, + [0][1][1][0][RTW89_FCC][12] = 68, + [0][1][1][0][RTW89_ETSI][12] = 46, + [0][1][1][0][RTW89_MKK][12] = 50, + [0][1][1][0][RTW89_IC][12] = 52, +- [0][1][1][0][RTW89_KCC][12] = 46, ++ [0][1][1][0][RTW89_KCC][12] = 72, + [0][1][1][0][RTW89_ACMA][12] = 46, + [0][1][1][0][RTW89_CHILE][12] = 42, + [0][1][1][0][RTW89_UKRAINE][12] = 40, ++ [0][1][1][0][RTW89_MEXICO][12] = 68, ++ [0][1][1][0][RTW89_CN][12] = 46, ++ [0][1][1][0][RTW89_QATAR][12] = 46, + [0][1][1][0][RTW89_FCC][14] = 68, + [0][1][1][0][RTW89_ETSI][14] = 46, + [0][1][1][0][RTW89_MKK][14] = 50, + [0][1][1][0][RTW89_IC][14] = 52, +- [0][1][1][0][RTW89_KCC][14] = 46, ++ [0][1][1][0][RTW89_KCC][14] = 72, + [0][1][1][0][RTW89_ACMA][14] = 46, + [0][1][1][0][RTW89_CHILE][14] = 42, + [0][1][1][0][RTW89_UKRAINE][14] = 40, ++ [0][1][1][0][RTW89_MEXICO][14] = 68, ++ [0][1][1][0][RTW89_CN][14] = 46, ++ [0][1][1][0][RTW89_QATAR][14] = 46, + [0][1][1][0][RTW89_FCC][15] = 68, + [0][1][1][0][RTW89_ETSI][15] = 46, + [0][1][1][0][RTW89_MKK][15] = 70, + [0][1][1][0][RTW89_IC][15] = 68, +- [0][1][1][0][RTW89_KCC][15] = 46, ++ [0][1][1][0][RTW89_KCC][15] = 72, + [0][1][1][0][RTW89_ACMA][15] = 46, + [0][1][1][0][RTW89_CHILE][15] = 42, + [0][1][1][0][RTW89_UKRAINE][15] = 40, ++ [0][1][1][0][RTW89_MEXICO][15] = 68, ++ [0][1][1][0][RTW89_CN][15] = 127, ++ [0][1][1][0][RTW89_QATAR][15] = 40, + [0][1][1][0][RTW89_FCC][17] = 68, + [0][1][1][0][RTW89_ETSI][17] = 46, + [0][1][1][0][RTW89_MKK][17] = 70, + [0][1][1][0][RTW89_IC][17] = 68, +- [0][1][1][0][RTW89_KCC][17] = 46, ++ [0][1][1][0][RTW89_KCC][17] = 72, + [0][1][1][0][RTW89_ACMA][17] = 46, + [0][1][1][0][RTW89_CHILE][17] = 42, + [0][1][1][0][RTW89_UKRAINE][17] = 40, ++ [0][1][1][0][RTW89_MEXICO][17] = 68, ++ [0][1][1][0][RTW89_CN][17] = 127, ++ [0][1][1][0][RTW89_QATAR][17] = 40, + [0][1][1][0][RTW89_FCC][19] = 68, + [0][1][1][0][RTW89_ETSI][19] = 46, + [0][1][1][0][RTW89_MKK][19] = 70, + [0][1][1][0][RTW89_IC][19] = 68, +- [0][1][1][0][RTW89_KCC][19] = 46, ++ [0][1][1][0][RTW89_KCC][19] = 72, + [0][1][1][0][RTW89_ACMA][19] = 46, + [0][1][1][0][RTW89_CHILE][19] = 42, + [0][1][1][0][RTW89_UKRAINE][19] = 40, ++ [0][1][1][0][RTW89_MEXICO][19] = 68, ++ [0][1][1][0][RTW89_CN][19] = 127, ++ [0][1][1][0][RTW89_QATAR][19] = 40, + [0][1][1][0][RTW89_FCC][21] = 68, + [0][1][1][0][RTW89_ETSI][21] = 46, + [0][1][1][0][RTW89_MKK][21] = 70, + [0][1][1][0][RTW89_IC][21] = 68, +- [0][1][1][0][RTW89_KCC][21] = 46, ++ [0][1][1][0][RTW89_KCC][21] = 72, + [0][1][1][0][RTW89_ACMA][21] = 46, + [0][1][1][0][RTW89_CHILE][21] = 42, + [0][1][1][0][RTW89_UKRAINE][21] = 40, ++ [0][1][1][0][RTW89_MEXICO][21] = 68, ++ [0][1][1][0][RTW89_CN][21] = 127, ++ [0][1][1][0][RTW89_QATAR][21] = 40, + [0][1][1][0][RTW89_FCC][23] = 68, + [0][1][1][0][RTW89_ETSI][23] = 46, + [0][1][1][0][RTW89_MKK][23] = 70, + [0][1][1][0][RTW89_IC][23] = 68, +- [0][1][1][0][RTW89_KCC][23] = 46, ++ [0][1][1][0][RTW89_KCC][23] = 72, + [0][1][1][0][RTW89_ACMA][23] = 46, + [0][1][1][0][RTW89_CHILE][23] = 42, + [0][1][1][0][RTW89_UKRAINE][23] = 40, ++ [0][1][1][0][RTW89_MEXICO][23] = 68, ++ [0][1][1][0][RTW89_CN][23] = 127, ++ [0][1][1][0][RTW89_QATAR][23] = 40, + [0][1][1][0][RTW89_FCC][25] = 68, + [0][1][1][0][RTW89_ETSI][25] = 46, + [0][1][1][0][RTW89_MKK][25] = 70, + [0][1][1][0][RTW89_IC][25] = 127, +- [0][1][1][0][RTW89_KCC][25] = 46, ++ [0][1][1][0][RTW89_KCC][25] = 72, + [0][1][1][0][RTW89_ACMA][25] = 127, + [0][1][1][0][RTW89_CHILE][25] = 42, + [0][1][1][0][RTW89_UKRAINE][25] = 40, ++ [0][1][1][0][RTW89_MEXICO][25] = 68, ++ [0][1][1][0][RTW89_CN][25] = 127, ++ [0][1][1][0][RTW89_QATAR][25] = 40, + [0][1][1][0][RTW89_FCC][27] = 68, + [0][1][1][0][RTW89_ETSI][27] = 46, + [0][1][1][0][RTW89_MKK][27] = 70, + [0][1][1][0][RTW89_IC][27] = 127, +- [0][1][1][0][RTW89_KCC][27] = 46, ++ [0][1][1][0][RTW89_KCC][27] = 72, + [0][1][1][0][RTW89_ACMA][27] = 127, + [0][1][1][0][RTW89_CHILE][27] = 42, + [0][1][1][0][RTW89_UKRAINE][27] = 40, ++ [0][1][1][0][RTW89_MEXICO][27] = 68, ++ [0][1][1][0][RTW89_CN][27] = 127, ++ [0][1][1][0][RTW89_QATAR][27] = 40, + [0][1][1][0][RTW89_FCC][29] = 68, + [0][1][1][0][RTW89_ETSI][29] = 46, + [0][1][1][0][RTW89_MKK][29] = 70, + [0][1][1][0][RTW89_IC][29] = 127, +- [0][1][1][0][RTW89_KCC][29] = 46, ++ [0][1][1][0][RTW89_KCC][29] = 72, + [0][1][1][0][RTW89_ACMA][29] = 127, + [0][1][1][0][RTW89_CHILE][29] = 42, + [0][1][1][0][RTW89_UKRAINE][29] = 40, ++ [0][1][1][0][RTW89_MEXICO][29] = 68, ++ [0][1][1][0][RTW89_CN][29] = 127, ++ [0][1][1][0][RTW89_QATAR][29] = 40, + [0][1][1][0][RTW89_FCC][31] = 68, + [0][1][1][0][RTW89_ETSI][31] = 46, + [0][1][1][0][RTW89_MKK][31] = 70, + [0][1][1][0][RTW89_IC][31] = 68, +- [0][1][1][0][RTW89_KCC][31] = 46, ++ [0][1][1][0][RTW89_KCC][31] = 72, + [0][1][1][0][RTW89_ACMA][31] = 46, + [0][1][1][0][RTW89_CHILE][31] = 42, + [0][1][1][0][RTW89_UKRAINE][31] = 40, ++ [0][1][1][0][RTW89_MEXICO][31] = 68, ++ [0][1][1][0][RTW89_CN][31] = 127, ++ [0][1][1][0][RTW89_QATAR][31] = 40, + [0][1][1][0][RTW89_FCC][33] = 68, + [0][1][1][0][RTW89_ETSI][33] = 46, + [0][1][1][0][RTW89_MKK][33] = 70, + [0][1][1][0][RTW89_IC][33] = 68, +- [0][1][1][0][RTW89_KCC][33] = 46, ++ [0][1][1][0][RTW89_KCC][33] = 72, + [0][1][1][0][RTW89_ACMA][33] = 46, + [0][1][1][0][RTW89_CHILE][33] = 42, + [0][1][1][0][RTW89_UKRAINE][33] = 40, ++ [0][1][1][0][RTW89_MEXICO][33] = 68, ++ [0][1][1][0][RTW89_CN][33] = 127, ++ [0][1][1][0][RTW89_QATAR][33] = 40, + [0][1][1][0][RTW89_FCC][35] = 66, + [0][1][1][0][RTW89_ETSI][35] = 46, + [0][1][1][0][RTW89_MKK][35] = 70, + [0][1][1][0][RTW89_IC][35] = 66, +- [0][1][1][0][RTW89_KCC][35] = 46, ++ [0][1][1][0][RTW89_KCC][35] = 72, + [0][1][1][0][RTW89_ACMA][35] = 46, + [0][1][1][0][RTW89_CHILE][35] = 42, + [0][1][1][0][RTW89_UKRAINE][35] = 40, ++ [0][1][1][0][RTW89_MEXICO][35] = 66, ++ [0][1][1][0][RTW89_CN][35] = 127, ++ [0][1][1][0][RTW89_QATAR][35] = 40, + [0][1][1][0][RTW89_FCC][37] = 68, + [0][1][1][0][RTW89_ETSI][37] = 127, + [0][1][1][0][RTW89_MKK][37] = 70, + [0][1][1][0][RTW89_IC][37] = 68, +- [0][1][1][0][RTW89_KCC][37] = 46, ++ [0][1][1][0][RTW89_KCC][37] = 72, + [0][1][1][0][RTW89_ACMA][37] = 68, + [0][1][1][0][RTW89_CHILE][37] = 42, + [0][1][1][0][RTW89_UKRAINE][37] = 127, ++ [0][1][1][0][RTW89_MEXICO][37] = 68, ++ [0][1][1][0][RTW89_CN][37] = 127, ++ [0][1][1][0][RTW89_QATAR][37] = 127, + [0][1][1][0][RTW89_FCC][38] = 76, + [0][1][1][0][RTW89_ETSI][38] = 16, + [0][1][1][0][RTW89_MKK][38] = 127, + [0][1][1][0][RTW89_IC][38] = 76, +- [0][1][1][0][RTW89_KCC][38] = 16, ++ [0][1][1][0][RTW89_KCC][38] = 72, + [0][1][1][0][RTW89_ACMA][38] = 76, + [0][1][1][0][RTW89_CHILE][38] = 42, +- [0][1][1][0][RTW89_UKRAINE][38] = 40, ++ [0][1][1][0][RTW89_UKRAINE][38] = 16, ++ [0][1][1][0][RTW89_MEXICO][38] = 76, ++ [0][1][1][0][RTW89_CN][38] = 72, ++ [0][1][1][0][RTW89_QATAR][38] = 16, + [0][1][1][0][RTW89_FCC][40] = 76, + [0][1][1][0][RTW89_ETSI][40] = 16, + [0][1][1][0][RTW89_MKK][40] = 127, + [0][1][1][0][RTW89_IC][40] = 76, +- [0][1][1][0][RTW89_KCC][40] = 16, ++ [0][1][1][0][RTW89_KCC][40] = 72, + [0][1][1][0][RTW89_ACMA][40] = 76, + [0][1][1][0][RTW89_CHILE][40] = 42, +- [0][1][1][0][RTW89_UKRAINE][40] = 40, ++ [0][1][1][0][RTW89_UKRAINE][40] = 16, ++ [0][1][1][0][RTW89_MEXICO][40] = 76, ++ [0][1][1][0][RTW89_CN][40] = 76, ++ [0][1][1][0][RTW89_QATAR][40] = 16, + [0][1][1][0][RTW89_FCC][42] = 76, + [0][1][1][0][RTW89_ETSI][42] = 16, + [0][1][1][0][RTW89_MKK][42] = 127, + [0][1][1][0][RTW89_IC][42] = 76, +- [0][1][1][0][RTW89_KCC][42] = 16, ++ [0][1][1][0][RTW89_KCC][42] = 72, + [0][1][1][0][RTW89_ACMA][42] = 76, + [0][1][1][0][RTW89_CHILE][42] = 42, +- [0][1][1][0][RTW89_UKRAINE][42] = 40, ++ [0][1][1][0][RTW89_UKRAINE][42] = 16, ++ [0][1][1][0][RTW89_MEXICO][42] = 76, ++ [0][1][1][0][RTW89_CN][42] = 76, ++ [0][1][1][0][RTW89_QATAR][42] = 16, + [0][1][1][0][RTW89_FCC][44] = 76, + [0][1][1][0][RTW89_ETSI][44] = 16, + [0][1][1][0][RTW89_MKK][44] = 127, + [0][1][1][0][RTW89_IC][44] = 76, +- [0][1][1][0][RTW89_KCC][44] = 16, ++ [0][1][1][0][RTW89_KCC][44] = 72, + [0][1][1][0][RTW89_ACMA][44] = 76, + [0][1][1][0][RTW89_CHILE][44] = 42, +- [0][1][1][0][RTW89_UKRAINE][44] = 40, ++ [0][1][1][0][RTW89_UKRAINE][44] = 16, ++ [0][1][1][0][RTW89_MEXICO][44] = 76, ++ [0][1][1][0][RTW89_CN][44] = 76, ++ [0][1][1][0][RTW89_QATAR][44] = 16, + [0][1][1][0][RTW89_FCC][46] = 76, + [0][1][1][0][RTW89_ETSI][46] = 16, + [0][1][1][0][RTW89_MKK][46] = 127, + [0][1][1][0][RTW89_IC][46] = 76, +- [0][1][1][0][RTW89_KCC][46] = 16, ++ [0][1][1][0][RTW89_KCC][46] = 72, + [0][1][1][0][RTW89_ACMA][46] = 76, + [0][1][1][0][RTW89_CHILE][46] = 42, +- [0][1][1][0][RTW89_UKRAINE][46] = 40, ++ [0][1][1][0][RTW89_UKRAINE][46] = 16, ++ [0][1][1][0][RTW89_MEXICO][46] = 76, ++ [0][1][1][0][RTW89_CN][46] = 76, ++ [0][1][1][0][RTW89_QATAR][46] = 16, + [0][0][2][0][RTW89_FCC][0] = 76, + [0][0][2][0][RTW89_ETSI][0] = 58, + [0][0][2][0][RTW89_MKK][0] = 62, + [0][0][2][0][RTW89_IC][0] = 62, +- [0][0][2][0][RTW89_KCC][0] = 58, ++ [0][0][2][0][RTW89_KCC][0] = 76, + [0][0][2][0][RTW89_ACMA][0] = 58, + [0][0][2][0][RTW89_CHILE][0] = 30, + [0][0][2][0][RTW89_UKRAINE][0] = 52, ++ [0][0][2][0][RTW89_MEXICO][0] = 62, ++ [0][0][2][0][RTW89_CN][0] = 58, ++ [0][0][2][0][RTW89_QATAR][0] = 58, + [0][0][2][0][RTW89_FCC][2] = 76, + [0][0][2][0][RTW89_ETSI][2] = 58, + [0][0][2][0][RTW89_MKK][2] = 62, + [0][0][2][0][RTW89_IC][2] = 62, +- [0][0][2][0][RTW89_KCC][2] = 58, ++ [0][0][2][0][RTW89_KCC][2] = 76, + [0][0][2][0][RTW89_ACMA][2] = 58, + [0][0][2][0][RTW89_CHILE][2] = 30, + [0][0][2][0][RTW89_UKRAINE][2] = 52, ++ [0][0][2][0][RTW89_MEXICO][2] = 62, ++ [0][0][2][0][RTW89_CN][2] = 58, ++ [0][0][2][0][RTW89_QATAR][2] = 58, + [0][0][2][0][RTW89_FCC][4] = 76, + [0][0][2][0][RTW89_ETSI][4] = 58, + [0][0][2][0][RTW89_MKK][4] = 62, + [0][0][2][0][RTW89_IC][4] = 62, +- [0][0][2][0][RTW89_KCC][4] = 58, ++ [0][0][2][0][RTW89_KCC][4] = 76, + [0][0][2][0][RTW89_ACMA][4] = 58, + [0][0][2][0][RTW89_CHILE][4] = 30, + [0][0][2][0][RTW89_UKRAINE][4] = 52, ++ [0][0][2][0][RTW89_MEXICO][4] = 62, ++ [0][0][2][0][RTW89_CN][4] = 58, ++ [0][0][2][0][RTW89_QATAR][4] = 58, + [0][0][2][0][RTW89_FCC][6] = 76, + [0][0][2][0][RTW89_ETSI][6] = 58, + [0][0][2][0][RTW89_MKK][6] = 62, + [0][0][2][0][RTW89_IC][6] = 62, +- [0][0][2][0][RTW89_KCC][6] = 54, ++ [0][0][2][0][RTW89_KCC][6] = 58, + [0][0][2][0][RTW89_ACMA][6] = 58, + [0][0][2][0][RTW89_CHILE][6] = 30, + [0][0][2][0][RTW89_UKRAINE][6] = 52, ++ [0][0][2][0][RTW89_MEXICO][6] = 62, ++ [0][0][2][0][RTW89_CN][6] = 58, ++ [0][0][2][0][RTW89_QATAR][6] = 58, + [0][0][2][0][RTW89_FCC][8] = 76, + [0][0][2][0][RTW89_ETSI][8] = 58, + [0][0][2][0][RTW89_MKK][8] = 62, + [0][0][2][0][RTW89_IC][8] = 64, +- [0][0][2][0][RTW89_KCC][8] = 58, ++ [0][0][2][0][RTW89_KCC][8] = 76, + [0][0][2][0][RTW89_ACMA][8] = 58, + [0][0][2][0][RTW89_CHILE][8] = 54, + [0][0][2][0][RTW89_UKRAINE][8] = 52, ++ [0][0][2][0][RTW89_MEXICO][8] = 76, ++ [0][0][2][0][RTW89_CN][8] = 58, ++ [0][0][2][0][RTW89_QATAR][8] = 58, + [0][0][2][0][RTW89_FCC][10] = 76, + [0][0][2][0][RTW89_ETSI][10] = 58, + [0][0][2][0][RTW89_MKK][10] = 62, + [0][0][2][0][RTW89_IC][10] = 64, +- [0][0][2][0][RTW89_KCC][10] = 58, ++ [0][0][2][0][RTW89_KCC][10] = 76, + [0][0][2][0][RTW89_ACMA][10] = 58, + [0][0][2][0][RTW89_CHILE][10] = 54, + [0][0][2][0][RTW89_UKRAINE][10] = 52, ++ [0][0][2][0][RTW89_MEXICO][10] = 76, ++ [0][0][2][0][RTW89_CN][10] = 58, ++ [0][0][2][0][RTW89_QATAR][10] = 58, + [0][0][2][0][RTW89_FCC][12] = 76, + [0][0][2][0][RTW89_ETSI][12] = 58, + [0][0][2][0][RTW89_MKK][12] = 62, + [0][0][2][0][RTW89_IC][12] = 64, +- [0][0][2][0][RTW89_KCC][12] = 58, ++ [0][0][2][0][RTW89_KCC][12] = 76, + [0][0][2][0][RTW89_ACMA][12] = 58, + [0][0][2][0][RTW89_CHILE][12] = 54, + [0][0][2][0][RTW89_UKRAINE][12] = 52, ++ [0][0][2][0][RTW89_MEXICO][12] = 76, ++ [0][0][2][0][RTW89_CN][12] = 58, ++ [0][0][2][0][RTW89_QATAR][12] = 58, + [0][0][2][0][RTW89_FCC][14] = 76, + [0][0][2][0][RTW89_ETSI][14] = 58, + [0][0][2][0][RTW89_MKK][14] = 62, + [0][0][2][0][RTW89_IC][14] = 64, +- [0][0][2][0][RTW89_KCC][14] = 58, ++ [0][0][2][0][RTW89_KCC][14] = 76, + [0][0][2][0][RTW89_ACMA][14] = 58, + [0][0][2][0][RTW89_CHILE][14] = 54, + [0][0][2][0][RTW89_UKRAINE][14] = 52, ++ [0][0][2][0][RTW89_MEXICO][14] = 76, ++ [0][0][2][0][RTW89_CN][14] = 58, ++ [0][0][2][0][RTW89_QATAR][14] = 58, + [0][0][2][0][RTW89_FCC][15] = 74, + [0][0][2][0][RTW89_ETSI][15] = 58, + [0][0][2][0][RTW89_MKK][15] = 76, + [0][0][2][0][RTW89_IC][15] = 74, +- [0][0][2][0][RTW89_KCC][15] = 58, ++ [0][0][2][0][RTW89_KCC][15] = 76, + [0][0][2][0][RTW89_ACMA][15] = 58, + [0][0][2][0][RTW89_CHILE][15] = 54, + [0][0][2][0][RTW89_UKRAINE][15] = 52, ++ [0][0][2][0][RTW89_MEXICO][15] = 74, ++ [0][0][2][0][RTW89_CN][15] = 127, ++ [0][0][2][0][RTW89_QATAR][15] = 52, + [0][0][2][0][RTW89_FCC][17] = 76, + [0][0][2][0][RTW89_ETSI][17] = 58, + [0][0][2][0][RTW89_MKK][17] = 76, + [0][0][2][0][RTW89_IC][17] = 76, +- [0][0][2][0][RTW89_KCC][17] = 58, ++ [0][0][2][0][RTW89_KCC][17] = 76, + [0][0][2][0][RTW89_ACMA][17] = 58, + [0][0][2][0][RTW89_CHILE][17] = 54, + [0][0][2][0][RTW89_UKRAINE][17] = 52, ++ [0][0][2][0][RTW89_MEXICO][17] = 76, ++ [0][0][2][0][RTW89_CN][17] = 127, ++ [0][0][2][0][RTW89_QATAR][17] = 52, + [0][0][2][0][RTW89_FCC][19] = 76, + [0][0][2][0][RTW89_ETSI][19] = 58, + [0][0][2][0][RTW89_MKK][19] = 76, + [0][0][2][0][RTW89_IC][19] = 76, +- [0][0][2][0][RTW89_KCC][19] = 58, ++ [0][0][2][0][RTW89_KCC][19] = 76, + [0][0][2][0][RTW89_ACMA][19] = 58, + [0][0][2][0][RTW89_CHILE][19] = 54, + [0][0][2][0][RTW89_UKRAINE][19] = 52, ++ [0][0][2][0][RTW89_MEXICO][19] = 76, ++ [0][0][2][0][RTW89_CN][19] = 127, ++ [0][0][2][0][RTW89_QATAR][19] = 52, + [0][0][2][0][RTW89_FCC][21] = 76, + [0][0][2][0][RTW89_ETSI][21] = 58, + [0][0][2][0][RTW89_MKK][21] = 76, + [0][0][2][0][RTW89_IC][21] = 76, +- [0][0][2][0][RTW89_KCC][21] = 58, ++ [0][0][2][0][RTW89_KCC][21] = 76, + [0][0][2][0][RTW89_ACMA][21] = 58, + [0][0][2][0][RTW89_CHILE][21] = 54, + [0][0][2][0][RTW89_UKRAINE][21] = 52, ++ [0][0][2][0][RTW89_MEXICO][21] = 76, ++ [0][0][2][0][RTW89_CN][21] = 127, ++ [0][0][2][0][RTW89_QATAR][21] = 52, + [0][0][2][0][RTW89_FCC][23] = 76, + [0][0][2][0][RTW89_ETSI][23] = 58, + [0][0][2][0][RTW89_MKK][23] = 76, + [0][0][2][0][RTW89_IC][23] = 76, +- [0][0][2][0][RTW89_KCC][23] = 58, ++ [0][0][2][0][RTW89_KCC][23] = 76, + [0][0][2][0][RTW89_ACMA][23] = 58, + [0][0][2][0][RTW89_CHILE][23] = 54, + [0][0][2][0][RTW89_UKRAINE][23] = 52, ++ [0][0][2][0][RTW89_MEXICO][23] = 76, ++ [0][0][2][0][RTW89_CN][23] = 127, ++ [0][0][2][0][RTW89_QATAR][23] = 52, + [0][0][2][0][RTW89_FCC][25] = 76, + [0][0][2][0][RTW89_ETSI][25] = 58, + [0][0][2][0][RTW89_MKK][25] = 76, + [0][0][2][0][RTW89_IC][25] = 127, +- [0][0][2][0][RTW89_KCC][25] = 58, ++ [0][0][2][0][RTW89_KCC][25] = 76, + [0][0][2][0][RTW89_ACMA][25] = 127, + [0][0][2][0][RTW89_CHILE][25] = 54, + [0][0][2][0][RTW89_UKRAINE][25] = 52, ++ [0][0][2][0][RTW89_MEXICO][25] = 76, ++ [0][0][2][0][RTW89_CN][25] = 127, ++ [0][0][2][0][RTW89_QATAR][25] = 52, + [0][0][2][0][RTW89_FCC][27] = 76, + [0][0][2][0][RTW89_ETSI][27] = 58, + [0][0][2][0][RTW89_MKK][27] = 76, + [0][0][2][0][RTW89_IC][27] = 127, +- [0][0][2][0][RTW89_KCC][27] = 58, ++ [0][0][2][0][RTW89_KCC][27] = 76, + [0][0][2][0][RTW89_ACMA][27] = 127, + [0][0][2][0][RTW89_CHILE][27] = 54, + [0][0][2][0][RTW89_UKRAINE][27] = 52, ++ [0][0][2][0][RTW89_MEXICO][27] = 76, ++ [0][0][2][0][RTW89_CN][27] = 127, ++ [0][0][2][0][RTW89_QATAR][27] = 52, + [0][0][2][0][RTW89_FCC][29] = 76, + [0][0][2][0][RTW89_ETSI][29] = 58, + [0][0][2][0][RTW89_MKK][29] = 76, + [0][0][2][0][RTW89_IC][29] = 127, +- [0][0][2][0][RTW89_KCC][29] = 58, ++ [0][0][2][0][RTW89_KCC][29] = 76, + [0][0][2][0][RTW89_ACMA][29] = 127, + [0][0][2][0][RTW89_CHILE][29] = 54, + [0][0][2][0][RTW89_UKRAINE][29] = 52, ++ [0][0][2][0][RTW89_MEXICO][29] = 76, ++ [0][0][2][0][RTW89_CN][29] = 127, ++ [0][0][2][0][RTW89_QATAR][29] = 52, + [0][0][2][0][RTW89_FCC][31] = 76, + [0][0][2][0][RTW89_ETSI][31] = 58, + [0][0][2][0][RTW89_MKK][31] = 76, + [0][0][2][0][RTW89_IC][31] = 76, +- [0][0][2][0][RTW89_KCC][31] = 58, ++ [0][0][2][0][RTW89_KCC][31] = 76, + [0][0][2][0][RTW89_ACMA][31] = 58, + [0][0][2][0][RTW89_CHILE][31] = 54, + [0][0][2][0][RTW89_UKRAINE][31] = 52, ++ [0][0][2][0][RTW89_MEXICO][31] = 76, ++ [0][0][2][0][RTW89_CN][31] = 127, ++ [0][0][2][0][RTW89_QATAR][31] = 52, + [0][0][2][0][RTW89_FCC][33] = 76, + [0][0][2][0][RTW89_ETSI][33] = 58, + [0][0][2][0][RTW89_MKK][33] = 76, + [0][0][2][0][RTW89_IC][33] = 76, +- [0][0][2][0][RTW89_KCC][33] = 58, ++ [0][0][2][0][RTW89_KCC][33] = 76, + [0][0][2][0][RTW89_ACMA][33] = 58, + [0][0][2][0][RTW89_CHILE][33] = 54, + [0][0][2][0][RTW89_UKRAINE][33] = 52, ++ [0][0][2][0][RTW89_MEXICO][33] = 76, ++ [0][0][2][0][RTW89_CN][33] = 127, ++ [0][0][2][0][RTW89_QATAR][33] = 52, + [0][0][2][0][RTW89_FCC][35] = 70, + [0][0][2][0][RTW89_ETSI][35] = 58, + [0][0][2][0][RTW89_MKK][35] = 76, + [0][0][2][0][RTW89_IC][35] = 70, +- [0][0][2][0][RTW89_KCC][35] = 58, ++ [0][0][2][0][RTW89_KCC][35] = 76, + [0][0][2][0][RTW89_ACMA][35] = 58, + [0][0][2][0][RTW89_CHILE][35] = 54, + [0][0][2][0][RTW89_UKRAINE][35] = 52, ++ [0][0][2][0][RTW89_MEXICO][35] = 70, ++ [0][0][2][0][RTW89_CN][35] = 127, ++ [0][0][2][0][RTW89_QATAR][35] = 52, + [0][0][2][0][RTW89_FCC][37] = 76, + [0][0][2][0][RTW89_ETSI][37] = 127, + [0][0][2][0][RTW89_MKK][37] = 76, + [0][0][2][0][RTW89_IC][37] = 76, +- [0][0][2][0][RTW89_KCC][37] = 58, ++ [0][0][2][0][RTW89_KCC][37] = 76, + [0][0][2][0][RTW89_ACMA][37] = 76, + [0][0][2][0][RTW89_CHILE][37] = 54, + [0][0][2][0][RTW89_UKRAINE][37] = 127, ++ [0][0][2][0][RTW89_MEXICO][37] = 76, ++ [0][0][2][0][RTW89_CN][37] = 127, ++ [0][0][2][0][RTW89_QATAR][37] = 127, + [0][0][2][0][RTW89_FCC][38] = 76, + [0][0][2][0][RTW89_ETSI][38] = 28, + [0][0][2][0][RTW89_MKK][38] = 127, + [0][0][2][0][RTW89_IC][38] = 76, +- [0][0][2][0][RTW89_KCC][38] = 28, ++ [0][0][2][0][RTW89_KCC][38] = 76, + [0][0][2][0][RTW89_ACMA][38] = 76, + [0][0][2][0][RTW89_CHILE][38] = 54, +- [0][0][2][0][RTW89_UKRAINE][38] = 52, ++ [0][0][2][0][RTW89_UKRAINE][38] = 28, ++ [0][0][2][0][RTW89_MEXICO][38] = 76, ++ [0][0][2][0][RTW89_CN][38] = 68, ++ [0][0][2][0][RTW89_QATAR][38] = 28, + [0][0][2][0][RTW89_FCC][40] = 76, + [0][0][2][0][RTW89_ETSI][40] = 28, + [0][0][2][0][RTW89_MKK][40] = 127, + [0][0][2][0][RTW89_IC][40] = 76, +- [0][0][2][0][RTW89_KCC][40] = 28, ++ [0][0][2][0][RTW89_KCC][40] = 76, + [0][0][2][0][RTW89_ACMA][40] = 76, + [0][0][2][0][RTW89_CHILE][40] = 54, +- [0][0][2][0][RTW89_UKRAINE][40] = 52, ++ [0][0][2][0][RTW89_UKRAINE][40] = 28, ++ [0][0][2][0][RTW89_MEXICO][40] = 76, ++ [0][0][2][0][RTW89_CN][40] = 76, ++ [0][0][2][0][RTW89_QATAR][40] = 28, + [0][0][2][0][RTW89_FCC][42] = 76, + [0][0][2][0][RTW89_ETSI][42] = 28, + [0][0][2][0][RTW89_MKK][42] = 127, + [0][0][2][0][RTW89_IC][42] = 76, +- [0][0][2][0][RTW89_KCC][42] = 28, ++ [0][0][2][0][RTW89_KCC][42] = 76, + [0][0][2][0][RTW89_ACMA][42] = 76, + [0][0][2][0][RTW89_CHILE][42] = 54, +- [0][0][2][0][RTW89_UKRAINE][42] = 52, ++ [0][0][2][0][RTW89_UKRAINE][42] = 28, ++ [0][0][2][0][RTW89_MEXICO][42] = 76, ++ [0][0][2][0][RTW89_CN][42] = 76, ++ [0][0][2][0][RTW89_QATAR][42] = 28, + [0][0][2][0][RTW89_FCC][44] = 76, + [0][0][2][0][RTW89_ETSI][44] = 28, + [0][0][2][0][RTW89_MKK][44] = 127, + [0][0][2][0][RTW89_IC][44] = 76, +- [0][0][2][0][RTW89_KCC][44] = 28, ++ [0][0][2][0][RTW89_KCC][44] = 76, + [0][0][2][0][RTW89_ACMA][44] = 76, + [0][0][2][0][RTW89_CHILE][44] = 54, +- [0][0][2][0][RTW89_UKRAINE][44] = 52, ++ [0][0][2][0][RTW89_UKRAINE][44] = 28, ++ [0][0][2][0][RTW89_MEXICO][44] = 76, ++ [0][0][2][0][RTW89_CN][44] = 76, ++ [0][0][2][0][RTW89_QATAR][44] = 28, + [0][0][2][0][RTW89_FCC][46] = 76, + [0][0][2][0][RTW89_ETSI][46] = 28, + [0][0][2][0][RTW89_MKK][46] = 127, + [0][0][2][0][RTW89_IC][46] = 76, +- [0][0][2][0][RTW89_KCC][46] = 28, ++ [0][0][2][0][RTW89_KCC][46] = 76, + [0][0][2][0][RTW89_ACMA][46] = 76, + [0][0][2][0][RTW89_CHILE][46] = 54, +- [0][0][2][0][RTW89_UKRAINE][46] = 52, ++ [0][0][2][0][RTW89_UKRAINE][46] = 28, ++ [0][0][2][0][RTW89_MEXICO][46] = 76, ++ [0][0][2][0][RTW89_CN][46] = 76, ++ [0][0][2][0][RTW89_QATAR][46] = 28, + [0][1][2][0][RTW89_FCC][0] = 68, + [0][1][2][0][RTW89_ETSI][0] = 46, + [0][1][2][0][RTW89_MKK][0] = 50, + [0][1][2][0][RTW89_IC][0] = 40, +- [0][1][2][0][RTW89_KCC][0] = 46, ++ [0][1][2][0][RTW89_KCC][0] = 68, + [0][1][2][0][RTW89_ACMA][0] = 46, + [0][1][2][0][RTW89_CHILE][0] = 18, + [0][1][2][0][RTW89_UKRAINE][0] = 40, ++ [0][1][2][0][RTW89_MEXICO][0] = 50, ++ [0][1][2][0][RTW89_CN][0] = 46, ++ [0][1][2][0][RTW89_QATAR][0] = 46, + [0][1][2][0][RTW89_FCC][2] = 68, + [0][1][2][0][RTW89_ETSI][2] = 46, + [0][1][2][0][RTW89_MKK][2] = 50, + [0][1][2][0][RTW89_IC][2] = 40, +- [0][1][2][0][RTW89_KCC][2] = 46, ++ [0][1][2][0][RTW89_KCC][2] = 68, + [0][1][2][0][RTW89_ACMA][2] = 46, + [0][1][2][0][RTW89_CHILE][2] = 18, + [0][1][2][0][RTW89_UKRAINE][2] = 40, ++ [0][1][2][0][RTW89_MEXICO][2] = 50, ++ [0][1][2][0][RTW89_CN][2] = 46, ++ [0][1][2][0][RTW89_QATAR][2] = 46, + [0][1][2][0][RTW89_FCC][4] = 68, + [0][1][2][0][RTW89_ETSI][4] = 46, + [0][1][2][0][RTW89_MKK][4] = 50, + [0][1][2][0][RTW89_IC][4] = 40, +- [0][1][2][0][RTW89_KCC][4] = 46, ++ [0][1][2][0][RTW89_KCC][4] = 68, + [0][1][2][0][RTW89_ACMA][4] = 46, + [0][1][2][0][RTW89_CHILE][4] = 18, + [0][1][2][0][RTW89_UKRAINE][4] = 40, ++ [0][1][2][0][RTW89_MEXICO][4] = 50, ++ [0][1][2][0][RTW89_CN][4] = 46, ++ [0][1][2][0][RTW89_QATAR][4] = 46, + [0][1][2][0][RTW89_FCC][6] = 68, + [0][1][2][0][RTW89_ETSI][6] = 46, + [0][1][2][0][RTW89_MKK][6] = 50, + [0][1][2][0][RTW89_IC][6] = 40, +- [0][1][2][0][RTW89_KCC][6] = 36, ++ [0][1][2][0][RTW89_KCC][6] = 38, + [0][1][2][0][RTW89_ACMA][6] = 46, + [0][1][2][0][RTW89_CHILE][6] = 18, + [0][1][2][0][RTW89_UKRAINE][6] = 40, ++ [0][1][2][0][RTW89_MEXICO][6] = 50, ++ [0][1][2][0][RTW89_CN][6] = 46, ++ [0][1][2][0][RTW89_QATAR][6] = 46, + [0][1][2][0][RTW89_FCC][8] = 68, + [0][1][2][0][RTW89_ETSI][8] = 46, + [0][1][2][0][RTW89_MKK][8] = 50, + [0][1][2][0][RTW89_IC][8] = 52, +- [0][1][2][0][RTW89_KCC][8] = 46, ++ [0][1][2][0][RTW89_KCC][8] = 68, + [0][1][2][0][RTW89_ACMA][8] = 46, + [0][1][2][0][RTW89_CHILE][8] = 42, + [0][1][2][0][RTW89_UKRAINE][8] = 40, ++ [0][1][2][0][RTW89_MEXICO][8] = 68, ++ [0][1][2][0][RTW89_CN][8] = 46, ++ [0][1][2][0][RTW89_QATAR][8] = 46, + [0][1][2][0][RTW89_FCC][10] = 68, + [0][1][2][0][RTW89_ETSI][10] = 46, + [0][1][2][0][RTW89_MKK][10] = 50, + [0][1][2][0][RTW89_IC][10] = 52, +- [0][1][2][0][RTW89_KCC][10] = 46, ++ [0][1][2][0][RTW89_KCC][10] = 68, + [0][1][2][0][RTW89_ACMA][10] = 46, + [0][1][2][0][RTW89_CHILE][10] = 42, + [0][1][2][0][RTW89_UKRAINE][10] = 40, ++ [0][1][2][0][RTW89_MEXICO][10] = 68, ++ [0][1][2][0][RTW89_CN][10] = 46, ++ [0][1][2][0][RTW89_QATAR][10] = 46, + [0][1][2][0][RTW89_FCC][12] = 68, + [0][1][2][0][RTW89_ETSI][12] = 46, + [0][1][2][0][RTW89_MKK][12] = 50, + [0][1][2][0][RTW89_IC][12] = 52, +- [0][1][2][0][RTW89_KCC][12] = 46, ++ [0][1][2][0][RTW89_KCC][12] = 68, + [0][1][2][0][RTW89_ACMA][12] = 46, + [0][1][2][0][RTW89_CHILE][12] = 42, + [0][1][2][0][RTW89_UKRAINE][12] = 40, ++ [0][1][2][0][RTW89_MEXICO][12] = 68, ++ [0][1][2][0][RTW89_CN][12] = 46, ++ [0][1][2][0][RTW89_QATAR][12] = 46, + [0][1][2][0][RTW89_FCC][14] = 68, + [0][1][2][0][RTW89_ETSI][14] = 46, + [0][1][2][0][RTW89_MKK][14] = 50, + [0][1][2][0][RTW89_IC][14] = 52, +- [0][1][2][0][RTW89_KCC][14] = 46, ++ [0][1][2][0][RTW89_KCC][14] = 68, + [0][1][2][0][RTW89_ACMA][14] = 46, + [0][1][2][0][RTW89_CHILE][14] = 42, + [0][1][2][0][RTW89_UKRAINE][14] = 40, ++ [0][1][2][0][RTW89_MEXICO][14] = 68, ++ [0][1][2][0][RTW89_CN][14] = 46, ++ [0][1][2][0][RTW89_QATAR][14] = 46, + [0][1][2][0][RTW89_FCC][15] = 68, + [0][1][2][0][RTW89_ETSI][15] = 46, + [0][1][2][0][RTW89_MKK][15] = 70, + [0][1][2][0][RTW89_IC][15] = 68, +- [0][1][2][0][RTW89_KCC][15] = 46, ++ [0][1][2][0][RTW89_KCC][15] = 66, + [0][1][2][0][RTW89_ACMA][15] = 46, + [0][1][2][0][RTW89_CHILE][15] = 42, + [0][1][2][0][RTW89_UKRAINE][15] = 40, ++ [0][1][2][0][RTW89_MEXICO][15] = 68, ++ [0][1][2][0][RTW89_CN][15] = 127, ++ [0][1][2][0][RTW89_QATAR][15] = 40, + [0][1][2][0][RTW89_FCC][17] = 68, + [0][1][2][0][RTW89_ETSI][17] = 46, + [0][1][2][0][RTW89_MKK][17] = 70, + [0][1][2][0][RTW89_IC][17] = 68, +- [0][1][2][0][RTW89_KCC][17] = 46, ++ [0][1][2][0][RTW89_KCC][17] = 66, + [0][1][2][0][RTW89_ACMA][17] = 46, + [0][1][2][0][RTW89_CHILE][17] = 42, + [0][1][2][0][RTW89_UKRAINE][17] = 40, ++ [0][1][2][0][RTW89_MEXICO][17] = 68, ++ [0][1][2][0][RTW89_CN][17] = 127, ++ [0][1][2][0][RTW89_QATAR][17] = 40, + [0][1][2][0][RTW89_FCC][19] = 68, + [0][1][2][0][RTW89_ETSI][19] = 46, + [0][1][2][0][RTW89_MKK][19] = 70, + [0][1][2][0][RTW89_IC][19] = 68, +- [0][1][2][0][RTW89_KCC][19] = 46, ++ [0][1][2][0][RTW89_KCC][19] = 66, + [0][1][2][0][RTW89_ACMA][19] = 46, + [0][1][2][0][RTW89_CHILE][19] = 42, + [0][1][2][0][RTW89_UKRAINE][19] = 40, ++ [0][1][2][0][RTW89_MEXICO][19] = 68, ++ [0][1][2][0][RTW89_CN][19] = 127, ++ [0][1][2][0][RTW89_QATAR][19] = 40, + [0][1][2][0][RTW89_FCC][21] = 68, + [0][1][2][0][RTW89_ETSI][21] = 46, + [0][1][2][0][RTW89_MKK][21] = 70, + [0][1][2][0][RTW89_IC][21] = 68, +- [0][1][2][0][RTW89_KCC][21] = 46, ++ [0][1][2][0][RTW89_KCC][21] = 66, + [0][1][2][0][RTW89_ACMA][21] = 46, + [0][1][2][0][RTW89_CHILE][21] = 42, + [0][1][2][0][RTW89_UKRAINE][21] = 40, ++ [0][1][2][0][RTW89_MEXICO][21] = 68, ++ [0][1][2][0][RTW89_CN][21] = 127, ++ [0][1][2][0][RTW89_QATAR][21] = 40, + [0][1][2][0][RTW89_FCC][23] = 68, + [0][1][2][0][RTW89_ETSI][23] = 46, + [0][1][2][0][RTW89_MKK][23] = 70, + [0][1][2][0][RTW89_IC][23] = 68, +- [0][1][2][0][RTW89_KCC][23] = 46, ++ [0][1][2][0][RTW89_KCC][23] = 66, + [0][1][2][0][RTW89_ACMA][23] = 46, + [0][1][2][0][RTW89_CHILE][23] = 42, + [0][1][2][0][RTW89_UKRAINE][23] = 40, ++ [0][1][2][0][RTW89_MEXICO][23] = 68, ++ [0][1][2][0][RTW89_CN][23] = 127, ++ [0][1][2][0][RTW89_QATAR][23] = 40, + [0][1][2][0][RTW89_FCC][25] = 68, + [0][1][2][0][RTW89_ETSI][25] = 46, + [0][1][2][0][RTW89_MKK][25] = 70, + [0][1][2][0][RTW89_IC][25] = 127, +- [0][1][2][0][RTW89_KCC][25] = 46, ++ [0][1][2][0][RTW89_KCC][25] = 66, + [0][1][2][0][RTW89_ACMA][25] = 127, + [0][1][2][0][RTW89_CHILE][25] = 42, + [0][1][2][0][RTW89_UKRAINE][25] = 40, ++ [0][1][2][0][RTW89_MEXICO][25] = 68, ++ [0][1][2][0][RTW89_CN][25] = 127, ++ [0][1][2][0][RTW89_QATAR][25] = 40, + [0][1][2][0][RTW89_FCC][27] = 68, + [0][1][2][0][RTW89_ETSI][27] = 46, + [0][1][2][0][RTW89_MKK][27] = 70, + [0][1][2][0][RTW89_IC][27] = 127, +- [0][1][2][0][RTW89_KCC][27] = 46, ++ [0][1][2][0][RTW89_KCC][27] = 66, + [0][1][2][0][RTW89_ACMA][27] = 127, + [0][1][2][0][RTW89_CHILE][27] = 42, + [0][1][2][0][RTW89_UKRAINE][27] = 40, ++ [0][1][2][0][RTW89_MEXICO][27] = 68, ++ [0][1][2][0][RTW89_CN][27] = 127, ++ [0][1][2][0][RTW89_QATAR][27] = 40, + [0][1][2][0][RTW89_FCC][29] = 68, + [0][1][2][0][RTW89_ETSI][29] = 46, + [0][1][2][0][RTW89_MKK][29] = 70, + [0][1][2][0][RTW89_IC][29] = 127, +- [0][1][2][0][RTW89_KCC][29] = 46, ++ [0][1][2][0][RTW89_KCC][29] = 66, + [0][1][2][0][RTW89_ACMA][29] = 127, + [0][1][2][0][RTW89_CHILE][29] = 42, + [0][1][2][0][RTW89_UKRAINE][29] = 40, ++ [0][1][2][0][RTW89_MEXICO][29] = 68, ++ [0][1][2][0][RTW89_CN][29] = 127, ++ [0][1][2][0][RTW89_QATAR][29] = 40, + [0][1][2][0][RTW89_FCC][31] = 68, + [0][1][2][0][RTW89_ETSI][31] = 46, + [0][1][2][0][RTW89_MKK][31] = 70, + [0][1][2][0][RTW89_IC][31] = 68, +- [0][1][2][0][RTW89_KCC][31] = 46, ++ [0][1][2][0][RTW89_KCC][31] = 66, + [0][1][2][0][RTW89_ACMA][31] = 46, + [0][1][2][0][RTW89_CHILE][31] = 42, + [0][1][2][0][RTW89_UKRAINE][31] = 40, ++ [0][1][2][0][RTW89_MEXICO][31] = 68, ++ [0][1][2][0][RTW89_CN][31] = 127, ++ [0][1][2][0][RTW89_QATAR][31] = 40, + [0][1][2][0][RTW89_FCC][33] = 68, + [0][1][2][0][RTW89_ETSI][33] = 46, + [0][1][2][0][RTW89_MKK][33] = 70, + [0][1][2][0][RTW89_IC][33] = 68, +- [0][1][2][0][RTW89_KCC][33] = 46, ++ [0][1][2][0][RTW89_KCC][33] = 66, + [0][1][2][0][RTW89_ACMA][33] = 46, + [0][1][2][0][RTW89_CHILE][33] = 42, + [0][1][2][0][RTW89_UKRAINE][33] = 40, ++ [0][1][2][0][RTW89_MEXICO][33] = 68, ++ [0][1][2][0][RTW89_CN][33] = 127, ++ [0][1][2][0][RTW89_QATAR][33] = 40, + [0][1][2][0][RTW89_FCC][35] = 64, + [0][1][2][0][RTW89_ETSI][35] = 46, + [0][1][2][0][RTW89_MKK][35] = 70, + [0][1][2][0][RTW89_IC][35] = 64, +- [0][1][2][0][RTW89_KCC][35] = 46, ++ [0][1][2][0][RTW89_KCC][35] = 66, + [0][1][2][0][RTW89_ACMA][35] = 46, + [0][1][2][0][RTW89_CHILE][35] = 42, + [0][1][2][0][RTW89_UKRAINE][35] = 40, ++ [0][1][2][0][RTW89_MEXICO][35] = 64, ++ [0][1][2][0][RTW89_CN][35] = 127, ++ [0][1][2][0][RTW89_QATAR][35] = 40, + [0][1][2][0][RTW89_FCC][37] = 68, + [0][1][2][0][RTW89_ETSI][37] = 127, + [0][1][2][0][RTW89_MKK][37] = 70, + [0][1][2][0][RTW89_IC][37] = 68, +- [0][1][2][0][RTW89_KCC][37] = 46, ++ [0][1][2][0][RTW89_KCC][37] = 66, + [0][1][2][0][RTW89_ACMA][37] = 68, + [0][1][2][0][RTW89_CHILE][37] = 42, + [0][1][2][0][RTW89_UKRAINE][37] = 127, ++ [0][1][2][0][RTW89_MEXICO][37] = 68, ++ [0][1][2][0][RTW89_CN][37] = 127, ++ [0][1][2][0][RTW89_QATAR][37] = 127, + [0][1][2][0][RTW89_FCC][38] = 76, + [0][1][2][0][RTW89_ETSI][38] = 16, + [0][1][2][0][RTW89_MKK][38] = 127, + [0][1][2][0][RTW89_IC][38] = 76, +- [0][1][2][0][RTW89_KCC][38] = 16, ++ [0][1][2][0][RTW89_KCC][38] = 66, + [0][1][2][0][RTW89_ACMA][38] = 76, + [0][1][2][0][RTW89_CHILE][38] = 42, +- [0][1][2][0][RTW89_UKRAINE][38] = 40, ++ [0][1][2][0][RTW89_UKRAINE][38] = 16, ++ [0][1][2][0][RTW89_MEXICO][38] = 76, ++ [0][1][2][0][RTW89_CN][38] = 68, ++ [0][1][2][0][RTW89_QATAR][38] = 16, + [0][1][2][0][RTW89_FCC][40] = 76, + [0][1][2][0][RTW89_ETSI][40] = 16, + [0][1][2][0][RTW89_MKK][40] = 127, + [0][1][2][0][RTW89_IC][40] = 76, +- [0][1][2][0][RTW89_KCC][40] = 16, ++ [0][1][2][0][RTW89_KCC][40] = 66, + [0][1][2][0][RTW89_ACMA][40] = 76, + [0][1][2][0][RTW89_CHILE][40] = 42, +- [0][1][2][0][RTW89_UKRAINE][40] = 40, ++ [0][1][2][0][RTW89_UKRAINE][40] = 16, ++ [0][1][2][0][RTW89_MEXICO][40] = 76, ++ [0][1][2][0][RTW89_CN][40] = 76, ++ [0][1][2][0][RTW89_QATAR][40] = 16, + [0][1][2][0][RTW89_FCC][42] = 76, + [0][1][2][0][RTW89_ETSI][42] = 16, + [0][1][2][0][RTW89_MKK][42] = 127, + [0][1][2][0][RTW89_IC][42] = 76, +- [0][1][2][0][RTW89_KCC][42] = 16, ++ [0][1][2][0][RTW89_KCC][42] = 66, + [0][1][2][0][RTW89_ACMA][42] = 76, + [0][1][2][0][RTW89_CHILE][42] = 42, +- [0][1][2][0][RTW89_UKRAINE][42] = 40, ++ [0][1][2][0][RTW89_UKRAINE][42] = 16, ++ [0][1][2][0][RTW89_MEXICO][42] = 76, ++ [0][1][2][0][RTW89_CN][42] = 76, ++ [0][1][2][0][RTW89_QATAR][42] = 16, + [0][1][2][0][RTW89_FCC][44] = 76, + [0][1][2][0][RTW89_ETSI][44] = 16, + [0][1][2][0][RTW89_MKK][44] = 127, + [0][1][2][0][RTW89_IC][44] = 76, +- [0][1][2][0][RTW89_KCC][44] = 16, ++ [0][1][2][0][RTW89_KCC][44] = 66, + [0][1][2][0][RTW89_ACMA][44] = 76, + [0][1][2][0][RTW89_CHILE][44] = 42, +- [0][1][2][0][RTW89_UKRAINE][44] = 40, ++ [0][1][2][0][RTW89_UKRAINE][44] = 16, ++ [0][1][2][0][RTW89_MEXICO][44] = 76, ++ [0][1][2][0][RTW89_CN][44] = 76, ++ [0][1][2][0][RTW89_QATAR][44] = 16, + [0][1][2][0][RTW89_FCC][46] = 76, + [0][1][2][0][RTW89_ETSI][46] = 16, + [0][1][2][0][RTW89_MKK][46] = 127, + [0][1][2][0][RTW89_IC][46] = 76, +- [0][1][2][0][RTW89_KCC][46] = 16, ++ [0][1][2][0][RTW89_KCC][46] = 66, + [0][1][2][0][RTW89_ACMA][46] = 76, + [0][1][2][0][RTW89_CHILE][46] = 42, +- [0][1][2][0][RTW89_UKRAINE][46] = 40, ++ [0][1][2][0][RTW89_UKRAINE][46] = 16, ++ [0][1][2][0][RTW89_MEXICO][46] = 76, ++ [0][1][2][0][RTW89_CN][46] = 76, ++ [0][1][2][0][RTW89_QATAR][46] = 16, + [0][1][2][1][RTW89_FCC][0] = 68, + [0][1][2][1][RTW89_ETSI][0] = 34, + [0][1][2][1][RTW89_MKK][0] = 50, + [0][1][2][1][RTW89_IC][0] = 38, +- [0][1][2][1][RTW89_KCC][0] = 34, ++ [0][1][2][1][RTW89_KCC][0] = 68, + [0][1][2][1][RTW89_ACMA][0] = 34, + [0][1][2][1][RTW89_CHILE][0] = 6, + [0][1][2][1][RTW89_UKRAINE][0] = 28, ++ [0][1][2][1][RTW89_MEXICO][0] = 50, ++ [0][1][2][1][RTW89_CN][0] = 34, ++ [0][1][2][1][RTW89_QATAR][0] = 34, + [0][1][2][1][RTW89_FCC][2] = 68, + [0][1][2][1][RTW89_ETSI][2] = 34, + [0][1][2][1][RTW89_MKK][2] = 50, + [0][1][2][1][RTW89_IC][2] = 38, +- [0][1][2][1][RTW89_KCC][2] = 34, ++ [0][1][2][1][RTW89_KCC][2] = 68, + [0][1][2][1][RTW89_ACMA][2] = 34, + [0][1][2][1][RTW89_CHILE][2] = 6, + [0][1][2][1][RTW89_UKRAINE][2] = 28, ++ [0][1][2][1][RTW89_MEXICO][2] = 50, ++ [0][1][2][1][RTW89_CN][2] = 34, ++ [0][1][2][1][RTW89_QATAR][2] = 34, + [0][1][2][1][RTW89_FCC][4] = 68, + [0][1][2][1][RTW89_ETSI][4] = 34, + [0][1][2][1][RTW89_MKK][4] = 50, + [0][1][2][1][RTW89_IC][4] = 38, +- [0][1][2][1][RTW89_KCC][4] = 34, ++ [0][1][2][1][RTW89_KCC][4] = 68, + [0][1][2][1][RTW89_ACMA][4] = 34, + [0][1][2][1][RTW89_CHILE][4] = 6, + [0][1][2][1][RTW89_UKRAINE][4] = 28, ++ [0][1][2][1][RTW89_MEXICO][4] = 50, ++ [0][1][2][1][RTW89_CN][4] = 34, ++ [0][1][2][1][RTW89_QATAR][4] = 34, + [0][1][2][1][RTW89_FCC][6] = 68, + [0][1][2][1][RTW89_ETSI][6] = 34, + [0][1][2][1][RTW89_MKK][6] = 50, + [0][1][2][1][RTW89_IC][6] = 38, +- [0][1][2][1][RTW89_KCC][6] = 34, ++ [0][1][2][1][RTW89_KCC][6] = 38, + [0][1][2][1][RTW89_ACMA][6] = 34, + [0][1][2][1][RTW89_CHILE][6] = 6, + [0][1][2][1][RTW89_UKRAINE][6] = 28, ++ [0][1][2][1][RTW89_MEXICO][6] = 50, ++ [0][1][2][1][RTW89_CN][6] = 34, ++ [0][1][2][1][RTW89_QATAR][6] = 34, + [0][1][2][1][RTW89_FCC][8] = 68, + [0][1][2][1][RTW89_ETSI][8] = 34, + [0][1][2][1][RTW89_MKK][8] = 50, + [0][1][2][1][RTW89_IC][8] = 38, +- [0][1][2][1][RTW89_KCC][8] = 34, ++ [0][1][2][1][RTW89_KCC][8] = 68, + [0][1][2][1][RTW89_ACMA][8] = 34, + [0][1][2][1][RTW89_CHILE][8] = 30, + [0][1][2][1][RTW89_UKRAINE][8] = 28, ++ [0][1][2][1][RTW89_MEXICO][8] = 68, ++ [0][1][2][1][RTW89_CN][8] = 34, ++ [0][1][2][1][RTW89_QATAR][8] = 34, + [0][1][2][1][RTW89_FCC][10] = 68, + [0][1][2][1][RTW89_ETSI][10] = 34, + [0][1][2][1][RTW89_MKK][10] = 50, + [0][1][2][1][RTW89_IC][10] = 38, +- [0][1][2][1][RTW89_KCC][10] = 34, ++ [0][1][2][1][RTW89_KCC][10] = 68, + [0][1][2][1][RTW89_ACMA][10] = 34, + [0][1][2][1][RTW89_CHILE][10] = 30, + [0][1][2][1][RTW89_UKRAINE][10] = 28, ++ [0][1][2][1][RTW89_MEXICO][10] = 68, ++ [0][1][2][1][RTW89_CN][10] = 34, ++ [0][1][2][1][RTW89_QATAR][10] = 34, + [0][1][2][1][RTW89_FCC][12] = 68, + [0][1][2][1][RTW89_ETSI][12] = 34, + [0][1][2][1][RTW89_MKK][12] = 50, + [0][1][2][1][RTW89_IC][12] = 38, +- [0][1][2][1][RTW89_KCC][12] = 34, ++ [0][1][2][1][RTW89_KCC][12] = 68, + [0][1][2][1][RTW89_ACMA][12] = 34, + [0][1][2][1][RTW89_CHILE][12] = 30, + [0][1][2][1][RTW89_UKRAINE][12] = 28, ++ [0][1][2][1][RTW89_MEXICO][12] = 68, ++ [0][1][2][1][RTW89_CN][12] = 34, ++ [0][1][2][1][RTW89_QATAR][12] = 34, + [0][1][2][1][RTW89_FCC][14] = 68, + [0][1][2][1][RTW89_ETSI][14] = 34, + [0][1][2][1][RTW89_MKK][14] = 50, + [0][1][2][1][RTW89_IC][14] = 38, +- [0][1][2][1][RTW89_KCC][14] = 34, ++ [0][1][2][1][RTW89_KCC][14] = 68, + [0][1][2][1][RTW89_ACMA][14] = 34, + [0][1][2][1][RTW89_CHILE][14] = 30, + [0][1][2][1][RTW89_UKRAINE][14] = 28, ++ [0][1][2][1][RTW89_MEXICO][14] = 68, ++ [0][1][2][1][RTW89_CN][14] = 34, ++ [0][1][2][1][RTW89_QATAR][14] = 34, + [0][1][2][1][RTW89_FCC][15] = 68, + [0][1][2][1][RTW89_ETSI][15] = 34, + [0][1][2][1][RTW89_MKK][15] = 70, + [0][1][2][1][RTW89_IC][15] = 62, +- [0][1][2][1][RTW89_KCC][15] = 34, ++ [0][1][2][1][RTW89_KCC][15] = 66, + [0][1][2][1][RTW89_ACMA][15] = 34, + [0][1][2][1][RTW89_CHILE][15] = 30, + [0][1][2][1][RTW89_UKRAINE][15] = 28, ++ [0][1][2][1][RTW89_MEXICO][15] = 68, ++ [0][1][2][1][RTW89_CN][15] = 127, ++ [0][1][2][1][RTW89_QATAR][15] = 28, + [0][1][2][1][RTW89_FCC][17] = 68, + [0][1][2][1][RTW89_ETSI][17] = 34, + [0][1][2][1][RTW89_MKK][17] = 70, + [0][1][2][1][RTW89_IC][17] = 62, +- [0][1][2][1][RTW89_KCC][17] = 34, ++ [0][1][2][1][RTW89_KCC][17] = 66, + [0][1][2][1][RTW89_ACMA][17] = 34, + [0][1][2][1][RTW89_CHILE][17] = 30, + [0][1][2][1][RTW89_UKRAINE][17] = 28, ++ [0][1][2][1][RTW89_MEXICO][17] = 68, ++ [0][1][2][1][RTW89_CN][17] = 127, ++ [0][1][2][1][RTW89_QATAR][17] = 28, + [0][1][2][1][RTW89_FCC][19] = 68, + [0][1][2][1][RTW89_ETSI][19] = 34, + [0][1][2][1][RTW89_MKK][19] = 70, + [0][1][2][1][RTW89_IC][19] = 62, +- [0][1][2][1][RTW89_KCC][19] = 34, ++ [0][1][2][1][RTW89_KCC][19] = 66, + [0][1][2][1][RTW89_ACMA][19] = 34, + [0][1][2][1][RTW89_CHILE][19] = 30, + [0][1][2][1][RTW89_UKRAINE][19] = 28, ++ [0][1][2][1][RTW89_MEXICO][19] = 68, ++ [0][1][2][1][RTW89_CN][19] = 127, ++ [0][1][2][1][RTW89_QATAR][19] = 28, + [0][1][2][1][RTW89_FCC][21] = 68, + [0][1][2][1][RTW89_ETSI][21] = 34, + [0][1][2][1][RTW89_MKK][21] = 70, + [0][1][2][1][RTW89_IC][21] = 62, +- [0][1][2][1][RTW89_KCC][21] = 34, ++ [0][1][2][1][RTW89_KCC][21] = 66, + [0][1][2][1][RTW89_ACMA][21] = 34, + [0][1][2][1][RTW89_CHILE][21] = 30, + [0][1][2][1][RTW89_UKRAINE][21] = 28, ++ [0][1][2][1][RTW89_MEXICO][21] = 68, ++ [0][1][2][1][RTW89_CN][21] = 127, ++ [0][1][2][1][RTW89_QATAR][21] = 28, + [0][1][2][1][RTW89_FCC][23] = 68, + [0][1][2][1][RTW89_ETSI][23] = 34, + [0][1][2][1][RTW89_MKK][23] = 70, + [0][1][2][1][RTW89_IC][23] = 62, +- [0][1][2][1][RTW89_KCC][23] = 34, ++ [0][1][2][1][RTW89_KCC][23] = 66, + [0][1][2][1][RTW89_ACMA][23] = 34, + [0][1][2][1][RTW89_CHILE][23] = 30, + [0][1][2][1][RTW89_UKRAINE][23] = 28, ++ [0][1][2][1][RTW89_MEXICO][23] = 68, ++ [0][1][2][1][RTW89_CN][23] = 127, ++ [0][1][2][1][RTW89_QATAR][23] = 28, + [0][1][2][1][RTW89_FCC][25] = 68, + [0][1][2][1][RTW89_ETSI][25] = 34, + [0][1][2][1][RTW89_MKK][25] = 70, + [0][1][2][1][RTW89_IC][25] = 127, +- [0][1][2][1][RTW89_KCC][25] = 34, ++ [0][1][2][1][RTW89_KCC][25] = 66, + [0][1][2][1][RTW89_ACMA][25] = 127, + [0][1][2][1][RTW89_CHILE][25] = 30, + [0][1][2][1][RTW89_UKRAINE][25] = 28, ++ [0][1][2][1][RTW89_MEXICO][25] = 68, ++ [0][1][2][1][RTW89_CN][25] = 127, ++ [0][1][2][1][RTW89_QATAR][25] = 28, + [0][1][2][1][RTW89_FCC][27] = 68, + [0][1][2][1][RTW89_ETSI][27] = 34, + [0][1][2][1][RTW89_MKK][27] = 70, + [0][1][2][1][RTW89_IC][27] = 127, +- [0][1][2][1][RTW89_KCC][27] = 34, ++ [0][1][2][1][RTW89_KCC][27] = 66, + [0][1][2][1][RTW89_ACMA][27] = 127, + [0][1][2][1][RTW89_CHILE][27] = 30, + [0][1][2][1][RTW89_UKRAINE][27] = 28, ++ [0][1][2][1][RTW89_MEXICO][27] = 68, ++ [0][1][2][1][RTW89_CN][27] = 127, ++ [0][1][2][1][RTW89_QATAR][27] = 28, + [0][1][2][1][RTW89_FCC][29] = 68, + [0][1][2][1][RTW89_ETSI][29] = 34, + [0][1][2][1][RTW89_MKK][29] = 70, + [0][1][2][1][RTW89_IC][29] = 127, +- [0][1][2][1][RTW89_KCC][29] = 34, ++ [0][1][2][1][RTW89_KCC][29] = 66, + [0][1][2][1][RTW89_ACMA][29] = 127, + [0][1][2][1][RTW89_CHILE][29] = 30, + [0][1][2][1][RTW89_UKRAINE][29] = 28, ++ [0][1][2][1][RTW89_MEXICO][29] = 68, ++ [0][1][2][1][RTW89_CN][29] = 127, ++ [0][1][2][1][RTW89_QATAR][29] = 28, + [0][1][2][1][RTW89_FCC][31] = 68, + [0][1][2][1][RTW89_ETSI][31] = 34, + [0][1][2][1][RTW89_MKK][31] = 70, + [0][1][2][1][RTW89_IC][31] = 62, +- [0][1][2][1][RTW89_KCC][31] = 34, ++ [0][1][2][1][RTW89_KCC][31] = 66, + [0][1][2][1][RTW89_ACMA][31] = 34, + [0][1][2][1][RTW89_CHILE][31] = 30, + [0][1][2][1][RTW89_UKRAINE][31] = 28, ++ [0][1][2][1][RTW89_MEXICO][31] = 68, ++ [0][1][2][1][RTW89_CN][31] = 127, ++ [0][1][2][1][RTW89_QATAR][31] = 28, + [0][1][2][1][RTW89_FCC][33] = 68, + [0][1][2][1][RTW89_ETSI][33] = 34, + [0][1][2][1][RTW89_MKK][33] = 70, + [0][1][2][1][RTW89_IC][33] = 62, +- [0][1][2][1][RTW89_KCC][33] = 34, ++ [0][1][2][1][RTW89_KCC][33] = 66, + [0][1][2][1][RTW89_ACMA][33] = 34, + [0][1][2][1][RTW89_CHILE][33] = 30, + [0][1][2][1][RTW89_UKRAINE][33] = 28, ++ [0][1][2][1][RTW89_MEXICO][33] = 68, ++ [0][1][2][1][RTW89_CN][33] = 127, ++ [0][1][2][1][RTW89_QATAR][33] = 28, + [0][1][2][1][RTW89_FCC][35] = 64, + [0][1][2][1][RTW89_ETSI][35] = 34, + [0][1][2][1][RTW89_MKK][35] = 70, + [0][1][2][1][RTW89_IC][35] = 62, +- [0][1][2][1][RTW89_KCC][35] = 34, ++ [0][1][2][1][RTW89_KCC][35] = 66, + [0][1][2][1][RTW89_ACMA][35] = 34, + [0][1][2][1][RTW89_CHILE][35] = 30, + [0][1][2][1][RTW89_UKRAINE][35] = 28, ++ [0][1][2][1][RTW89_MEXICO][35] = 64, ++ [0][1][2][1][RTW89_CN][35] = 127, ++ [0][1][2][1][RTW89_QATAR][35] = 28, + [0][1][2][1][RTW89_FCC][37] = 68, + [0][1][2][1][RTW89_ETSI][37] = 127, + [0][1][2][1][RTW89_MKK][37] = 70, + [0][1][2][1][RTW89_IC][37] = 62, +- [0][1][2][1][RTW89_KCC][37] = 34, ++ [0][1][2][1][RTW89_KCC][37] = 66, + [0][1][2][1][RTW89_ACMA][37] = 68, + [0][1][2][1][RTW89_CHILE][37] = 30, + [0][1][2][1][RTW89_UKRAINE][37] = 127, ++ [0][1][2][1][RTW89_MEXICO][37] = 68, ++ [0][1][2][1][RTW89_CN][37] = 127, ++ [0][1][2][1][RTW89_QATAR][37] = 127, + [0][1][2][1][RTW89_FCC][38] = 76, + [0][1][2][1][RTW89_ETSI][38] = 4, + [0][1][2][1][RTW89_MKK][38] = 127, + [0][1][2][1][RTW89_IC][38] = 76, +- [0][1][2][1][RTW89_KCC][38] = 4, ++ [0][1][2][1][RTW89_KCC][38] = 66, + [0][1][2][1][RTW89_ACMA][38] = 76, + [0][1][2][1][RTW89_CHILE][38] = 30, +- [0][1][2][1][RTW89_UKRAINE][38] = 28, ++ [0][1][2][1][RTW89_UKRAINE][38] = 4, ++ [0][1][2][1][RTW89_MEXICO][38] = 76, ++ [0][1][2][1][RTW89_CN][38] = 68, ++ [0][1][2][1][RTW89_QATAR][38] = 4, + [0][1][2][1][RTW89_FCC][40] = 76, + [0][1][2][1][RTW89_ETSI][40] = 4, + [0][1][2][1][RTW89_MKK][40] = 127, + [0][1][2][1][RTW89_IC][40] = 76, +- [0][1][2][1][RTW89_KCC][40] = 4, ++ [0][1][2][1][RTW89_KCC][40] = 66, + [0][1][2][1][RTW89_ACMA][40] = 76, + [0][1][2][1][RTW89_CHILE][40] = 30, +- [0][1][2][1][RTW89_UKRAINE][40] = 28, ++ [0][1][2][1][RTW89_UKRAINE][40] = 4, ++ [0][1][2][1][RTW89_MEXICO][40] = 76, ++ [0][1][2][1][RTW89_CN][40] = 70, ++ [0][1][2][1][RTW89_QATAR][40] = 4, + [0][1][2][1][RTW89_FCC][42] = 76, + [0][1][2][1][RTW89_ETSI][42] = 4, + [0][1][2][1][RTW89_MKK][42] = 127, + [0][1][2][1][RTW89_IC][42] = 76, +- [0][1][2][1][RTW89_KCC][42] = 4, ++ [0][1][2][1][RTW89_KCC][42] = 66, + [0][1][2][1][RTW89_ACMA][42] = 76, + [0][1][2][1][RTW89_CHILE][42] = 30, +- [0][1][2][1][RTW89_UKRAINE][42] = 28, ++ [0][1][2][1][RTW89_UKRAINE][42] = 4, ++ [0][1][2][1][RTW89_MEXICO][42] = 76, ++ [0][1][2][1][RTW89_CN][42] = 70, ++ [0][1][2][1][RTW89_QATAR][42] = 4, + [0][1][2][1][RTW89_FCC][44] = 76, + [0][1][2][1][RTW89_ETSI][44] = 4, + [0][1][2][1][RTW89_MKK][44] = 127, + [0][1][2][1][RTW89_IC][44] = 76, +- [0][1][2][1][RTW89_KCC][44] = 4, ++ [0][1][2][1][RTW89_KCC][44] = 66, + [0][1][2][1][RTW89_ACMA][44] = 76, + [0][1][2][1][RTW89_CHILE][44] = 30, +- [0][1][2][1][RTW89_UKRAINE][44] = 28, ++ [0][1][2][1][RTW89_UKRAINE][44] = 4, ++ [0][1][2][1][RTW89_MEXICO][44] = 76, ++ [0][1][2][1][RTW89_CN][44] = 70, ++ [0][1][2][1][RTW89_QATAR][44] = 4, + [0][1][2][1][RTW89_FCC][46] = 76, + [0][1][2][1][RTW89_ETSI][46] = 4, + [0][1][2][1][RTW89_MKK][46] = 127, + [0][1][2][1][RTW89_IC][46] = 76, +- [0][1][2][1][RTW89_KCC][46] = 4, ++ [0][1][2][1][RTW89_KCC][46] = 66, + [0][1][2][1][RTW89_ACMA][46] = 76, + [0][1][2][1][RTW89_CHILE][46] = 30, +- [0][1][2][1][RTW89_UKRAINE][46] = 28, ++ [0][1][2][1][RTW89_UKRAINE][46] = 4, ++ [0][1][2][1][RTW89_MEXICO][46] = 76, ++ [0][1][2][1][RTW89_CN][46] = 70, ++ [0][1][2][1][RTW89_QATAR][46] = 4, + [1][0][2][0][RTW89_FCC][1] = 68, + [1][0][2][0][RTW89_ETSI][1] = 64, + [1][0][2][0][RTW89_MKK][1] = 62, + [1][0][2][0][RTW89_IC][1] = 64, +- [1][0][2][0][RTW89_KCC][1] = 64, ++ [1][0][2][0][RTW89_KCC][1] = 72, + [1][0][2][0][RTW89_ACMA][1] = 64, + [1][0][2][0][RTW89_CHILE][1] = 30, + [1][0][2][0][RTW89_UKRAINE][1] = 52, ++ [1][0][2][0][RTW89_MEXICO][1] = 62, ++ [1][0][2][0][RTW89_CN][1] = 64, ++ [1][0][2][0][RTW89_QATAR][1] = 64, + [1][0][2][0][RTW89_FCC][5] = 72, + [1][0][2][0][RTW89_ETSI][5] = 64, + [1][0][2][0][RTW89_MKK][5] = 62, + [1][0][2][0][RTW89_IC][5] = 64, +- [1][0][2][0][RTW89_KCC][5] = 60, ++ [1][0][2][0][RTW89_KCC][5] = 72, + [1][0][2][0][RTW89_ACMA][5] = 64, + [1][0][2][0][RTW89_CHILE][5] = 30, + [1][0][2][0][RTW89_UKRAINE][5] = 52, ++ [1][0][2][0][RTW89_MEXICO][5] = 62, ++ [1][0][2][0][RTW89_CN][5] = 64, ++ [1][0][2][0][RTW89_QATAR][5] = 64, + [1][0][2][0][RTW89_FCC][9] = 72, + [1][0][2][0][RTW89_ETSI][9] = 64, + [1][0][2][0][RTW89_MKK][9] = 62, + [1][0][2][0][RTW89_IC][9] = 64, +- [1][0][2][0][RTW89_KCC][9] = 64, ++ [1][0][2][0][RTW89_KCC][9] = 72, + [1][0][2][0][RTW89_ACMA][9] = 64, + [1][0][2][0][RTW89_CHILE][9] = 54, + [1][0][2][0][RTW89_UKRAINE][9] = 52, ++ [1][0][2][0][RTW89_MEXICO][9] = 72, ++ [1][0][2][0][RTW89_CN][9] = 64, ++ [1][0][2][0][RTW89_QATAR][9] = 64, + [1][0][2][0][RTW89_FCC][13] = 66, + [1][0][2][0][RTW89_ETSI][13] = 64, + [1][0][2][0][RTW89_MKK][13] = 62, + [1][0][2][0][RTW89_IC][13] = 64, +- [1][0][2][0][RTW89_KCC][13] = 64, ++ [1][0][2][0][RTW89_KCC][13] = 68, + [1][0][2][0][RTW89_ACMA][13] = 64, + [1][0][2][0][RTW89_CHILE][13] = 54, + [1][0][2][0][RTW89_UKRAINE][13] = 52, ++ [1][0][2][0][RTW89_MEXICO][13] = 66, ++ [1][0][2][0][RTW89_CN][13] = 64, ++ [1][0][2][0][RTW89_QATAR][13] = 64, + [1][0][2][0][RTW89_FCC][16] = 62, + [1][0][2][0][RTW89_ETSI][16] = 64, + [1][0][2][0][RTW89_MKK][16] = 72, + [1][0][2][0][RTW89_IC][16] = 62, +- [1][0][2][0][RTW89_KCC][16] = 64, ++ [1][0][2][0][RTW89_KCC][16] = 72, + [1][0][2][0][RTW89_ACMA][16] = 64, + [1][0][2][0][RTW89_CHILE][16] = 54, + [1][0][2][0][RTW89_UKRAINE][16] = 52, ++ [1][0][2][0][RTW89_MEXICO][16] = 62, ++ [1][0][2][0][RTW89_CN][16] = 127, ++ [1][0][2][0][RTW89_QATAR][16] = 52, + [1][0][2][0][RTW89_FCC][20] = 72, + [1][0][2][0][RTW89_ETSI][20] = 64, + [1][0][2][0][RTW89_MKK][20] = 72, + [1][0][2][0][RTW89_IC][20] = 72, +- [1][0][2][0][RTW89_KCC][20] = 64, ++ [1][0][2][0][RTW89_KCC][20] = 72, + [1][0][2][0][RTW89_ACMA][20] = 64, + [1][0][2][0][RTW89_CHILE][20] = 54, + [1][0][2][0][RTW89_UKRAINE][20] = 52, ++ [1][0][2][0][RTW89_MEXICO][20] = 72, ++ [1][0][2][0][RTW89_CN][20] = 127, ++ [1][0][2][0][RTW89_QATAR][20] = 52, + [1][0][2][0][RTW89_FCC][24] = 72, + [1][0][2][0][RTW89_ETSI][24] = 64, + [1][0][2][0][RTW89_MKK][24] = 72, + [1][0][2][0][RTW89_IC][24] = 127, +- [1][0][2][0][RTW89_KCC][24] = 64, ++ [1][0][2][0][RTW89_KCC][24] = 72, + [1][0][2][0][RTW89_ACMA][24] = 127, + [1][0][2][0][RTW89_CHILE][24] = 54, + [1][0][2][0][RTW89_UKRAINE][24] = 52, ++ [1][0][2][0][RTW89_MEXICO][24] = 72, ++ [1][0][2][0][RTW89_CN][24] = 127, ++ [1][0][2][0][RTW89_QATAR][24] = 52, + [1][0][2][0][RTW89_FCC][28] = 72, + [1][0][2][0][RTW89_ETSI][28] = 64, + [1][0][2][0][RTW89_MKK][28] = 72, + [1][0][2][0][RTW89_IC][28] = 127, +- [1][0][2][0][RTW89_KCC][28] = 64, ++ [1][0][2][0][RTW89_KCC][28] = 72, + [1][0][2][0][RTW89_ACMA][28] = 127, + [1][0][2][0][RTW89_CHILE][28] = 54, + [1][0][2][0][RTW89_UKRAINE][28] = 52, ++ [1][0][2][0][RTW89_MEXICO][28] = 72, ++ [1][0][2][0][RTW89_CN][28] = 127, ++ [1][0][2][0][RTW89_QATAR][28] = 52, + [1][0][2][0][RTW89_FCC][32] = 72, + [1][0][2][0][RTW89_ETSI][32] = 64, + [1][0][2][0][RTW89_MKK][32] = 72, + [1][0][2][0][RTW89_IC][32] = 72, +- [1][0][2][0][RTW89_KCC][32] = 64, ++ [1][0][2][0][RTW89_KCC][32] = 72, + [1][0][2][0][RTW89_ACMA][32] = 64, + [1][0][2][0][RTW89_CHILE][32] = 54, + [1][0][2][0][RTW89_UKRAINE][32] = 52, ++ [1][0][2][0][RTW89_MEXICO][32] = 72, ++ [1][0][2][0][RTW89_CN][32] = 127, ++ [1][0][2][0][RTW89_QATAR][32] = 52, + [1][0][2][0][RTW89_FCC][36] = 72, + [1][0][2][0][RTW89_ETSI][36] = 127, + [1][0][2][0][RTW89_MKK][36] = 72, + [1][0][2][0][RTW89_IC][36] = 72, +- [1][0][2][0][RTW89_KCC][36] = 64, ++ [1][0][2][0][RTW89_KCC][36] = 72, + [1][0][2][0][RTW89_ACMA][36] = 72, + [1][0][2][0][RTW89_CHILE][36] = 54, + [1][0][2][0][RTW89_UKRAINE][36] = 127, ++ [1][0][2][0][RTW89_MEXICO][36] = 72, ++ [1][0][2][0][RTW89_CN][36] = 127, ++ [1][0][2][0][RTW89_QATAR][36] = 127, + [1][0][2][0][RTW89_FCC][39] = 72, + [1][0][2][0][RTW89_ETSI][39] = 28, + [1][0][2][0][RTW89_MKK][39] = 127, + [1][0][2][0][RTW89_IC][39] = 72, +- [1][0][2][0][RTW89_KCC][39] = 28, ++ [1][0][2][0][RTW89_KCC][39] = 72, + [1][0][2][0][RTW89_ACMA][39] = 72, + [1][0][2][0][RTW89_CHILE][39] = 54, +- [1][0][2][0][RTW89_UKRAINE][39] = 52, ++ [1][0][2][0][RTW89_UKRAINE][39] = 28, ++ [1][0][2][0][RTW89_MEXICO][39] = 72, ++ [1][0][2][0][RTW89_CN][39] = 68, ++ [1][0][2][0][RTW89_QATAR][39] = 28, + [1][0][2][0][RTW89_FCC][43] = 72, + [1][0][2][0][RTW89_ETSI][43] = 28, + [1][0][2][0][RTW89_MKK][43] = 127, + [1][0][2][0][RTW89_IC][43] = 72, +- [1][0][2][0][RTW89_KCC][43] = 28, ++ [1][0][2][0][RTW89_KCC][43] = 72, + [1][0][2][0][RTW89_ACMA][43] = 72, + [1][0][2][0][RTW89_CHILE][43] = 54, +- [1][0][2][0][RTW89_UKRAINE][43] = 52, ++ [1][0][2][0][RTW89_UKRAINE][43] = 28, ++ [1][0][2][0][RTW89_MEXICO][43] = 72, ++ [1][0][2][0][RTW89_CN][43] = 72, ++ [1][0][2][0][RTW89_QATAR][43] = 28, + [1][1][2][0][RTW89_FCC][1] = 58, + [1][1][2][0][RTW89_ETSI][1] = 52, + [1][1][2][0][RTW89_MKK][1] = 50, + [1][1][2][0][RTW89_IC][1] = 52, +- [1][1][2][0][RTW89_KCC][1] = 52, ++ [1][1][2][0][RTW89_KCC][1] = 66, + [1][1][2][0][RTW89_ACMA][1] = 52, + [1][1][2][0][RTW89_CHILE][1] = 18, + [1][1][2][0][RTW89_UKRAINE][1] = 40, ++ [1][1][2][0][RTW89_MEXICO][1] = 50, ++ [1][1][2][0][RTW89_CN][1] = 52, ++ [1][1][2][0][RTW89_QATAR][1] = 52, + [1][1][2][0][RTW89_FCC][5] = 72, + [1][1][2][0][RTW89_ETSI][5] = 52, + [1][1][2][0][RTW89_MKK][5] = 50, + [1][1][2][0][RTW89_IC][5] = 52, +- [1][1][2][0][RTW89_KCC][5] = 46, ++ [1][1][2][0][RTW89_KCC][5] = 50, + [1][1][2][0][RTW89_ACMA][5] = 52, + [1][1][2][0][RTW89_CHILE][5] = 18, + [1][1][2][0][RTW89_UKRAINE][5] = 40, ++ [1][1][2][0][RTW89_MEXICO][5] = 50, ++ [1][1][2][0][RTW89_CN][5] = 52, ++ [1][1][2][0][RTW89_QATAR][5] = 52, + [1][1][2][0][RTW89_FCC][9] = 72, + [1][1][2][0][RTW89_ETSI][9] = 52, + [1][1][2][0][RTW89_MKK][9] = 50, + [1][1][2][0][RTW89_IC][9] = 52, +- [1][1][2][0][RTW89_KCC][9] = 52, ++ [1][1][2][0][RTW89_KCC][9] = 66, + [1][1][2][0][RTW89_ACMA][9] = 52, + [1][1][2][0][RTW89_CHILE][9] = 42, + [1][1][2][0][RTW89_UKRAINE][9] = 40, ++ [1][1][2][0][RTW89_MEXICO][9] = 72, ++ [1][1][2][0][RTW89_CN][9] = 52, ++ [1][1][2][0][RTW89_QATAR][9] = 52, + [1][1][2][0][RTW89_FCC][13] = 58, + [1][1][2][0][RTW89_ETSI][13] = 52, + [1][1][2][0][RTW89_MKK][13] = 50, + [1][1][2][0][RTW89_IC][13] = 52, +- [1][1][2][0][RTW89_KCC][13] = 52, ++ [1][1][2][0][RTW89_KCC][13] = 66, + [1][1][2][0][RTW89_ACMA][13] = 52, + [1][1][2][0][RTW89_CHILE][13] = 42, + [1][1][2][0][RTW89_UKRAINE][13] = 40, ++ [1][1][2][0][RTW89_MEXICO][13] = 58, ++ [1][1][2][0][RTW89_CN][13] = 52, ++ [1][1][2][0][RTW89_QATAR][13] = 52, + [1][1][2][0][RTW89_FCC][16] = 56, + [1][1][2][0][RTW89_ETSI][16] = 52, + [1][1][2][0][RTW89_MKK][16] = 72, + [1][1][2][0][RTW89_IC][16] = 56, +- [1][1][2][0][RTW89_KCC][16] = 52, ++ [1][1][2][0][RTW89_KCC][16] = 64, + [1][1][2][0][RTW89_ACMA][16] = 52, + [1][1][2][0][RTW89_CHILE][16] = 42, + [1][1][2][0][RTW89_UKRAINE][16] = 40, ++ [1][1][2][0][RTW89_MEXICO][16] = 56, ++ [1][1][2][0][RTW89_CN][16] = 127, ++ [1][1][2][0][RTW89_QATAR][16] = 40, + [1][1][2][0][RTW89_FCC][20] = 72, + [1][1][2][0][RTW89_ETSI][20] = 52, + [1][1][2][0][RTW89_MKK][20] = 72, + [1][1][2][0][RTW89_IC][20] = 72, +- [1][1][2][0][RTW89_KCC][20] = 52, ++ [1][1][2][0][RTW89_KCC][20] = 66, + [1][1][2][0][RTW89_ACMA][20] = 52, + [1][1][2][0][RTW89_CHILE][20] = 42, + [1][1][2][0][RTW89_UKRAINE][20] = 40, ++ [1][1][2][0][RTW89_MEXICO][20] = 72, ++ [1][1][2][0][RTW89_CN][20] = 127, ++ [1][1][2][0][RTW89_QATAR][20] = 40, + [1][1][2][0][RTW89_FCC][24] = 72, + [1][1][2][0][RTW89_ETSI][24] = 52, + [1][1][2][0][RTW89_MKK][24] = 72, + [1][1][2][0][RTW89_IC][24] = 127, +- [1][1][2][0][RTW89_KCC][24] = 52, ++ [1][1][2][0][RTW89_KCC][24] = 66, + [1][1][2][0][RTW89_ACMA][24] = 127, + [1][1][2][0][RTW89_CHILE][24] = 42, + [1][1][2][0][RTW89_UKRAINE][24] = 40, ++ [1][1][2][0][RTW89_MEXICO][24] = 72, ++ [1][1][2][0][RTW89_CN][24] = 127, ++ [1][1][2][0][RTW89_QATAR][24] = 40, + [1][1][2][0][RTW89_FCC][28] = 72, + [1][1][2][0][RTW89_ETSI][28] = 52, + [1][1][2][0][RTW89_MKK][28] = 72, + [1][1][2][0][RTW89_IC][28] = 127, +- [1][1][2][0][RTW89_KCC][28] = 52, ++ [1][1][2][0][RTW89_KCC][28] = 66, + [1][1][2][0][RTW89_ACMA][28] = 127, + [1][1][2][0][RTW89_CHILE][28] = 42, + [1][1][2][0][RTW89_UKRAINE][28] = 40, ++ [1][1][2][0][RTW89_MEXICO][28] = 72, ++ [1][1][2][0][RTW89_CN][28] = 127, ++ [1][1][2][0][RTW89_QATAR][28] = 40, + [1][1][2][0][RTW89_FCC][32] = 68, + [1][1][2][0][RTW89_ETSI][32] = 52, + [1][1][2][0][RTW89_MKK][32] = 72, + [1][1][2][0][RTW89_IC][32] = 68, +- [1][1][2][0][RTW89_KCC][32] = 52, ++ [1][1][2][0][RTW89_KCC][32] = 66, + [1][1][2][0][RTW89_ACMA][32] = 52, + [1][1][2][0][RTW89_CHILE][32] = 42, + [1][1][2][0][RTW89_UKRAINE][32] = 40, ++ [1][1][2][0][RTW89_MEXICO][32] = 68, ++ [1][1][2][0][RTW89_CN][32] = 127, ++ [1][1][2][0][RTW89_QATAR][32] = 40, + [1][1][2][0][RTW89_FCC][36] = 72, + [1][1][2][0][RTW89_ETSI][36] = 127, + [1][1][2][0][RTW89_MKK][36] = 72, + [1][1][2][0][RTW89_IC][36] = 72, +- [1][1][2][0][RTW89_KCC][36] = 52, ++ [1][1][2][0][RTW89_KCC][36] = 66, + [1][1][2][0][RTW89_ACMA][36] = 72, + [1][1][2][0][RTW89_CHILE][36] = 42, + [1][1][2][0][RTW89_UKRAINE][36] = 127, ++ [1][1][2][0][RTW89_MEXICO][36] = 72, ++ [1][1][2][0][RTW89_CN][36] = 127, ++ [1][1][2][0][RTW89_QATAR][36] = 127, + [1][1][2][0][RTW89_FCC][39] = 72, + [1][1][2][0][RTW89_ETSI][39] = 16, + [1][1][2][0][RTW89_MKK][39] = 127, + [1][1][2][0][RTW89_IC][39] = 72, +- [1][1][2][0][RTW89_KCC][39] = 16, ++ [1][1][2][0][RTW89_KCC][39] = 66, + [1][1][2][0][RTW89_ACMA][39] = 72, + [1][1][2][0][RTW89_CHILE][39] = 42, +- [1][1][2][0][RTW89_UKRAINE][39] = 40, ++ [1][1][2][0][RTW89_UKRAINE][39] = 16, ++ [1][1][2][0][RTW89_MEXICO][39] = 72, ++ [1][1][2][0][RTW89_CN][39] = 68, ++ [1][1][2][0][RTW89_QATAR][39] = 16, + [1][1][2][0][RTW89_FCC][43] = 72, + [1][1][2][0][RTW89_ETSI][43] = 16, + [1][1][2][0][RTW89_MKK][43] = 127, + [1][1][2][0][RTW89_IC][43] = 72, +- [1][1][2][0][RTW89_KCC][43] = 16, ++ [1][1][2][0][RTW89_KCC][43] = 66, + [1][1][2][0][RTW89_ACMA][43] = 72, + [1][1][2][0][RTW89_CHILE][43] = 42, +- [1][1][2][0][RTW89_UKRAINE][43] = 40, ++ [1][1][2][0][RTW89_UKRAINE][43] = 16, ++ [1][1][2][0][RTW89_MEXICO][43] = 72, ++ [1][1][2][0][RTW89_CN][43] = 72, ++ [1][1][2][0][RTW89_QATAR][43] = 16, + [1][1][2][1][RTW89_FCC][1] = 58, + [1][1][2][1][RTW89_ETSI][1] = 40, + [1][1][2][1][RTW89_MKK][1] = 50, + [1][1][2][1][RTW89_IC][1] = 40, +- [1][1][2][1][RTW89_KCC][1] = 40, ++ [1][1][2][1][RTW89_KCC][1] = 66, + [1][1][2][1][RTW89_ACMA][1] = 40, + [1][1][2][1][RTW89_CHILE][1] = 6, + [1][1][2][1][RTW89_UKRAINE][1] = 28, ++ [1][1][2][1][RTW89_MEXICO][1] = 50, ++ [1][1][2][1][RTW89_CN][1] = 40, ++ [1][1][2][1][RTW89_QATAR][1] = 40, + [1][1][2][1][RTW89_FCC][5] = 68, + [1][1][2][1][RTW89_ETSI][5] = 40, + [1][1][2][1][RTW89_MKK][5] = 50, + [1][1][2][1][RTW89_IC][5] = 40, +- [1][1][2][1][RTW89_KCC][5] = 40, ++ [1][1][2][1][RTW89_KCC][5] = 50, + [1][1][2][1][RTW89_ACMA][5] = 40, + [1][1][2][1][RTW89_CHILE][5] = 6, + [1][1][2][1][RTW89_UKRAINE][5] = 28, ++ [1][1][2][1][RTW89_MEXICO][5] = 50, ++ [1][1][2][1][RTW89_CN][5] = 40, ++ [1][1][2][1][RTW89_QATAR][5] = 40, + [1][1][2][1][RTW89_FCC][9] = 68, + [1][1][2][1][RTW89_ETSI][9] = 40, + [1][1][2][1][RTW89_MKK][9] = 50, + [1][1][2][1][RTW89_IC][9] = 40, +- [1][1][2][1][RTW89_KCC][9] = 40, ++ [1][1][2][1][RTW89_KCC][9] = 66, + [1][1][2][1][RTW89_ACMA][9] = 40, + [1][1][2][1][RTW89_CHILE][9] = 30, + [1][1][2][1][RTW89_UKRAINE][9] = 28, ++ [1][1][2][1][RTW89_MEXICO][9] = 68, ++ [1][1][2][1][RTW89_CN][9] = 40, ++ [1][1][2][1][RTW89_QATAR][9] = 40, + [1][1][2][1][RTW89_FCC][13] = 58, + [1][1][2][1][RTW89_ETSI][13] = 40, + [1][1][2][1][RTW89_MKK][13] = 50, + [1][1][2][1][RTW89_IC][13] = 40, +- [1][1][2][1][RTW89_KCC][13] = 40, ++ [1][1][2][1][RTW89_KCC][13] = 66, + [1][1][2][1][RTW89_ACMA][13] = 40, + [1][1][2][1][RTW89_CHILE][13] = 30, + [1][1][2][1][RTW89_UKRAINE][13] = 28, ++ [1][1][2][1][RTW89_MEXICO][13] = 58, ++ [1][1][2][1][RTW89_CN][13] = 40, ++ [1][1][2][1][RTW89_QATAR][13] = 40, + [1][1][2][1][RTW89_FCC][16] = 56, + [1][1][2][1][RTW89_ETSI][16] = 40, + [1][1][2][1][RTW89_MKK][16] = 72, + [1][1][2][1][RTW89_IC][16] = 56, +- [1][1][2][1][RTW89_KCC][16] = 40, ++ [1][1][2][1][RTW89_KCC][16] = 64, + [1][1][2][1][RTW89_ACMA][16] = 40, + [1][1][2][1][RTW89_CHILE][16] = 30, + [1][1][2][1][RTW89_UKRAINE][16] = 28, ++ [1][1][2][1][RTW89_MEXICO][16] = 56, ++ [1][1][2][1][RTW89_CN][16] = 127, ++ [1][1][2][1][RTW89_QATAR][16] = 28, + [1][1][2][1][RTW89_FCC][20] = 68, + [1][1][2][1][RTW89_ETSI][20] = 40, + [1][1][2][1][RTW89_MKK][20] = 72, + [1][1][2][1][RTW89_IC][20] = 68, +- [1][1][2][1][RTW89_KCC][20] = 40, ++ [1][1][2][1][RTW89_KCC][20] = 66, + [1][1][2][1][RTW89_ACMA][20] = 40, + [1][1][2][1][RTW89_CHILE][20] = 30, + [1][1][2][1][RTW89_UKRAINE][20] = 28, ++ [1][1][2][1][RTW89_MEXICO][20] = 68, ++ [1][1][2][1][RTW89_CN][20] = 127, ++ [1][1][2][1][RTW89_QATAR][20] = 28, + [1][1][2][1][RTW89_FCC][24] = 68, + [1][1][2][1][RTW89_ETSI][24] = 40, + [1][1][2][1][RTW89_MKK][24] = 72, + [1][1][2][1][RTW89_IC][24] = 127, +- [1][1][2][1][RTW89_KCC][24] = 40, ++ [1][1][2][1][RTW89_KCC][24] = 66, + [1][1][2][1][RTW89_ACMA][24] = 127, + [1][1][2][1][RTW89_CHILE][24] = 30, + [1][1][2][1][RTW89_UKRAINE][24] = 28, ++ [1][1][2][1][RTW89_MEXICO][24] = 68, ++ [1][1][2][1][RTW89_CN][24] = 127, ++ [1][1][2][1][RTW89_QATAR][24] = 28, + [1][1][2][1][RTW89_FCC][28] = 68, + [1][1][2][1][RTW89_ETSI][28] = 40, + [1][1][2][1][RTW89_MKK][28] = 72, + [1][1][2][1][RTW89_IC][28] = 127, +- [1][1][2][1][RTW89_KCC][28] = 40, ++ [1][1][2][1][RTW89_KCC][28] = 66, + [1][1][2][1][RTW89_ACMA][28] = 127, + [1][1][2][1][RTW89_CHILE][28] = 30, + [1][1][2][1][RTW89_UKRAINE][28] = 28, ++ [1][1][2][1][RTW89_MEXICO][28] = 68, ++ [1][1][2][1][RTW89_CN][28] = 127, ++ [1][1][2][1][RTW89_QATAR][28] = 28, + [1][1][2][1][RTW89_FCC][32] = 68, + [1][1][2][1][RTW89_ETSI][32] = 40, + [1][1][2][1][RTW89_MKK][32] = 72, + [1][1][2][1][RTW89_IC][32] = 68, +- [1][1][2][1][RTW89_KCC][32] = 40, ++ [1][1][2][1][RTW89_KCC][32] = 66, + [1][1][2][1][RTW89_ACMA][32] = 40, + [1][1][2][1][RTW89_CHILE][32] = 30, + [1][1][2][1][RTW89_UKRAINE][32] = 28, ++ [1][1][2][1][RTW89_MEXICO][32] = 68, ++ [1][1][2][1][RTW89_CN][32] = 127, ++ [1][1][2][1][RTW89_QATAR][32] = 28, + [1][1][2][1][RTW89_FCC][36] = 68, + [1][1][2][1][RTW89_ETSI][36] = 127, + [1][1][2][1][RTW89_MKK][36] = 72, + [1][1][2][1][RTW89_IC][36] = 68, +- [1][1][2][1][RTW89_KCC][36] = 40, ++ [1][1][2][1][RTW89_KCC][36] = 66, + [1][1][2][1][RTW89_ACMA][36] = 68, + [1][1][2][1][RTW89_CHILE][36] = 30, + [1][1][2][1][RTW89_UKRAINE][36] = 127, ++ [1][1][2][1][RTW89_MEXICO][36] = 68, ++ [1][1][2][1][RTW89_CN][36] = 127, ++ [1][1][2][1][RTW89_QATAR][36] = 127, + [1][1][2][1][RTW89_FCC][39] = 72, + [1][1][2][1][RTW89_ETSI][39] = 4, + [1][1][2][1][RTW89_MKK][39] = 127, + [1][1][2][1][RTW89_IC][39] = 72, +- [1][1][2][1][RTW89_KCC][39] = 4, ++ [1][1][2][1][RTW89_KCC][39] = 66, + [1][1][2][1][RTW89_ACMA][39] = 72, + [1][1][2][1][RTW89_CHILE][39] = 30, +- [1][1][2][1][RTW89_UKRAINE][39] = 28, ++ [1][1][2][1][RTW89_UKRAINE][39] = 4, ++ [1][1][2][1][RTW89_MEXICO][39] = 72, ++ [1][1][2][1][RTW89_CN][39] = 62, ++ [1][1][2][1][RTW89_QATAR][39] = 4, + [1][1][2][1][RTW89_FCC][43] = 72, + [1][1][2][1][RTW89_ETSI][43] = 4, + [1][1][2][1][RTW89_MKK][43] = 127, + [1][1][2][1][RTW89_IC][43] = 72, +- [1][1][2][1][RTW89_KCC][43] = 4, ++ [1][1][2][1][RTW89_KCC][43] = 66, + [1][1][2][1][RTW89_ACMA][43] = 72, + [1][1][2][1][RTW89_CHILE][43] = 30, +- [1][1][2][1][RTW89_UKRAINE][43] = 28, ++ [1][1][2][1][RTW89_UKRAINE][43] = 4, ++ [1][1][2][1][RTW89_MEXICO][43] = 72, ++ [1][1][2][1][RTW89_CN][43] = 72, ++ [1][1][2][1][RTW89_QATAR][43] = 4, + [2][0][2][0][RTW89_FCC][3] = 64, + [2][0][2][0][RTW89_ETSI][3] = 64, + [2][0][2][0][RTW89_MKK][3] = 64, + [2][0][2][0][RTW89_IC][3] = 62, +- [2][0][2][0][RTW89_KCC][3] = 64, ++ [2][0][2][0][RTW89_KCC][3] = 72, + [2][0][2][0][RTW89_ACMA][3] = 64, + [2][0][2][0][RTW89_CHILE][3] = 30, + [2][0][2][0][RTW89_UKRAINE][3] = 52, ++ [2][0][2][0][RTW89_MEXICO][3] = 62, ++ [2][0][2][0][RTW89_CN][3] = 64, ++ [2][0][2][0][RTW89_QATAR][3] = 64, + [2][0][2][0][RTW89_FCC][11] = 64, + [2][0][2][0][RTW89_ETSI][11] = 64, + [2][0][2][0][RTW89_MKK][11] = 64, + [2][0][2][0][RTW89_IC][11] = 62, +- [2][0][2][0][RTW89_KCC][11] = 64, ++ [2][0][2][0][RTW89_KCC][11] = 72, + [2][0][2][0][RTW89_ACMA][11] = 64, + [2][0][2][0][RTW89_CHILE][11] = 54, + [2][0][2][0][RTW89_UKRAINE][11] = 52, ++ [2][0][2][0][RTW89_MEXICO][11] = 64, ++ [2][0][2][0][RTW89_CN][11] = 64, ++ [2][0][2][0][RTW89_QATAR][11] = 64, + [2][0][2][0][RTW89_FCC][18] = 62, + [2][0][2][0][RTW89_ETSI][18] = 64, + [2][0][2][0][RTW89_MKK][18] = 72, + [2][0][2][0][RTW89_IC][18] = 66, +- [2][0][2][0][RTW89_KCC][18] = 64, ++ [2][0][2][0][RTW89_KCC][18] = 70, + [2][0][2][0][RTW89_ACMA][18] = 64, + [2][0][2][0][RTW89_CHILE][18] = 54, + [2][0][2][0][RTW89_UKRAINE][18] = 52, ++ [2][0][2][0][RTW89_MEXICO][18] = 62, ++ [2][0][2][0][RTW89_CN][18] = 127, ++ [2][0][2][0][RTW89_QATAR][18] = 52, + [2][0][2][0][RTW89_FCC][26] = 72, + [2][0][2][0][RTW89_ETSI][26] = 64, + [2][0][2][0][RTW89_MKK][26] = 72, + [2][0][2][0][RTW89_IC][26] = 127, +- [2][0][2][0][RTW89_KCC][26] = 64, ++ [2][0][2][0][RTW89_KCC][26] = 72, + [2][0][2][0][RTW89_ACMA][26] = 127, + [2][0][2][0][RTW89_CHILE][26] = 54, + [2][0][2][0][RTW89_UKRAINE][26] = 52, ++ [2][0][2][0][RTW89_MEXICO][26] = 72, ++ [2][0][2][0][RTW89_CN][26] = 127, ++ [2][0][2][0][RTW89_QATAR][26] = 52, + [2][0][2][0][RTW89_FCC][34] = 72, + [2][0][2][0][RTW89_ETSI][34] = 127, + [2][0][2][0][RTW89_MKK][34] = 72, + [2][0][2][0][RTW89_IC][34] = 72, +- [2][0][2][0][RTW89_KCC][34] = 64, ++ [2][0][2][0][RTW89_KCC][34] = 72, + [2][0][2][0][RTW89_ACMA][34] = 72, + [2][0][2][0][RTW89_CHILE][34] = 54, + [2][0][2][0][RTW89_UKRAINE][34] = 127, ++ [2][0][2][0][RTW89_MEXICO][34] = 72, ++ [2][0][2][0][RTW89_CN][34] = 127, ++ [2][0][2][0][RTW89_QATAR][34] = 127, + [2][0][2][0][RTW89_FCC][41] = 72, + [2][0][2][0][RTW89_ETSI][41] = 28, + [2][0][2][0][RTW89_MKK][41] = 127, + [2][0][2][0][RTW89_IC][41] = 72, +- [2][0][2][0][RTW89_KCC][41] = 28, ++ [2][0][2][0][RTW89_KCC][41] = 68, + [2][0][2][0][RTW89_ACMA][41] = 72, + [2][0][2][0][RTW89_CHILE][41] = 54, +- [2][0][2][0][RTW89_UKRAINE][41] = 52, ++ [2][0][2][0][RTW89_UKRAINE][41] = 28, ++ [2][0][2][0][RTW89_MEXICO][41] = 72, ++ [2][0][2][0][RTW89_CN][41] = 68, ++ [2][0][2][0][RTW89_QATAR][41] = 28, + [2][1][2][0][RTW89_FCC][3] = 56, + [2][1][2][0][RTW89_ETSI][3] = 52, + [2][1][2][0][RTW89_MKK][3] = 52, + [2][1][2][0][RTW89_IC][3] = 52, +- [2][1][2][0][RTW89_KCC][3] = 52, ++ [2][1][2][0][RTW89_KCC][3] = 66, + [2][1][2][0][RTW89_ACMA][3] = 52, + [2][1][2][0][RTW89_CHILE][3] = 18, + [2][1][2][0][RTW89_UKRAINE][3] = 40, ++ [2][1][2][0][RTW89_MEXICO][3] = 50, ++ [2][1][2][0][RTW89_CN][3] = 52, ++ [2][1][2][0][RTW89_QATAR][3] = 52, + [2][1][2][0][RTW89_FCC][11] = 56, + [2][1][2][0][RTW89_ETSI][11] = 52, + [2][1][2][0][RTW89_MKK][11] = 52, + [2][1][2][0][RTW89_IC][11] = 52, +- [2][1][2][0][RTW89_KCC][11] = 52, ++ [2][1][2][0][RTW89_KCC][11] = 64, + [2][1][2][0][RTW89_ACMA][11] = 52, + [2][1][2][0][RTW89_CHILE][11] = 42, + [2][1][2][0][RTW89_UKRAINE][11] = 40, ++ [2][1][2][0][RTW89_MEXICO][11] = 56, ++ [2][1][2][0][RTW89_CN][11] = 52, ++ [2][1][2][0][RTW89_QATAR][11] = 52, + [2][1][2][0][RTW89_FCC][18] = 56, + [2][1][2][0][RTW89_ETSI][18] = 52, + [2][1][2][0][RTW89_MKK][18] = 72, + [2][1][2][0][RTW89_IC][18] = 56, +- [2][1][2][0][RTW89_KCC][18] = 52, ++ [2][1][2][0][RTW89_KCC][18] = 58, + [2][1][2][0][RTW89_ACMA][18] = 52, + [2][1][2][0][RTW89_CHILE][18] = 42, + [2][1][2][0][RTW89_UKRAINE][18] = 40, ++ [2][1][2][0][RTW89_MEXICO][18] = 56, ++ [2][1][2][0][RTW89_CN][18] = 127, ++ [2][1][2][0][RTW89_QATAR][18] = 40, + [2][1][2][0][RTW89_FCC][26] = 72, + [2][1][2][0][RTW89_ETSI][26] = 52, + [2][1][2][0][RTW89_MKK][26] = 72, + [2][1][2][0][RTW89_IC][26] = 127, +- [2][1][2][0][RTW89_KCC][26] = 52, ++ [2][1][2][0][RTW89_KCC][26] = 64, + [2][1][2][0][RTW89_ACMA][26] = 127, + [2][1][2][0][RTW89_CHILE][26] = 42, + [2][1][2][0][RTW89_UKRAINE][26] = 40, ++ [2][1][2][0][RTW89_MEXICO][26] = 72, ++ [2][1][2][0][RTW89_CN][26] = 127, ++ [2][1][2][0][RTW89_QATAR][26] = 40, + [2][1][2][0][RTW89_FCC][34] = 72, + [2][1][2][0][RTW89_ETSI][34] = 127, + [2][1][2][0][RTW89_MKK][34] = 72, + [2][1][2][0][RTW89_IC][34] = 72, +- [2][1][2][0][RTW89_KCC][34] = 52, ++ [2][1][2][0][RTW89_KCC][34] = 64, + [2][1][2][0][RTW89_ACMA][34] = 72, + [2][1][2][0][RTW89_CHILE][34] = 42, + [2][1][2][0][RTW89_UKRAINE][34] = 127, ++ [2][1][2][0][RTW89_MEXICO][34] = 72, ++ [2][1][2][0][RTW89_CN][34] = 127, ++ [2][1][2][0][RTW89_QATAR][34] = 127, + [2][1][2][0][RTW89_FCC][41] = 72, + [2][1][2][0][RTW89_ETSI][41] = 16, + [2][1][2][0][RTW89_MKK][41] = 127, + [2][1][2][0][RTW89_IC][41] = 72, +- [2][1][2][0][RTW89_KCC][41] = 16, ++ [2][1][2][0][RTW89_KCC][41] = 58, + [2][1][2][0][RTW89_ACMA][41] = 72, + [2][1][2][0][RTW89_CHILE][41] = 42, +- [2][1][2][0][RTW89_UKRAINE][41] = 40, ++ [2][1][2][0][RTW89_UKRAINE][41] = 16, ++ [2][1][2][0][RTW89_MEXICO][41] = 72, ++ [2][1][2][0][RTW89_CN][41] = 68, ++ [2][1][2][0][RTW89_QATAR][41] = 16, + [2][1][2][1][RTW89_FCC][3] = 56, + [2][1][2][1][RTW89_ETSI][3] = 40, + [2][1][2][1][RTW89_MKK][3] = 52, + [2][1][2][1][RTW89_IC][3] = 40, +- [2][1][2][1][RTW89_KCC][3] = 40, ++ [2][1][2][1][RTW89_KCC][3] = 66, + [2][1][2][1][RTW89_ACMA][3] = 40, + [2][1][2][1][RTW89_CHILE][3] = 6, + [2][1][2][1][RTW89_UKRAINE][3] = 28, ++ [2][1][2][1][RTW89_MEXICO][3] = 50, ++ [2][1][2][1][RTW89_CN][3] = 40, ++ [2][1][2][1][RTW89_QATAR][3] = 40, + [2][1][2][1][RTW89_FCC][11] = 56, + [2][1][2][1][RTW89_ETSI][11] = 40, + [2][1][2][1][RTW89_MKK][11] = 52, + [2][1][2][1][RTW89_IC][11] = 40, +- [2][1][2][1][RTW89_KCC][11] = 40, ++ [2][1][2][1][RTW89_KCC][11] = 64, + [2][1][2][1][RTW89_ACMA][11] = 40, + [2][1][2][1][RTW89_CHILE][11] = 30, + [2][1][2][1][RTW89_UKRAINE][11] = 28, ++ [2][1][2][1][RTW89_MEXICO][11] = 56, ++ [2][1][2][1][RTW89_CN][11] = 40, ++ [2][1][2][1][RTW89_QATAR][11] = 40, + [2][1][2][1][RTW89_FCC][18] = 56, + [2][1][2][1][RTW89_ETSI][18] = 40, + [2][1][2][1][RTW89_MKK][18] = 72, + [2][1][2][1][RTW89_IC][18] = 56, +- [2][1][2][1][RTW89_KCC][18] = 40, ++ [2][1][2][1][RTW89_KCC][18] = 58, + [2][1][2][1][RTW89_ACMA][18] = 40, + [2][1][2][1][RTW89_CHILE][18] = 30, + [2][1][2][1][RTW89_UKRAINE][18] = 28, ++ [2][1][2][1][RTW89_MEXICO][18] = 56, ++ [2][1][2][1][RTW89_CN][18] = 127, ++ [2][1][2][1][RTW89_QATAR][18] = 28, + [2][1][2][1][RTW89_FCC][26] = 68, + [2][1][2][1][RTW89_ETSI][26] = 40, + [2][1][2][1][RTW89_MKK][26] = 72, + [2][1][2][1][RTW89_IC][26] = 127, +- [2][1][2][1][RTW89_KCC][26] = 40, ++ [2][1][2][1][RTW89_KCC][26] = 64, + [2][1][2][1][RTW89_ACMA][26] = 127, + [2][1][2][1][RTW89_CHILE][26] = 30, + [2][1][2][1][RTW89_UKRAINE][26] = 28, ++ [2][1][2][1][RTW89_MEXICO][26] = 68, ++ [2][1][2][1][RTW89_CN][26] = 127, ++ [2][1][2][1][RTW89_QATAR][26] = 28, + [2][1][2][1][RTW89_FCC][34] = 68, + [2][1][2][1][RTW89_ETSI][34] = 127, + [2][1][2][1][RTW89_MKK][34] = 72, + [2][1][2][1][RTW89_IC][34] = 68, +- [2][1][2][1][RTW89_KCC][34] = 40, ++ [2][1][2][1][RTW89_KCC][34] = 64, + [2][1][2][1][RTW89_ACMA][34] = 68, + [2][1][2][1][RTW89_CHILE][34] = 30, + [2][1][2][1][RTW89_UKRAINE][34] = 127, ++ [2][1][2][1][RTW89_MEXICO][34] = 68, ++ [2][1][2][1][RTW89_CN][34] = 127, ++ [2][1][2][1][RTW89_QATAR][34] = 127, + [2][1][2][1][RTW89_FCC][41] = 72, + [2][1][2][1][RTW89_ETSI][41] = 4, + [2][1][2][1][RTW89_MKK][41] = 127, + [2][1][2][1][RTW89_IC][41] = 72, +- [2][1][2][1][RTW89_KCC][41] = 4, ++ [2][1][2][1][RTW89_KCC][41] = 58, + [2][1][2][1][RTW89_ACMA][41] = 72, + [2][1][2][1][RTW89_CHILE][41] = 30, +- [2][1][2][1][RTW89_UKRAINE][41] = 28, ++ [2][1][2][1][RTW89_UKRAINE][41] = 4, ++ [2][1][2][1][RTW89_MEXICO][41] = 72, ++ [2][1][2][1][RTW89_CN][41] = 64, ++ [2][1][2][1][RTW89_QATAR][41] = 4, + }; + + const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] +@@ -46604,106 +47645,145 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][0][RTW89_ETSI][0] = 32, + [0][0][RTW89_MKK][0] = 40, + [0][0][RTW89_IC][0] = 70, +- [0][0][RTW89_KCC][0] = 32, ++ [0][0][RTW89_KCC][0] = 46, + [0][0][RTW89_ACMA][0] = 32, + [0][0][RTW89_CHILE][0] = 60, + [0][0][RTW89_UKRAINE][0] = 32, ++ [0][0][RTW89_MEXICO][0] = 70, ++ [0][0][RTW89_CN][0] = 32, ++ [0][0][RTW89_QATAR][0] = 32, + [0][0][RTW89_FCC][1] = 70, + [0][0][RTW89_ETSI][1] = 32, + [0][0][RTW89_MKK][1] = 40, + [0][0][RTW89_IC][1] = 70, +- [0][0][RTW89_KCC][1] = 32, ++ [0][0][RTW89_KCC][1] = 46, + [0][0][RTW89_ACMA][1] = 32, + [0][0][RTW89_CHILE][1] = 60, + [0][0][RTW89_UKRAINE][1] = 32, ++ [0][0][RTW89_MEXICO][1] = 70, ++ [0][0][RTW89_CN][1] = 32, ++ [0][0][RTW89_QATAR][1] = 32, + [0][0][RTW89_FCC][2] = 74, + [0][0][RTW89_ETSI][2] = 32, + [0][0][RTW89_MKK][2] = 40, + [0][0][RTW89_IC][2] = 74, +- [0][0][RTW89_KCC][2] = 32, ++ [0][0][RTW89_KCC][2] = 46, + [0][0][RTW89_ACMA][2] = 32, + [0][0][RTW89_CHILE][2] = 60, + [0][0][RTW89_UKRAINE][2] = 32, ++ [0][0][RTW89_MEXICO][2] = 74, ++ [0][0][RTW89_CN][2] = 32, ++ [0][0][RTW89_QATAR][2] = 32, + [0][0][RTW89_FCC][3] = 78, + [0][0][RTW89_ETSI][3] = 32, + [0][0][RTW89_MKK][3] = 40, + [0][0][RTW89_IC][3] = 78, +- [0][0][RTW89_KCC][3] = 32, ++ [0][0][RTW89_KCC][3] = 46, + [0][0][RTW89_ACMA][3] = 32, + [0][0][RTW89_CHILE][3] = 60, + [0][0][RTW89_UKRAINE][3] = 32, ++ [0][0][RTW89_MEXICO][3] = 78, ++ [0][0][RTW89_CN][3] = 32, ++ [0][0][RTW89_QATAR][3] = 32, + [0][0][RTW89_FCC][4] = 78, + [0][0][RTW89_ETSI][4] = 32, + [0][0][RTW89_MKK][4] = 40, + [0][0][RTW89_IC][4] = 78, +- [0][0][RTW89_KCC][4] = 32, ++ [0][0][RTW89_KCC][4] = 46, + [0][0][RTW89_ACMA][4] = 32, + [0][0][RTW89_CHILE][4] = 60, + [0][0][RTW89_UKRAINE][4] = 32, ++ [0][0][RTW89_MEXICO][4] = 78, ++ [0][0][RTW89_CN][4] = 32, ++ [0][0][RTW89_QATAR][4] = 32, + [0][0][RTW89_FCC][5] = 78, + [0][0][RTW89_ETSI][5] = 32, + [0][0][RTW89_MKK][5] = 40, + [0][0][RTW89_IC][5] = 78, +- [0][0][RTW89_KCC][5] = 32, ++ [0][0][RTW89_KCC][5] = 46, + [0][0][RTW89_ACMA][5] = 32, + [0][0][RTW89_CHILE][5] = 60, + [0][0][RTW89_UKRAINE][5] = 32, ++ [0][0][RTW89_MEXICO][5] = 78, ++ [0][0][RTW89_CN][5] = 32, ++ [0][0][RTW89_QATAR][5] = 32, + [0][0][RTW89_FCC][6] = 78, + [0][0][RTW89_ETSI][6] = 32, + [0][0][RTW89_MKK][6] = 40, + [0][0][RTW89_IC][6] = 78, +- [0][0][RTW89_KCC][6] = 32, ++ [0][0][RTW89_KCC][6] = 46, + [0][0][RTW89_ACMA][6] = 32, + [0][0][RTW89_CHILE][6] = 60, + [0][0][RTW89_UKRAINE][6] = 32, ++ [0][0][RTW89_MEXICO][6] = 78, ++ [0][0][RTW89_CN][6] = 32, ++ [0][0][RTW89_QATAR][6] = 32, + [0][0][RTW89_FCC][7] = 78, + [0][0][RTW89_ETSI][7] = 32, + [0][0][RTW89_MKK][7] = 40, + [0][0][RTW89_IC][7] = 78, +- [0][0][RTW89_KCC][7] = 32, ++ [0][0][RTW89_KCC][7] = 46, + [0][0][RTW89_ACMA][7] = 32, + [0][0][RTW89_CHILE][7] = 60, + [0][0][RTW89_UKRAINE][7] = 32, ++ [0][0][RTW89_MEXICO][7] = 78, ++ [0][0][RTW89_CN][7] = 32, ++ [0][0][RTW89_QATAR][7] = 32, + [0][0][RTW89_FCC][8] = 74, + [0][0][RTW89_ETSI][8] = 32, + [0][0][RTW89_MKK][8] = 40, + [0][0][RTW89_IC][8] = 74, +- [0][0][RTW89_KCC][8] = 32, ++ [0][0][RTW89_KCC][8] = 46, + [0][0][RTW89_ACMA][8] = 32, + [0][0][RTW89_CHILE][8] = 60, + [0][0][RTW89_UKRAINE][8] = 32, ++ [0][0][RTW89_MEXICO][8] = 74, ++ [0][0][RTW89_CN][8] = 32, ++ [0][0][RTW89_QATAR][8] = 32, + [0][0][RTW89_FCC][9] = 70, + [0][0][RTW89_ETSI][9] = 32, + [0][0][RTW89_MKK][9] = 40, + [0][0][RTW89_IC][9] = 70, +- [0][0][RTW89_KCC][9] = 32, ++ [0][0][RTW89_KCC][9] = 46, + [0][0][RTW89_ACMA][9] = 32, + [0][0][RTW89_CHILE][9] = 60, + [0][0][RTW89_UKRAINE][9] = 32, ++ [0][0][RTW89_MEXICO][9] = 70, ++ [0][0][RTW89_CN][9] = 32, ++ [0][0][RTW89_QATAR][9] = 32, + [0][0][RTW89_FCC][10] = 70, + [0][0][RTW89_ETSI][10] = 32, + [0][0][RTW89_MKK][10] = 40, + [0][0][RTW89_IC][10] = 70, +- [0][0][RTW89_KCC][10] = 32, ++ [0][0][RTW89_KCC][10] = 46, + [0][0][RTW89_ACMA][10] = 32, + [0][0][RTW89_CHILE][10] = 60, + [0][0][RTW89_UKRAINE][10] = 32, ++ [0][0][RTW89_MEXICO][10] = 70, ++ [0][0][RTW89_CN][10] = 32, ++ [0][0][RTW89_QATAR][10] = 32, + [0][0][RTW89_FCC][11] = 58, + [0][0][RTW89_ETSI][11] = 32, + [0][0][RTW89_MKK][11] = 40, + [0][0][RTW89_IC][11] = 58, +- [0][0][RTW89_KCC][11] = 32, ++ [0][0][RTW89_KCC][11] = 46, + [0][0][RTW89_ACMA][11] = 32, +- [0][0][RTW89_CHILE][11] = 60, ++ [0][0][RTW89_CHILE][11] = 58, + [0][0][RTW89_UKRAINE][11] = 32, ++ [0][0][RTW89_MEXICO][11] = 58, ++ [0][0][RTW89_CN][11] = 32, ++ [0][0][RTW89_QATAR][11] = 32, + [0][0][RTW89_FCC][12] = 34, + [0][0][RTW89_ETSI][12] = 32, + [0][0][RTW89_MKK][12] = 40, + [0][0][RTW89_IC][12] = 34, +- [0][0][RTW89_KCC][12] = 32, ++ [0][0][RTW89_KCC][12] = 46, + [0][0][RTW89_ACMA][12] = 32, +- [0][0][RTW89_CHILE][12] = 60, ++ [0][0][RTW89_CHILE][12] = 34, + [0][0][RTW89_UKRAINE][12] = 32, ++ [0][0][RTW89_MEXICO][12] = 34, ++ [0][0][RTW89_CN][12] = 32, ++ [0][0][RTW89_QATAR][12] = 32, + [0][0][RTW89_FCC][13] = 127, + [0][0][RTW89_ETSI][13] = 127, + [0][0][RTW89_MKK][13] = 127, +@@ -46712,110 +47792,152 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][0][RTW89_ACMA][13] = 127, + [0][0][RTW89_CHILE][13] = 127, + [0][0][RTW89_UKRAINE][13] = 127, ++ [0][0][RTW89_MEXICO][13] = 127, ++ [0][0][RTW89_CN][13] = 127, ++ [0][0][RTW89_QATAR][13] = 127, + [0][1][RTW89_FCC][0] = 64, + [0][1][RTW89_ETSI][0] = 20, + [0][1][RTW89_MKK][0] = 28, + [0][1][RTW89_IC][0] = 64, +- [0][1][RTW89_KCC][0] = 20, ++ [0][1][RTW89_KCC][0] = 32, + [0][1][RTW89_ACMA][0] = 20, + [0][1][RTW89_CHILE][0] = 48, + [0][1][RTW89_UKRAINE][0] = 20, ++ [0][1][RTW89_MEXICO][0] = 64, ++ [0][1][RTW89_CN][0] = 20, ++ [0][1][RTW89_QATAR][0] = 20, + [0][1][RTW89_FCC][1] = 64, + [0][1][RTW89_ETSI][1] = 20, + [0][1][RTW89_MKK][1] = 28, + [0][1][RTW89_IC][1] = 64, +- [0][1][RTW89_KCC][1] = 20, ++ [0][1][RTW89_KCC][1] = 32, + [0][1][RTW89_ACMA][1] = 20, + [0][1][RTW89_CHILE][1] = 48, + [0][1][RTW89_UKRAINE][1] = 20, ++ [0][1][RTW89_MEXICO][1] = 64, ++ [0][1][RTW89_CN][1] = 20, ++ [0][1][RTW89_QATAR][1] = 20, + [0][1][RTW89_FCC][2] = 68, + [0][1][RTW89_ETSI][2] = 20, + [0][1][RTW89_MKK][2] = 28, + [0][1][RTW89_IC][2] = 68, +- [0][1][RTW89_KCC][2] = 20, ++ [0][1][RTW89_KCC][2] = 32, + [0][1][RTW89_ACMA][2] = 20, + [0][1][RTW89_CHILE][2] = 48, + [0][1][RTW89_UKRAINE][2] = 20, ++ [0][1][RTW89_MEXICO][2] = 68, ++ [0][1][RTW89_CN][2] = 20, ++ [0][1][RTW89_QATAR][2] = 20, + [0][1][RTW89_FCC][3] = 72, + [0][1][RTW89_ETSI][3] = 20, + [0][1][RTW89_MKK][3] = 28, + [0][1][RTW89_IC][3] = 72, +- [0][1][RTW89_KCC][3] = 20, ++ [0][1][RTW89_KCC][3] = 32, + [0][1][RTW89_ACMA][3] = 20, + [0][1][RTW89_CHILE][3] = 48, + [0][1][RTW89_UKRAINE][3] = 20, ++ [0][1][RTW89_MEXICO][3] = 72, ++ [0][1][RTW89_CN][3] = 20, ++ [0][1][RTW89_QATAR][3] = 20, + [0][1][RTW89_FCC][4] = 76, + [0][1][RTW89_ETSI][4] = 20, + [0][1][RTW89_MKK][4] = 28, + [0][1][RTW89_IC][4] = 76, +- [0][1][RTW89_KCC][4] = 20, ++ [0][1][RTW89_KCC][4] = 32, + [0][1][RTW89_ACMA][4] = 20, + [0][1][RTW89_CHILE][4] = 48, + [0][1][RTW89_UKRAINE][4] = 20, ++ [0][1][RTW89_MEXICO][4] = 76, ++ [0][1][RTW89_CN][4] = 20, ++ [0][1][RTW89_QATAR][4] = 20, + [0][1][RTW89_FCC][5] = 78, + [0][1][RTW89_ETSI][5] = 20, + [0][1][RTW89_MKK][5] = 28, + [0][1][RTW89_IC][5] = 78, +- [0][1][RTW89_KCC][5] = 20, ++ [0][1][RTW89_KCC][5] = 32, + [0][1][RTW89_ACMA][5] = 20, + [0][1][RTW89_CHILE][5] = 48, + [0][1][RTW89_UKRAINE][5] = 20, ++ [0][1][RTW89_MEXICO][5] = 78, ++ [0][1][RTW89_CN][5] = 20, ++ [0][1][RTW89_QATAR][5] = 20, + [0][1][RTW89_FCC][6] = 76, + [0][1][RTW89_ETSI][6] = 20, + [0][1][RTW89_MKK][6] = 28, + [0][1][RTW89_IC][6] = 76, +- [0][1][RTW89_KCC][6] = 20, ++ [0][1][RTW89_KCC][6] = 32, + [0][1][RTW89_ACMA][6] = 20, + [0][1][RTW89_CHILE][6] = 48, + [0][1][RTW89_UKRAINE][6] = 20, ++ [0][1][RTW89_MEXICO][6] = 76, ++ [0][1][RTW89_CN][6] = 20, ++ [0][1][RTW89_QATAR][6] = 20, + [0][1][RTW89_FCC][7] = 72, + [0][1][RTW89_ETSI][7] = 20, + [0][1][RTW89_MKK][7] = 28, + [0][1][RTW89_IC][7] = 72, +- [0][1][RTW89_KCC][7] = 20, ++ [0][1][RTW89_KCC][7] = 32, + [0][1][RTW89_ACMA][7] = 20, + [0][1][RTW89_CHILE][7] = 48, + [0][1][RTW89_UKRAINE][7] = 20, ++ [0][1][RTW89_MEXICO][7] = 72, ++ [0][1][RTW89_CN][7] = 20, ++ [0][1][RTW89_QATAR][7] = 20, + [0][1][RTW89_FCC][8] = 68, + [0][1][RTW89_ETSI][8] = 20, + [0][1][RTW89_MKK][8] = 28, + [0][1][RTW89_IC][8] = 68, +- [0][1][RTW89_KCC][8] = 20, ++ [0][1][RTW89_KCC][8] = 32, + [0][1][RTW89_ACMA][8] = 20, + [0][1][RTW89_CHILE][8] = 48, + [0][1][RTW89_UKRAINE][8] = 20, ++ [0][1][RTW89_MEXICO][8] = 68, ++ [0][1][RTW89_CN][8] = 20, ++ [0][1][RTW89_QATAR][8] = 20, + [0][1][RTW89_FCC][9] = 64, + [0][1][RTW89_ETSI][9] = 20, + [0][1][RTW89_MKK][9] = 28, + [0][1][RTW89_IC][9] = 64, +- [0][1][RTW89_KCC][9] = 20, ++ [0][1][RTW89_KCC][9] = 32, + [0][1][RTW89_ACMA][9] = 20, + [0][1][RTW89_CHILE][9] = 48, + [0][1][RTW89_UKRAINE][9] = 20, ++ [0][1][RTW89_MEXICO][9] = 64, ++ [0][1][RTW89_CN][9] = 20, ++ [0][1][RTW89_QATAR][9] = 20, + [0][1][RTW89_FCC][10] = 64, + [0][1][RTW89_ETSI][10] = 20, + [0][1][RTW89_MKK][10] = 28, + [0][1][RTW89_IC][10] = 64, +- [0][1][RTW89_KCC][10] = 20, ++ [0][1][RTW89_KCC][10] = 32, + [0][1][RTW89_ACMA][10] = 20, + [0][1][RTW89_CHILE][10] = 48, + [0][1][RTW89_UKRAINE][10] = 20, ++ [0][1][RTW89_MEXICO][10] = 64, ++ [0][1][RTW89_CN][10] = 20, ++ [0][1][RTW89_QATAR][10] = 20, + [0][1][RTW89_FCC][11] = 54, + [0][1][RTW89_ETSI][11] = 20, + [0][1][RTW89_MKK][11] = 28, + [0][1][RTW89_IC][11] = 54, +- [0][1][RTW89_KCC][11] = 20, ++ [0][1][RTW89_KCC][11] = 32, + [0][1][RTW89_ACMA][11] = 20, + [0][1][RTW89_CHILE][11] = 48, + [0][1][RTW89_UKRAINE][11] = 20, ++ [0][1][RTW89_MEXICO][11] = 54, ++ [0][1][RTW89_CN][11] = 20, ++ [0][1][RTW89_QATAR][11] = 20, + [0][1][RTW89_FCC][12] = 32, + [0][1][RTW89_ETSI][12] = 20, + [0][1][RTW89_MKK][12] = 28, + [0][1][RTW89_IC][12] = 32, +- [0][1][RTW89_KCC][12] = 20, ++ [0][1][RTW89_KCC][12] = 32, + [0][1][RTW89_ACMA][12] = 20, +- [0][1][RTW89_CHILE][12] = 48, ++ [0][1][RTW89_CHILE][12] = 32, + [0][1][RTW89_UKRAINE][12] = 20, ++ [0][1][RTW89_MEXICO][12] = 32, ++ [0][1][RTW89_CN][12] = 20, ++ [0][1][RTW89_QATAR][12] = 20, + [0][1][RTW89_FCC][13] = 127, + [0][1][RTW89_ETSI][13] = 127, + [0][1][RTW89_MKK][13] = 127, +@@ -46824,110 +47946,152 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][1][RTW89_ACMA][13] = 127, + [0][1][RTW89_CHILE][13] = 127, + [0][1][RTW89_UKRAINE][13] = 127, ++ [0][1][RTW89_MEXICO][13] = 127, ++ [0][1][RTW89_CN][13] = 127, ++ [0][1][RTW89_QATAR][13] = 127, + [1][0][RTW89_FCC][0] = 72, + [1][0][RTW89_ETSI][0] = 42, + [1][0][RTW89_MKK][0] = 50, + [1][0][RTW89_IC][0] = 72, +- [1][0][RTW89_KCC][0] = 42, ++ [1][0][RTW89_KCC][0] = 58, + [1][0][RTW89_ACMA][0] = 42, + [1][0][RTW89_CHILE][0] = 60, + [1][0][RTW89_UKRAINE][0] = 42, ++ [1][0][RTW89_MEXICO][0] = 72, ++ [1][0][RTW89_CN][0] = 42, ++ [1][0][RTW89_QATAR][0] = 42, + [1][0][RTW89_FCC][1] = 72, + [1][0][RTW89_ETSI][1] = 42, + [1][0][RTW89_MKK][1] = 50, + [1][0][RTW89_IC][1] = 72, +- [1][0][RTW89_KCC][1] = 42, ++ [1][0][RTW89_KCC][1] = 58, + [1][0][RTW89_ACMA][1] = 42, + [1][0][RTW89_CHILE][1] = 60, + [1][0][RTW89_UKRAINE][1] = 42, ++ [1][0][RTW89_MEXICO][1] = 72, ++ [1][0][RTW89_CN][1] = 42, ++ [1][0][RTW89_QATAR][1] = 42, + [1][0][RTW89_FCC][2] = 76, + [1][0][RTW89_ETSI][2] = 42, + [1][0][RTW89_MKK][2] = 50, + [1][0][RTW89_IC][2] = 76, +- [1][0][RTW89_KCC][2] = 42, ++ [1][0][RTW89_KCC][2] = 58, + [1][0][RTW89_ACMA][2] = 42, + [1][0][RTW89_CHILE][2] = 60, + [1][0][RTW89_UKRAINE][2] = 42, ++ [1][0][RTW89_MEXICO][2] = 76, ++ [1][0][RTW89_CN][2] = 42, ++ [1][0][RTW89_QATAR][2] = 42, + [1][0][RTW89_FCC][3] = 78, + [1][0][RTW89_ETSI][3] = 42, + [1][0][RTW89_MKK][3] = 50, + [1][0][RTW89_IC][3] = 78, +- [1][0][RTW89_KCC][3] = 42, ++ [1][0][RTW89_KCC][3] = 58, + [1][0][RTW89_ACMA][3] = 42, + [1][0][RTW89_CHILE][3] = 60, + [1][0][RTW89_UKRAINE][3] = 42, ++ [1][0][RTW89_MEXICO][3] = 78, ++ [1][0][RTW89_CN][3] = 42, ++ [1][0][RTW89_QATAR][3] = 42, + [1][0][RTW89_FCC][4] = 78, + [1][0][RTW89_ETSI][4] = 42, + [1][0][RTW89_MKK][4] = 50, + [1][0][RTW89_IC][4] = 78, +- [1][0][RTW89_KCC][4] = 42, ++ [1][0][RTW89_KCC][4] = 58, + [1][0][RTW89_ACMA][4] = 42, + [1][0][RTW89_CHILE][4] = 60, + [1][0][RTW89_UKRAINE][4] = 42, ++ [1][0][RTW89_MEXICO][4] = 78, ++ [1][0][RTW89_CN][4] = 42, ++ [1][0][RTW89_QATAR][4] = 42, + [1][0][RTW89_FCC][5] = 78, + [1][0][RTW89_ETSI][5] = 42, + [1][0][RTW89_MKK][5] = 50, + [1][0][RTW89_IC][5] = 78, +- [1][0][RTW89_KCC][5] = 42, ++ [1][0][RTW89_KCC][5] = 58, + [1][0][RTW89_ACMA][5] = 42, + [1][0][RTW89_CHILE][5] = 60, + [1][0][RTW89_UKRAINE][5] = 42, ++ [1][0][RTW89_MEXICO][5] = 78, ++ [1][0][RTW89_CN][5] = 42, ++ [1][0][RTW89_QATAR][5] = 42, + [1][0][RTW89_FCC][6] = 78, + [1][0][RTW89_ETSI][6] = 42, + [1][0][RTW89_MKK][6] = 50, + [1][0][RTW89_IC][6] = 78, +- [1][0][RTW89_KCC][6] = 42, ++ [1][0][RTW89_KCC][6] = 58, + [1][0][RTW89_ACMA][6] = 42, + [1][0][RTW89_CHILE][6] = 60, + [1][0][RTW89_UKRAINE][6] = 42, ++ [1][0][RTW89_MEXICO][6] = 78, ++ [1][0][RTW89_CN][6] = 42, ++ [1][0][RTW89_QATAR][6] = 42, + [1][0][RTW89_FCC][7] = 78, + [1][0][RTW89_ETSI][7] = 42, + [1][0][RTW89_MKK][7] = 50, + [1][0][RTW89_IC][7] = 78, +- [1][0][RTW89_KCC][7] = 42, ++ [1][0][RTW89_KCC][7] = 58, + [1][0][RTW89_ACMA][7] = 42, + [1][0][RTW89_CHILE][7] = 60, + [1][0][RTW89_UKRAINE][7] = 42, ++ [1][0][RTW89_MEXICO][7] = 78, ++ [1][0][RTW89_CN][7] = 42, ++ [1][0][RTW89_QATAR][7] = 42, + [1][0][RTW89_FCC][8] = 78, + [1][0][RTW89_ETSI][8] = 42, + [1][0][RTW89_MKK][8] = 50, + [1][0][RTW89_IC][8] = 78, +- [1][0][RTW89_KCC][8] = 42, ++ [1][0][RTW89_KCC][8] = 58, + [1][0][RTW89_ACMA][8] = 42, + [1][0][RTW89_CHILE][8] = 60, + [1][0][RTW89_UKRAINE][8] = 42, ++ [1][0][RTW89_MEXICO][8] = 78, ++ [1][0][RTW89_CN][8] = 42, ++ [1][0][RTW89_QATAR][8] = 42, + [1][0][RTW89_FCC][9] = 74, + [1][0][RTW89_ETSI][9] = 42, + [1][0][RTW89_MKK][9] = 50, + [1][0][RTW89_IC][9] = 74, +- [1][0][RTW89_KCC][9] = 42, ++ [1][0][RTW89_KCC][9] = 58, + [1][0][RTW89_ACMA][9] = 42, + [1][0][RTW89_CHILE][9] = 60, + [1][0][RTW89_UKRAINE][9] = 42, ++ [1][0][RTW89_MEXICO][9] = 74, ++ [1][0][RTW89_CN][9] = 42, ++ [1][0][RTW89_QATAR][9] = 42, + [1][0][RTW89_FCC][10] = 74, + [1][0][RTW89_ETSI][10] = 42, + [1][0][RTW89_MKK][10] = 50, + [1][0][RTW89_IC][10] = 74, +- [1][0][RTW89_KCC][10] = 42, ++ [1][0][RTW89_KCC][10] = 58, + [1][0][RTW89_ACMA][10] = 42, + [1][0][RTW89_CHILE][10] = 60, + [1][0][RTW89_UKRAINE][10] = 42, ++ [1][0][RTW89_MEXICO][10] = 74, ++ [1][0][RTW89_CN][10] = 42, ++ [1][0][RTW89_QATAR][10] = 42, + [1][0][RTW89_FCC][11] = 64, + [1][0][RTW89_ETSI][11] = 42, + [1][0][RTW89_MKK][11] = 50, + [1][0][RTW89_IC][11] = 64, +- [1][0][RTW89_KCC][11] = 42, ++ [1][0][RTW89_KCC][11] = 58, + [1][0][RTW89_ACMA][11] = 42, + [1][0][RTW89_CHILE][11] = 60, + [1][0][RTW89_UKRAINE][11] = 42, ++ [1][0][RTW89_MEXICO][11] = 64, ++ [1][0][RTW89_CN][11] = 42, ++ [1][0][RTW89_QATAR][11] = 42, + [1][0][RTW89_FCC][12] = 36, + [1][0][RTW89_ETSI][12] = 42, + [1][0][RTW89_MKK][12] = 50, + [1][0][RTW89_IC][12] = 36, +- [1][0][RTW89_KCC][12] = 42, ++ [1][0][RTW89_KCC][12] = 58, + [1][0][RTW89_ACMA][12] = 42, +- [1][0][RTW89_CHILE][12] = 60, ++ [1][0][RTW89_CHILE][12] = 36, + [1][0][RTW89_UKRAINE][12] = 42, ++ [1][0][RTW89_MEXICO][12] = 36, ++ [1][0][RTW89_CN][12] = 42, ++ [1][0][RTW89_QATAR][12] = 42, + [1][0][RTW89_FCC][13] = 127, + [1][0][RTW89_ETSI][13] = 127, + [1][0][RTW89_MKK][13] = 127, +@@ -46936,110 +48100,152 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [1][0][RTW89_ACMA][13] = 127, + [1][0][RTW89_CHILE][13] = 127, + [1][0][RTW89_UKRAINE][13] = 127, ++ [1][0][RTW89_MEXICO][13] = 127, ++ [1][0][RTW89_CN][13] = 127, ++ [1][0][RTW89_QATAR][13] = 127, + [1][1][RTW89_FCC][0] = 66, + [1][1][RTW89_ETSI][0] = 30, + [1][1][RTW89_MKK][0] = 38, + [1][1][RTW89_IC][0] = 66, +- [1][1][RTW89_KCC][0] = 30, ++ [1][1][RTW89_KCC][0] = 44, + [1][1][RTW89_ACMA][0] = 30, + [1][1][RTW89_CHILE][0] = 48, + [1][1][RTW89_UKRAINE][0] = 30, ++ [1][1][RTW89_MEXICO][0] = 66, ++ [1][1][RTW89_CN][0] = 30, ++ [1][1][RTW89_QATAR][0] = 30, + [1][1][RTW89_FCC][1] = 66, + [1][1][RTW89_ETSI][1] = 30, + [1][1][RTW89_MKK][1] = 38, + [1][1][RTW89_IC][1] = 66, +- [1][1][RTW89_KCC][1] = 30, ++ [1][1][RTW89_KCC][1] = 44, + [1][1][RTW89_ACMA][1] = 30, + [1][1][RTW89_CHILE][1] = 48, + [1][1][RTW89_UKRAINE][1] = 30, ++ [1][1][RTW89_MEXICO][1] = 66, ++ [1][1][RTW89_CN][1] = 30, ++ [1][1][RTW89_QATAR][1] = 30, + [1][1][RTW89_FCC][2] = 70, + [1][1][RTW89_ETSI][2] = 30, + [1][1][RTW89_MKK][2] = 38, + [1][1][RTW89_IC][2] = 70, +- [1][1][RTW89_KCC][2] = 30, ++ [1][1][RTW89_KCC][2] = 44, + [1][1][RTW89_ACMA][2] = 30, + [1][1][RTW89_CHILE][2] = 48, + [1][1][RTW89_UKRAINE][2] = 30, ++ [1][1][RTW89_MEXICO][2] = 70, ++ [1][1][RTW89_CN][2] = 30, ++ [1][1][RTW89_QATAR][2] = 30, + [1][1][RTW89_FCC][3] = 74, + [1][1][RTW89_ETSI][3] = 30, + [1][1][RTW89_MKK][3] = 38, + [1][1][RTW89_IC][3] = 74, +- [1][1][RTW89_KCC][3] = 30, ++ [1][1][RTW89_KCC][3] = 44, + [1][1][RTW89_ACMA][3] = 30, + [1][1][RTW89_CHILE][3] = 48, + [1][1][RTW89_UKRAINE][3] = 30, ++ [1][1][RTW89_MEXICO][3] = 74, ++ [1][1][RTW89_CN][3] = 30, ++ [1][1][RTW89_QATAR][3] = 30, + [1][1][RTW89_FCC][4] = 78, + [1][1][RTW89_ETSI][4] = 30, + [1][1][RTW89_MKK][4] = 38, + [1][1][RTW89_IC][4] = 78, +- [1][1][RTW89_KCC][4] = 30, ++ [1][1][RTW89_KCC][4] = 44, + [1][1][RTW89_ACMA][4] = 30, + [1][1][RTW89_CHILE][4] = 48, + [1][1][RTW89_UKRAINE][4] = 30, ++ [1][1][RTW89_MEXICO][4] = 78, ++ [1][1][RTW89_CN][4] = 30, ++ [1][1][RTW89_QATAR][4] = 30, + [1][1][RTW89_FCC][5] = 78, + [1][1][RTW89_ETSI][5] = 30, + [1][1][RTW89_MKK][5] = 38, + [1][1][RTW89_IC][5] = 78, +- [1][1][RTW89_KCC][5] = 30, ++ [1][1][RTW89_KCC][5] = 44, + [1][1][RTW89_ACMA][5] = 30, + [1][1][RTW89_CHILE][5] = 48, + [1][1][RTW89_UKRAINE][5] = 30, ++ [1][1][RTW89_MEXICO][5] = 78, ++ [1][1][RTW89_CN][5] = 30, ++ [1][1][RTW89_QATAR][5] = 30, + [1][1][RTW89_FCC][6] = 78, + [1][1][RTW89_ETSI][6] = 30, + [1][1][RTW89_MKK][6] = 38, + [1][1][RTW89_IC][6] = 78, +- [1][1][RTW89_KCC][6] = 30, ++ [1][1][RTW89_KCC][6] = 44, + [1][1][RTW89_ACMA][6] = 30, + [1][1][RTW89_CHILE][6] = 48, + [1][1][RTW89_UKRAINE][6] = 30, ++ [1][1][RTW89_MEXICO][6] = 78, ++ [1][1][RTW89_CN][6] = 30, ++ [1][1][RTW89_QATAR][6] = 30, + [1][1][RTW89_FCC][7] = 74, + [1][1][RTW89_ETSI][7] = 30, + [1][1][RTW89_MKK][7] = 38, + [1][1][RTW89_IC][7] = 74, +- [1][1][RTW89_KCC][7] = 30, ++ [1][1][RTW89_KCC][7] = 44, + [1][1][RTW89_ACMA][7] = 30, + [1][1][RTW89_CHILE][7] = 48, + [1][1][RTW89_UKRAINE][7] = 30, ++ [1][1][RTW89_MEXICO][7] = 74, ++ [1][1][RTW89_CN][7] = 30, ++ [1][1][RTW89_QATAR][7] = 30, + [1][1][RTW89_FCC][8] = 70, + [1][1][RTW89_ETSI][8] = 30, + [1][1][RTW89_MKK][8] = 38, + [1][1][RTW89_IC][8] = 70, +- [1][1][RTW89_KCC][8] = 30, ++ [1][1][RTW89_KCC][8] = 44, + [1][1][RTW89_ACMA][8] = 30, + [1][1][RTW89_CHILE][8] = 48, + [1][1][RTW89_UKRAINE][8] = 30, ++ [1][1][RTW89_MEXICO][8] = 70, ++ [1][1][RTW89_CN][8] = 30, ++ [1][1][RTW89_QATAR][8] = 30, + [1][1][RTW89_FCC][9] = 66, + [1][1][RTW89_ETSI][9] = 30, + [1][1][RTW89_MKK][9] = 38, + [1][1][RTW89_IC][9] = 66, +- [1][1][RTW89_KCC][9] = 30, ++ [1][1][RTW89_KCC][9] = 44, + [1][1][RTW89_ACMA][9] = 30, + [1][1][RTW89_CHILE][9] = 48, + [1][1][RTW89_UKRAINE][9] = 30, ++ [1][1][RTW89_MEXICO][9] = 66, ++ [1][1][RTW89_CN][9] = 30, ++ [1][1][RTW89_QATAR][9] = 30, + [1][1][RTW89_FCC][10] = 66, + [1][1][RTW89_ETSI][10] = 30, + [1][1][RTW89_MKK][10] = 38, + [1][1][RTW89_IC][10] = 66, +- [1][1][RTW89_KCC][10] = 30, ++ [1][1][RTW89_KCC][10] = 44, + [1][1][RTW89_ACMA][10] = 30, + [1][1][RTW89_CHILE][10] = 48, + [1][1][RTW89_UKRAINE][10] = 30, ++ [1][1][RTW89_MEXICO][10] = 66, ++ [1][1][RTW89_CN][10] = 30, ++ [1][1][RTW89_QATAR][10] = 30, + [1][1][RTW89_FCC][11] = 60, + [1][1][RTW89_ETSI][11] = 30, + [1][1][RTW89_MKK][11] = 38, + [1][1][RTW89_IC][11] = 60, +- [1][1][RTW89_KCC][11] = 30, ++ [1][1][RTW89_KCC][11] = 44, + [1][1][RTW89_ACMA][11] = 30, + [1][1][RTW89_CHILE][11] = 48, + [1][1][RTW89_UKRAINE][11] = 30, ++ [1][1][RTW89_MEXICO][11] = 60, ++ [1][1][RTW89_CN][11] = 30, ++ [1][1][RTW89_QATAR][11] = 30, + [1][1][RTW89_FCC][12] = 32, + [1][1][RTW89_ETSI][12] = 30, + [1][1][RTW89_MKK][12] = 38, + [1][1][RTW89_IC][12] = 32, +- [1][1][RTW89_KCC][12] = 30, ++ [1][1][RTW89_KCC][12] = 44, + [1][1][RTW89_ACMA][12] = 30, +- [1][1][RTW89_CHILE][12] = 48, ++ [1][1][RTW89_CHILE][12] = 32, + [1][1][RTW89_UKRAINE][12] = 30, ++ [1][1][RTW89_MEXICO][12] = 32, ++ [1][1][RTW89_CN][12] = 30, ++ [1][1][RTW89_QATAR][12] = 30, + [1][1][RTW89_FCC][13] = 127, + [1][1][RTW89_ETSI][13] = 127, + [1][1][RTW89_MKK][13] = 127, +@@ -47048,110 +48254,152 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [1][1][RTW89_ACMA][13] = 127, + [1][1][RTW89_CHILE][13] = 127, + [1][1][RTW89_UKRAINE][13] = 127, ++ [1][1][RTW89_MEXICO][13] = 127, ++ [1][1][RTW89_CN][13] = 127, ++ [1][1][RTW89_QATAR][13] = 127, + [2][0][RTW89_FCC][0] = 76, + [2][0][RTW89_ETSI][0] = 52, + [2][0][RTW89_MKK][0] = 64, + [2][0][RTW89_IC][0] = 76, +- [2][0][RTW89_KCC][0] = 52, ++ [2][0][RTW89_KCC][0] = 70, + [2][0][RTW89_ACMA][0] = 52, + [2][0][RTW89_CHILE][0] = 60, + [2][0][RTW89_UKRAINE][0] = 52, ++ [2][0][RTW89_MEXICO][0] = 76, ++ [2][0][RTW89_CN][0] = 52, ++ [2][0][RTW89_QATAR][0] = 52, + [2][0][RTW89_FCC][1] = 76, + [2][0][RTW89_ETSI][1] = 52, + [2][0][RTW89_MKK][1] = 64, + [2][0][RTW89_IC][1] = 76, +- [2][0][RTW89_KCC][1] = 52, ++ [2][0][RTW89_KCC][1] = 70, + [2][0][RTW89_ACMA][1] = 52, + [2][0][RTW89_CHILE][1] = 60, + [2][0][RTW89_UKRAINE][1] = 52, ++ [2][0][RTW89_MEXICO][1] = 76, ++ [2][0][RTW89_CN][1] = 52, ++ [2][0][RTW89_QATAR][1] = 52, + [2][0][RTW89_FCC][2] = 78, + [2][0][RTW89_ETSI][2] = 52, + [2][0][RTW89_MKK][2] = 64, + [2][0][RTW89_IC][2] = 78, +- [2][0][RTW89_KCC][2] = 52, ++ [2][0][RTW89_KCC][2] = 70, + [2][0][RTW89_ACMA][2] = 52, + [2][0][RTW89_CHILE][2] = 60, + [2][0][RTW89_UKRAINE][2] = 52, ++ [2][0][RTW89_MEXICO][2] = 78, ++ [2][0][RTW89_CN][2] = 52, ++ [2][0][RTW89_QATAR][2] = 52, + [2][0][RTW89_FCC][3] = 78, + [2][0][RTW89_ETSI][3] = 52, + [2][0][RTW89_MKK][3] = 64, + [2][0][RTW89_IC][3] = 78, +- [2][0][RTW89_KCC][3] = 52, ++ [2][0][RTW89_KCC][3] = 70, + [2][0][RTW89_ACMA][3] = 52, + [2][0][RTW89_CHILE][3] = 60, + [2][0][RTW89_UKRAINE][3] = 52, ++ [2][0][RTW89_MEXICO][3] = 78, ++ [2][0][RTW89_CN][3] = 52, ++ [2][0][RTW89_QATAR][3] = 52, + [2][0][RTW89_FCC][4] = 78, + [2][0][RTW89_ETSI][4] = 52, + [2][0][RTW89_MKK][4] = 64, + [2][0][RTW89_IC][4] = 78, +- [2][0][RTW89_KCC][4] = 52, ++ [2][0][RTW89_KCC][4] = 70, + [2][0][RTW89_ACMA][4] = 52, + [2][0][RTW89_CHILE][4] = 60, + [2][0][RTW89_UKRAINE][4] = 52, ++ [2][0][RTW89_MEXICO][4] = 78, ++ [2][0][RTW89_CN][4] = 52, ++ [2][0][RTW89_QATAR][4] = 52, + [2][0][RTW89_FCC][5] = 78, + [2][0][RTW89_ETSI][5] = 52, + [2][0][RTW89_MKK][5] = 64, + [2][0][RTW89_IC][5] = 78, +- [2][0][RTW89_KCC][5] = 52, ++ [2][0][RTW89_KCC][5] = 70, + [2][0][RTW89_ACMA][5] = 52, + [2][0][RTW89_CHILE][5] = 60, + [2][0][RTW89_UKRAINE][5] = 52, ++ [2][0][RTW89_MEXICO][5] = 78, ++ [2][0][RTW89_CN][5] = 52, ++ [2][0][RTW89_QATAR][5] = 52, + [2][0][RTW89_FCC][6] = 78, + [2][0][RTW89_ETSI][6] = 52, + [2][0][RTW89_MKK][6] = 64, + [2][0][RTW89_IC][6] = 78, +- [2][0][RTW89_KCC][6] = 52, ++ [2][0][RTW89_KCC][6] = 70, + [2][0][RTW89_ACMA][6] = 52, + [2][0][RTW89_CHILE][6] = 60, + [2][0][RTW89_UKRAINE][6] = 52, ++ [2][0][RTW89_MEXICO][6] = 78, ++ [2][0][RTW89_CN][6] = 52, ++ [2][0][RTW89_QATAR][6] = 52, + [2][0][RTW89_FCC][7] = 78, + [2][0][RTW89_ETSI][7] = 52, + [2][0][RTW89_MKK][7] = 64, + [2][0][RTW89_IC][7] = 78, +- [2][0][RTW89_KCC][7] = 52, ++ [2][0][RTW89_KCC][7] = 70, + [2][0][RTW89_ACMA][7] = 52, + [2][0][RTW89_CHILE][7] = 60, + [2][0][RTW89_UKRAINE][7] = 52, ++ [2][0][RTW89_MEXICO][7] = 78, ++ [2][0][RTW89_CN][7] = 52, ++ [2][0][RTW89_QATAR][7] = 52, + [2][0][RTW89_FCC][8] = 78, + [2][0][RTW89_ETSI][8] = 52, + [2][0][RTW89_MKK][8] = 64, + [2][0][RTW89_IC][8] = 78, +- [2][0][RTW89_KCC][8] = 52, ++ [2][0][RTW89_KCC][8] = 70, + [2][0][RTW89_ACMA][8] = 52, + [2][0][RTW89_CHILE][8] = 60, + [2][0][RTW89_UKRAINE][8] = 52, ++ [2][0][RTW89_MEXICO][8] = 78, ++ [2][0][RTW89_CN][8] = 52, ++ [2][0][RTW89_QATAR][8] = 52, + [2][0][RTW89_FCC][9] = 76, + [2][0][RTW89_ETSI][9] = 52, + [2][0][RTW89_MKK][9] = 64, + [2][0][RTW89_IC][9] = 76, +- [2][0][RTW89_KCC][9] = 52, ++ [2][0][RTW89_KCC][9] = 70, + [2][0][RTW89_ACMA][9] = 52, + [2][0][RTW89_CHILE][9] = 60, + [2][0][RTW89_UKRAINE][9] = 52, ++ [2][0][RTW89_MEXICO][9] = 76, ++ [2][0][RTW89_CN][9] = 52, ++ [2][0][RTW89_QATAR][9] = 52, + [2][0][RTW89_FCC][10] = 76, + [2][0][RTW89_ETSI][10] = 52, + [2][0][RTW89_MKK][10] = 64, + [2][0][RTW89_IC][10] = 76, +- [2][0][RTW89_KCC][10] = 52, ++ [2][0][RTW89_KCC][10] = 70, + [2][0][RTW89_ACMA][10] = 52, + [2][0][RTW89_CHILE][10] = 60, + [2][0][RTW89_UKRAINE][10] = 52, ++ [2][0][RTW89_MEXICO][10] = 76, ++ [2][0][RTW89_CN][10] = 52, ++ [2][0][RTW89_QATAR][10] = 52, + [2][0][RTW89_FCC][11] = 68, + [2][0][RTW89_ETSI][11] = 52, + [2][0][RTW89_MKK][11] = 64, + [2][0][RTW89_IC][11] = 68, +- [2][0][RTW89_KCC][11] = 52, ++ [2][0][RTW89_KCC][11] = 70, + [2][0][RTW89_ACMA][11] = 52, + [2][0][RTW89_CHILE][11] = 60, + [2][0][RTW89_UKRAINE][11] = 52, ++ [2][0][RTW89_MEXICO][11] = 68, ++ [2][0][RTW89_CN][11] = 52, ++ [2][0][RTW89_QATAR][11] = 52, + [2][0][RTW89_FCC][12] = 40, + [2][0][RTW89_ETSI][12] = 52, + [2][0][RTW89_MKK][12] = 64, + [2][0][RTW89_IC][12] = 40, +- [2][0][RTW89_KCC][12] = 52, ++ [2][0][RTW89_KCC][12] = 70, + [2][0][RTW89_ACMA][12] = 52, +- [2][0][RTW89_CHILE][12] = 60, ++ [2][0][RTW89_CHILE][12] = 40, + [2][0][RTW89_UKRAINE][12] = 52, ++ [2][0][RTW89_MEXICO][12] = 40, ++ [2][0][RTW89_CN][12] = 52, ++ [2][0][RTW89_QATAR][12] = 52, + [2][0][RTW89_FCC][13] = 127, + [2][0][RTW89_ETSI][13] = 127, + [2][0][RTW89_MKK][13] = 127, +@@ -47160,110 +48408,152 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [2][0][RTW89_ACMA][13] = 127, + [2][0][RTW89_CHILE][13] = 127, + [2][0][RTW89_UKRAINE][13] = 127, ++ [2][0][RTW89_MEXICO][13] = 127, ++ [2][0][RTW89_CN][13] = 127, ++ [2][0][RTW89_QATAR][13] = 127, + [2][1][RTW89_FCC][0] = 68, + [2][1][RTW89_ETSI][0] = 40, + [2][1][RTW89_MKK][0] = 52, + [2][1][RTW89_IC][0] = 68, +- [2][1][RTW89_KCC][0] = 40, ++ [2][1][RTW89_KCC][0] = 56, + [2][1][RTW89_ACMA][0] = 40, + [2][1][RTW89_CHILE][0] = 48, + [2][1][RTW89_UKRAINE][0] = 40, ++ [2][1][RTW89_MEXICO][0] = 68, ++ [2][1][RTW89_CN][0] = 40, ++ [2][1][RTW89_QATAR][0] = 40, + [2][1][RTW89_FCC][1] = 68, + [2][1][RTW89_ETSI][1] = 40, + [2][1][RTW89_MKK][1] = 52, + [2][1][RTW89_IC][1] = 68, +- [2][1][RTW89_KCC][1] = 40, ++ [2][1][RTW89_KCC][1] = 56, + [2][1][RTW89_ACMA][1] = 40, + [2][1][RTW89_CHILE][1] = 48, + [2][1][RTW89_UKRAINE][1] = 40, ++ [2][1][RTW89_MEXICO][1] = 68, ++ [2][1][RTW89_CN][1] = 40, ++ [2][1][RTW89_QATAR][1] = 40, + [2][1][RTW89_FCC][2] = 72, + [2][1][RTW89_ETSI][2] = 40, + [2][1][RTW89_MKK][2] = 52, + [2][1][RTW89_IC][2] = 72, +- [2][1][RTW89_KCC][2] = 40, ++ [2][1][RTW89_KCC][2] = 56, + [2][1][RTW89_ACMA][2] = 40, + [2][1][RTW89_CHILE][2] = 48, + [2][1][RTW89_UKRAINE][2] = 40, ++ [2][1][RTW89_MEXICO][2] = 72, ++ [2][1][RTW89_CN][2] = 40, ++ [2][1][RTW89_QATAR][2] = 40, + [2][1][RTW89_FCC][3] = 76, + [2][1][RTW89_ETSI][3] = 40, + [2][1][RTW89_MKK][3] = 52, + [2][1][RTW89_IC][3] = 76, +- [2][1][RTW89_KCC][3] = 40, ++ [2][1][RTW89_KCC][3] = 56, + [2][1][RTW89_ACMA][3] = 40, + [2][1][RTW89_CHILE][3] = 48, + [2][1][RTW89_UKRAINE][3] = 40, ++ [2][1][RTW89_MEXICO][3] = 76, ++ [2][1][RTW89_CN][3] = 40, ++ [2][1][RTW89_QATAR][3] = 40, + [2][1][RTW89_FCC][4] = 78, + [2][1][RTW89_ETSI][4] = 40, + [2][1][RTW89_MKK][4] = 52, + [2][1][RTW89_IC][4] = 78, +- [2][1][RTW89_KCC][4] = 40, ++ [2][1][RTW89_KCC][4] = 56, + [2][1][RTW89_ACMA][4] = 40, + [2][1][RTW89_CHILE][4] = 48, + [2][1][RTW89_UKRAINE][4] = 40, ++ [2][1][RTW89_MEXICO][4] = 78, ++ [2][1][RTW89_CN][4] = 40, ++ [2][1][RTW89_QATAR][4] = 40, + [2][1][RTW89_FCC][5] = 78, + [2][1][RTW89_ETSI][5] = 40, + [2][1][RTW89_MKK][5] = 52, + [2][1][RTW89_IC][5] = 78, +- [2][1][RTW89_KCC][5] = 40, ++ [2][1][RTW89_KCC][5] = 56, + [2][1][RTW89_ACMA][5] = 40, + [2][1][RTW89_CHILE][5] = 48, + [2][1][RTW89_UKRAINE][5] = 40, ++ [2][1][RTW89_MEXICO][5] = 78, ++ [2][1][RTW89_CN][5] = 40, ++ [2][1][RTW89_QATAR][5] = 40, + [2][1][RTW89_FCC][6] = 78, + [2][1][RTW89_ETSI][6] = 40, + [2][1][RTW89_MKK][6] = 52, + [2][1][RTW89_IC][6] = 78, +- [2][1][RTW89_KCC][6] = 40, ++ [2][1][RTW89_KCC][6] = 56, + [2][1][RTW89_ACMA][6] = 40, + [2][1][RTW89_CHILE][6] = 48, + [2][1][RTW89_UKRAINE][6] = 40, ++ [2][1][RTW89_MEXICO][6] = 78, ++ [2][1][RTW89_CN][6] = 40, ++ [2][1][RTW89_QATAR][6] = 40, + [2][1][RTW89_FCC][7] = 78, + [2][1][RTW89_ETSI][7] = 40, + [2][1][RTW89_MKK][7] = 52, + [2][1][RTW89_IC][7] = 78, +- [2][1][RTW89_KCC][7] = 40, ++ [2][1][RTW89_KCC][7] = 56, + [2][1][RTW89_ACMA][7] = 40, + [2][1][RTW89_CHILE][7] = 48, + [2][1][RTW89_UKRAINE][7] = 40, ++ [2][1][RTW89_MEXICO][7] = 78, ++ [2][1][RTW89_CN][7] = 40, ++ [2][1][RTW89_QATAR][7] = 40, + [2][1][RTW89_FCC][8] = 74, + [2][1][RTW89_ETSI][8] = 40, + [2][1][RTW89_MKK][8] = 52, + [2][1][RTW89_IC][8] = 74, +- [2][1][RTW89_KCC][8] = 40, ++ [2][1][RTW89_KCC][8] = 56, + [2][1][RTW89_ACMA][8] = 40, + [2][1][RTW89_CHILE][8] = 48, + [2][1][RTW89_UKRAINE][8] = 40, ++ [2][1][RTW89_MEXICO][8] = 74, ++ [2][1][RTW89_CN][8] = 40, ++ [2][1][RTW89_QATAR][8] = 40, + [2][1][RTW89_FCC][9] = 70, + [2][1][RTW89_ETSI][9] = 40, + [2][1][RTW89_MKK][9] = 52, + [2][1][RTW89_IC][9] = 70, +- [2][1][RTW89_KCC][9] = 40, ++ [2][1][RTW89_KCC][9] = 56, + [2][1][RTW89_ACMA][9] = 40, + [2][1][RTW89_CHILE][9] = 48, + [2][1][RTW89_UKRAINE][9] = 40, ++ [2][1][RTW89_MEXICO][9] = 70, ++ [2][1][RTW89_CN][9] = 40, ++ [2][1][RTW89_QATAR][9] = 40, + [2][1][RTW89_FCC][10] = 70, + [2][1][RTW89_ETSI][10] = 40, + [2][1][RTW89_MKK][10] = 52, + [2][1][RTW89_IC][10] = 70, +- [2][1][RTW89_KCC][10] = 40, ++ [2][1][RTW89_KCC][10] = 56, + [2][1][RTW89_ACMA][10] = 40, + [2][1][RTW89_CHILE][10] = 48, + [2][1][RTW89_UKRAINE][10] = 40, ++ [2][1][RTW89_MEXICO][10] = 70, ++ [2][1][RTW89_CN][10] = 40, ++ [2][1][RTW89_QATAR][10] = 40, + [2][1][RTW89_FCC][11] = 48, + [2][1][RTW89_ETSI][11] = 40, + [2][1][RTW89_MKK][11] = 52, + [2][1][RTW89_IC][11] = 48, +- [2][1][RTW89_KCC][11] = 40, ++ [2][1][RTW89_KCC][11] = 56, + [2][1][RTW89_ACMA][11] = 40, + [2][1][RTW89_CHILE][11] = 48, + [2][1][RTW89_UKRAINE][11] = 40, ++ [2][1][RTW89_MEXICO][11] = 48, ++ [2][1][RTW89_CN][11] = 40, ++ [2][1][RTW89_QATAR][11] = 40, + [2][1][RTW89_FCC][12] = 26, + [2][1][RTW89_ETSI][12] = 40, + [2][1][RTW89_MKK][12] = 52, + [2][1][RTW89_IC][12] = 26, +- [2][1][RTW89_KCC][12] = 40, ++ [2][1][RTW89_KCC][12] = 56, + [2][1][RTW89_ACMA][12] = 40, +- [2][1][RTW89_CHILE][12] = 48, ++ [2][1][RTW89_CHILE][12] = 26, + [2][1][RTW89_UKRAINE][12] = 40, ++ [2][1][RTW89_MEXICO][12] = 26, ++ [2][1][RTW89_CN][12] = 40, ++ [2][1][RTW89_QATAR][12] = 40, + [2][1][RTW89_FCC][13] = 127, + [2][1][RTW89_ETSI][13] = 127, + [2][1][RTW89_MKK][13] = 127, +@@ -47272,6 +48562,9 @@ const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM] + [2][1][RTW89_ACMA][13] = 127, + [2][1][RTW89_CHILE][13] = 127, + [2][1][RTW89_UKRAINE][13] = 127, ++ [2][1][RTW89_MEXICO][13] = 127, ++ [2][1][RTW89_CN][13] = 127, ++ [2][1][RTW89_QATAR][13] = 127, + }; + + const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] +@@ -47279,7 +48572,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][0][RTW89_WW][0] = 22, + [0][0][RTW89_WW][2] = 22, + [0][0][RTW89_WW][4] = 22, +- [0][0][RTW89_WW][6] = 22, ++ [0][0][RTW89_WW][6] = 20, + [0][0][RTW89_WW][8] = 24, + [0][0][RTW89_WW][10] = 24, + [0][0][RTW89_WW][12] = 24, +@@ -47295,7 +48588,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][0][RTW89_WW][31] = 24, + [0][0][RTW89_WW][33] = 24, + [0][0][RTW89_WW][35] = 24, +- [0][0][RTW89_WW][37] = 24, ++ [0][0][RTW89_WW][37] = 44, + [0][0][RTW89_WW][38] = 28, + [0][0][RTW89_WW][40] = 28, + [0][0][RTW89_WW][42] = 28, +@@ -47304,7 +48597,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][1][RTW89_WW][0] = 8, + [0][1][RTW89_WW][2] = 8, + [0][1][RTW89_WW][4] = 8, +- [0][1][RTW89_WW][6] = 8, ++ [0][1][RTW89_WW][6] = 4, + [0][1][RTW89_WW][8] = 12, + [0][1][RTW89_WW][10] = 12, + [0][1][RTW89_WW][12] = 12, +@@ -47320,7 +48613,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][1][RTW89_WW][31] = 12, + [0][1][RTW89_WW][33] = 12, + [0][1][RTW89_WW][35] = 12, +- [0][1][RTW89_WW][37] = 12, ++ [0][1][RTW89_WW][37] = 32, + [0][1][RTW89_WW][38] = 16, + [0][1][RTW89_WW][40] = 16, + [0][1][RTW89_WW][42] = 16, +@@ -47345,7 +48638,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [1][0][RTW89_WW][31] = 36, + [1][0][RTW89_WW][33] = 36, + [1][0][RTW89_WW][35] = 36, +- [1][0][RTW89_WW][37] = 36, ++ [1][0][RTW89_WW][37] = 54, + [1][0][RTW89_WW][38] = 28, + [1][0][RTW89_WW][40] = 28, + [1][0][RTW89_WW][42] = 28, +@@ -47354,7 +48647,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [1][1][RTW89_WW][0] = 18, + [1][1][RTW89_WW][2] = 18, + [1][1][RTW89_WW][4] = 18, +- [1][1][RTW89_WW][6] = 18, ++ [1][1][RTW89_WW][6] = 16, + [1][1][RTW89_WW][8] = 22, + [1][1][RTW89_WW][10] = 22, + [1][1][RTW89_WW][12] = 22, +@@ -47370,7 +48663,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [1][1][RTW89_WW][31] = 22, + [1][1][RTW89_WW][33] = 22, + [1][1][RTW89_WW][35] = 22, +- [1][1][RTW89_WW][37] = 22, ++ [1][1][RTW89_WW][37] = 42, + [1][1][RTW89_WW][38] = 16, + [1][1][RTW89_WW][40] = 16, + [1][1][RTW89_WW][42] = 16, +@@ -47395,7 +48688,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [2][0][RTW89_WW][31] = 46, + [2][0][RTW89_WW][33] = 46, + [2][0][RTW89_WW][35] = 46, +- [2][0][RTW89_WW][37] = 46, ++ [2][0][RTW89_WW][37] = 54, + [2][0][RTW89_WW][38] = 28, + [2][0][RTW89_WW][40] = 28, + [2][0][RTW89_WW][42] = 28, +@@ -47420,7 +48713,7 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [2][1][RTW89_WW][31] = 32, + [2][1][RTW89_WW][33] = 32, + [2][1][RTW89_WW][35] = 32, +- [2][1][RTW89_WW][37] = 32, ++ [2][1][RTW89_WW][37] = 42, + [2][1][RTW89_WW][38] = 16, + [2][1][RTW89_WW][40] = 16, + [2][1][RTW89_WW][42] = 16, +@@ -47430,1202 +48723,1652 @@ const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM] + [0][0][RTW89_ETSI][0] = 24, + [0][0][RTW89_MKK][0] = 26, + [0][0][RTW89_IC][0] = 22, +- [0][0][RTW89_KCC][0] = 24, ++ [0][0][RTW89_KCC][0] = 46, + [0][0][RTW89_ACMA][0] = 24, + [0][0][RTW89_CHILE][0] = 30, + [0][0][RTW89_UKRAINE][0] = 24, ++ [0][0][RTW89_MEXICO][0] = 48, ++ [0][0][RTW89_CN][0] = 24, ++ [0][0][RTW89_QATAR][0] = 24, + [0][0][RTW89_FCC][2] = 48, + [0][0][RTW89_ETSI][2] = 24, + [0][0][RTW89_MKK][2] = 26, + [0][0][RTW89_IC][2] = 22, +- [0][0][RTW89_KCC][2] = 24, ++ [0][0][RTW89_KCC][2] = 46, + [0][0][RTW89_ACMA][2] = 24, + [0][0][RTW89_CHILE][2] = 30, + [0][0][RTW89_UKRAINE][2] = 24, ++ [0][0][RTW89_MEXICO][2] = 48, ++ [0][0][RTW89_CN][2] = 24, ++ [0][0][RTW89_QATAR][2] = 24, + [0][0][RTW89_FCC][4] = 48, + [0][0][RTW89_ETSI][4] = 24, + [0][0][RTW89_MKK][4] = 26, + [0][0][RTW89_IC][4] = 22, +- [0][0][RTW89_KCC][4] = 24, ++ [0][0][RTW89_KCC][4] = 46, + [0][0][RTW89_ACMA][4] = 24, + [0][0][RTW89_CHILE][4] = 30, + [0][0][RTW89_UKRAINE][4] = 24, ++ [0][0][RTW89_MEXICO][4] = 48, ++ [0][0][RTW89_CN][4] = 24, ++ [0][0][RTW89_QATAR][4] = 24, + [0][0][RTW89_FCC][6] = 48, + [0][0][RTW89_ETSI][6] = 24, + [0][0][RTW89_MKK][6] = 26, + [0][0][RTW89_IC][6] = 22, +- [0][0][RTW89_KCC][6] = 24, ++ [0][0][RTW89_KCC][6] = 20, + [0][0][RTW89_ACMA][6] = 24, + [0][0][RTW89_CHILE][6] = 30, + [0][0][RTW89_UKRAINE][6] = 24, ++ [0][0][RTW89_MEXICO][6] = 48, ++ [0][0][RTW89_CN][6] = 24, ++ [0][0][RTW89_QATAR][6] = 24, + [0][0][RTW89_FCC][8] = 48, + [0][0][RTW89_ETSI][8] = 24, + [0][0][RTW89_MKK][8] = 26, + [0][0][RTW89_IC][8] = 48, +- [0][0][RTW89_KCC][8] = 24, ++ [0][0][RTW89_KCC][8] = 46, + [0][0][RTW89_ACMA][8] = 24, +- [0][0][RTW89_CHILE][8] = 54, ++ [0][0][RTW89_CHILE][8] = 48, + [0][0][RTW89_UKRAINE][8] = 24, ++ [0][0][RTW89_MEXICO][8] = 48, ++ [0][0][RTW89_CN][8] = 24, ++ [0][0][RTW89_QATAR][8] = 24, + [0][0][RTW89_FCC][10] = 48, + [0][0][RTW89_ETSI][10] = 24, + [0][0][RTW89_MKK][10] = 26, + [0][0][RTW89_IC][10] = 48, +- [0][0][RTW89_KCC][10] = 24, ++ [0][0][RTW89_KCC][10] = 46, + [0][0][RTW89_ACMA][10] = 24, +- [0][0][RTW89_CHILE][10] = 54, ++ [0][0][RTW89_CHILE][10] = 48, + [0][0][RTW89_UKRAINE][10] = 24, ++ [0][0][RTW89_MEXICO][10] = 48, ++ [0][0][RTW89_CN][10] = 24, ++ [0][0][RTW89_QATAR][10] = 24, + [0][0][RTW89_FCC][12] = 48, + [0][0][RTW89_ETSI][12] = 24, + [0][0][RTW89_MKK][12] = 26, + [0][0][RTW89_IC][12] = 48, +- [0][0][RTW89_KCC][12] = 24, ++ [0][0][RTW89_KCC][12] = 46, + [0][0][RTW89_ACMA][12] = 24, +- [0][0][RTW89_CHILE][12] = 54, ++ [0][0][RTW89_CHILE][12] = 48, + [0][0][RTW89_UKRAINE][12] = 24, ++ [0][0][RTW89_MEXICO][12] = 48, ++ [0][0][RTW89_CN][12] = 24, ++ [0][0][RTW89_QATAR][12] = 24, + [0][0][RTW89_FCC][14] = 48, + [0][0][RTW89_ETSI][14] = 24, + [0][0][RTW89_MKK][14] = 26, + [0][0][RTW89_IC][14] = 48, +- [0][0][RTW89_KCC][14] = 24, ++ [0][0][RTW89_KCC][14] = 46, + [0][0][RTW89_ACMA][14] = 24, +- [0][0][RTW89_CHILE][14] = 54, ++ [0][0][RTW89_CHILE][14] = 48, + [0][0][RTW89_UKRAINE][14] = 24, ++ [0][0][RTW89_MEXICO][14] = 48, ++ [0][0][RTW89_CN][14] = 24, ++ [0][0][RTW89_QATAR][14] = 24, + [0][0][RTW89_FCC][15] = 48, + [0][0][RTW89_ETSI][15] = 24, + [0][0][RTW89_MKK][15] = 44, + [0][0][RTW89_IC][15] = 48, +- [0][0][RTW89_KCC][15] = 24, ++ [0][0][RTW89_KCC][15] = 46, + [0][0][RTW89_ACMA][15] = 24, +- [0][0][RTW89_CHILE][15] = 54, ++ [0][0][RTW89_CHILE][15] = 48, + [0][0][RTW89_UKRAINE][15] = 24, ++ [0][0][RTW89_MEXICO][15] = 48, ++ [0][0][RTW89_CN][15] = 127, ++ [0][0][RTW89_QATAR][15] = 24, + [0][0][RTW89_FCC][17] = 48, + [0][0][RTW89_ETSI][17] = 24, + [0][0][RTW89_MKK][17] = 44, + [0][0][RTW89_IC][17] = 48, +- [0][0][RTW89_KCC][17] = 24, ++ [0][0][RTW89_KCC][17] = 46, + [0][0][RTW89_ACMA][17] = 24, +- [0][0][RTW89_CHILE][17] = 54, ++ [0][0][RTW89_CHILE][17] = 48, + [0][0][RTW89_UKRAINE][17] = 24, ++ [0][0][RTW89_MEXICO][17] = 48, ++ [0][0][RTW89_CN][17] = 127, ++ [0][0][RTW89_QATAR][17] = 24, + [0][0][RTW89_FCC][19] = 48, + [0][0][RTW89_ETSI][19] = 24, + [0][0][RTW89_MKK][19] = 44, + [0][0][RTW89_IC][19] = 48, +- [0][0][RTW89_KCC][19] = 24, ++ [0][0][RTW89_KCC][19] = 46, + [0][0][RTW89_ACMA][19] = 24, +- [0][0][RTW89_CHILE][19] = 54, ++ [0][0][RTW89_CHILE][19] = 48, + [0][0][RTW89_UKRAINE][19] = 24, ++ [0][0][RTW89_MEXICO][19] = 48, ++ [0][0][RTW89_CN][19] = 127, ++ [0][0][RTW89_QATAR][19] = 24, + [0][0][RTW89_FCC][21] = 48, + [0][0][RTW89_ETSI][21] = 24, + [0][0][RTW89_MKK][21] = 44, + [0][0][RTW89_IC][21] = 48, +- [0][0][RTW89_KCC][21] = 24, ++ [0][0][RTW89_KCC][21] = 46, + [0][0][RTW89_ACMA][21] = 24, +- [0][0][RTW89_CHILE][21] = 54, ++ [0][0][RTW89_CHILE][21] = 48, + [0][0][RTW89_UKRAINE][21] = 24, ++ [0][0][RTW89_MEXICO][21] = 48, ++ [0][0][RTW89_CN][21] = 127, ++ [0][0][RTW89_QATAR][21] = 24, + [0][0][RTW89_FCC][23] = 48, + [0][0][RTW89_ETSI][23] = 24, + [0][0][RTW89_MKK][23] = 44, + [0][0][RTW89_IC][23] = 48, +- [0][0][RTW89_KCC][23] = 24, ++ [0][0][RTW89_KCC][23] = 46, + [0][0][RTW89_ACMA][23] = 24, +- [0][0][RTW89_CHILE][23] = 54, ++ [0][0][RTW89_CHILE][23] = 48, + [0][0][RTW89_UKRAINE][23] = 24, ++ [0][0][RTW89_MEXICO][23] = 48, ++ [0][0][RTW89_CN][23] = 127, ++ [0][0][RTW89_QATAR][23] = 24, + [0][0][RTW89_FCC][25] = 48, + [0][0][RTW89_ETSI][25] = 24, + [0][0][RTW89_MKK][25] = 44, + [0][0][RTW89_IC][25] = 127, +- [0][0][RTW89_KCC][25] = 24, ++ [0][0][RTW89_KCC][25] = 46, + [0][0][RTW89_ACMA][25] = 127, +- [0][0][RTW89_CHILE][25] = 54, ++ [0][0][RTW89_CHILE][25] = 48, + [0][0][RTW89_UKRAINE][25] = 24, ++ [0][0][RTW89_MEXICO][25] = 48, ++ [0][0][RTW89_CN][25] = 127, ++ [0][0][RTW89_QATAR][25] = 24, + [0][0][RTW89_FCC][27] = 48, + [0][0][RTW89_ETSI][27] = 24, + [0][0][RTW89_MKK][27] = 44, + [0][0][RTW89_IC][27] = 127, +- [0][0][RTW89_KCC][27] = 24, ++ [0][0][RTW89_KCC][27] = 46, + [0][0][RTW89_ACMA][27] = 127, +- [0][0][RTW89_CHILE][27] = 54, ++ [0][0][RTW89_CHILE][27] = 48, + [0][0][RTW89_UKRAINE][27] = 24, ++ [0][0][RTW89_MEXICO][27] = 48, ++ [0][0][RTW89_CN][27] = 127, ++ [0][0][RTW89_QATAR][27] = 24, + [0][0][RTW89_FCC][29] = 48, + [0][0][RTW89_ETSI][29] = 24, + [0][0][RTW89_MKK][29] = 44, + [0][0][RTW89_IC][29] = 127, +- [0][0][RTW89_KCC][29] = 24, ++ [0][0][RTW89_KCC][29] = 46, + [0][0][RTW89_ACMA][29] = 127, +- [0][0][RTW89_CHILE][29] = 54, ++ [0][0][RTW89_CHILE][29] = 48, + [0][0][RTW89_UKRAINE][29] = 24, ++ [0][0][RTW89_MEXICO][29] = 48, ++ [0][0][RTW89_CN][29] = 127, ++ [0][0][RTW89_QATAR][29] = 24, + [0][0][RTW89_FCC][31] = 48, + [0][0][RTW89_ETSI][31] = 24, + [0][0][RTW89_MKK][31] = 44, + [0][0][RTW89_IC][31] = 48, +- [0][0][RTW89_KCC][31] = 24, ++ [0][0][RTW89_KCC][31] = 46, + [0][0][RTW89_ACMA][31] = 24, +- [0][0][RTW89_CHILE][31] = 54, ++ [0][0][RTW89_CHILE][31] = 48, + [0][0][RTW89_UKRAINE][31] = 24, ++ [0][0][RTW89_MEXICO][31] = 48, ++ [0][0][RTW89_CN][31] = 127, ++ [0][0][RTW89_QATAR][31] = 24, + [0][0][RTW89_FCC][33] = 48, + [0][0][RTW89_ETSI][33] = 24, + [0][0][RTW89_MKK][33] = 44, + [0][0][RTW89_IC][33] = 48, +- [0][0][RTW89_KCC][33] = 24, ++ [0][0][RTW89_KCC][33] = 46, + [0][0][RTW89_ACMA][33] = 24, +- [0][0][RTW89_CHILE][33] = 54, ++ [0][0][RTW89_CHILE][33] = 48, + [0][0][RTW89_UKRAINE][33] = 24, ++ [0][0][RTW89_MEXICO][33] = 48, ++ [0][0][RTW89_CN][33] = 127, ++ [0][0][RTW89_QATAR][33] = 24, + [0][0][RTW89_FCC][35] = 48, + [0][0][RTW89_ETSI][35] = 24, + [0][0][RTW89_MKK][35] = 44, + [0][0][RTW89_IC][35] = 48, +- [0][0][RTW89_KCC][35] = 24, ++ [0][0][RTW89_KCC][35] = 46, + [0][0][RTW89_ACMA][35] = 24, +- [0][0][RTW89_CHILE][35] = 54, ++ [0][0][RTW89_CHILE][35] = 48, + [0][0][RTW89_UKRAINE][35] = 24, ++ [0][0][RTW89_MEXICO][35] = 48, ++ [0][0][RTW89_CN][35] = 127, ++ [0][0][RTW89_QATAR][35] = 24, + [0][0][RTW89_FCC][37] = 48, + [0][0][RTW89_ETSI][37] = 127, + [0][0][RTW89_MKK][37] = 44, + [0][0][RTW89_IC][37] = 48, +- [0][0][RTW89_KCC][37] = 24, ++ [0][0][RTW89_KCC][37] = 46, + [0][0][RTW89_ACMA][37] = 48, +- [0][0][RTW89_CHILE][37] = 54, ++ [0][0][RTW89_CHILE][37] = 48, + [0][0][RTW89_UKRAINE][37] = 127, ++ [0][0][RTW89_MEXICO][37] = 48, ++ [0][0][RTW89_CN][37] = 127, ++ [0][0][RTW89_QATAR][37] = 127, + [0][0][RTW89_FCC][38] = 76, + [0][0][RTW89_ETSI][38] = 28, + [0][0][RTW89_MKK][38] = 127, + [0][0][RTW89_IC][38] = 76, +- [0][0][RTW89_KCC][38] = 28, ++ [0][0][RTW89_KCC][38] = 46, + [0][0][RTW89_ACMA][38] = 76, + [0][0][RTW89_CHILE][38] = 54, + [0][0][RTW89_UKRAINE][38] = 28, ++ [0][0][RTW89_MEXICO][38] = 76, ++ [0][0][RTW89_CN][38] = 62, ++ [0][0][RTW89_QATAR][38] = 28, + [0][0][RTW89_FCC][40] = 76, + [0][0][RTW89_ETSI][40] = 28, + [0][0][RTW89_MKK][40] = 127, + [0][0][RTW89_IC][40] = 76, +- [0][0][RTW89_KCC][40] = 28, ++ [0][0][RTW89_KCC][40] = 46, + [0][0][RTW89_ACMA][40] = 76, + [0][0][RTW89_CHILE][40] = 54, + [0][0][RTW89_UKRAINE][40] = 28, ++ [0][0][RTW89_MEXICO][40] = 76, ++ [0][0][RTW89_CN][40] = 62, ++ [0][0][RTW89_QATAR][40] = 28, + [0][0][RTW89_FCC][42] = 76, + [0][0][RTW89_ETSI][42] = 28, + [0][0][RTW89_MKK][42] = 127, + [0][0][RTW89_IC][42] = 76, +- [0][0][RTW89_KCC][42] = 28, ++ [0][0][RTW89_KCC][42] = 46, + [0][0][RTW89_ACMA][42] = 76, + [0][0][RTW89_CHILE][42] = 54, + [0][0][RTW89_UKRAINE][42] = 28, ++ [0][0][RTW89_MEXICO][42] = 76, ++ [0][0][RTW89_CN][42] = 62, ++ [0][0][RTW89_QATAR][42] = 28, + [0][0][RTW89_FCC][44] = 76, + [0][0][RTW89_ETSI][44] = 28, + [0][0][RTW89_MKK][44] = 127, + [0][0][RTW89_IC][44] = 76, +- [0][0][RTW89_KCC][44] = 28, ++ [0][0][RTW89_KCC][44] = 46, + [0][0][RTW89_ACMA][44] = 76, + [0][0][RTW89_CHILE][44] = 54, + [0][0][RTW89_UKRAINE][44] = 28, ++ [0][0][RTW89_MEXICO][44] = 76, ++ [0][0][RTW89_CN][44] = 62, ++ [0][0][RTW89_QATAR][44] = 28, + [0][0][RTW89_FCC][46] = 76, + [0][0][RTW89_ETSI][46] = 28, + [0][0][RTW89_MKK][46] = 127, + [0][0][RTW89_IC][46] = 76, +- [0][0][RTW89_KCC][46] = 28, ++ [0][0][RTW89_KCC][46] = 46, + [0][0][RTW89_ACMA][46] = 76, + [0][0][RTW89_CHILE][46] = 54, + [0][0][RTW89_UKRAINE][46] = 28, ++ [0][0][RTW89_MEXICO][46] = 76, ++ [0][0][RTW89_CN][46] = 62, ++ [0][0][RTW89_QATAR][46] = 28, + [0][1][RTW89_FCC][0] = 36, + [0][1][RTW89_ETSI][0] = 12, + [0][1][RTW89_MKK][0] = 14, + [0][1][RTW89_IC][0] = 8, +- [0][1][RTW89_KCC][0] = 12, ++ [0][1][RTW89_KCC][0] = 32, + [0][1][RTW89_ACMA][0] = 12, + [0][1][RTW89_CHILE][0] = 18, + [0][1][RTW89_UKRAINE][0] = 12, ++ [0][1][RTW89_MEXICO][0] = 36, ++ [0][1][RTW89_CN][0] = 12, ++ [0][1][RTW89_QATAR][0] = 12, + [0][1][RTW89_FCC][2] = 36, + [0][1][RTW89_ETSI][2] = 12, + [0][1][RTW89_MKK][2] = 14, + [0][1][RTW89_IC][2] = 8, +- [0][1][RTW89_KCC][2] = 12, ++ [0][1][RTW89_KCC][2] = 32, + [0][1][RTW89_ACMA][2] = 12, + [0][1][RTW89_CHILE][2] = 18, + [0][1][RTW89_UKRAINE][2] = 12, ++ [0][1][RTW89_MEXICO][2] = 36, ++ [0][1][RTW89_CN][2] = 12, ++ [0][1][RTW89_QATAR][2] = 12, + [0][1][RTW89_FCC][4] = 36, + [0][1][RTW89_ETSI][4] = 12, + [0][1][RTW89_MKK][4] = 14, + [0][1][RTW89_IC][4] = 8, +- [0][1][RTW89_KCC][4] = 12, ++ [0][1][RTW89_KCC][4] = 32, + [0][1][RTW89_ACMA][4] = 12, + [0][1][RTW89_CHILE][4] = 18, + [0][1][RTW89_UKRAINE][4] = 12, ++ [0][1][RTW89_MEXICO][4] = 36, ++ [0][1][RTW89_CN][4] = 12, ++ [0][1][RTW89_QATAR][4] = 12, + [0][1][RTW89_FCC][6] = 36, + [0][1][RTW89_ETSI][6] = 12, + [0][1][RTW89_MKK][6] = 14, + [0][1][RTW89_IC][6] = 8, +- [0][1][RTW89_KCC][6] = 12, ++ [0][1][RTW89_KCC][6] = 4, + [0][1][RTW89_ACMA][6] = 12, + [0][1][RTW89_CHILE][6] = 18, + [0][1][RTW89_UKRAINE][6] = 12, ++ [0][1][RTW89_MEXICO][6] = 36, ++ [0][1][RTW89_CN][6] = 12, ++ [0][1][RTW89_QATAR][6] = 12, + [0][1][RTW89_FCC][8] = 36, + [0][1][RTW89_ETSI][8] = 12, + [0][1][RTW89_MKK][8] = 14, + [0][1][RTW89_IC][8] = 36, +- [0][1][RTW89_KCC][8] = 12, ++ [0][1][RTW89_KCC][8] = 32, + [0][1][RTW89_ACMA][8] = 12, +- [0][1][RTW89_CHILE][8] = 42, ++ [0][1][RTW89_CHILE][8] = 36, + [0][1][RTW89_UKRAINE][8] = 12, ++ [0][1][RTW89_MEXICO][8] = 36, ++ [0][1][RTW89_CN][8] = 12, ++ [0][1][RTW89_QATAR][8] = 12, + [0][1][RTW89_FCC][10] = 36, + [0][1][RTW89_ETSI][10] = 12, + [0][1][RTW89_MKK][10] = 14, + [0][1][RTW89_IC][10] = 36, +- [0][1][RTW89_KCC][10] = 12, ++ [0][1][RTW89_KCC][10] = 32, + [0][1][RTW89_ACMA][10] = 12, +- [0][1][RTW89_CHILE][10] = 42, ++ [0][1][RTW89_CHILE][10] = 36, + [0][1][RTW89_UKRAINE][10] = 12, ++ [0][1][RTW89_MEXICO][10] = 36, ++ [0][1][RTW89_CN][10] = 12, ++ [0][1][RTW89_QATAR][10] = 12, + [0][1][RTW89_FCC][12] = 36, + [0][1][RTW89_ETSI][12] = 12, + [0][1][RTW89_MKK][12] = 14, + [0][1][RTW89_IC][12] = 36, +- [0][1][RTW89_KCC][12] = 12, ++ [0][1][RTW89_KCC][12] = 32, + [0][1][RTW89_ACMA][12] = 12, +- [0][1][RTW89_CHILE][12] = 42, ++ [0][1][RTW89_CHILE][12] = 36, + [0][1][RTW89_UKRAINE][12] = 12, ++ [0][1][RTW89_MEXICO][12] = 36, ++ [0][1][RTW89_CN][12] = 12, ++ [0][1][RTW89_QATAR][12] = 12, + [0][1][RTW89_FCC][14] = 36, + [0][1][RTW89_ETSI][14] = 12, + [0][1][RTW89_MKK][14] = 14, + [0][1][RTW89_IC][14] = 36, +- [0][1][RTW89_KCC][14] = 12, ++ [0][1][RTW89_KCC][14] = 32, + [0][1][RTW89_ACMA][14] = 12, +- [0][1][RTW89_CHILE][14] = 42, ++ [0][1][RTW89_CHILE][14] = 36, + [0][1][RTW89_UKRAINE][14] = 12, ++ [0][1][RTW89_MEXICO][14] = 36, ++ [0][1][RTW89_CN][14] = 12, ++ [0][1][RTW89_QATAR][14] = 12, + [0][1][RTW89_FCC][15] = 36, + [0][1][RTW89_ETSI][15] = 12, + [0][1][RTW89_MKK][15] = 32, + [0][1][RTW89_IC][15] = 36, +- [0][1][RTW89_KCC][15] = 12, ++ [0][1][RTW89_KCC][15] = 32, + [0][1][RTW89_ACMA][15] = 12, +- [0][1][RTW89_CHILE][15] = 42, ++ [0][1][RTW89_CHILE][15] = 36, + [0][1][RTW89_UKRAINE][15] = 12, ++ [0][1][RTW89_MEXICO][15] = 36, ++ [0][1][RTW89_CN][15] = 127, ++ [0][1][RTW89_QATAR][15] = 12, + [0][1][RTW89_FCC][17] = 36, + [0][1][RTW89_ETSI][17] = 12, + [0][1][RTW89_MKK][17] = 32, + [0][1][RTW89_IC][17] = 36, +- [0][1][RTW89_KCC][17] = 12, ++ [0][1][RTW89_KCC][17] = 32, + [0][1][RTW89_ACMA][17] = 12, +- [0][1][RTW89_CHILE][17] = 42, ++ [0][1][RTW89_CHILE][17] = 36, + [0][1][RTW89_UKRAINE][17] = 12, ++ [0][1][RTW89_MEXICO][17] = 36, ++ [0][1][RTW89_CN][17] = 127, ++ [0][1][RTW89_QATAR][17] = 12, + [0][1][RTW89_FCC][19] = 36, + [0][1][RTW89_ETSI][19] = 12, + [0][1][RTW89_MKK][19] = 32, + [0][1][RTW89_IC][19] = 36, +- [0][1][RTW89_KCC][19] = 12, ++ [0][1][RTW89_KCC][19] = 32, + [0][1][RTW89_ACMA][19] = 12, +- [0][1][RTW89_CHILE][19] = 42, ++ [0][1][RTW89_CHILE][19] = 36, + [0][1][RTW89_UKRAINE][19] = 12, ++ [0][1][RTW89_MEXICO][19] = 36, ++ [0][1][RTW89_CN][19] = 127, ++ [0][1][RTW89_QATAR][19] = 12, + [0][1][RTW89_FCC][21] = 36, + [0][1][RTW89_ETSI][21] = 12, + [0][1][RTW89_MKK][21] = 32, + [0][1][RTW89_IC][21] = 36, +- [0][1][RTW89_KCC][21] = 12, ++ [0][1][RTW89_KCC][21] = 32, + [0][1][RTW89_ACMA][21] = 12, +- [0][1][RTW89_CHILE][21] = 42, ++ [0][1][RTW89_CHILE][21] = 36, + [0][1][RTW89_UKRAINE][21] = 12, ++ [0][1][RTW89_MEXICO][21] = 36, ++ [0][1][RTW89_CN][21] = 127, ++ [0][1][RTW89_QATAR][21] = 12, + [0][1][RTW89_FCC][23] = 36, + [0][1][RTW89_ETSI][23] = 12, + [0][1][RTW89_MKK][23] = 32, + [0][1][RTW89_IC][23] = 36, +- [0][1][RTW89_KCC][23] = 12, ++ [0][1][RTW89_KCC][23] = 32, + [0][1][RTW89_ACMA][23] = 12, +- [0][1][RTW89_CHILE][23] = 42, ++ [0][1][RTW89_CHILE][23] = 36, + [0][1][RTW89_UKRAINE][23] = 12, ++ [0][1][RTW89_MEXICO][23] = 36, ++ [0][1][RTW89_CN][23] = 127, ++ [0][1][RTW89_QATAR][23] = 12, + [0][1][RTW89_FCC][25] = 36, + [0][1][RTW89_ETSI][25] = 12, + [0][1][RTW89_MKK][25] = 32, + [0][1][RTW89_IC][25] = 127, +- [0][1][RTW89_KCC][25] = 12, ++ [0][1][RTW89_KCC][25] = 32, + [0][1][RTW89_ACMA][25] = 127, +- [0][1][RTW89_CHILE][25] = 42, ++ [0][1][RTW89_CHILE][25] = 36, + [0][1][RTW89_UKRAINE][25] = 12, ++ [0][1][RTW89_MEXICO][25] = 36, ++ [0][1][RTW89_CN][25] = 127, ++ [0][1][RTW89_QATAR][25] = 12, + [0][1][RTW89_FCC][27] = 36, + [0][1][RTW89_ETSI][27] = 12, + [0][1][RTW89_MKK][27] = 32, + [0][1][RTW89_IC][27] = 127, +- [0][1][RTW89_KCC][27] = 12, ++ [0][1][RTW89_KCC][27] = 32, + [0][1][RTW89_ACMA][27] = 127, +- [0][1][RTW89_CHILE][27] = 42, ++ [0][1][RTW89_CHILE][27] = 36, + [0][1][RTW89_UKRAINE][27] = 12, ++ [0][1][RTW89_MEXICO][27] = 36, ++ [0][1][RTW89_CN][27] = 127, ++ [0][1][RTW89_QATAR][27] = 12, + [0][1][RTW89_FCC][29] = 36, + [0][1][RTW89_ETSI][29] = 12, + [0][1][RTW89_MKK][29] = 32, + [0][1][RTW89_IC][29] = 127, +- [0][1][RTW89_KCC][29] = 12, ++ [0][1][RTW89_KCC][29] = 32, + [0][1][RTW89_ACMA][29] = 127, +- [0][1][RTW89_CHILE][29] = 42, ++ [0][1][RTW89_CHILE][29] = 36, + [0][1][RTW89_UKRAINE][29] = 12, ++ [0][1][RTW89_MEXICO][29] = 36, ++ [0][1][RTW89_CN][29] = 127, ++ [0][1][RTW89_QATAR][29] = 12, + [0][1][RTW89_FCC][31] = 36, + [0][1][RTW89_ETSI][31] = 12, + [0][1][RTW89_MKK][31] = 32, + [0][1][RTW89_IC][31] = 36, +- [0][1][RTW89_KCC][31] = 12, ++ [0][1][RTW89_KCC][31] = 32, + [0][1][RTW89_ACMA][31] = 12, +- [0][1][RTW89_CHILE][31] = 42, ++ [0][1][RTW89_CHILE][31] = 36, + [0][1][RTW89_UKRAINE][31] = 12, ++ [0][1][RTW89_MEXICO][31] = 36, ++ [0][1][RTW89_CN][31] = 127, ++ [0][1][RTW89_QATAR][31] = 12, + [0][1][RTW89_FCC][33] = 36, + [0][1][RTW89_ETSI][33] = 12, + [0][1][RTW89_MKK][33] = 32, + [0][1][RTW89_IC][33] = 36, +- [0][1][RTW89_KCC][33] = 12, ++ [0][1][RTW89_KCC][33] = 32, + [0][1][RTW89_ACMA][33] = 12, +- [0][1][RTW89_CHILE][33] = 42, ++ [0][1][RTW89_CHILE][33] = 36, + [0][1][RTW89_UKRAINE][33] = 12, ++ [0][1][RTW89_MEXICO][33] = 36, ++ [0][1][RTW89_CN][33] = 127, ++ [0][1][RTW89_QATAR][33] = 12, + [0][1][RTW89_FCC][35] = 36, + [0][1][RTW89_ETSI][35] = 12, + [0][1][RTW89_MKK][35] = 32, + [0][1][RTW89_IC][35] = 36, +- [0][1][RTW89_KCC][35] = 12, ++ [0][1][RTW89_KCC][35] = 32, + [0][1][RTW89_ACMA][35] = 12, +- [0][1][RTW89_CHILE][35] = 42, ++ [0][1][RTW89_CHILE][35] = 36, + [0][1][RTW89_UKRAINE][35] = 12, ++ [0][1][RTW89_MEXICO][35] = 36, ++ [0][1][RTW89_CN][35] = 127, ++ [0][1][RTW89_QATAR][35] = 12, + [0][1][RTW89_FCC][37] = 36, + [0][1][RTW89_ETSI][37] = 127, + [0][1][RTW89_MKK][37] = 32, + [0][1][RTW89_IC][37] = 36, +- [0][1][RTW89_KCC][37] = 12, ++ [0][1][RTW89_KCC][37] = 32, + [0][1][RTW89_ACMA][37] = 36, +- [0][1][RTW89_CHILE][37] = 42, ++ [0][1][RTW89_CHILE][37] = 36, + [0][1][RTW89_UKRAINE][37] = 127, ++ [0][1][RTW89_MEXICO][37] = 36, ++ [0][1][RTW89_CN][37] = 127, ++ [0][1][RTW89_QATAR][37] = 127, + [0][1][RTW89_FCC][38] = 72, + [0][1][RTW89_ETSI][38] = 16, + [0][1][RTW89_MKK][38] = 127, + [0][1][RTW89_IC][38] = 72, +- [0][1][RTW89_KCC][38] = 16, ++ [0][1][RTW89_KCC][38] = 32, + [0][1][RTW89_ACMA][38] = 76, + [0][1][RTW89_CHILE][38] = 42, + [0][1][RTW89_UKRAINE][38] = 16, ++ [0][1][RTW89_MEXICO][38] = 72, ++ [0][1][RTW89_CN][38] = 50, ++ [0][1][RTW89_QATAR][38] = 16, + [0][1][RTW89_FCC][40] = 76, + [0][1][RTW89_ETSI][40] = 16, + [0][1][RTW89_MKK][40] = 127, + [0][1][RTW89_IC][40] = 76, +- [0][1][RTW89_KCC][40] = 16, ++ [0][1][RTW89_KCC][40] = 32, + [0][1][RTW89_ACMA][40] = 76, + [0][1][RTW89_CHILE][40] = 42, + [0][1][RTW89_UKRAINE][40] = 16, ++ [0][1][RTW89_MEXICO][40] = 76, ++ [0][1][RTW89_CN][40] = 50, ++ [0][1][RTW89_QATAR][40] = 16, + [0][1][RTW89_FCC][42] = 76, + [0][1][RTW89_ETSI][42] = 16, + [0][1][RTW89_MKK][42] = 127, + [0][1][RTW89_IC][42] = 76, +- [0][1][RTW89_KCC][42] = 16, ++ [0][1][RTW89_KCC][42] = 32, + [0][1][RTW89_ACMA][42] = 76, + [0][1][RTW89_CHILE][42] = 42, + [0][1][RTW89_UKRAINE][42] = 16, ++ [0][1][RTW89_MEXICO][42] = 76, ++ [0][1][RTW89_CN][42] = 50, ++ [0][1][RTW89_QATAR][42] = 16, + [0][1][RTW89_FCC][44] = 76, + [0][1][RTW89_ETSI][44] = 16, + [0][1][RTW89_MKK][44] = 127, + [0][1][RTW89_IC][44] = 76, +- [0][1][RTW89_KCC][44] = 16, ++ [0][1][RTW89_KCC][44] = 32, + [0][1][RTW89_ACMA][44] = 76, + [0][1][RTW89_CHILE][44] = 42, + [0][1][RTW89_UKRAINE][44] = 16, ++ [0][1][RTW89_MEXICO][44] = 76, ++ [0][1][RTW89_CN][44] = 50, ++ [0][1][RTW89_QATAR][44] = 16, + [0][1][RTW89_FCC][46] = 76, + [0][1][RTW89_ETSI][46] = 16, + [0][1][RTW89_MKK][46] = 127, + [0][1][RTW89_IC][46] = 76, +- [0][1][RTW89_KCC][46] = 16, ++ [0][1][RTW89_KCC][46] = 32, + [0][1][RTW89_ACMA][46] = 76, + [0][1][RTW89_CHILE][46] = 42, + [0][1][RTW89_UKRAINE][46] = 16, ++ [0][1][RTW89_MEXICO][46] = 76, ++ [0][1][RTW89_CN][46] = 50, ++ [0][1][RTW89_QATAR][46] = 16, + [1][0][RTW89_FCC][0] = 62, + [1][0][RTW89_ETSI][0] = 36, + [1][0][RTW89_MKK][0] = 36, + [1][0][RTW89_IC][0] = 34, +- [1][0][RTW89_KCC][0] = 36, ++ [1][0][RTW89_KCC][0] = 58, + [1][0][RTW89_ACMA][0] = 36, + [1][0][RTW89_CHILE][0] = 30, + [1][0][RTW89_UKRAINE][0] = 36, ++ [1][0][RTW89_MEXICO][0] = 62, ++ [1][0][RTW89_CN][0] = 36, ++ [1][0][RTW89_QATAR][0] = 36, + [1][0][RTW89_FCC][2] = 62, + [1][0][RTW89_ETSI][2] = 36, + [1][0][RTW89_MKK][2] = 36, + [1][0][RTW89_IC][2] = 34, +- [1][0][RTW89_KCC][2] = 36, ++ [1][0][RTW89_KCC][2] = 58, + [1][0][RTW89_ACMA][2] = 36, + [1][0][RTW89_CHILE][2] = 30, + [1][0][RTW89_UKRAINE][2] = 36, ++ [1][0][RTW89_MEXICO][2] = 62, ++ [1][0][RTW89_CN][2] = 36, ++ [1][0][RTW89_QATAR][2] = 36, + [1][0][RTW89_FCC][4] = 62, + [1][0][RTW89_ETSI][4] = 36, + [1][0][RTW89_MKK][4] = 36, + [1][0][RTW89_IC][4] = 34, +- [1][0][RTW89_KCC][4] = 36, ++ [1][0][RTW89_KCC][4] = 58, + [1][0][RTW89_ACMA][4] = 36, + [1][0][RTW89_CHILE][4] = 30, + [1][0][RTW89_UKRAINE][4] = 36, ++ [1][0][RTW89_MEXICO][4] = 62, ++ [1][0][RTW89_CN][4] = 36, ++ [1][0][RTW89_QATAR][4] = 36, + [1][0][RTW89_FCC][6] = 62, + [1][0][RTW89_ETSI][6] = 36, + [1][0][RTW89_MKK][6] = 36, + [1][0][RTW89_IC][6] = 34, +- [1][0][RTW89_KCC][6] = 36, ++ [1][0][RTW89_KCC][6] = 32, + [1][0][RTW89_ACMA][6] = 36, + [1][0][RTW89_CHILE][6] = 30, + [1][0][RTW89_UKRAINE][6] = 36, ++ [1][0][RTW89_MEXICO][6] = 62, ++ [1][0][RTW89_CN][6] = 36, ++ [1][0][RTW89_QATAR][6] = 36, + [1][0][RTW89_FCC][8] = 62, + [1][0][RTW89_ETSI][8] = 36, + [1][0][RTW89_MKK][8] = 36, + [1][0][RTW89_IC][8] = 62, +- [1][0][RTW89_KCC][8] = 36, ++ [1][0][RTW89_KCC][8] = 58, + [1][0][RTW89_ACMA][8] = 36, + [1][0][RTW89_CHILE][8] = 54, + [1][0][RTW89_UKRAINE][8] = 36, ++ [1][0][RTW89_MEXICO][8] = 62, ++ [1][0][RTW89_CN][8] = 36, ++ [1][0][RTW89_QATAR][8] = 36, + [1][0][RTW89_FCC][10] = 62, + [1][0][RTW89_ETSI][10] = 36, + [1][0][RTW89_MKK][10] = 36, + [1][0][RTW89_IC][10] = 62, +- [1][0][RTW89_KCC][10] = 36, ++ [1][0][RTW89_KCC][10] = 58, + [1][0][RTW89_ACMA][10] = 36, + [1][0][RTW89_CHILE][10] = 54, + [1][0][RTW89_UKRAINE][10] = 36, ++ [1][0][RTW89_MEXICO][10] = 62, ++ [1][0][RTW89_CN][10] = 36, ++ [1][0][RTW89_QATAR][10] = 36, + [1][0][RTW89_FCC][12] = 62, + [1][0][RTW89_ETSI][12] = 36, + [1][0][RTW89_MKK][12] = 36, + [1][0][RTW89_IC][12] = 62, +- [1][0][RTW89_KCC][12] = 36, ++ [1][0][RTW89_KCC][12] = 58, + [1][0][RTW89_ACMA][12] = 36, + [1][0][RTW89_CHILE][12] = 54, + [1][0][RTW89_UKRAINE][12] = 36, ++ [1][0][RTW89_MEXICO][12] = 62, ++ [1][0][RTW89_CN][12] = 36, ++ [1][0][RTW89_QATAR][12] = 36, + [1][0][RTW89_FCC][14] = 62, + [1][0][RTW89_ETSI][14] = 36, + [1][0][RTW89_MKK][14] = 36, + [1][0][RTW89_IC][14] = 62, +- [1][0][RTW89_KCC][14] = 36, ++ [1][0][RTW89_KCC][14] = 58, + [1][0][RTW89_ACMA][14] = 36, + [1][0][RTW89_CHILE][14] = 54, + [1][0][RTW89_UKRAINE][14] = 36, ++ [1][0][RTW89_MEXICO][14] = 62, ++ [1][0][RTW89_CN][14] = 36, ++ [1][0][RTW89_QATAR][14] = 36, + [1][0][RTW89_FCC][15] = 62, + [1][0][RTW89_ETSI][15] = 36, + [1][0][RTW89_MKK][15] = 58, + [1][0][RTW89_IC][15] = 62, +- [1][0][RTW89_KCC][15] = 36, ++ [1][0][RTW89_KCC][15] = 58, + [1][0][RTW89_ACMA][15] = 36, + [1][0][RTW89_CHILE][15] = 54, + [1][0][RTW89_UKRAINE][15] = 36, ++ [1][0][RTW89_MEXICO][15] = 62, ++ [1][0][RTW89_CN][15] = 127, ++ [1][0][RTW89_QATAR][15] = 36, + [1][0][RTW89_FCC][17] = 62, + [1][0][RTW89_ETSI][17] = 36, + [1][0][RTW89_MKK][17] = 58, + [1][0][RTW89_IC][17] = 62, +- [1][0][RTW89_KCC][17] = 36, ++ [1][0][RTW89_KCC][17] = 58, + [1][0][RTW89_ACMA][17] = 36, + [1][0][RTW89_CHILE][17] = 54, + [1][0][RTW89_UKRAINE][17] = 36, ++ [1][0][RTW89_MEXICO][17] = 62, ++ [1][0][RTW89_CN][17] = 127, ++ [1][0][RTW89_QATAR][17] = 36, + [1][0][RTW89_FCC][19] = 62, + [1][0][RTW89_ETSI][19] = 36, + [1][0][RTW89_MKK][19] = 58, + [1][0][RTW89_IC][19] = 62, +- [1][0][RTW89_KCC][19] = 36, ++ [1][0][RTW89_KCC][19] = 58, + [1][0][RTW89_ACMA][19] = 36, + [1][0][RTW89_CHILE][19] = 54, + [1][0][RTW89_UKRAINE][19] = 36, ++ [1][0][RTW89_MEXICO][19] = 62, ++ [1][0][RTW89_CN][19] = 127, ++ [1][0][RTW89_QATAR][19] = 36, + [1][0][RTW89_FCC][21] = 62, + [1][0][RTW89_ETSI][21] = 36, + [1][0][RTW89_MKK][21] = 58, + [1][0][RTW89_IC][21] = 62, +- [1][0][RTW89_KCC][21] = 36, ++ [1][0][RTW89_KCC][21] = 58, + [1][0][RTW89_ACMA][21] = 36, + [1][0][RTW89_CHILE][21] = 54, + [1][0][RTW89_UKRAINE][21] = 36, ++ [1][0][RTW89_MEXICO][21] = 62, ++ [1][0][RTW89_CN][21] = 127, ++ [1][0][RTW89_QATAR][21] = 36, + [1][0][RTW89_FCC][23] = 62, + [1][0][RTW89_ETSI][23] = 36, + [1][0][RTW89_MKK][23] = 58, + [1][0][RTW89_IC][23] = 62, +- [1][0][RTW89_KCC][23] = 36, ++ [1][0][RTW89_KCC][23] = 58, + [1][0][RTW89_ACMA][23] = 36, + [1][0][RTW89_CHILE][23] = 54, + [1][0][RTW89_UKRAINE][23] = 36, ++ [1][0][RTW89_MEXICO][23] = 62, ++ [1][0][RTW89_CN][23] = 127, ++ [1][0][RTW89_QATAR][23] = 36, + [1][0][RTW89_FCC][25] = 62, + [1][0][RTW89_ETSI][25] = 36, + [1][0][RTW89_MKK][25] = 58, + [1][0][RTW89_IC][25] = 127, +- [1][0][RTW89_KCC][25] = 36, ++ [1][0][RTW89_KCC][25] = 58, + [1][0][RTW89_ACMA][25] = 127, + [1][0][RTW89_CHILE][25] = 54, + [1][0][RTW89_UKRAINE][25] = 36, ++ [1][0][RTW89_MEXICO][25] = 62, ++ [1][0][RTW89_CN][25] = 127, ++ [1][0][RTW89_QATAR][25] = 36, + [1][0][RTW89_FCC][27] = 62, + [1][0][RTW89_ETSI][27] = 36, + [1][0][RTW89_MKK][27] = 58, + [1][0][RTW89_IC][27] = 127, +- [1][0][RTW89_KCC][27] = 36, ++ [1][0][RTW89_KCC][27] = 58, + [1][0][RTW89_ACMA][27] = 127, + [1][0][RTW89_CHILE][27] = 54, + [1][0][RTW89_UKRAINE][27] = 36, ++ [1][0][RTW89_MEXICO][27] = 62, ++ [1][0][RTW89_CN][27] = 127, ++ [1][0][RTW89_QATAR][27] = 36, + [1][0][RTW89_FCC][29] = 62, + [1][0][RTW89_ETSI][29] = 36, + [1][0][RTW89_MKK][29] = 58, + [1][0][RTW89_IC][29] = 127, +- [1][0][RTW89_KCC][29] = 36, ++ [1][0][RTW89_KCC][29] = 58, + [1][0][RTW89_ACMA][29] = 127, + [1][0][RTW89_CHILE][29] = 54, + [1][0][RTW89_UKRAINE][29] = 36, ++ [1][0][RTW89_MEXICO][29] = 62, ++ [1][0][RTW89_CN][29] = 127, ++ [1][0][RTW89_QATAR][29] = 36, + [1][0][RTW89_FCC][31] = 62, + [1][0][RTW89_ETSI][31] = 36, + [1][0][RTW89_MKK][31] = 58, + [1][0][RTW89_IC][31] = 62, +- [1][0][RTW89_KCC][31] = 36, ++ [1][0][RTW89_KCC][31] = 58, + [1][0][RTW89_ACMA][31] = 36, + [1][0][RTW89_CHILE][31] = 54, + [1][0][RTW89_UKRAINE][31] = 36, ++ [1][0][RTW89_MEXICO][31] = 62, ++ [1][0][RTW89_CN][31] = 127, ++ [1][0][RTW89_QATAR][31] = 36, + [1][0][RTW89_FCC][33] = 62, + [1][0][RTW89_ETSI][33] = 36, + [1][0][RTW89_MKK][33] = 58, + [1][0][RTW89_IC][33] = 62, +- [1][0][RTW89_KCC][33] = 36, ++ [1][0][RTW89_KCC][33] = 58, + [1][0][RTW89_ACMA][33] = 36, + [1][0][RTW89_CHILE][33] = 54, + [1][0][RTW89_UKRAINE][33] = 36, ++ [1][0][RTW89_MEXICO][33] = 62, ++ [1][0][RTW89_CN][33] = 127, ++ [1][0][RTW89_QATAR][33] = 36, + [1][0][RTW89_FCC][35] = 62, + [1][0][RTW89_ETSI][35] = 36, + [1][0][RTW89_MKK][35] = 58, + [1][0][RTW89_IC][35] = 62, +- [1][0][RTW89_KCC][35] = 36, ++ [1][0][RTW89_KCC][35] = 58, + [1][0][RTW89_ACMA][35] = 36, + [1][0][RTW89_CHILE][35] = 54, + [1][0][RTW89_UKRAINE][35] = 36, +- [1][0][RTW89_FCC][37] = 56, +- [1][0][RTW89_ETSI][37] = 62, +- [1][0][RTW89_MKK][37] = 127, +- [1][0][RTW89_IC][37] = 58, +- [1][0][RTW89_KCC][37] = 62, +- [1][0][RTW89_ACMA][37] = 36, +- [1][0][RTW89_CHILE][37] = 62, +- [1][0][RTW89_UKRAINE][37] = 54, ++ [1][0][RTW89_MEXICO][35] = 62, ++ [1][0][RTW89_CN][35] = 127, ++ [1][0][RTW89_QATAR][35] = 36, ++ [1][0][RTW89_FCC][37] = 62, ++ [1][0][RTW89_ETSI][37] = 127, ++ [1][0][RTW89_MKK][37] = 58, ++ [1][0][RTW89_IC][37] = 62, ++ [1][0][RTW89_KCC][37] = 58, ++ [1][0][RTW89_ACMA][37] = 62, ++ [1][0][RTW89_CHILE][37] = 54, ++ [1][0][RTW89_UKRAINE][37] = 127, ++ [1][0][RTW89_MEXICO][37] = 62, ++ [1][0][RTW89_CN][37] = 127, ++ [1][0][RTW89_QATAR][37] = 127, + [1][0][RTW89_FCC][38] = 76, + [1][0][RTW89_ETSI][38] = 28, + [1][0][RTW89_MKK][38] = 127, + [1][0][RTW89_IC][38] = 76, +- [1][0][RTW89_KCC][38] = 28, ++ [1][0][RTW89_KCC][38] = 58, + [1][0][RTW89_ACMA][38] = 76, + [1][0][RTW89_CHILE][38] = 54, + [1][0][RTW89_UKRAINE][38] = 28, ++ [1][0][RTW89_MEXICO][38] = 76, ++ [1][0][RTW89_CN][38] = 74, ++ [1][0][RTW89_QATAR][38] = 28, + [1][0][RTW89_FCC][40] = 76, + [1][0][RTW89_ETSI][40] = 28, + [1][0][RTW89_MKK][40] = 127, + [1][0][RTW89_IC][40] = 76, +- [1][0][RTW89_KCC][40] = 28, ++ [1][0][RTW89_KCC][40] = 58, + [1][0][RTW89_ACMA][40] = 76, + [1][0][RTW89_CHILE][40] = 54, + [1][0][RTW89_UKRAINE][40] = 28, ++ [1][0][RTW89_MEXICO][40] = 76, ++ [1][0][RTW89_CN][40] = 74, ++ [1][0][RTW89_QATAR][40] = 28, + [1][0][RTW89_FCC][42] = 76, + [1][0][RTW89_ETSI][42] = 28, + [1][0][RTW89_MKK][42] = 127, + [1][0][RTW89_IC][42] = 76, +- [1][0][RTW89_KCC][42] = 28, ++ [1][0][RTW89_KCC][42] = 58, + [1][0][RTW89_ACMA][42] = 76, + [1][0][RTW89_CHILE][42] = 54, + [1][0][RTW89_UKRAINE][42] = 28, ++ [1][0][RTW89_MEXICO][42] = 76, ++ [1][0][RTW89_CN][42] = 74, ++ [1][0][RTW89_QATAR][42] = 28, + [1][0][RTW89_FCC][44] = 76, + [1][0][RTW89_ETSI][44] = 28, + [1][0][RTW89_MKK][44] = 127, + [1][0][RTW89_IC][44] = 76, +- [1][0][RTW89_KCC][44] = 28, ++ [1][0][RTW89_KCC][44] = 58, + [1][0][RTW89_ACMA][44] = 76, + [1][0][RTW89_CHILE][44] = 54, + [1][0][RTW89_UKRAINE][44] = 28, ++ [1][0][RTW89_MEXICO][44] = 76, ++ [1][0][RTW89_CN][44] = 74, ++ [1][0][RTW89_QATAR][44] = 28, + [1][0][RTW89_FCC][46] = 76, + [1][0][RTW89_ETSI][46] = 28, + [1][0][RTW89_MKK][46] = 127, + [1][0][RTW89_IC][46] = 76, +- [1][0][RTW89_KCC][46] = 28, ++ [1][0][RTW89_KCC][46] = 58, + [1][0][RTW89_ACMA][46] = 76, + [1][0][RTW89_CHILE][46] = 54, + [1][0][RTW89_UKRAINE][46] = 28, ++ [1][0][RTW89_MEXICO][46] = 76, ++ [1][0][RTW89_CN][46] = 74, ++ [1][0][RTW89_QATAR][46] = 28, + [1][1][RTW89_FCC][0] = 46, + [1][1][RTW89_ETSI][0] = 22, + [1][1][RTW89_MKK][0] = 24, + [1][1][RTW89_IC][0] = 18, +- [1][1][RTW89_KCC][0] = 22, ++ [1][1][RTW89_KCC][0] = 44, + [1][1][RTW89_ACMA][0] = 22, + [1][1][RTW89_CHILE][0] = 18, + [1][1][RTW89_UKRAINE][0] = 22, ++ [1][1][RTW89_MEXICO][0] = 46, ++ [1][1][RTW89_CN][0] = 22, ++ [1][1][RTW89_QATAR][0] = 22, + [1][1][RTW89_FCC][2] = 46, + [1][1][RTW89_ETSI][2] = 22, + [1][1][RTW89_MKK][2] = 24, + [1][1][RTW89_IC][2] = 18, +- [1][1][RTW89_KCC][2] = 22, ++ [1][1][RTW89_KCC][2] = 44, + [1][1][RTW89_ACMA][2] = 22, + [1][1][RTW89_CHILE][2] = 18, + [1][1][RTW89_UKRAINE][2] = 22, ++ [1][1][RTW89_MEXICO][2] = 46, ++ [1][1][RTW89_CN][2] = 22, ++ [1][1][RTW89_QATAR][2] = 22, + [1][1][RTW89_FCC][4] = 46, + [1][1][RTW89_ETSI][4] = 22, + [1][1][RTW89_MKK][4] = 24, + [1][1][RTW89_IC][4] = 18, +- [1][1][RTW89_KCC][4] = 22, ++ [1][1][RTW89_KCC][4] = 44, + [1][1][RTW89_ACMA][4] = 22, + [1][1][RTW89_CHILE][4] = 18, + [1][1][RTW89_UKRAINE][4] = 22, ++ [1][1][RTW89_MEXICO][4] = 46, ++ [1][1][RTW89_CN][4] = 22, ++ [1][1][RTW89_QATAR][4] = 22, + [1][1][RTW89_FCC][6] = 46, + [1][1][RTW89_ETSI][6] = 22, + [1][1][RTW89_MKK][6] = 24, + [1][1][RTW89_IC][6] = 18, +- [1][1][RTW89_KCC][6] = 22, ++ [1][1][RTW89_KCC][6] = 16, + [1][1][RTW89_ACMA][6] = 22, + [1][1][RTW89_CHILE][6] = 18, + [1][1][RTW89_UKRAINE][6] = 22, ++ [1][1][RTW89_MEXICO][6] = 46, ++ [1][1][RTW89_CN][6] = 22, ++ [1][1][RTW89_QATAR][6] = 22, + [1][1][RTW89_FCC][8] = 46, + [1][1][RTW89_ETSI][8] = 22, + [1][1][RTW89_MKK][8] = 24, + [1][1][RTW89_IC][8] = 46, +- [1][1][RTW89_KCC][8] = 22, ++ [1][1][RTW89_KCC][8] = 44, + [1][1][RTW89_ACMA][8] = 22, + [1][1][RTW89_CHILE][8] = 42, + [1][1][RTW89_UKRAINE][8] = 22, ++ [1][1][RTW89_MEXICO][8] = 46, ++ [1][1][RTW89_CN][8] = 22, ++ [1][1][RTW89_QATAR][8] = 22, + [1][1][RTW89_FCC][10] = 46, + [1][1][RTW89_ETSI][10] = 22, + [1][1][RTW89_MKK][10] = 24, + [1][1][RTW89_IC][10] = 46, +- [1][1][RTW89_KCC][10] = 22, ++ [1][1][RTW89_KCC][10] = 44, + [1][1][RTW89_ACMA][10] = 22, + [1][1][RTW89_CHILE][10] = 42, + [1][1][RTW89_UKRAINE][10] = 22, ++ [1][1][RTW89_MEXICO][10] = 46, ++ [1][1][RTW89_CN][10] = 22, ++ [1][1][RTW89_QATAR][10] = 22, + [1][1][RTW89_FCC][12] = 46, + [1][1][RTW89_ETSI][12] = 22, + [1][1][RTW89_MKK][12] = 24, + [1][1][RTW89_IC][12] = 46, +- [1][1][RTW89_KCC][12] = 22, ++ [1][1][RTW89_KCC][12] = 44, + [1][1][RTW89_ACMA][12] = 22, + [1][1][RTW89_CHILE][12] = 42, + [1][1][RTW89_UKRAINE][12] = 22, ++ [1][1][RTW89_MEXICO][12] = 46, ++ [1][1][RTW89_CN][12] = 22, ++ [1][1][RTW89_QATAR][12] = 22, + [1][1][RTW89_FCC][14] = 46, + [1][1][RTW89_ETSI][14] = 22, + [1][1][RTW89_MKK][14] = 24, + [1][1][RTW89_IC][14] = 46, +- [1][1][RTW89_KCC][14] = 22, ++ [1][1][RTW89_KCC][14] = 44, + [1][1][RTW89_ACMA][14] = 22, + [1][1][RTW89_CHILE][14] = 42, + [1][1][RTW89_UKRAINE][14] = 22, ++ [1][1][RTW89_MEXICO][14] = 46, ++ [1][1][RTW89_CN][14] = 22, ++ [1][1][RTW89_QATAR][14] = 22, + [1][1][RTW89_FCC][15] = 46, + [1][1][RTW89_ETSI][15] = 22, + [1][1][RTW89_MKK][15] = 46, + [1][1][RTW89_IC][15] = 46, +- [1][1][RTW89_KCC][15] = 22, ++ [1][1][RTW89_KCC][15] = 44, + [1][1][RTW89_ACMA][15] = 22, + [1][1][RTW89_CHILE][15] = 42, + [1][1][RTW89_UKRAINE][15] = 22, ++ [1][1][RTW89_MEXICO][15] = 46, ++ [1][1][RTW89_CN][15] = 127, ++ [1][1][RTW89_QATAR][15] = 22, + [1][1][RTW89_FCC][17] = 46, + [1][1][RTW89_ETSI][17] = 22, + [1][1][RTW89_MKK][17] = 46, + [1][1][RTW89_IC][17] = 46, +- [1][1][RTW89_KCC][17] = 22, ++ [1][1][RTW89_KCC][17] = 44, + [1][1][RTW89_ACMA][17] = 22, + [1][1][RTW89_CHILE][17] = 42, + [1][1][RTW89_UKRAINE][17] = 22, ++ [1][1][RTW89_MEXICO][17] = 46, ++ [1][1][RTW89_CN][17] = 127, ++ [1][1][RTW89_QATAR][17] = 22, + [1][1][RTW89_FCC][19] = 46, + [1][1][RTW89_ETSI][19] = 22, + [1][1][RTW89_MKK][19] = 46, + [1][1][RTW89_IC][19] = 46, +- [1][1][RTW89_KCC][19] = 22, ++ [1][1][RTW89_KCC][19] = 44, + [1][1][RTW89_ACMA][19] = 22, + [1][1][RTW89_CHILE][19] = 42, + [1][1][RTW89_UKRAINE][19] = 22, ++ [1][1][RTW89_MEXICO][19] = 46, ++ [1][1][RTW89_CN][19] = 127, ++ [1][1][RTW89_QATAR][19] = 22, + [1][1][RTW89_FCC][21] = 46, + [1][1][RTW89_ETSI][21] = 22, + [1][1][RTW89_MKK][21] = 46, + [1][1][RTW89_IC][21] = 46, +- [1][1][RTW89_KCC][21] = 22, ++ [1][1][RTW89_KCC][21] = 44, + [1][1][RTW89_ACMA][21] = 22, + [1][1][RTW89_CHILE][21] = 42, + [1][1][RTW89_UKRAINE][21] = 22, ++ [1][1][RTW89_MEXICO][21] = 46, ++ [1][1][RTW89_CN][21] = 127, ++ [1][1][RTW89_QATAR][21] = 22, + [1][1][RTW89_FCC][23] = 46, + [1][1][RTW89_ETSI][23] = 22, + [1][1][RTW89_MKK][23] = 46, + [1][1][RTW89_IC][23] = 46, +- [1][1][RTW89_KCC][23] = 22, ++ [1][1][RTW89_KCC][23] = 44, + [1][1][RTW89_ACMA][23] = 22, + [1][1][RTW89_CHILE][23] = 42, + [1][1][RTW89_UKRAINE][23] = 22, ++ [1][1][RTW89_MEXICO][23] = 46, ++ [1][1][RTW89_CN][23] = 127, ++ [1][1][RTW89_QATAR][23] = 22, + [1][1][RTW89_FCC][25] = 46, + [1][1][RTW89_ETSI][25] = 22, + [1][1][RTW89_MKK][25] = 46, + [1][1][RTW89_IC][25] = 127, +- [1][1][RTW89_KCC][25] = 22, ++ [1][1][RTW89_KCC][25] = 44, + [1][1][RTW89_ACMA][25] = 127, + [1][1][RTW89_CHILE][25] = 42, + [1][1][RTW89_UKRAINE][25] = 22, ++ [1][1][RTW89_MEXICO][25] = 46, ++ [1][1][RTW89_CN][25] = 127, ++ [1][1][RTW89_QATAR][25] = 22, + [1][1][RTW89_FCC][27] = 46, + [1][1][RTW89_ETSI][27] = 22, + [1][1][RTW89_MKK][27] = 46, + [1][1][RTW89_IC][27] = 127, +- [1][1][RTW89_KCC][27] = 22, ++ [1][1][RTW89_KCC][27] = 44, + [1][1][RTW89_ACMA][27] = 127, + [1][1][RTW89_CHILE][27] = 42, + [1][1][RTW89_UKRAINE][27] = 22, ++ [1][1][RTW89_MEXICO][27] = 46, ++ [1][1][RTW89_CN][27] = 127, ++ [1][1][RTW89_QATAR][27] = 22, + [1][1][RTW89_FCC][29] = 46, + [1][1][RTW89_ETSI][29] = 22, + [1][1][RTW89_MKK][29] = 46, + [1][1][RTW89_IC][29] = 127, +- [1][1][RTW89_KCC][29] = 22, ++ [1][1][RTW89_KCC][29] = 44, + [1][1][RTW89_ACMA][29] = 127, + [1][1][RTW89_CHILE][29] = 42, + [1][1][RTW89_UKRAINE][29] = 22, ++ [1][1][RTW89_MEXICO][29] = 46, ++ [1][1][RTW89_CN][29] = 127, ++ [1][1][RTW89_QATAR][29] = 22, + [1][1][RTW89_FCC][31] = 46, + [1][1][RTW89_ETSI][31] = 22, + [1][1][RTW89_MKK][31] = 46, + [1][1][RTW89_IC][31] = 46, +- [1][1][RTW89_KCC][31] = 22, ++ [1][1][RTW89_KCC][31] = 44, + [1][1][RTW89_ACMA][31] = 22, + [1][1][RTW89_CHILE][31] = 42, + [1][1][RTW89_UKRAINE][31] = 22, ++ [1][1][RTW89_MEXICO][31] = 46, ++ [1][1][RTW89_CN][31] = 127, ++ [1][1][RTW89_QATAR][31] = 22, + [1][1][RTW89_FCC][33] = 46, + [1][1][RTW89_ETSI][33] = 22, + [1][1][RTW89_MKK][33] = 46, + [1][1][RTW89_IC][33] = 46, +- [1][1][RTW89_KCC][33] = 22, ++ [1][1][RTW89_KCC][33] = 44, + [1][1][RTW89_ACMA][33] = 22, + [1][1][RTW89_CHILE][33] = 42, + [1][1][RTW89_UKRAINE][33] = 22, ++ [1][1][RTW89_MEXICO][33] = 46, ++ [1][1][RTW89_CN][33] = 127, ++ [1][1][RTW89_QATAR][33] = 22, + [1][1][RTW89_FCC][35] = 46, + [1][1][RTW89_ETSI][35] = 22, + [1][1][RTW89_MKK][35] = 46, + [1][1][RTW89_IC][35] = 46, +- [1][1][RTW89_KCC][35] = 22, ++ [1][1][RTW89_KCC][35] = 44, + [1][1][RTW89_ACMA][35] = 22, + [1][1][RTW89_CHILE][35] = 42, + [1][1][RTW89_UKRAINE][35] = 22, ++ [1][1][RTW89_MEXICO][35] = 46, ++ [1][1][RTW89_CN][35] = 127, ++ [1][1][RTW89_QATAR][35] = 22, + [1][1][RTW89_FCC][37] = 46, + [1][1][RTW89_ETSI][37] = 127, + [1][1][RTW89_MKK][37] = 46, + [1][1][RTW89_IC][37] = 46, +- [1][1][RTW89_KCC][37] = 22, ++ [1][1][RTW89_KCC][37] = 44, + [1][1][RTW89_ACMA][37] = 50, + [1][1][RTW89_CHILE][37] = 42, + [1][1][RTW89_UKRAINE][37] = 127, ++ [1][1][RTW89_MEXICO][37] = 46, ++ [1][1][RTW89_CN][37] = 127, ++ [1][1][RTW89_QATAR][37] = 127, + [1][1][RTW89_FCC][38] = 74, + [1][1][RTW89_ETSI][38] = 16, + [1][1][RTW89_MKK][38] = 127, + [1][1][RTW89_IC][38] = 74, +- [1][1][RTW89_KCC][38] = 16, ++ [1][1][RTW89_KCC][38] = 44, + [1][1][RTW89_ACMA][38] = 76, + [1][1][RTW89_CHILE][38] = 42, + [1][1][RTW89_UKRAINE][38] = 16, ++ [1][1][RTW89_MEXICO][38] = 74, ++ [1][1][RTW89_CN][38] = 62, ++ [1][1][RTW89_QATAR][38] = 16, + [1][1][RTW89_FCC][40] = 76, + [1][1][RTW89_ETSI][40] = 16, + [1][1][RTW89_MKK][40] = 127, + [1][1][RTW89_IC][40] = 76, +- [1][1][RTW89_KCC][40] = 16, ++ [1][1][RTW89_KCC][40] = 44, + [1][1][RTW89_ACMA][40] = 76, + [1][1][RTW89_CHILE][40] = 42, + [1][1][RTW89_UKRAINE][40] = 16, ++ [1][1][RTW89_MEXICO][40] = 76, ++ [1][1][RTW89_CN][40] = 62, ++ [1][1][RTW89_QATAR][40] = 16, + [1][1][RTW89_FCC][42] = 76, + [1][1][RTW89_ETSI][42] = 16, + [1][1][RTW89_MKK][42] = 127, + [1][1][RTW89_IC][42] = 76, +- [1][1][RTW89_KCC][42] = 16, ++ [1][1][RTW89_KCC][42] = 44, + [1][1][RTW89_ACMA][42] = 76, + [1][1][RTW89_CHILE][42] = 42, + [1][1][RTW89_UKRAINE][42] = 16, ++ [1][1][RTW89_MEXICO][42] = 76, ++ [1][1][RTW89_CN][42] = 62, ++ [1][1][RTW89_QATAR][42] = 16, + [1][1][RTW89_FCC][44] = 76, + [1][1][RTW89_ETSI][44] = 16, + [1][1][RTW89_MKK][44] = 127, + [1][1][RTW89_IC][44] = 76, +- [1][1][RTW89_KCC][44] = 16, ++ [1][1][RTW89_KCC][44] = 44, + [1][1][RTW89_ACMA][44] = 76, + [1][1][RTW89_CHILE][44] = 42, + [1][1][RTW89_UKRAINE][44] = 16, ++ [1][1][RTW89_MEXICO][44] = 76, ++ [1][1][RTW89_CN][44] = 62, ++ [1][1][RTW89_QATAR][44] = 16, + [1][1][RTW89_FCC][46] = 76, + [1][1][RTW89_ETSI][46] = 16, + [1][1][RTW89_MKK][46] = 127, + [1][1][RTW89_IC][46] = 76, +- [1][1][RTW89_KCC][46] = 16, ++ [1][1][RTW89_KCC][46] = 44, + [1][1][RTW89_ACMA][46] = 76, + [1][1][RTW89_CHILE][46] = 42, + [1][1][RTW89_UKRAINE][46] = 16, ++ [1][1][RTW89_MEXICO][46] = 76, ++ [1][1][RTW89_CN][46] = 62, ++ [1][1][RTW89_QATAR][46] = 16, + [2][0][RTW89_FCC][0] = 74, + [2][0][RTW89_ETSI][0] = 46, + [2][0][RTW89_MKK][0] = 50, + [2][0][RTW89_IC][0] = 46, +- [2][0][RTW89_KCC][0] = 46, ++ [2][0][RTW89_KCC][0] = 70, + [2][0][RTW89_ACMA][0] = 46, + [2][0][RTW89_CHILE][0] = 30, + [2][0][RTW89_UKRAINE][0] = 46, ++ [2][0][RTW89_MEXICO][0] = 62, ++ [2][0][RTW89_CN][0] = 46, ++ [2][0][RTW89_QATAR][0] = 46, + [2][0][RTW89_FCC][2] = 74, + [2][0][RTW89_ETSI][2] = 46, + [2][0][RTW89_MKK][2] = 50, + [2][0][RTW89_IC][2] = 46, +- [2][0][RTW89_KCC][2] = 46, ++ [2][0][RTW89_KCC][2] = 70, + [2][0][RTW89_ACMA][2] = 46, + [2][0][RTW89_CHILE][2] = 30, + [2][0][RTW89_UKRAINE][2] = 46, ++ [2][0][RTW89_MEXICO][2] = 62, ++ [2][0][RTW89_CN][2] = 46, ++ [2][0][RTW89_QATAR][2] = 46, + [2][0][RTW89_FCC][4] = 74, + [2][0][RTW89_ETSI][4] = 46, + [2][0][RTW89_MKK][4] = 50, + [2][0][RTW89_IC][4] = 46, +- [2][0][RTW89_KCC][4] = 46, ++ [2][0][RTW89_KCC][4] = 70, + [2][0][RTW89_ACMA][4] = 46, + [2][0][RTW89_CHILE][4] = 30, + [2][0][RTW89_UKRAINE][4] = 46, ++ [2][0][RTW89_MEXICO][4] = 62, ++ [2][0][RTW89_CN][4] = 46, ++ [2][0][RTW89_QATAR][4] = 46, + [2][0][RTW89_FCC][6] = 74, + [2][0][RTW89_ETSI][6] = 46, + [2][0][RTW89_MKK][6] = 50, + [2][0][RTW89_IC][6] = 46, +- [2][0][RTW89_KCC][6] = 46, ++ [2][0][RTW89_KCC][6] = 44, + [2][0][RTW89_ACMA][6] = 46, + [2][0][RTW89_CHILE][6] = 30, + [2][0][RTW89_UKRAINE][6] = 46, ++ [2][0][RTW89_MEXICO][6] = 62, ++ [2][0][RTW89_CN][6] = 46, ++ [2][0][RTW89_QATAR][6] = 46, + [2][0][RTW89_FCC][8] = 74, + [2][0][RTW89_ETSI][8] = 46, + [2][0][RTW89_MKK][8] = 50, + [2][0][RTW89_IC][8] = 66, +- [2][0][RTW89_KCC][8] = 46, ++ [2][0][RTW89_KCC][8] = 70, + [2][0][RTW89_ACMA][8] = 46, + [2][0][RTW89_CHILE][8] = 54, + [2][0][RTW89_UKRAINE][8] = 46, ++ [2][0][RTW89_MEXICO][8] = 74, ++ [2][0][RTW89_CN][8] = 46, ++ [2][0][RTW89_QATAR][8] = 46, + [2][0][RTW89_FCC][10] = 74, + [2][0][RTW89_ETSI][10] = 46, + [2][0][RTW89_MKK][10] = 50, + [2][0][RTW89_IC][10] = 66, +- [2][0][RTW89_KCC][10] = 46, ++ [2][0][RTW89_KCC][10] = 70, + [2][0][RTW89_ACMA][10] = 46, + [2][0][RTW89_CHILE][10] = 54, + [2][0][RTW89_UKRAINE][10] = 46, ++ [2][0][RTW89_MEXICO][10] = 74, ++ [2][0][RTW89_CN][10] = 46, ++ [2][0][RTW89_QATAR][10] = 46, + [2][0][RTW89_FCC][12] = 74, + [2][0][RTW89_ETSI][12] = 46, + [2][0][RTW89_MKK][12] = 50, + [2][0][RTW89_IC][12] = 66, +- [2][0][RTW89_KCC][12] = 46, ++ [2][0][RTW89_KCC][12] = 70, + [2][0][RTW89_ACMA][12] = 46, + [2][0][RTW89_CHILE][12] = 54, + [2][0][RTW89_UKRAINE][12] = 46, ++ [2][0][RTW89_MEXICO][12] = 74, ++ [2][0][RTW89_CN][12] = 46, ++ [2][0][RTW89_QATAR][12] = 46, + [2][0][RTW89_FCC][14] = 74, + [2][0][RTW89_ETSI][14] = 46, + [2][0][RTW89_MKK][14] = 50, + [2][0][RTW89_IC][14] = 66, +- [2][0][RTW89_KCC][14] = 46, ++ [2][0][RTW89_KCC][14] = 70, + [2][0][RTW89_ACMA][14] = 46, + [2][0][RTW89_CHILE][14] = 54, + [2][0][RTW89_UKRAINE][14] = 46, ++ [2][0][RTW89_MEXICO][14] = 74, ++ [2][0][RTW89_CN][14] = 46, ++ [2][0][RTW89_QATAR][14] = 46, + [2][0][RTW89_FCC][15] = 74, + [2][0][RTW89_ETSI][15] = 46, + [2][0][RTW89_MKK][15] = 70, + [2][0][RTW89_IC][15] = 74, +- [2][0][RTW89_KCC][15] = 46, ++ [2][0][RTW89_KCC][15] = 70, + [2][0][RTW89_ACMA][15] = 46, + [2][0][RTW89_CHILE][15] = 54, + [2][0][RTW89_UKRAINE][15] = 46, ++ [2][0][RTW89_MEXICO][15] = 74, ++ [2][0][RTW89_CN][15] = 127, ++ [2][0][RTW89_QATAR][15] = 46, + [2][0][RTW89_FCC][17] = 74, + [2][0][RTW89_ETSI][17] = 46, + [2][0][RTW89_MKK][17] = 70, + [2][0][RTW89_IC][17] = 74, +- [2][0][RTW89_KCC][17] = 46, ++ [2][0][RTW89_KCC][17] = 70, + [2][0][RTW89_ACMA][17] = 46, + [2][0][RTW89_CHILE][17] = 54, + [2][0][RTW89_UKRAINE][17] = 46, ++ [2][0][RTW89_MEXICO][17] = 74, ++ [2][0][RTW89_CN][17] = 127, ++ [2][0][RTW89_QATAR][17] = 46, + [2][0][RTW89_FCC][19] = 74, + [2][0][RTW89_ETSI][19] = 46, + [2][0][RTW89_MKK][19] = 70, + [2][0][RTW89_IC][19] = 74, +- [2][0][RTW89_KCC][19] = 46, ++ [2][0][RTW89_KCC][19] = 70, + [2][0][RTW89_ACMA][19] = 46, + [2][0][RTW89_CHILE][19] = 54, + [2][0][RTW89_UKRAINE][19] = 46, ++ [2][0][RTW89_MEXICO][19] = 74, ++ [2][0][RTW89_CN][19] = 127, ++ [2][0][RTW89_QATAR][19] = 46, + [2][0][RTW89_FCC][21] = 74, + [2][0][RTW89_ETSI][21] = 46, + [2][0][RTW89_MKK][21] = 70, + [2][0][RTW89_IC][21] = 74, +- [2][0][RTW89_KCC][21] = 46, ++ [2][0][RTW89_KCC][21] = 70, + [2][0][RTW89_ACMA][21] = 46, + [2][0][RTW89_CHILE][21] = 54, + [2][0][RTW89_UKRAINE][21] = 46, ++ [2][0][RTW89_MEXICO][21] = 74, ++ [2][0][RTW89_CN][21] = 127, ++ [2][0][RTW89_QATAR][21] = 46, + [2][0][RTW89_FCC][23] = 74, + [2][0][RTW89_ETSI][23] = 46, + [2][0][RTW89_MKK][23] = 70, + [2][0][RTW89_IC][23] = 74, +- [2][0][RTW89_KCC][23] = 46, ++ [2][0][RTW89_KCC][23] = 70, + [2][0][RTW89_ACMA][23] = 46, + [2][0][RTW89_CHILE][23] = 54, + [2][0][RTW89_UKRAINE][23] = 46, ++ [2][0][RTW89_MEXICO][23] = 74, ++ [2][0][RTW89_CN][23] = 127, ++ [2][0][RTW89_QATAR][23] = 46, + [2][0][RTW89_FCC][25] = 74, + [2][0][RTW89_ETSI][25] = 46, + [2][0][RTW89_MKK][25] = 70, + [2][0][RTW89_IC][25] = 127, +- [2][0][RTW89_KCC][25] = 46, ++ [2][0][RTW89_KCC][25] = 70, + [2][0][RTW89_ACMA][25] = 127, + [2][0][RTW89_CHILE][25] = 54, + [2][0][RTW89_UKRAINE][25] = 46, ++ [2][0][RTW89_MEXICO][25] = 74, ++ [2][0][RTW89_CN][25] = 127, ++ [2][0][RTW89_QATAR][25] = 46, + [2][0][RTW89_FCC][27] = 74, + [2][0][RTW89_ETSI][27] = 46, + [2][0][RTW89_MKK][27] = 70, + [2][0][RTW89_IC][27] = 127, +- [2][0][RTW89_KCC][27] = 46, ++ [2][0][RTW89_KCC][27] = 70, + [2][0][RTW89_ACMA][27] = 127, + [2][0][RTW89_CHILE][27] = 54, + [2][0][RTW89_UKRAINE][27] = 46, ++ [2][0][RTW89_MEXICO][27] = 74, ++ [2][0][RTW89_CN][27] = 127, ++ [2][0][RTW89_QATAR][27] = 46, + [2][0][RTW89_FCC][29] = 74, + [2][0][RTW89_ETSI][29] = 46, + [2][0][RTW89_MKK][29] = 70, + [2][0][RTW89_IC][29] = 127, +- [2][0][RTW89_KCC][29] = 46, ++ [2][0][RTW89_KCC][29] = 70, + [2][0][RTW89_ACMA][29] = 127, + [2][0][RTW89_CHILE][29] = 54, + [2][0][RTW89_UKRAINE][29] = 46, ++ [2][0][RTW89_MEXICO][29] = 74, ++ [2][0][RTW89_CN][29] = 127, ++ [2][0][RTW89_QATAR][29] = 46, + [2][0][RTW89_FCC][31] = 74, + [2][0][RTW89_ETSI][31] = 46, + [2][0][RTW89_MKK][31] = 70, + [2][0][RTW89_IC][31] = 74, +- [2][0][RTW89_KCC][31] = 46, ++ [2][0][RTW89_KCC][31] = 70, + [2][0][RTW89_ACMA][31] = 46, + [2][0][RTW89_CHILE][31] = 54, + [2][0][RTW89_UKRAINE][31] = 46, ++ [2][0][RTW89_MEXICO][31] = 74, ++ [2][0][RTW89_CN][31] = 127, ++ [2][0][RTW89_QATAR][31] = 46, + [2][0][RTW89_FCC][33] = 74, + [2][0][RTW89_ETSI][33] = 46, + [2][0][RTW89_MKK][33] = 70, + [2][0][RTW89_IC][33] = 74, +- [2][0][RTW89_KCC][33] = 46, ++ [2][0][RTW89_KCC][33] = 70, + [2][0][RTW89_ACMA][33] = 46, + [2][0][RTW89_CHILE][33] = 54, + [2][0][RTW89_UKRAINE][33] = 46, ++ [2][0][RTW89_MEXICO][33] = 74, ++ [2][0][RTW89_CN][33] = 127, ++ [2][0][RTW89_QATAR][33] = 46, + [2][0][RTW89_FCC][35] = 74, + [2][0][RTW89_ETSI][35] = 46, + [2][0][RTW89_MKK][35] = 70, + [2][0][RTW89_IC][35] = 74, +- [2][0][RTW89_KCC][35] = 46, ++ [2][0][RTW89_KCC][35] = 70, + [2][0][RTW89_ACMA][35] = 46, + [2][0][RTW89_CHILE][35] = 54, + [2][0][RTW89_UKRAINE][35] = 46, ++ [2][0][RTW89_MEXICO][35] = 74, ++ [2][0][RTW89_CN][35] = 127, ++ [2][0][RTW89_QATAR][35] = 46, + [2][0][RTW89_FCC][37] = 74, + [2][0][RTW89_ETSI][37] = 127, + [2][0][RTW89_MKK][37] = 70, + [2][0][RTW89_IC][37] = 74, +- [2][0][RTW89_KCC][37] = 46, ++ [2][0][RTW89_KCC][37] = 70, + [2][0][RTW89_ACMA][37] = 74, + [2][0][RTW89_CHILE][37] = 54, + [2][0][RTW89_UKRAINE][37] = 127, ++ [2][0][RTW89_MEXICO][37] = 74, ++ [2][0][RTW89_CN][37] = 127, ++ [2][0][RTW89_QATAR][37] = 127, + [2][0][RTW89_FCC][38] = 76, + [2][0][RTW89_ETSI][38] = 28, + [2][0][RTW89_MKK][38] = 127, + [2][0][RTW89_IC][38] = 76, +- [2][0][RTW89_KCC][38] = 28, ++ [2][0][RTW89_KCC][38] = 70, + [2][0][RTW89_ACMA][38] = 76, + [2][0][RTW89_CHILE][38] = 54, + [2][0][RTW89_UKRAINE][38] = 28, ++ [2][0][RTW89_MEXICO][38] = 76, ++ [2][0][RTW89_CN][38] = 76, ++ [2][0][RTW89_QATAR][38] = 28, + [2][0][RTW89_FCC][40] = 76, + [2][0][RTW89_ETSI][40] = 28, + [2][0][RTW89_MKK][40] = 127, + [2][0][RTW89_IC][40] = 76, +- [2][0][RTW89_KCC][40] = 28, ++ [2][0][RTW89_KCC][40] = 70, + [2][0][RTW89_ACMA][40] = 76, + [2][0][RTW89_CHILE][40] = 54, + [2][0][RTW89_UKRAINE][40] = 28, ++ [2][0][RTW89_MEXICO][40] = 76, ++ [2][0][RTW89_CN][40] = 76, ++ [2][0][RTW89_QATAR][40] = 28, + [2][0][RTW89_FCC][42] = 76, + [2][0][RTW89_ETSI][42] = 28, + [2][0][RTW89_MKK][42] = 127, + [2][0][RTW89_IC][42] = 76, +- [2][0][RTW89_KCC][42] = 28, ++ [2][0][RTW89_KCC][42] = 70, + [2][0][RTW89_ACMA][42] = 76, + [2][0][RTW89_CHILE][42] = 54, + [2][0][RTW89_UKRAINE][42] = 28, ++ [2][0][RTW89_MEXICO][42] = 76, ++ [2][0][RTW89_CN][42] = 76, ++ [2][0][RTW89_QATAR][42] = 28, + [2][0][RTW89_FCC][44] = 76, + [2][0][RTW89_ETSI][44] = 28, + [2][0][RTW89_MKK][44] = 127, + [2][0][RTW89_IC][44] = 76, +- [2][0][RTW89_KCC][44] = 28, ++ [2][0][RTW89_KCC][44] = 70, + [2][0][RTW89_ACMA][44] = 76, + [2][0][RTW89_CHILE][44] = 54, + [2][0][RTW89_UKRAINE][44] = 28, ++ [2][0][RTW89_MEXICO][44] = 76, ++ [2][0][RTW89_CN][44] = 76, ++ [2][0][RTW89_QATAR][44] = 28, + [2][0][RTW89_FCC][46] = 76, + [2][0][RTW89_ETSI][46] = 28, + [2][0][RTW89_MKK][46] = 127, + [2][0][RTW89_IC][46] = 76, +- [2][0][RTW89_KCC][46] = 28, ++ [2][0][RTW89_KCC][46] = 70, + [2][0][RTW89_ACMA][46] = 76, + [2][0][RTW89_CHILE][46] = 54, + [2][0][RTW89_UKRAINE][46] = 28, ++ [2][0][RTW89_MEXICO][46] = 76, ++ [2][0][RTW89_CN][46] = 76, ++ [2][0][RTW89_QATAR][46] = 28, + [2][1][RTW89_FCC][0] = 58, + [2][1][RTW89_ETSI][0] = 32, + [2][1][RTW89_MKK][0] = 38, + [2][1][RTW89_IC][0] = 30, +- [2][1][RTW89_KCC][0] = 32, ++ [2][1][RTW89_KCC][0] = 54, + [2][1][RTW89_ACMA][0] = 32, + [2][1][RTW89_CHILE][0] = 18, + [2][1][RTW89_UKRAINE][0] = 32, ++ [2][1][RTW89_MEXICO][0] = 50, ++ [2][1][RTW89_CN][0] = 32, ++ [2][1][RTW89_QATAR][0] = 32, + [2][1][RTW89_FCC][2] = 58, + [2][1][RTW89_ETSI][2] = 32, + [2][1][RTW89_MKK][2] = 38, + [2][1][RTW89_IC][2] = 30, +- [2][1][RTW89_KCC][2] = 32, ++ [2][1][RTW89_KCC][2] = 54, + [2][1][RTW89_ACMA][2] = 32, + [2][1][RTW89_CHILE][2] = 18, + [2][1][RTW89_UKRAINE][2] = 32, ++ [2][1][RTW89_MEXICO][2] = 50, ++ [2][1][RTW89_CN][2] = 32, ++ [2][1][RTW89_QATAR][2] = 32, + [2][1][RTW89_FCC][4] = 58, + [2][1][RTW89_ETSI][4] = 32, + [2][1][RTW89_MKK][4] = 38, + [2][1][RTW89_IC][4] = 30, +- [2][1][RTW89_KCC][4] = 32, ++ [2][1][RTW89_KCC][4] = 54, + [2][1][RTW89_ACMA][4] = 32, + [2][1][RTW89_CHILE][4] = 18, + [2][1][RTW89_UKRAINE][4] = 32, ++ [2][1][RTW89_MEXICO][4] = 50, ++ [2][1][RTW89_CN][4] = 32, ++ [2][1][RTW89_QATAR][4] = 32, + [2][1][RTW89_FCC][6] = 58, + [2][1][RTW89_ETSI][6] = 32, + [2][1][RTW89_MKK][6] = 38, + [2][1][RTW89_IC][6] = 30, +- [2][1][RTW89_KCC][6] = 32, ++ [2][1][RTW89_KCC][6] = 26, + [2][1][RTW89_ACMA][6] = 32, + [2][1][RTW89_CHILE][6] = 18, + [2][1][RTW89_UKRAINE][6] = 32, ++ [2][1][RTW89_MEXICO][6] = 50, ++ [2][1][RTW89_CN][6] = 32, ++ [2][1][RTW89_QATAR][6] = 32, + [2][1][RTW89_FCC][8] = 58, + [2][1][RTW89_ETSI][8] = 32, + [2][1][RTW89_MKK][8] = 38, + [2][1][RTW89_IC][8] = 52, +- [2][1][RTW89_KCC][8] = 32, ++ [2][1][RTW89_KCC][8] = 54, + [2][1][RTW89_ACMA][8] = 32, + [2][1][RTW89_CHILE][8] = 42, + [2][1][RTW89_UKRAINE][8] = 32, ++ [2][1][RTW89_MEXICO][8] = 58, ++ [2][1][RTW89_CN][8] = 32, ++ [2][1][RTW89_QATAR][8] = 32, + [2][1][RTW89_FCC][10] = 58, + [2][1][RTW89_ETSI][10] = 32, + [2][1][RTW89_MKK][10] = 38, + [2][1][RTW89_IC][10] = 52, +- [2][1][RTW89_KCC][10] = 32, ++ [2][1][RTW89_KCC][10] = 54, + [2][1][RTW89_ACMA][10] = 32, + [2][1][RTW89_CHILE][10] = 42, + [2][1][RTW89_UKRAINE][10] = 32, ++ [2][1][RTW89_MEXICO][10] = 58, ++ [2][1][RTW89_CN][10] = 32, ++ [2][1][RTW89_QATAR][10] = 32, + [2][1][RTW89_FCC][12] = 58, + [2][1][RTW89_ETSI][12] = 32, + [2][1][RTW89_MKK][12] = 38, + [2][1][RTW89_IC][12] = 52, +- [2][1][RTW89_KCC][12] = 32, ++ [2][1][RTW89_KCC][12] = 54, + [2][1][RTW89_ACMA][12] = 32, + [2][1][RTW89_CHILE][12] = 42, + [2][1][RTW89_UKRAINE][12] = 32, ++ [2][1][RTW89_MEXICO][12] = 58, ++ [2][1][RTW89_CN][12] = 32, ++ [2][1][RTW89_QATAR][12] = 32, + [2][1][RTW89_FCC][14] = 58, + [2][1][RTW89_ETSI][14] = 32, + [2][1][RTW89_MKK][14] = 38, + [2][1][RTW89_IC][14] = 52, +- [2][1][RTW89_KCC][14] = 32, ++ [2][1][RTW89_KCC][14] = 54, + [2][1][RTW89_ACMA][14] = 32, + [2][1][RTW89_CHILE][14] = 42, + [2][1][RTW89_UKRAINE][14] = 32, ++ [2][1][RTW89_MEXICO][14] = 58, ++ [2][1][RTW89_CN][14] = 32, ++ [2][1][RTW89_QATAR][14] = 32, + [2][1][RTW89_FCC][15] = 58, + [2][1][RTW89_ETSI][15] = 32, + [2][1][RTW89_MKK][15] = 58, + [2][1][RTW89_IC][15] = 58, +- [2][1][RTW89_KCC][15] = 32, ++ [2][1][RTW89_KCC][15] = 54, + [2][1][RTW89_ACMA][15] = 32, + [2][1][RTW89_CHILE][15] = 42, + [2][1][RTW89_UKRAINE][15] = 32, ++ [2][1][RTW89_MEXICO][15] = 58, ++ [2][1][RTW89_CN][15] = 127, ++ [2][1][RTW89_QATAR][15] = 32, + [2][1][RTW89_FCC][17] = 58, + [2][1][RTW89_ETSI][17] = 32, + [2][1][RTW89_MKK][17] = 58, + [2][1][RTW89_IC][17] = 58, +- [2][1][RTW89_KCC][17] = 32, ++ [2][1][RTW89_KCC][17] = 54, + [2][1][RTW89_ACMA][17] = 32, + [2][1][RTW89_CHILE][17] = 42, + [2][1][RTW89_UKRAINE][17] = 32, ++ [2][1][RTW89_MEXICO][17] = 58, ++ [2][1][RTW89_CN][17] = 127, ++ [2][1][RTW89_QATAR][17] = 32, + [2][1][RTW89_FCC][19] = 58, + [2][1][RTW89_ETSI][19] = 32, + [2][1][RTW89_MKK][19] = 58, + [2][1][RTW89_IC][19] = 58, +- [2][1][RTW89_KCC][19] = 32, ++ [2][1][RTW89_KCC][19] = 54, + [2][1][RTW89_ACMA][19] = 32, + [2][1][RTW89_CHILE][19] = 42, + [2][1][RTW89_UKRAINE][19] = 32, ++ [2][1][RTW89_MEXICO][19] = 58, ++ [2][1][RTW89_CN][19] = 127, ++ [2][1][RTW89_QATAR][19] = 32, + [2][1][RTW89_FCC][21] = 58, + [2][1][RTW89_ETSI][21] = 32, + [2][1][RTW89_MKK][21] = 58, + [2][1][RTW89_IC][21] = 58, +- [2][1][RTW89_KCC][21] = 32, ++ [2][1][RTW89_KCC][21] = 54, + [2][1][RTW89_ACMA][21] = 32, + [2][1][RTW89_CHILE][21] = 42, + [2][1][RTW89_UKRAINE][21] = 32, ++ [2][1][RTW89_MEXICO][21] = 58, ++ [2][1][RTW89_CN][21] = 127, ++ [2][1][RTW89_QATAR][21] = 32, + [2][1][RTW89_FCC][23] = 58, + [2][1][RTW89_ETSI][23] = 32, + [2][1][RTW89_MKK][23] = 58, + [2][1][RTW89_IC][23] = 58, +- [2][1][RTW89_KCC][23] = 32, ++ [2][1][RTW89_KCC][23] = 54, + [2][1][RTW89_ACMA][23] = 32, + [2][1][RTW89_CHILE][23] = 42, + [2][1][RTW89_UKRAINE][23] = 32, ++ [2][1][RTW89_MEXICO][23] = 58, ++ [2][1][RTW89_CN][23] = 127, ++ [2][1][RTW89_QATAR][23] = 32, + [2][1][RTW89_FCC][25] = 58, + [2][1][RTW89_ETSI][25] = 32, + [2][1][RTW89_MKK][25] = 58, + [2][1][RTW89_IC][25] = 127, +- [2][1][RTW89_KCC][25] = 32, ++ [2][1][RTW89_KCC][25] = 54, + [2][1][RTW89_ACMA][25] = 127, + [2][1][RTW89_CHILE][25] = 42, + [2][1][RTW89_UKRAINE][25] = 32, ++ [2][1][RTW89_MEXICO][25] = 58, ++ [2][1][RTW89_CN][25] = 127, ++ [2][1][RTW89_QATAR][25] = 32, + [2][1][RTW89_FCC][27] = 58, + [2][1][RTW89_ETSI][27] = 32, + [2][1][RTW89_MKK][27] = 58, + [2][1][RTW89_IC][27] = 127, +- [2][1][RTW89_KCC][27] = 32, ++ [2][1][RTW89_KCC][27] = 54, + [2][1][RTW89_ACMA][27] = 127, + [2][1][RTW89_CHILE][27] = 42, + [2][1][RTW89_UKRAINE][27] = 32, ++ [2][1][RTW89_MEXICO][27] = 58, ++ [2][1][RTW89_CN][27] = 127, ++ [2][1][RTW89_QATAR][27] = 32, + [2][1][RTW89_FCC][29] = 58, + [2][1][RTW89_ETSI][29] = 32, + [2][1][RTW89_MKK][29] = 58, + [2][1][RTW89_IC][29] = 127, +- [2][1][RTW89_KCC][29] = 32, ++ [2][1][RTW89_KCC][29] = 54, + [2][1][RTW89_ACMA][29] = 127, + [2][1][RTW89_CHILE][29] = 42, + [2][1][RTW89_UKRAINE][29] = 32, ++ [2][1][RTW89_MEXICO][29] = 58, ++ [2][1][RTW89_CN][29] = 127, ++ [2][1][RTW89_QATAR][29] = 32, + [2][1][RTW89_FCC][31] = 58, + [2][1][RTW89_ETSI][31] = 32, + [2][1][RTW89_MKK][31] = 58, + [2][1][RTW89_IC][31] = 58, +- [2][1][RTW89_KCC][31] = 32, ++ [2][1][RTW89_KCC][31] = 54, + [2][1][RTW89_ACMA][31] = 32, + [2][1][RTW89_CHILE][31] = 42, + [2][1][RTW89_UKRAINE][31] = 32, ++ [2][1][RTW89_MEXICO][31] = 58, ++ [2][1][RTW89_CN][31] = 127, ++ [2][1][RTW89_QATAR][31] = 32, + [2][1][RTW89_FCC][33] = 58, + [2][1][RTW89_ETSI][33] = 32, + [2][1][RTW89_MKK][33] = 58, + [2][1][RTW89_IC][33] = 58, +- [2][1][RTW89_KCC][33] = 32, ++ [2][1][RTW89_KCC][33] = 54, + [2][1][RTW89_ACMA][33] = 32, + [2][1][RTW89_CHILE][33] = 42, + [2][1][RTW89_UKRAINE][33] = 32, ++ [2][1][RTW89_MEXICO][33] = 58, ++ [2][1][RTW89_CN][33] = 127, ++ [2][1][RTW89_QATAR][33] = 32, + [2][1][RTW89_FCC][35] = 58, + [2][1][RTW89_ETSI][35] = 32, + [2][1][RTW89_MKK][35] = 58, + [2][1][RTW89_IC][35] = 58, +- [2][1][RTW89_KCC][35] = 32, ++ [2][1][RTW89_KCC][35] = 54, + [2][1][RTW89_ACMA][35] = 32, + [2][1][RTW89_CHILE][35] = 42, + [2][1][RTW89_UKRAINE][35] = 32, ++ [2][1][RTW89_MEXICO][35] = 58, ++ [2][1][RTW89_CN][35] = 127, ++ [2][1][RTW89_QATAR][35] = 32, + [2][1][RTW89_FCC][37] = 58, + [2][1][RTW89_ETSI][37] = 127, + [2][1][RTW89_MKK][37] = 58, + [2][1][RTW89_IC][37] = 58, +- [2][1][RTW89_KCC][37] = 32, ++ [2][1][RTW89_KCC][37] = 54, + [2][1][RTW89_ACMA][37] = 62, + [2][1][RTW89_CHILE][37] = 42, + [2][1][RTW89_UKRAINE][37] = 127, ++ [2][1][RTW89_MEXICO][37] = 58, ++ [2][1][RTW89_CN][37] = 127, ++ [2][1][RTW89_QATAR][37] = 127, + [2][1][RTW89_FCC][38] = 76, + [2][1][RTW89_ETSI][38] = 16, + [2][1][RTW89_MKK][38] = 127, + [2][1][RTW89_IC][38] = 76, +- [2][1][RTW89_KCC][38] = 16, ++ [2][1][RTW89_KCC][38] = 54, + [2][1][RTW89_ACMA][38] = 76, + [2][1][RTW89_CHILE][38] = 42, + [2][1][RTW89_UKRAINE][38] = 16, ++ [2][1][RTW89_MEXICO][38] = 76, ++ [2][1][RTW89_CN][38] = 64, ++ [2][1][RTW89_QATAR][38] = 16, + [2][1][RTW89_FCC][40] = 76, + [2][1][RTW89_ETSI][40] = 16, + [2][1][RTW89_MKK][40] = 127, + [2][1][RTW89_IC][40] = 76, +- [2][1][RTW89_KCC][40] = 16, ++ [2][1][RTW89_KCC][40] = 54, + [2][1][RTW89_ACMA][40] = 76, + [2][1][RTW89_CHILE][40] = 42, + [2][1][RTW89_UKRAINE][40] = 16, ++ [2][1][RTW89_MEXICO][40] = 76, ++ [2][1][RTW89_CN][40] = 64, ++ [2][1][RTW89_QATAR][40] = 16, + [2][1][RTW89_FCC][42] = 76, + [2][1][RTW89_ETSI][42] = 16, + [2][1][RTW89_MKK][42] = 127, + [2][1][RTW89_IC][42] = 76, +- [2][1][RTW89_KCC][42] = 16, ++ [2][1][RTW89_KCC][42] = 54, + [2][1][RTW89_ACMA][42] = 76, + [2][1][RTW89_CHILE][42] = 42, + [2][1][RTW89_UKRAINE][42] = 16, ++ [2][1][RTW89_MEXICO][42] = 76, ++ [2][1][RTW89_CN][42] = 64, ++ [2][1][RTW89_QATAR][42] = 16, + [2][1][RTW89_FCC][44] = 76, + [2][1][RTW89_ETSI][44] = 16, + [2][1][RTW89_MKK][44] = 127, + [2][1][RTW89_IC][44] = 76, +- [2][1][RTW89_KCC][44] = 16, ++ [2][1][RTW89_KCC][44] = 54, + [2][1][RTW89_ACMA][44] = 76, + [2][1][RTW89_CHILE][44] = 42, + [2][1][RTW89_UKRAINE][44] = 16, ++ [2][1][RTW89_MEXICO][44] = 76, ++ [2][1][RTW89_CN][44] = 64, ++ [2][1][RTW89_QATAR][44] = 16, + [2][1][RTW89_FCC][46] = 76, + [2][1][RTW89_ETSI][46] = 16, + [2][1][RTW89_MKK][46] = 127, + [2][1][RTW89_IC][46] = 76, +- [2][1][RTW89_KCC][46] = 16, ++ [2][1][RTW89_KCC][46] = 54, + [2][1][RTW89_ACMA][46] = 76, + [2][1][RTW89_CHILE][46] = 42, + [2][1][RTW89_UKRAINE][46] = 16, ++ [2][1][RTW89_MEXICO][46] = 76, ++ [2][1][RTW89_CN][46] = 64, ++ [2][1][RTW89_QATAR][46] = 16, + }; + + #define DECLARE_DIG_TABLE(name) \ +-- +2.13.6 + diff --git a/SOURCES/0014-rtw89-update-rtw89_regulatory-map-to-R58-R31.patch b/SOURCES/0014-rtw89-update-rtw89_regulatory-map-to-R58-R31.patch new file mode 100644 index 0000000..b841619 --- /dev/null +++ b/SOURCES/0014-rtw89-update-rtw89_regulatory-map-to-R58-R31.patch @@ -0,0 +1,468 @@ +From c3c0d755be0ab69370213e321b4c67d7c9688153 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:02 +0100 +Subject: [PATCH 14/36] rtw89: update rtw89_regulatory map to R58-R31 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 08e16498e01b289dc9cfd41043c91a4b84fe6ce9 +Author: Zong-Zhe Yang +Date: Mon Nov 1 17:31:06 2021 +0800 + + rtw89: update rtw89_regulatory map to R58-R31 + + Start to configure entries with RTW89_QATAR, RTW89_UKRAINE, RTW89_CN. + Adjust some entries with explicit rtw89_regulatory instead of RTW89_WW. + + Signed-off-by: Zong-Zhe Yang + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211101093106.28848-5-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/regd.c | 375 +++++++++++++++--------------- + 1 file changed, 188 insertions(+), 187 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/regd.c b/drivers/net/wireless/realtek/rtw89/regd.c +index f00b94ecfff4..4c37e590e43c 100644 +--- a/drivers/net/wireless/realtek/rtw89/regd.c ++++ b/drivers/net/wireless/realtek/rtw89/regd.c +@@ -15,243 +15,244 @@ static const struct rtw89_regulatory rtw89_ww_regd = + COUNTRY_REGD("00", RTW89_WW, RTW89_WW); + + static const struct rtw89_regulatory rtw89_regd_map[] = { +- COUNTRY_REGD("AR", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("BO", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("AR", RTW89_MEXICO, RTW89_MEXICO), ++ COUNTRY_REGD("BO", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("BR", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("CL", RTW89_WW, RTW89_CHILE), ++ COUNTRY_REGD("CL", RTW89_CHILE, RTW89_CHILE), + COUNTRY_REGD("CO", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("CR", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("EC", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("SV", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("SV", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("GT", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("HN", RTW89_WW, RTW89_FCC), +- COUNTRY_REGD("MX", RTW89_FCC, RTW89_MEXICO), ++ COUNTRY_REGD("HN", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("MX", RTW89_MEXICO, RTW89_MEXICO), + COUNTRY_REGD("NI", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("PA", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("PY", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("PE", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("US", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("UY", RTW89_WW, RTW89_FCC), +- COUNTRY_REGD("VE", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("UY", RTW89_FCC, RTW89_FCC), ++ COUNTRY_REGD("VE", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("PR", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("DO", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("AT", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CY", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("DK", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("EE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("FI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("FR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("DE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("HU", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IS", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IT", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LV", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LT", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LU", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MT", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MC", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NL", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("PL", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("PT", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SK", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ES", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GB", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AL", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("HR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("EG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IQ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IL", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("JO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KW", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LB", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LS", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MK", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("OM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("QA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("RO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("RU", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SN", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("RS", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ME", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ZA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("UA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("YE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ZW", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BD", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CN", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("HK", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AT", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CY", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("DK", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("EE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("FI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("FR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("DE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("HU", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IS", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IT", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LV", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LT", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LU", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MT", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MC", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NL", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("PL", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("PT", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SK", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ES", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GB", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("AL", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("AZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("HR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("EG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IQ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IL", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("JO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KW", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LB", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LS", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MK", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("OM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("QA", RTW89_QATAR, RTW89_QATAR), ++ COUNTRY_REGD("RO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("RU", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SN", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("RS", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ME", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ZA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("UA", RTW89_UKRAINE, RTW89_UKRAINE), ++ COUNTRY_REGD("AE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("YE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ZW", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BD", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CN", RTW89_CN, RTW89_CN), ++ COUNTRY_REGD("HK", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IN", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("ID", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("KR", RTW89_KCC, RTW89_KCC), +- COUNTRY_REGD("MY", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("PK", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("PH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MY", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("PK", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("PH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LK", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("TW", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("TH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("VN", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AU", RTW89_WW, RTW89_ACMA), +- COUNTRY_REGD("NZ", RTW89_WW, RTW89_ACMA), +- COUNTRY_REGD("PG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("VN", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("AU", RTW89_ACMA, RTW89_ACMA), ++ COUNTRY_REGD("NZ", RTW89_ACMA, RTW89_ACMA), ++ COUNTRY_REGD("PG", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("CA", RTW89_IC, RTW89_IC), + COUNTRY_REGD("JP", RTW89_MKK, RTW89_MKK), +- COUNTRY_REGD("JM", RTW89_WW, RTW89_FCC), ++ COUNTRY_REGD("JM", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("AN", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("TT", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("TN", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("TN", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("AF", RTW89_ETSI, RTW89_ETSI), +- COUNTRY_REGD("DZ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DZ", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("AS", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("AD", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("AQ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AD", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("AO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("AI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("AQ", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("AG", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("AM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("AM", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("AW", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("BS", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("BB", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("BY", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BY", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("BZ", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("BJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BJ", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("BM", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("BT", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BW", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BV", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BT", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BW", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BV", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IO", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("VG", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("BN", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BF", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("BI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CV", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("BN", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("BI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CV", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("KY", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("CF", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TD", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CX", RTW89_WW, RTW89_ACMA), +- COUNTRY_REGD("CC", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CD", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("CK", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("CF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TD", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CX", RTW89_ACMA, RTW89_ACMA), ++ COUNTRY_REGD("CC", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CD", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("CK", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("CI", RTW89_ETSI, RTW89_ETSI), +- COUNTRY_REGD("DJ", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("DJ", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("DM", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("GQ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ER", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ET", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("FK", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("FO", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GQ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ER", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ET", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("FK", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("FO", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("FJ", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("GF", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("PF", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TF", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GL", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("PF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GL", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("GD", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("GP", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("GP", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("GU", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("GG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GN", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GW", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GY", RTW89_FCC, RTW89_NCC), ++ COUNTRY_REGD("GG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GN", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GW", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GY", RTW89_NCC, RTW89_NCC), + COUNTRY_REGD("HT", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("HM", RTW89_WW, RTW89_ACMA), +- COUNTRY_REGD("VA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("JE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("KI", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LA", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("LY", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MW", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MV", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ML", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("HM", RTW89_ACMA, RTW89_ACMA), ++ COUNTRY_REGD("VA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("JE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("KI", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LA", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("LY", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MW", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MV", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ML", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("MH", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("MQ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MU", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("YT", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("MQ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MU", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("YT", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("FM", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("MD", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MN", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("MS", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NR", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NP", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NC", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("NU", RTW89_WW, RTW89_ACMA), +- COUNTRY_REGD("NF", RTW89_WW, RTW89_ACMA), ++ COUNTRY_REGD("MD", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MN", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("MS", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NP", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NC", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("NU", RTW89_ACMA, RTW89_ACMA), ++ COUNTRY_REGD("NF", RTW89_ACMA, RTW89_ACMA), + COUNTRY_REGD("MP", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("PW", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("RE", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("RW", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SH", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("RE", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("RW", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SH", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("KN", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("LC", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("MF", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("SX", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("PM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("PM", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("VC", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("WS", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("SM", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SM", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("ST", RTW89_FCC, RTW89_FCC), + COUNTRY_REGD("SC", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("SL", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SB", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("GS", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SL", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SB", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("GS", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("SR", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("SJ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("SZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TJ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TG", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TK", RTW89_WW, RTW89_ACMA), +- COUNTRY_REGD("TO", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("TC", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("SJ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("SZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TJ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TG", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TK", RTW89_ACMA, RTW89_ACMA), ++ COUNTRY_REGD("TO", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("TC", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("TV", RTW89_ETSI, RTW89_NA), +- COUNTRY_REGD("UG", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("UG", RTW89_ETSI, RTW89_ETSI), + COUNTRY_REGD("VI", RTW89_FCC, RTW89_FCC), +- COUNTRY_REGD("UZ", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("VU", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("WF", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("EH", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("ZM", RTW89_WW, RTW89_ETSI), +- COUNTRY_REGD("IR", RTW89_WW, RTW89_ETSI), ++ COUNTRY_REGD("UZ", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("VU", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("WF", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("EH", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("ZM", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("IR", RTW89_ETSI, RTW89_ETSI), ++ COUNTRY_REGD("PS", RTW89_ETSI, RTW89_ETSI), + }; + + static const struct rtw89_regulatory *rtw89_regd_find_reg_by_name(char *alpha2) +-- +2.13.6 + diff --git a/SOURCES/0015-rtw89-remove-unnecessary-conditional-operators.patch b/SOURCES/0015-rtw89-remove-unnecessary-conditional-operators.patch new file mode 100644 index 0000000..f777780 --- /dev/null +++ b/SOURCES/0015-rtw89-remove-unnecessary-conditional-operators.patch @@ -0,0 +1,92 @@ +From 32bb5a6874a7ee13bc39d76e9629b75accfd0afe Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 15/36] rtw89: remove unnecessary conditional operators +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 1646ce8f83b953a675cb99e7b6708d8121b5fecf +Author: Ye Guojin +Date: Thu Nov 4 06:11:19 2021 +0000 + + rtw89: remove unnecessary conditional operators + + The conditional operator is unnecessary while assigning values to the + bool variables. + + Reported-by: Zeal Robot + Signed-off-by: Ye Guojin + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211104061119.1685-1-ye.guojin@zte.com.cn + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/debug.c | 2 +- + drivers/net/wireless/realtek/rtw89/mac.c | 2 +- + drivers/net/wireless/realtek/rtw89/phy.c | 2 +- + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 4 ++-- + 4 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c +index 29eb188c888c..75f10627585b 100644 +--- a/drivers/net/wireless/realtek/rtw89/debug.c ++++ b/drivers/net/wireless/realtek/rtw89/debug.c +@@ -814,7 +814,7 @@ rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, + return -EINVAL; + } + +- enable = set == 0 ? false : true; ++ enable = set != 0; + switch (sel) { + case 0: + debugfs_priv->dbgpkg_en.ss_dbg = enable; +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index afcd07ab1de7..944c23293cb9 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -3695,7 +3695,7 @@ void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) + { + struct rtw89_traffic_stats *stats = &rtwdev->stats; + struct rtw89_vif *rtwvif; +- bool en = stats->tx_tfc_lv > stats->rx_tfc_lv ? false : true; ++ bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; + bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); + + if (en == old) +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +index 0620ef02e275..abb4cdcd03e7 100644 +--- a/drivers/net/wireless/realtek/rtw89/phy.c ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -1779,7 +1779,7 @@ static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) + } + rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); + cfo->cfo_avg_pre = new_cfo; +- x_cap_update = cfo->crystal_cap == pre_x_cap ? false : true; ++ x_cap_update = cfo->crystal_cap != pre_x_cap; + rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); + rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", + cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +index 5c6ffca3a324..9e25e53f6c4a 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -1053,10 +1053,10 @@ static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, + struct rtw89_channel_params *param, + enum rtw89_phy_idx phy_idx) + { +- bool cck_en = param->center_chan > 14 ? false : true; ++ bool cck_en = param->center_chan <= 14; + u8 pri_ch_idx = param->pri_ch_idx; + +- if (param->center_chan <= 14) ++ if (cck_en) + rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan, + param->primary_chan, param->bandwidth); + +-- +2.13.6 + diff --git a/SOURCES/0016-rtw89-remove-unneeded-variable.patch b/SOURCES/0016-rtw89-remove-unneeded-variable.patch new file mode 100644 index 0000000..1ef81ba --- /dev/null +++ b/SOURCES/0016-rtw89-remove-unneeded-variable.patch @@ -0,0 +1,56 @@ +From 05f245f4d2fa4441a1cdf959dcb7c935a6274018 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 16/36] rtw89: remove unneeded variable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 43863efeada6eda380bd08537d1e4719341dc50d +Author: Changcheng Deng +Date: Wed Nov 10 12:11:35 2021 +0000 + + rtw89: remove unneeded variable + + Fix the following coccicheck review: + ./drivers/net/wireless/realtek/rtw89/mac.c: 1096: 5-8: Unneeded variable + + Remove unneeded variable used to store return value. + + Reported-by: Zeal Robot + Signed-off-by: Changcheng Deng + Acked-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211110121135.151187-1-deng.changcheng@zte.com.cn + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/mac.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index 944c23293cb9..f8389e849c67 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -1093,7 +1093,6 @@ static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) + static int dmac_func_en(struct rtw89_dev *rtwdev) + { + u32 val32; +- u32 ret = 0; + + val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MAC_SEC_EN | + B_AX_DISPATCHER_EN | B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | +@@ -1107,7 +1106,7 @@ static int dmac_func_en(struct rtw89_dev *rtwdev) + B_AX_WD_RLS_CLK_EN); + rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); + +- return ret; ++ return 0; + } + + static int chip_func_en(struct rtw89_dev *rtwdev) +-- +2.13.6 + diff --git a/SOURCES/0017-rtw89-fix-potentially-access-out-of-range-of-RF-regi.patch b/SOURCES/0017-rtw89-fix-potentially-access-out-of-range-of-RF-regi.patch new file mode 100644 index 0000000..b506a21 --- /dev/null +++ b/SOURCES/0017-rtw89-fix-potentially-access-out-of-range-of-RF-regi.patch @@ -0,0 +1,98 @@ +From 5e753fef71954c833fa859b2e48e57874500a2fd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 17/36] rtw89: fix potentially access out of range of RF + register array +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 30101812a09b37bc8aa409a83f603d4c072198f2 +Author: Ping-Ke Shih +Date: Fri Nov 19 13:57:29 2021 +0800 + + rtw89: fix potentially access out of range of RF register array + + The RF register array is used to help firmware to restore RF settings. + The original code can potentially access out of range, if the size is + between (RTW89_H2C_RF_PAGE_SIZE * RTW89_H2C_RF_PAGE_NUM + 1) to + ((RTW89_H2C_RF_PAGE_SIZE + 1) * RTW89_H2C_RF_PAGE_NUM). Fortunately, + current used size doesn't fall into the wrong case, and the size will not + change if we don't update RF parameter. + + Reported-by: Dan Carpenter + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211119055729.12826-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/phy.c | 33 ++++++++++++++++++-------------- + 1 file changed, 19 insertions(+), 14 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +index abb4cdcd03e7..312d9a07599d 100644 +--- a/drivers/net/wireless/realtek/rtw89/phy.c ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -654,6 +654,12 @@ rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, + u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; + u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; + ++ if (page >= RTW89_H2C_RF_PAGE_NUM) { ++ rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", ++ rf_path, info->curr_idx); ++ return; ++ } ++ + info->rtw89_phy_config_rf_h2c[page][idx] = + cpu_to_le32((reg->addr << 20) | reg->data); + info->curr_idx++; +@@ -662,30 +668,29 @@ rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, + static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, + struct rtw89_fw_h2c_rf_reg_info *info) + { +- u16 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; +- u16 len = (info->curr_idx % RTW89_H2C_RF_PAGE_SIZE) * 4; ++ u16 remain = info->curr_idx; ++ u16 len = 0; + u8 i; + int ret = 0; + +- if (page > RTW89_H2C_RF_PAGE_NUM) { ++ if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { + rtw89_warn(rtwdev, +- "rf reg h2c total page num %d larger than %d (RTW89_H2C_RF_PAGE_NUM)\n", +- page, RTW89_H2C_RF_PAGE_NUM); +- return -EINVAL; ++ "rf reg h2c total len %d larger than %d\n", ++ remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); ++ ret = -EINVAL; ++ goto out; + } + +- for (i = 0; i < page; i++) { +- ret = rtw89_fw_h2c_rf_reg(rtwdev, info, +- RTW89_H2C_RF_PAGE_SIZE * 4, i); ++ for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { ++ len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; ++ ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); + if (ret) +- return ret; ++ goto out; + } +- ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len, i); +- if (ret) +- return ret; ++out: + info->curr_idx = 0; + +- return 0; ++ return ret; + } + + static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, +-- +2.13.6 + diff --git a/SOURCES/0018-rtw89-add-AXIDMA-and-TX-FIFO-dump-in-mac_mem_dump.patch b/SOURCES/0018-rtw89-add-AXIDMA-and-TX-FIFO-dump-in-mac_mem_dump.patch new file mode 100644 index 0000000..76803b7 --- /dev/null +++ b/SOURCES/0018-rtw89-add-AXIDMA-and-TX-FIFO-dump-in-mac_mem_dump.patch @@ -0,0 +1,97 @@ +From f97fbc5fb6e05ce555777c234f31b70fff32c8dc Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 18/36] rtw89: add AXIDMA and TX FIFO dump in mac_mem_dump +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 5da7075c1126f70578a111b8ea64d93f56bc84dd +Author: Chia-Yuan Li +Date: Mon Nov 22 10:11:29 2021 +0800 + + rtw89: add AXIDMA and TX FIFO dump in mac_mem_dump + + The AXIDMA is tx/rx packet transmission between PCIE host + and device, and TX FIFO is MAC TX data. + We dump them to verify that these memory buffers are correct. + + Signed-off-by: Chia-Yuan Li + Signed-off-by: Ping-Ke Shih + Reviewed-by: Larry Finger + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211122021129.4339-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/debug.c | 5 +++++ + drivers/net/wireless/realtek/rtw89/mac.h | 10 ++++++++++ + 2 files changed, 15 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c +index 75f10627585b..1e85808aaf4b 100644 +--- a/drivers/net/wireless/realtek/rtw89/debug.c ++++ b/drivers/net/wireless/realtek/rtw89/debug.c +@@ -723,6 +723,7 @@ rtw89_debug_priv_mac_mem_dump_select(struct file *filp, + } + + static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { ++ [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, + [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, + [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, + [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, +@@ -735,6 +736,10 @@ static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { + [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, + [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, + [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, ++ [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, ++ [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, ++ [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, ++ [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, + }; + + static void rtw89_debug_dump_mac_mem(struct seq_file *m, +diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h +index 6f3db8a2a9c2..94cd29bd83d7 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.h ++++ b/drivers/net/wireless/realtek/rtw89/mac.h +@@ -227,6 +227,7 @@ enum rtw89_mac_dbg_port_sel { + /* SRAM mem dump */ + #define R_AX_INDIR_ACCESS_ENTRY 0x40000 + ++#define AXIDMA_BASE_ADDR 0x18006000 + #define STA_SCHED_BASE_ADDR 0x18808000 + #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 + #define SECURITY_CAM_BASE_ADDR 0x18814000 +@@ -240,10 +241,15 @@ enum rtw89_mac_dbg_port_sel { + #define DMAC_TBL_BASE_ADDR 0x18800000 + #define SHCUT_MACHDR_BASE_ADDR 0x18800800 + #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 ++#define TXD_FIFO_0_BASE_ADDR 0x18856200 ++#define TXD_FIFO_1_BASE_ADDR 0x188A1080 ++#define TXDATA_FIFO_0_BASE_ADDR 0x18856000 ++#define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 + + #define CCTL_INFO_SIZE 32 + + enum rtw89_mac_mem_sel { ++ RTW89_MAC_MEM_AXIDMA, + RTW89_MAC_MEM_SHARED_BUF, + RTW89_MAC_MEM_DMAC_TBL, + RTW89_MAC_MEM_SHCUT_MACHDR, +@@ -256,6 +262,10 @@ enum rtw89_mac_mem_sel { + RTW89_MAC_MEM_BA_CAM, + RTW89_MAC_MEM_BCN_IE_CAM0, + RTW89_MAC_MEM_BCN_IE_CAM1, ++ RTW89_MAC_MEM_TXD_FIFO_0, ++ RTW89_MAC_MEM_TXD_FIFO_1, ++ RTW89_MAC_MEM_TXDATA_FIFO_0, ++ RTW89_MAC_MEM_TXDATA_FIFO_1, + + /* keep last */ + RTW89_MAC_MEM_LAST, +-- +2.13.6 + diff --git a/SOURCES/0019-rtw89-add-const-in-the-cast-of-le32_get_bits.patch b/SOURCES/0019-rtw89-add-const-in-the-cast-of-le32_get_bits.patch new file mode 100644 index 0000000..4e5ef14 --- /dev/null +++ b/SOURCES/0019-rtw89-add-const-in-the-cast-of-le32_get_bits.patch @@ -0,0 +1,239 @@ +From 2cdc98b8d11857fee31fd79f8b15bf04f76e0f78 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 19/36] rtw89: add const in the cast of le32_get_bits() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 321e763ccc5260364600b4facd9e9acf645949b2 +Author: Ping-Ke Shih +Date: Fri Nov 19 13:45:11 2021 +0800 + + rtw89: add const in the cast of le32_get_bits() + + Add 'const' to be clear that this is a read-only access, and this patch + doesn't change logic at all. + + Signed-off-by: Ping-Ke Shih + Tested-by: Takashi Iwai + Tested-by: Larry Finger + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211119054512.10620-3-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/fw.h | 68 +++++++++++++++---------------- + drivers/net/wireless/realtek/rtw89/txrx.h | 46 ++++++++++----------- + 2 files changed, 57 insertions(+), 57 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +index 36e8d0da6c1e..2a9953d1ae0c 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.h ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -252,36 +252,36 @@ struct rtw89_h2creg_sch_tx_en { + #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) + + #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 0)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) + #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(28)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) + #define GET_FWSECTION_HDR_REDL(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(29)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) + #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr)), GENMASK(31, 0)) ++ le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) + + #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(7, 0)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) + #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) + #define GET_FW_HDR_SUBVERSION(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) + #define GET_FW_HDR_SUBINDEX(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(31, 24)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) + #define GET_FW_HDR_MONTH(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(7, 0)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) + #define GET_FW_HDR_DATE(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) + #define GET_FW_HDR_HOUR(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) + #define GET_FW_HDR_MIN(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(31, 24)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) + #define GET_FW_HDR_YEAR(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 5), GENMASK(31, 0)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) + #define GET_FW_HDR_SEC_NUM(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 6), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) + #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ +- le32_get_bits(*((__le32 *)(fwhdr) + 7), GENMASK(31, 24)) ++ le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) + static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) + { + le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); +@@ -1170,49 +1170,49 @@ enum rtw89_btc_cxdrvinfo { + #define RTW89_C2H_HEADER_LEN 8 + + #define RTW89_GET_C2H_CATEGORY(c2h) \ +- le32_get_bits(*((__le32 *)c2h), GENMASK(1, 0)) ++ le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) + #define RTW89_GET_C2H_CLASS(c2h) \ +- le32_get_bits(*((__le32 *)c2h), GENMASK(7, 2)) ++ le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) + #define RTW89_GET_C2H_FUNC(c2h) \ +- le32_get_bits(*((__le32 *)c2h), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) + #define RTW89_GET_C2H_LEN(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 1), GENMASK(13, 0)) ++ le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) + + #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) + #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) + + #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) + #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) + #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) + #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) + #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(31, 24)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) + + #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) + #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) + #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) + #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) + + #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 0)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) + #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) + #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(6, 0)) ++ le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) + #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(9, 8)) ++ le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) + #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(12, 10)) ++ le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) + #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ +- le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(14, 13)) ++ le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) + + /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS + * HT-new: [6:5]: NA, [4:0]: MCS +diff --git a/drivers/net/wireless/realtek/rtw89/txrx.h b/drivers/net/wireless/realtek/rtw89/txrx.h +index f1e0fe36107d..5570d8ccf136 100644 +--- a/drivers/net/wireless/realtek/rtw89/txrx.h ++++ b/drivers/net/wireless/realtek/rtw89/txrx.h +@@ -140,52 +140,52 @@ + le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) + + #define RTW89_GET_RXINFO_USR_NUM(rpt) \ +- le32_get_bits(*((__le32 *)rpt), GENMASK(3, 0)) ++ le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0)) + #define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ +- le32_get_bits(*((__le32 *)rpt), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8)) + #define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ +- le32_get_bits(*((__le32 *)rpt), GENMASK(27, 16)) ++ le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16)) + #define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ +- le32_get_bits(*((__le32 *)rpt), BIT(28)) ++ le32_get_bits(*((const __le32 *)rpt), BIT(28)) + #define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ +- le32_get_bits(*((__le32 *)rpt), BIT(29)) ++ le32_get_bits(*((const __le32 *)rpt), BIT(29)) + #define RTW89_GET_RXINFO_LONG_RXD(rpt) \ +- le32_get_bits(*((__le32 *)rpt), GENMASK(31, 30)) ++ le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30)) + #define RTW89_GET_RXINFO_SERVICE(rpt) \ +- le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(15, 0)) ++ le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0)) + #define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ +- le32_get_bits(*((__le32 *)(rpt) + 1), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16)) + #define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ +- le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(0)) ++ le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0)) + #define RTW89_GET_RXINFO_DATA(rpt, usr) \ +- le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(1)) ++ le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1)) + #define RTW89_GET_RXINFO_CTRL(rpt, usr) \ +- le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(2)) ++ le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2)) + #define RTW89_GET_RXINFO_MGMT(rpt, usr) \ +- le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(3)) ++ le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3)) + #define RTW89_GET_RXINFO_BCM(rpt, usr) \ +- le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), BIT(4)) ++ le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4)) + #define RTW89_GET_RXINFO_MACID(rpt, usr) \ +- le32_get_bits(*((__le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) + + #define RTW89_GET_PHY_STS_RSSI_A(sts) \ +- le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(7, 0)) ++ le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0)) + #define RTW89_GET_PHY_STS_RSSI_B(sts) \ +- le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8)) + #define RTW89_GET_PHY_STS_RSSI_C(sts) \ +- le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(23, 16)) ++ le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16)) + #define RTW89_GET_PHY_STS_RSSI_D(sts) \ +- le32_get_bits(*((__le32 *)(sts) + 1), GENMASK(31, 24)) ++ le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24)) + #define RTW89_GET_PHY_STS_LEN(sts) \ +- le32_get_bits(*((__le32 *)sts), GENMASK(15, 8)) ++ le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8)) + #define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ +- le32_get_bits(*((__le32 *)sts), GENMASK(31, 24)) ++ le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24)) + #define RTW89_GET_PHY_STS_IE_TYPE(ie) \ +- le32_get_bits(*((__le32 *)ie), GENMASK(4, 0)) ++ le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0)) + #define RTW89_GET_PHY_STS_IE_LEN(ie) \ +- le32_get_bits(*((__le32 *)ie), GENMASK(11, 5)) ++ le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5)) + #define RTW89_GET_PHY_STS_IE0_CFO(ie) \ +- le32_get_bits(*((__le32 *)(ie) + 1), GENMASK(31, 20)) ++ le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20)) + + enum rtw89_tx_channel { + RTW89_TXCH_ACH0 = 0, +-- +2.13.6 + diff --git a/SOURCES/0020-rtw89-use-inline-function-instead-macro-to-set-H2C-a.patch b/SOURCES/0020-rtw89-use-inline-function-instead-macro-to-set-H2C-a.patch new file mode 100644 index 0000000..3530cf6 --- /dev/null +++ b/SOURCES/0020-rtw89-use-inline-function-instead-macro-to-set-H2C-a.patch @@ -0,0 +1,2726 @@ +From fcd09e74bd70cae75e59f9cdda3b49fc49656ad0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 20/36] rtw89: use inline function instead macro to set H2C and + CAM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 00224aa70891ec4cdca54100674e0ca201535f84 +Author: Ping-Ke Shih +Date: Fri Nov 19 13:45:12 2021 +0800 + + rtw89: use inline function instead macro to set H2C and CAM + + In order to use compiler to check if we do improper cast of const* on + arguments of inline function. + + Signed-off-by: Ping-Ke Shih + Tested-by: Takashi Iwai + Tested-by: Larry Finger + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211119054512.10620-4-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/cam.h | 468 +++++-- + drivers/net/wireless/realtek/rtw89/fw.h | 2099 ++++++++++++++++++------------ + 2 files changed, 1593 insertions(+), 974 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/cam.h b/drivers/net/wireless/realtek/rtw89/cam.h +index 90a20a5375c6..41d7d2712027 100644 +--- a/drivers/net/wireless/realtek/rtw89/cam.h ++++ b/drivers/net/wireless/realtek/rtw89/cam.h +@@ -9,140 +9,340 @@ + + #define RTW89_SEC_CAM_LEN 20 + +-#define FWCMD_SET_ADDR_IDX(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_OFFSET(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_LEN(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_VALID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0)) +-#define FWCMD_SET_ADDR_NET_TYPE(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)) +-#define FWCMD_SET_ADDR_BCN_HIT_COND(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3)) +-#define FWCMD_SET_ADDR_HIT_RULE(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5)) +-#define FWCMD_SET_ADDR_BB_SEL(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(7)) +-#define FWCMD_SET_ADDR_ADDR_MASK(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8)) +-#define FWCMD_SET_ADDR_MASK_SEL(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(15, 14)) +-#define FWCMD_SET_ADDR_SMA_HASH(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_TMA_HASH(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0)) +-#define FWCMD_SET_ADDR_SMA0(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_SMA1(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_SMA2(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_SMA3(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_SMA4(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_SMA5(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_TMA0(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_TMA1(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_TMA2(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_TMA3(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_TMA4(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_TMA5(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_MACID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_PORT_INT(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(10, 8)) +-#define FWCMD_SET_ADDR_TSF_SYNC(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(13, 11)) +-#define FWCMD_SET_ADDR_TF_TRS(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(14)) +-#define FWCMD_SET_ADDR_LSIG_TXOP(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(15)) +-#define FWCMD_SET_ADDR_TGT_IND(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(26, 24)) +-#define FWCMD_SET_ADDR_FRM_TGT_IND(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(29, 27)) +-#define FWCMD_SET_ADDR_AID12(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 0)) +-#define FWCMD_SET_ADDR_AID12_0(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_AID12_1(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 8)) +-#define FWCMD_SET_ADDR_WOL_PATTERN(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(12)) +-#define FWCMD_SET_ADDR_WOL_UC(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(13)) +-#define FWCMD_SET_ADDR_WOL_MAGIC(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(14)) +-#define FWCMD_SET_ADDR_WAPI(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(15)) +-#define FWCMD_SET_ADDR_SEC_ENT_MODE(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(17, 16)) +-#define FWCMD_SET_ADDR_SEC_ENT0_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(19, 18)) +-#define FWCMD_SET_ADDR_SEC_ENT1_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(21, 20)) +-#define FWCMD_SET_ADDR_SEC_ENT2_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(23, 22)) +-#define FWCMD_SET_ADDR_SEC_ENT3_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(25, 24)) +-#define FWCMD_SET_ADDR_SEC_ENT4_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(27, 26)) +-#define FWCMD_SET_ADDR_SEC_ENT5_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(29, 28)) +-#define FWCMD_SET_ADDR_SEC_ENT6_KEYID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(31, 30)) +-#define FWCMD_SET_ADDR_SEC_ENT_VALID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_SEC_ENT0(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_SEC_ENT1(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_SEC_ENT2(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_SEC_ENT3(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_SEC_ENT4(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_SEC_ENT5(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_SEC_ENT6(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_BSSID_IDX(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_BSSID_OFFSET(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_BSSID_LEN(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_BSSID_VALID(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(0)) +-#define FWCMD_SET_ADDR_BSSID_BB_SEL(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(1)) +-#define FWCMD_SET_ADDR_BSSID_BSS_COLOR(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(13, 8)) +-#define FWCMD_SET_ADDR_BSSID_BSSID0(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_BSSID_BSSID1(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(31, 24)) +-#define FWCMD_SET_ADDR_BSSID_BSSID2(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(7, 0)) +-#define FWCMD_SET_ADDR_BSSID_BSSID3(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(15, 8)) +-#define FWCMD_SET_ADDR_BSSID_BSSID4(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(23, 16)) +-#define FWCMD_SET_ADDR_BSSID_BSSID5(cmd, value) \ +- le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(31, 24)) ++static inline void FWCMD_SET_ADDR_IDX(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_OFFSET(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_LEN(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_VALID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0)); ++} ++ ++static inline void FWCMD_SET_ADDR_NET_TYPE(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)); ++} ++ ++static inline void FWCMD_SET_ADDR_BCN_HIT_COND(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3)); ++} ++ ++static inline void FWCMD_SET_ADDR_HIT_RULE(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5)); ++} ++ ++static inline void FWCMD_SET_ADDR_BB_SEL(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(7)); ++} ++ ++static inline void FWCMD_SET_ADDR_ADDR_MASK(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_MASK_SEL(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(15, 14)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA_HASH(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA_HASH(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_CAM_IDX(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA0(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA1(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA2(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA3(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA4(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_SMA5(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA0(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA1(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 5, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA2(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA3(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA4(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_TMA5(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 6, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_MACID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_PORT_INT(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(10, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_TSF_SYNC(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(13, 11)); ++} ++ ++static inline void FWCMD_SET_ADDR_TF_TRS(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(14)); ++} ++ ++static inline void FWCMD_SET_ADDR_LSIG_TXOP(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, BIT(15)); ++} ++ ++static inline void FWCMD_SET_ADDR_TGT_IND(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(26, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_FRM_TGT_IND(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 8, value, GENMASK(29, 27)); ++} ++ ++static inline void FWCMD_SET_ADDR_AID12(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_AID12_0(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_AID12_1(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(11, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_WOL_PATTERN(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(12)); ++} ++ ++static inline void FWCMD_SET_ADDR_WOL_UC(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(13)); ++} ++ ++static inline void FWCMD_SET_ADDR_WOL_MAGIC(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(14)); ++} ++ ++static inline void FWCMD_SET_ADDR_WAPI(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, BIT(15)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT_MODE(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(17, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT0_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(19, 18)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT1_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(21, 20)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT2_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(23, 22)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT3_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(25, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT4_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(27, 26)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT5_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(29, 28)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT6_KEYID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 9, value, GENMASK(31, 30)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT_VALID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT0(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT1(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT2(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 10, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT3(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT4(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT5(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_SEC_ENT6(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 11, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_IDX(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_OFFSET(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_LEN(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 12, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_VALID(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(0)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BB_SEL(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, BIT(1)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSS_COLOR(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(13, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSSID0(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSSID1(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 13, value, GENMASK(31, 24)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSSID2(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(7, 0)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSSID3(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(15, 8)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSSID4(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(23, 16)); ++} ++ ++static inline void FWCMD_SET_ADDR_BSSID_BSSID5(void *cmd, u32 value) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 14, value, GENMASK(31, 24)); ++} + + int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); + void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +index 2a9953d1ae0c..cf6898f7aaee 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.h ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -156,96 +156,225 @@ struct rtw89_h2creg_sch_tx_en { + u16 rsvd:15; + } __packed; + +-#define RTW89_SET_FWCMD_RA_IS_DIS(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)) +-#define RTW89_SET_FWCMD_RA_MODE(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)) +-#define RTW89_SET_FWCMD_RA_BW_CAP(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)) +-#define RTW89_SET_FWCMD_RA_MACID(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) +-#define RTW89_SET_FWCMD_RA_DCM(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)) +-#define RTW89_SET_FWCMD_RA_ER(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)) +-#define RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)) +-#define RTW89_SET_FWCMD_RA_UPD_ALL(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)) +-#define RTW89_SET_FWCMD_RA_SGI(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)) +-#define RTW89_SET_FWCMD_RA_LDPC(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)) +-#define RTW89_SET_FWCMD_RA_STBC(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)) +-#define RTW89_SET_FWCMD_RA_SS_NUM(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)) +-#define RTW89_SET_FWCMD_RA_GILTF(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)) +-#define RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)) +-#define RTW89_SET_FWCMD_RA_UPD_MASK(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)) +-#define RTW89_SET_FWCMD_RA_MASK_0(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_RA_MASK_1(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)) +-#define RTW89_SET_FWCMD_RA_MASK_2(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)) +-#define RTW89_SET_FWCMD_RA_MASK_3(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)) +-#define RTW89_SET_FWCMD_RA_MASK_4(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)) +-#define RTW89_SET_FWCMD_RA_BAND_NUM(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)) +-#define RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)) +-#define RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)) +-#define RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)) +-#define RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)) +-#define RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)) +-#define RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)) +- +-#define RTW89_SET_FWCMD_SEC_IDX(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_SEC_OFFSET(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) +-#define RTW89_SET_FWCMD_SEC_LEN(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)) +-#define RTW89_SET_FWCMD_SEC_TYPE(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)) +-#define RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)) +-#define RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)) +-#define RTW89_SET_FWCMD_SEC_KEY0(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)) +-#define RTW89_SET_FWCMD_SEC_KEY1(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)) +-#define RTW89_SET_FWCMD_SEC_KEY2(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)) +-#define RTW89_SET_FWCMD_SEC_KEY3(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)) +- +-#define RTW89_SET_EDCA_SEL(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)) +-#define RTW89_SET_EDCA_BAND(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)) +-#define RTW89_SET_EDCA_WMM(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)) +-#define RTW89_SET_EDCA_AC(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)) +-#define RTW89_SET_EDCA_PARAM(cmd, val) \ +- le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)) ++static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); ++} ++ ++static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); ++} ++ ++static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); ++} ++ ++static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); ++} ++ ++static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); ++} ++ ++static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); ++} ++ ++static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); ++} + #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) + #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) + #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) +@@ -287,732 +416,865 @@ static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) + le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); + } + +-#define SET_CTRL_INFO_MACID(table, val) \ +- le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)) +-#define SET_CTRL_INFO_OPERATION(table, val) \ +- le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)) ++static inline void SET_CTRL_INFO_MACID(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); ++} ++ ++static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); ++} + #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) +-#define SET_CMC_TBL_DATARATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, \ +- GENMASK(8, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, ++ GENMASK(8, 0)); ++} + #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) +-#define SET_CMC_TBL_FORCE_TXOP(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, \ +- BIT(9)); \ +-} while (0) ++static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, ++ BIT(9)); ++} + #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) +-#define SET_CMC_TBL_DATA_BW(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, \ +- GENMASK(11, 10)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, ++ GENMASK(11, 10)); ++} + #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) +-#define SET_CMC_TBL_DATA_GI_LTF(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, \ +- GENMASK(14, 12)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, ++ GENMASK(14, 12)); ++} + #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) +-#define SET_CMC_TBL_DARF_TC_INDEX(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, \ +- BIT(15)); \ +-} while (0) ++static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, ++ BIT(15)); ++} + #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) +-#define SET_CMC_TBL_ARFR_CTRL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, \ +- GENMASK(19, 16)); \ +-} while (0) ++static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, ++ GENMASK(19, 16)); ++} + #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) +-#define SET_CMC_TBL_ACQ_RPT_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, \ +- BIT(20)); \ +-} while (0) ++static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, ++ BIT(20)); ++} + #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) +-#define SET_CMC_TBL_MGQ_RPT_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, \ +- BIT(21)); \ +-} while (0) ++static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, ++ BIT(21)); ++} + #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) +-#define SET_CMC_TBL_ULQ_RPT_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, \ +- BIT(22)); \ +-} while (0) ++static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, ++ BIT(22)); ++} + #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) +-#define SET_CMC_TBL_TWTQ_RPT_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, \ +- BIT(23)); \ +-} while (0) ++static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, ++ BIT(23)); ++} + #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) +-#define SET_CMC_TBL_DISRTSFB(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, \ +- BIT(25)); \ +-} while (0) ++static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, ++ BIT(25)); ++} + #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) +-#define SET_CMC_TBL_DISDATAFB(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, \ +- BIT(26)); \ +-} while (0) ++static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, ++ BIT(26)); ++} + #define SET_CMC_TBL_MASK_TRYRATE BIT(0) +-#define SET_CMC_TBL_TRYRATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, \ +- BIT(27)); \ +-} while (0) ++static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, ++ BIT(27)); ++} + #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) +-#define SET_CMC_TBL_AMPDU_DENSITY(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); \ +- le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, \ +- GENMASK(31, 28)); \ +-} while (0) ++static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); ++ le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, ++ GENMASK(31, 28)); ++} + #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) +-#define SET_CMC_TBL_DATA_RTY_LOWEST_RATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, \ +- GENMASK(8, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, ++ GENMASK(8, 0)); ++} + #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) +-#define SET_CMC_TBL_AMPDU_TIME_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, \ +- BIT(9)); \ +-} while (0) ++static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, ++ BIT(9)); ++} + #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) +-#define SET_CMC_TBL_AMPDU_LEN_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, \ +- BIT(10)); \ +-} while (0) ++static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, ++ BIT(10)); ++} + #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) +-#define SET_CMC_TBL_RTS_TXCNT_LMT_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, \ +- BIT(11)); \ +-} while (0) ++static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, ++ BIT(11)); ++} + #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) +-#define SET_CMC_TBL_RTS_TXCNT_LMT(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, \ +- GENMASK(15, 12)); \ +-} while (0) ++static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, ++ GENMASK(15, 12)); ++} + #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) +-#define SET_CMC_TBL_RTSRATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, \ +- GENMASK(24, 16)); \ +-} while (0) ++static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, ++ GENMASK(24, 16)); ++} + #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) +-#define SET_CMC_TBL_VCS_STBC(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, \ +- BIT(27)); \ +-} while (0) ++static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, ++ BIT(27)); ++} + #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) +-#define SET_CMC_TBL_RTS_RTY_LOWEST_RATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); \ +- le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, \ +- GENMASK(31, 28)); \ +-} while (0) ++static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); ++ le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, ++ GENMASK(31, 28)); ++} + #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) +-#define SET_CMC_TBL_DATA_TX_CNT_LMT(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, \ +- GENMASK(5, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, ++ GENMASK(5, 0)); ++} + #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) +-#define SET_CMC_TBL_DATA_TXCNT_LMT_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, \ +- BIT(6)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, ++ BIT(6)); ++} + #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) +-#define SET_CMC_TBL_MAX_AGG_NUM_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, \ +- BIT(7)); \ +-} while (0) ++static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, ++ BIT(7)); ++} + #define SET_CMC_TBL_MASK_RTS_EN BIT(0) +-#define SET_CMC_TBL_RTS_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, \ +- BIT(8)); \ +-} while (0) ++static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, ++ BIT(8)); ++} + #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) +-#define SET_CMC_TBL_CTS2SELF_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, \ +- BIT(9)); \ +-} while (0) ++static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, ++ BIT(9)); ++} + #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) +-#define SET_CMC_TBL_CCA_RTS(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, \ +- GENMASK(11, 10)); \ +-} while (0) ++static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, ++ GENMASK(11, 10)); ++} + #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) +-#define SET_CMC_TBL_HW_RTS_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, \ +- BIT(12)); \ +-} while (0) ++static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, ++ BIT(12)); ++} + #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) +-#define SET_CMC_TBL_RTS_DROP_DATA_MODE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, \ +- GENMASK(14, 13)); \ +-} while (0) ++static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, ++ GENMASK(14, 13)); ++} + #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) +-#define SET_CMC_TBL_AMPDU_MAX_LEN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, \ +- GENMASK(26, 16)); \ +-} while (0) ++static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, ++ GENMASK(26, 16)); ++} + #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) +-#define SET_CMC_TBL_UL_MU_DIS(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, \ +- BIT(27)); \ +-} while (0) ++static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, ++ BIT(27)); ++} + #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) +-#define SET_CMC_TBL_AMPDU_MAX_TIME(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); \ +- le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, \ +- GENMASK(31, 28)); \ +-} while (0) ++static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); ++ le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, ++ GENMASK(31, 28)); ++} + #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) +-#define SET_CMC_TBL_MAX_AGG_NUM(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, \ +- GENMASK(7, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, ++ GENMASK(7, 0)); ++} + #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) +-#define SET_CMC_TBL_BA_BMAP(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, \ +- GENMASK(9, 8)); \ +-} while (0) ++static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, ++ GENMASK(9, 8)); ++} + #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) +-#define SET_CMC_TBL_VO_LFTIME_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, \ +- GENMASK(18, 16)); \ +-} while (0) ++static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, ++ GENMASK(18, 16)); ++} + #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) +-#define SET_CMC_TBL_VI_LFTIME_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, \ +- GENMASK(21, 19)); \ +-} while (0) ++static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, ++ GENMASK(21, 19)); ++} + #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) +-#define SET_CMC_TBL_BE_LFTIME_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, \ +- GENMASK(24, 22)); \ +-} while (0) ++static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, ++ GENMASK(24, 22)); ++} + #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) +-#define SET_CMC_TBL_BK_LFTIME_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, \ +- GENMASK(27, 25)); \ +-} while (0) ++static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, ++ GENMASK(27, 25)); ++} + #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) +-#define SET_CMC_TBL_SECTYPE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); \ +- le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, \ +- GENMASK(31, 28)); \ +-} while (0) ++static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); ++ le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, ++ GENMASK(31, 28)); ++} + #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) +-#define SET_CMC_TBL_MULTI_PORT_ID(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, \ +- GENMASK(2, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, ++ GENMASK(2, 0)); ++} + #define SET_CMC_TBL_MASK_BMC BIT(0) +-#define SET_CMC_TBL_BMC(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, \ +- BIT(3)); \ +-} while (0) ++static inline void SET_CMC_TBL_BMC(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, ++ BIT(3)); ++} + #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) +-#define SET_CMC_TBL_MBSSID(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, \ +- GENMASK(7, 4)); \ +-} while (0) ++static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, ++ GENMASK(7, 4)); ++} + #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) +-#define SET_CMC_TBL_NAVUSEHDR(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, \ +- BIT(8)); \ +-} while (0) ++static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, ++ BIT(8)); ++} + #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) +-#define SET_CMC_TBL_TXPWR_MODE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, \ +- GENMASK(11, 9)); \ +-} while (0) ++static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, ++ GENMASK(11, 9)); ++} + #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) +-#define SET_CMC_TBL_DATA_DCM(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, \ +- BIT(12)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, ++ BIT(12)); ++} + #define SET_CMC_TBL_MASK_DATA_ER BIT(0) +-#define SET_CMC_TBL_DATA_ER(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, \ +- BIT(13)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, ++ BIT(13)); ++} + #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) +-#define SET_CMC_TBL_DATA_LDPC(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, \ +- BIT(14)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, ++ BIT(14)); ++} + #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) +-#define SET_CMC_TBL_DATA_STBC(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, \ +- BIT(15)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, ++ BIT(15)); ++} + #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) +-#define SET_CMC_TBL_A_CTRL_BQR(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, \ +- BIT(16)); \ +-} while (0) ++static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, ++ BIT(16)); ++} + #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) +-#define SET_CMC_TBL_A_CTRL_UPH(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, \ +- BIT(17)); \ +-} while (0) ++static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, ++ BIT(17)); ++} + #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) +-#define SET_CMC_TBL_A_CTRL_BSR(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, \ +- BIT(18)); \ +-} while (0) ++static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, ++ BIT(18)); ++} + #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) +-#define SET_CMC_TBL_A_CTRL_CAS(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, \ +- BIT(19)); \ +-} while (0) ++static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, ++ BIT(19)); ++} + #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) +-#define SET_CMC_TBL_DATA_BW_ER(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, \ +- BIT(20)); \ +-} while (0) ++static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, ++ BIT(20)); ++} + #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) +-#define SET_CMC_TBL_LSIG_TXOP_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, \ +- BIT(21)); \ +-} while (0) ++static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, ++ BIT(21)); ++} + #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) +-#define SET_CMC_TBL_CTRL_CNT_VLD(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, \ +- BIT(27)); \ +-} while (0) ++static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, ++ BIT(27)); ++} + #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) +-#define SET_CMC_TBL_CTRL_CNT(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); \ +- le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, \ +- GENMASK(31, 28)); \ +-} while (0) ++static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); ++ le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, ++ GENMASK(31, 28)); ++} + #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) +-#define SET_CMC_TBL_RESP_REF_RATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, \ +- GENMASK(8, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, ++ GENMASK(8, 0)); ++} + #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) +-#define SET_CMC_TBL_ALL_ACK_SUPPORT(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, \ +- BIT(12)); \ +-} while (0) ++static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, ++ BIT(12)); ++} + #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) +-#define SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, \ +- BIT(13)); \ +-} while (0) ++static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, ++ BIT(13)); ++} + #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) +-#define SET_CMC_TBL_NTX_PATH_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, \ +- GENMASK(19, 16)); \ +-} while (0) ++static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, ++ GENMASK(19, 16)); ++} + #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) +-#define SET_CMC_TBL_PATH_MAP_A(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, \ +- GENMASK(21, 20)); \ +-} while (0) ++static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, ++ GENMASK(21, 20)); ++} + #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) +-#define SET_CMC_TBL_PATH_MAP_B(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, \ +- GENMASK(23, 22)); \ +-} while (0) ++static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, ++ GENMASK(23, 22)); ++} + #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) +-#define SET_CMC_TBL_PATH_MAP_C(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, \ +- GENMASK(25, 24)); \ +-} while (0) ++static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, ++ GENMASK(25, 24)); ++} + #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) +-#define SET_CMC_TBL_PATH_MAP_D(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, \ +- GENMASK(27, 26)); \ +-} while (0) ++static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, ++ GENMASK(27, 26)); ++} + #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) +-#define SET_CMC_TBL_ANTSEL_A(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, \ +- BIT(28)); \ +-} while (0) ++static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, ++ BIT(28)); ++} + #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) +-#define SET_CMC_TBL_ANTSEL_B(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, \ +- BIT(29)); \ +-} while (0) ++static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, ++ BIT(29)); ++} + #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) +-#define SET_CMC_TBL_ANTSEL_C(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, \ +- BIT(30)); \ +-} while (0) ++static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, ++ BIT(30)); ++} + #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) +-#define SET_CMC_TBL_ANTSEL_D(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); \ +- le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, \ +- BIT(31)); \ +-} while (0) ++static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); ++ le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, ++ BIT(31)); ++} + #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) +-#define SET_CMC_TBL_ADDR_CAM_INDEX(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, \ +- GENMASK(7, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, ++ GENMASK(7, 0)); ++} + #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) +-#define SET_CMC_TBL_PAID(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, \ +- GENMASK(16, 8)); \ +-} while (0) ++static inline void SET_CMC_TBL_PAID(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, ++ GENMASK(16, 8)); ++} + #define SET_CMC_TBL_MASK_ULDL BIT(0) +-#define SET_CMC_TBL_ULDL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, \ +- BIT(17)); \ +-} while (0) ++static inline void SET_CMC_TBL_ULDL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, ++ BIT(17)); ++} + #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) +-#define SET_CMC_TBL_DOPPLER_CTRL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, \ +- GENMASK(19, 18)); \ +-} while (0) ++static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, ++ GENMASK(19, 18)); ++} + #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) +-#define SET_CMC_TBL_NOMINAL_PKT_PADDING(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ +- GENMASK(21, 20)); \ +-} while (0) +-#define SET_CMC_TBL_NOMINAL_PKT_PADDING40(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ +- GENMASK(23, 22)); \ +-} while (0) ++static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, ++ GENMASK(21, 20)); ++} ++ ++static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, ++ GENMASK(23, 22)); ++} + #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) +-#define SET_CMC_TBL_TXPWR_TOLERENCE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, \ +- GENMASK(27, 24)); \ +-} while (0) +-#define SET_CMC_TBL_NOMINAL_PKT_PADDING80(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); \ +- le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ +- GENMASK(31, 30)); \ +-} while (0) ++static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, ++ GENMASK(27, 24)); ++} ++ ++static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); ++ le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, ++ GENMASK(31, 30)); ++} + #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) +-#define SET_CMC_TBL_NC(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, \ +- GENMASK(2, 0)); \ +-} while (0) ++static inline void SET_CMC_TBL_NC(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, ++ GENMASK(2, 0)); ++} + #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) +-#define SET_CMC_TBL_NR(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, \ +- GENMASK(5, 3)); \ +-} while (0) ++static inline void SET_CMC_TBL_NR(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, ++ GENMASK(5, 3)); ++} + #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) +-#define SET_CMC_TBL_NG(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, \ +- GENMASK(7, 6)); \ +-} while (0) ++static inline void SET_CMC_TBL_NG(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, ++ GENMASK(7, 6)); ++} + #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) +-#define SET_CMC_TBL_CB(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, \ +- GENMASK(9, 8)); \ +-} while (0) ++static inline void SET_CMC_TBL_CB(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, ++ GENMASK(9, 8)); ++} + #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) +-#define SET_CMC_TBL_CS(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, \ +- GENMASK(11, 10)); \ +-} while (0) ++static inline void SET_CMC_TBL_CS(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, ++ GENMASK(11, 10)); ++} + #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) +-#define SET_CMC_TBL_CSI_TXBF_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, \ +- BIT(12)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, ++ BIT(12)); ++} + #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) +-#define SET_CMC_TBL_CSI_STBC_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, \ +- BIT(13)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, ++ BIT(13)); ++} + #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) +-#define SET_CMC_TBL_CSI_LDPC_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, \ +- BIT(14)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, ++ BIT(14)); ++} + #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) +-#define SET_CMC_TBL_CSI_PARA_EN(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, \ +- BIT(15)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, ++ BIT(15)); ++} + #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) +-#define SET_CMC_TBL_CSI_FIX_RATE(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, \ +- GENMASK(24, 16)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, ++ GENMASK(24, 16)); ++} + #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) +-#define SET_CMC_TBL_CSI_GI_LTF(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, \ +- GENMASK(27, 25)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, ++ GENMASK(27, 25)); ++} + #define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0) +-#define SET_CMC_TBL_CSI_GID_SEL(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, \ +- BIT(29)); \ +-} while (0) ++static inline void SET_CMC_TBL_CSI_GID_SEL(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, ++ BIT(29)); ++} + #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) +-#define SET_CMC_TBL_CSI_BW(table, val) \ +-do { \ +- le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); \ +- le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, \ +- GENMASK(31, 30)); \ +-} while (0) +- +-#define SET_FWROLE_MAINTAIN_MACID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) +-#define SET_FWROLE_MAINTAIN_SELF_ROLE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)) +-#define SET_FWROLE_MAINTAIN_UPD_MODE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)) +-#define SET_FWROLE_MAINTAIN_WIFI_ROLE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)) +- +-#define SET_JOININFO_MACID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) +-#define SET_JOININFO_OP(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, BIT(8)) +-#define SET_JOININFO_BAND(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, BIT(9)) +-#define SET_JOININFO_WMM(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)) +-#define SET_JOININFO_TGR(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, BIT(12)) +-#define SET_JOININFO_ISHESTA(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, BIT(13)) +-#define SET_JOININFO_DLBW(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)) +-#define SET_JOININFO_TF_MAC_PAD(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)) +-#define SET_JOININFO_DL_T_PE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)) +-#define SET_JOININFO_PORT_ID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)) +-#define SET_JOININFO_NET_TYPE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)) +-#define SET_JOININFO_WIFI_ROLE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)) +-#define SET_JOININFO_SELF_ROLE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)) +- +-#define SET_GENERAL_PKT_MACID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) +-#define SET_GENERAL_PKT_PROBRSP_ID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) +-#define SET_GENERAL_PKT_PSPOLL_ID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)) +-#define SET_GENERAL_PKT_NULL_ID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) +-#define SET_GENERAL_PKT_QOS_NULL_ID(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)) +-#define SET_GENERAL_PKT_CTS2SELF_ID(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) +- +-#define SET_LOG_CFG_LEVEL(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) +-#define SET_LOG_CFG_PATH(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) +-#define SET_LOG_CFG_COMP(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)) +-#define SET_LOG_CFG_COMP_EXT(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)) +- +-#define SET_BA_CAM_VALID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, BIT(0)) +-#define SET_BA_CAM_INIT_REQ(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, BIT(1)) +-#define SET_BA_CAM_ENTRY_IDX(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)) +-#define SET_BA_CAM_TID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)) +-#define SET_BA_CAM_MACID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) +-#define SET_BA_CAM_BMAP_SIZE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) +-#define SET_BA_CAM_SSN(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)) +- +-#define SET_LPS_PARM_MACID(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) +-#define SET_LPS_PARM_PSMODE(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) +-#define SET_LPS_PARM_RLBM(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) +-#define SET_LPS_PARM_SMARTPS(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)) +-#define SET_LPS_PARM_AWAKEINTERVAL(h2c, val) \ +- le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) +-#define SET_LPS_PARM_VOUAPSD(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)) +-#define SET_LPS_PARM_VIUAPSD(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)) +-#define SET_LPS_PARM_BEUAPSD(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)) +-#define SET_LPS_PARM_BKUAPSD(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)) +-#define SET_LPS_PARM_LASTRPWM(h2c, val) \ +- le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) ++static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); ++ le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, ++ GENMASK(31, 30)); ++} ++ ++static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); ++} ++ ++static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); ++} ++ ++static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); ++} ++ ++static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); ++} ++ ++static inline void SET_JOININFO_MACID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); ++} ++ ++static inline void SET_JOININFO_OP(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(8)); ++} ++ ++static inline void SET_JOININFO_BAND(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(9)); ++} ++ ++static inline void SET_JOININFO_WMM(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); ++} ++ ++static inline void SET_JOININFO_TGR(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(12)); ++} ++ ++static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(13)); ++} ++ ++static inline void SET_JOININFO_DLBW(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); ++} ++ ++static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); ++} ++ ++static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); ++} ++ ++static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); ++} ++ ++static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); ++} ++ ++static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); ++} ++ ++static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); ++} ++ ++static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); ++} ++ ++static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); ++} ++ ++static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); ++} ++ ++static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); ++} ++ ++static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); ++} ++ ++static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); ++} ++ ++static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); ++} ++ ++static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); ++} ++ ++static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); ++} ++ ++static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); ++} ++ ++static inline void SET_BA_CAM_VALID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(0)); ++} ++ ++static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, BIT(1)); ++} ++ ++static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); ++} ++ ++static inline void SET_BA_CAM_TID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); ++} ++ ++static inline void SET_BA_CAM_MACID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); ++} ++ ++static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); ++} ++ ++static inline void SET_BA_CAM_SSN(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); ++} ++ ++static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); ++} ++ ++static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); ++} ++ ++static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); ++} ++ ++static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); ++} ++ ++static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); ++} ++ ++static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); ++} ++ ++static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); ++} ++ ++static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); ++} ++ ++static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); ++} ++ ++static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) ++{ ++ le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); ++} + + enum rtw89_btc_btf_h2c_class { + BTFC_SET = 0x10, +@@ -1054,118 +1316,275 @@ enum rtw89_btc_cxdrvinfo { + CXDRVINFO_MAX, + }; + +-#define RTW89_SET_FWCMD_CXHDR_TYPE(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXHDR_LEN(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)) +- +-#define RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)) +-#define RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)) +-#define RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)) +-#define RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)) +-#define RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)) +-#define RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)) +-#define RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)) +-#define RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)) +-#define RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)) +-#define RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)) +- +-#define RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, val) \ +- u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)) +-#define RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, val) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, val, n) \ +- u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, val, n) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, val, n) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, val, n) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0)) +-#define RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, val, n) \ +- le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0)) +- +-#define RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)) +-#define RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)) +-#define RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)) +-#define RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)) +- +-#define RTW89_SET_FWCMD_CXRFK_STATE(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)) +-#define RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)) +-#define RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)) +-#define RTW89_SET_FWCMD_CXRFK_BAND(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)) +-#define RTW89_SET_FWCMD_CXRFK_TYPE(cmd, val) \ +- le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)) ++static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) ++{ ++ u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n) ++{ ++ u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n) ++{ ++ le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); ++} ++ ++static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) ++{ ++ le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); ++} + + #define RTW89_C2H_HEADER_LEN 8 + +-- +2.13.6 + diff --git a/SOURCES/0021-rtw89-update-scan_mac_addr-during-scanning-period.patch b/SOURCES/0021-rtw89-update-scan_mac_addr-during-scanning-period.patch new file mode 100644 index 0000000..32c83e6 --- /dev/null +++ b/SOURCES/0021-rtw89-update-scan_mac_addr-during-scanning-period.patch @@ -0,0 +1,246 @@ +From 8e579520ae0aa2dc263b033b3ae93339804e6b38 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 21/36] rtw89: update scan_mac_addr during scanning period +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit e45a9e6265d2591efb745c9ffa46f4e9cceb5c65 +Author: Ping-Ke Shih +Date: Thu Nov 11 10:37:05 2021 +0800 + + rtw89: update scan_mac_addr during scanning period + + Update scan_mac_addr to address CAM as A1, so hardware can ACK probe + response properly. + + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211111023706.14154-2-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/cam.c | 22 ++++++++++++---------- + drivers/net/wireless/realtek/rtw89/cam.h | 3 ++- + drivers/net/wireless/realtek/rtw89/core.c | 4 ++-- + drivers/net/wireless/realtek/rtw89/fw.c | 5 +++-- + drivers/net/wireless/realtek/rtw89/fw.h | 3 ++- + drivers/net/wireless/realtek/rtw89/mac.c | 4 ++-- + drivers/net/wireless/realtek/rtw89/mac80211.c | 6 +++++- + 7 files changed, 28 insertions(+), 19 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/cam.c b/drivers/net/wireless/realtek/rtw89/cam.c +index ad7a8155dbed..ce5056ad1e5c 100644 +--- a/drivers/net/wireless/realtek/rtw89/cam.c ++++ b/drivers/net/wireless/realtek/rtw89/cam.c +@@ -243,7 +243,7 @@ static int rtw89_cam_attach_sec_cam(struct rtw89_dev *rtwdev, + addr_cam->sec_ent[key_idx] = sec_cam->sec_cam_idx; + addr_cam->sec_entries[key_idx] = sec_cam; + set_bit(key_idx, addr_cam->sec_cam_map); +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + if (ret) { + rtw89_err(rtwdev, "failed to update addr cam sec entry: %d\n", + ret); +@@ -394,7 +394,7 @@ int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, + clear_bit(key_idx, addr_cam->sec_cam_map); + addr_cam->sec_entries[key_idx] = NULL; + if (inform_fw) { +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + if (ret) + rtw89_err(rtwdev, "failed to update cam del key: %d\n", ret); + } +@@ -593,7 +593,7 @@ int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, + return 0; + } + +-static u8 rtw89_cam_addr_hash(u8 start, u8 *addr) ++static u8 rtw89_cam_addr_hash(u8 start, const u8 *addr) + { + u8 hash = 0; + u8 i; +@@ -606,12 +606,14 @@ static u8 rtw89_cam_addr_hash(u8 start, u8 *addr) + + void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + struct rtw89_vif *rtwvif, ++ const u8 *scan_mac_addr, + u8 *cmd) + { + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); + struct ieee80211_sta *sta; + struct rtw89_sta *rtwsta; + struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ const u8 *sma = scan_mac_addr ? scan_mac_addr : rtwvif->mac_addr; + u8 sma_hash, tma_hash, addr_msk_start; + u8 sma_start = 0; + u8 tma_start = 0; +@@ -623,7 +625,7 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + else if (addr_cam->mask_sel == RTW89_TMA) + tma_start = addr_msk_start; + } +- sma_hash = rtw89_cam_addr_hash(sma_start, rtwvif->mac_addr); ++ sma_hash = rtw89_cam_addr_hash(sma_start, sma); + tma_hash = rtw89_cam_addr_hash(tma_start, addr_cam->tma); + + FWCMD_SET_ADDR_IDX(cmd, addr_cam->addr_cam_idx); +@@ -642,12 +644,12 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + + FWCMD_SET_ADDR_BSSID_CAM_IDX(cmd, addr_cam->bssid_cam_idx); + +- FWCMD_SET_ADDR_SMA0(cmd, rtwvif->mac_addr[0]); +- FWCMD_SET_ADDR_SMA1(cmd, rtwvif->mac_addr[1]); +- FWCMD_SET_ADDR_SMA2(cmd, rtwvif->mac_addr[2]); +- FWCMD_SET_ADDR_SMA3(cmd, rtwvif->mac_addr[3]); +- FWCMD_SET_ADDR_SMA4(cmd, rtwvif->mac_addr[4]); +- FWCMD_SET_ADDR_SMA5(cmd, rtwvif->mac_addr[5]); ++ FWCMD_SET_ADDR_SMA0(cmd, sma[0]); ++ FWCMD_SET_ADDR_SMA1(cmd, sma[1]); ++ FWCMD_SET_ADDR_SMA2(cmd, sma[2]); ++ FWCMD_SET_ADDR_SMA3(cmd, sma[3]); ++ FWCMD_SET_ADDR_SMA4(cmd, sma[4]); ++ FWCMD_SET_ADDR_SMA5(cmd, sma[5]); + + FWCMD_SET_ADDR_TMA0(cmd, addr_cam->tma[0]); + FWCMD_SET_ADDR_TMA1(cmd, addr_cam->tma[1]); +diff --git a/drivers/net/wireless/realtek/rtw89/cam.h b/drivers/net/wireless/realtek/rtw89/cam.h +index 41d7d2712027..c0f9ef12f530 100644 +--- a/drivers/net/wireless/realtek/rtw89/cam.h ++++ b/drivers/net/wireless/realtek/rtw89/cam.h +@@ -347,7 +347,8 @@ static inline void FWCMD_SET_ADDR_BSSID_BSSID5(void *cmd, u32 value) + int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); + void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); + void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, +- struct rtw89_vif *vif, u8 *cmd); ++ struct rtw89_vif *vif, ++ const u8 *scan_mac_addr, u8 *cmd); + int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, + struct rtw89_vif *vif, u8 *cmd); + int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev, +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +index d02ec5a735cb..6c91e99fd28f 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.c ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -1872,7 +1872,7 @@ int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, + } + + /* update cam aid mac_id net_type */ +- rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + if (ret) { + rtw89_warn(rtwdev, "failed to send h2c cam\n"); + return ret; +@@ -1908,7 +1908,7 @@ int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, + } + + /* update cam aid mac_id net_type */ +- rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + if (ret) { + rtw89_warn(rtwdev, "failed to send h2c cam\n"); + return ret; +diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c +index 65ef3dc9d061..c9aa86e5d4e4 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.c ++++ b/drivers/net/wireless/realtek/rtw89/fw.c +@@ -523,7 +523,8 @@ void rtw89_unload_firmware(struct rtw89_dev *rtwdev) + } + + #define H2C_CAM_LEN 60 +-int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) ++int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, ++ const u8 *scan_mac_addr) + { + struct sk_buff *skb; + +@@ -533,7 +534,7 @@ int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) + return -ENOMEM; + } + skb_put(skb, H2C_CAM_LEN); +- rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, skb->data); ++ rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, scan_mac_addr, skb->data); + rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif, skb->data); + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +index cf6898f7aaee..865170a89c4a 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.h ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -1756,7 +1756,8 @@ int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, + struct ieee80211_sta *sta); + int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, + struct rtw89_sta *rtwsta); +-int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); ++int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, ++ const u8 *scan_mac_addr); + void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); + void rtw89_fw_c2h_work(struct work_struct *work); + int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index f8389e849c67..04c5f9966521 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -2990,7 +2990,7 @@ int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) + if (ret) + return ret; + +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + if (ret) + return ret; + +@@ -3011,7 +3011,7 @@ int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) + + rtw89_cam_deinit(rtwdev, rtwvif); + +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + if (ret) + return ret; + +diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c +index 16dc6fb7dbb0..16381adf006e 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -336,7 +336,7 @@ static void rtw89_ops_bss_info_changed(struct ieee80211_hw *hw, + if (changed & BSS_CHANGED_BSSID) { + ether_addr_copy(rtwvif->bssid, conf->bssid); + rtw89_cam_bssid_changed(rtwdev, rtwvif); +- rtw89_fw_h2c_cam(rtwdev, rtwvif); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + } + + if (changed & BSS_CHANGED_ERP_SLOT) +@@ -615,6 +615,7 @@ static void rtw89_ops_sw_scan_start(struct ieee80211_hw *hw, + const u8 *mac_addr) + { + struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; + struct rtw89_hal *hal = &rtwdev->hal; + + mutex_lock(&rtwdev->mutex); +@@ -623,6 +624,7 @@ static void rtw89_ops_sw_scan_start(struct ieee80211_hw *hw, + rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, hal->current_band_type); + rtw89_chip_rfk_scan(rtwdev, true); + rtw89_hci_recalc_int_mit(rtwdev); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, mac_addr); + mutex_unlock(&rtwdev->mutex); + } + +@@ -630,8 +632,10 @@ static void rtw89_ops_sw_scan_complete(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) + { + struct rtw89_dev *rtwdev = hw->priv; ++ struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; + + mutex_lock(&rtwdev->mutex); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); + rtw89_chip_rfk_scan(rtwdev, false); + rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); + rtwdev->scanning = false; +-- +2.13.6 + diff --git a/SOURCES/0022-rtw89-fix-incorrect-channel-info-during-scan.patch b/SOURCES/0022-rtw89-fix-incorrect-channel-info-during-scan.patch new file mode 100644 index 0000000..191e671 --- /dev/null +++ b/SOURCES/0022-rtw89-fix-incorrect-channel-info-during-scan.patch @@ -0,0 +1,566 @@ +From 7de840de78a263730688f5f298f8dea0e954b980 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 22/36] rtw89: fix incorrect channel info during scan +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit eb4e52b3f38dfd08a89e1084f5980a2bb93456fb +Author: Po Hao Huang +Date: Thu Nov 11 10:37:06 2021 +0800 + + rtw89: fix incorrect channel info during scan + + We used to fill in rx skbs' frequency field by mac80211's current + channel value. In some cases, mac80211 switches channel before all + rx packets have been processed. This results in incorrect bss info. + We fix this by filling in frequency field with channel index obtained + from hardware, then fix potential cck missing issue by skb's original + hw rate. After all fix is done, convert hw rate back to the supported + band rate index. + + Signed-off-by: Po Hao Huang + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211111023706.14154-3-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/core.c | 53 +++++++++--- + drivers/net/wireless/realtek/rtw89/core.h | 4 + + drivers/net/wireless/realtek/rtw89/debug.c | 2 +- + drivers/net/wireless/realtek/rtw89/phy.c | 111 ++++++++++++++++++++++++++ + drivers/net/wireless/realtek/rtw89/phy.h | 60 ++++++++++++++ + drivers/net/wireless/realtek/rtw89/reg.h | 23 ++++++ + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 19 +++++ + drivers/net/wireless/realtek/rtw89/txrx.h | 45 ++--------- + 8 files changed, 264 insertions(+), 53 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +index 6c91e99fd28f..2c079388a664 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.c ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -242,6 +242,7 @@ void rtw89_set_channel(struct rtw89_dev *rtwdev) + + hal->current_band_width = bandwidth; + hal->current_channel = center_chan; ++ hal->prev_primary_channel = hal->current_primary_channel; + hal->current_primary_channel = ch_param.primary_chan; + hal->current_band_type = band_type; + +@@ -881,8 +882,11 @@ static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, + { + s16 cfo; + ++ phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); ++ if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) ++ return; + /* sign conversion for S(12,2) */ +- cfo = sign_extend32(RTW89_GET_PHY_STS_IE0_CFO(addr), 11); ++ cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_CFO(addr), 11); + rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); + } + +@@ -908,6 +912,7 @@ static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) + s8 *rssi = phy_ppdu->rssi; + u8 *buf = phy_ppdu->buf; + ++ phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); + phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); + rssi[RF_PATH_A] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_A(buf)); + rssi[RF_PATH_B] = RTW89_RSSI_RAW_TO_DBM(RTW89_GET_PHY_STS_RSSI_B(buf)); +@@ -936,8 +941,9 @@ static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, + u16 ie_len; + u8 *pos, *end; + +- if (!phy_ppdu->to_self) +- return 0; ++ /* mark invalid reports and bypass them */ ++ if (phy_ppdu->ie < RTW89_CCK_PKT) ++ return -EINVAL; + + pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; + end = (u8 *)phy_ppdu->buf + phy_ppdu->len; +@@ -1000,9 +1006,7 @@ static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, + data_rate_mode = GET_DATA_RATE_MODE(data_rate); + if (data_rate_mode == DATA_RATE_MODE_NON_HT) { + rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); +- /* No 4 CCK rates for 5G */ +- if (status->band == NL80211_BAND_5GHZ) +- rate_idx -= 4; ++ /* rate_idx is still hardware value here */ + } else if (data_rate_mode == DATA_RATE_MODE_HT) { + rate_idx = GET_DATA_RATE_HT_IDX(data_rate); + } else if (data_rate_mode == DATA_RATE_MODE_VHT) { +@@ -1081,6 +1085,29 @@ static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, + rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); + } + ++static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, ++ struct ieee80211_rx_status *status) ++{ ++ u16 chan = rtwdev->hal.prev_primary_channel; ++ u8 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; ++ ++ if (status->band != NL80211_BAND_2GHZ && ++ status->encoding == RX_ENC_LEGACY && ++ status->rate_idx < RTW89_HW_RATE_OFDM6) { ++ status->freq = ieee80211_channel_to_frequency(chan, band); ++ status->band = band; ++ } ++} ++ ++static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) ++{ ++ if (rx_status->band == NL80211_BAND_2GHZ || ++ rx_status->encoding != RX_ENC_LEGACY) ++ return; ++ /* No 4 CCK rates for non-2G */ ++ rx_status->rate_idx -= 4; ++} ++ + static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, + struct rtw89_rx_phy_ppdu *phy_ppdu, + struct rtw89_rx_desc_info *desc_info, +@@ -1099,6 +1126,8 @@ static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, + rx_status = IEEE80211_SKB_RXCB(skb_ppdu); + if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) + rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); ++ rtw89_correct_cck_chan(rtwdev, rx_status); ++ rtw89_core_hw_to_sband_rate(rx_status); + rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); + ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, &rtwdev->napi); + rtwdev->napi_budget_countdown--; +@@ -1112,6 +1141,7 @@ static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, + struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, + .len = skb->len, + .to_self = desc_info->addr1_match, ++ .rate = desc_info->data_rate, + .mac_id = desc_info->mac_id}; + int ret; + +@@ -1267,12 +1297,7 @@ static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, + if (data_rate_mode == DATA_RATE_MODE_NON_HT) { + rx_status->encoding = RX_ENC_LEGACY; + rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); +- /* No 4 CCK rates for 5G */ +- if (rx_status->band == NL80211_BAND_5GHZ) +- rx_status->rate_idx -= 4; +- if (rtwdev->scanning) +- rx_status->rate_idx = min_t(u8, rx_status->rate_idx, +- ARRAY_SIZE(rtw89_bitrates) - 5); ++ /* convert rate_idx after we get the correct band */ + } else if (data_rate_mode == DATA_RATE_MODE_HT) { + rx_status->encoding = RX_ENC_HT; + rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); +@@ -1324,10 +1349,13 @@ static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, + { + struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; + u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; ++ struct ieee80211_rx_status *rx_status; + struct sk_buff *skb_ppdu, *tmp; + + skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { + skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); ++ rx_status = IEEE80211_SKB_RXCB(skb_ppdu); ++ rtw89_core_hw_to_sband_rate(rx_status); + rtw89_core_rx_stats(rtwdev, NULL, desc_info, skb_ppdu); + ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, &rtwdev->napi); + rtwdev->napi_budget_countdown--; +@@ -1360,6 +1388,7 @@ void rtw89_core_rx(struct rtw89_dev *rtwdev, + BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) { + skb_queue_tail(&ppdu_sts->rx_queue[band], skb); + } else { ++ rtw89_core_hw_to_sband_rate(rx_status); + rtw89_core_rx_stats(rtwdev, NULL, desc_info, skb); + ieee80211_rx_napi(rtwdev->hw, NULL, skb, &rtwdev->napi); + rtwdev->napi_budget_countdown--; +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +index 3729abda04f9..ef3f5de26f13 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.h ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -473,6 +473,9 @@ struct rtw89_rx_phy_ppdu { + u8 rssi_avg; + s8 rssi[RF_PATH_MAX]; + u8 mac_id; ++ u8 chan_idx; ++ u8 ie; ++ u16 rate; + bool to_self; + bool valid; + }; +@@ -2355,6 +2358,7 @@ struct rtw89_hal { + u32 rx_fltr; + u8 cv; + u8 current_channel; ++ u8 prev_primary_channel; + u8 current_primary_channel; + enum rtw89_subband current_subband; + u8 current_band_width; +diff --git a/drivers/net/wireless/realtek/rtw89/debug.c b/drivers/net/wireless/realtek/rtw89/debug.c +index 1e85808aaf4b..9756d75ef24e 100644 +--- a/drivers/net/wireless/realtek/rtw89/debug.c ++++ b/drivers/net/wireless/realtek/rtw89/debug.c +@@ -2285,7 +2285,7 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) + switch (status->encoding) { + case RX_ENC_LEGACY: + seq_printf(m, "Legacy %d", status->rate_idx + +- (status->band == NL80211_BAND_5GHZ ? 4 : 0)); ++ (status->band != NL80211_BAND_2GHZ ? 4 : 0)); + break; + case RX_ENC_HT: + seq_printf(m, "HT MCS-%d%s", status->rate_idx, +diff --git a/drivers/net/wireless/realtek/rtw89/phy.c b/drivers/net/wireless/realtek/rtw89/phy.c +index 312d9a07599d..147009888de0 100644 +--- a/drivers/net/wireless/realtek/rtw89/phy.c ++++ b/drivers/net/wireless/realtek/rtw89/phy.c +@@ -2421,6 +2421,116 @@ void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) + env->ccx_watchdog_result, chk_result); + } + ++static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) ++{ ++ if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || ++ *ie_page == RTW89_RSVD_9) ++ return false; ++ else if (*ie_page > RTW89_RSVD_9) ++ *ie_page -= 1; ++ ++ return true; ++} ++ ++static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) ++{ ++ static const u8 ie_page_shift = 2; ++ ++ return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); ++} ++ ++static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_status_bitmap ie_page) ++{ ++ u32 addr; ++ ++ if (!rtw89_physts_ie_page_valid(&ie_page)) ++ return 0; ++ ++ addr = rtw89_phy_get_ie_bitmap_addr(ie_page); ++ ++ return rtw89_phy_read32(rtwdev, addr); ++} ++ ++static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_status_bitmap ie_page, ++ u32 val) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u32 addr; ++ ++ if (!rtw89_physts_ie_page_valid(&ie_page)) ++ return; ++ ++ if (chip->chip_id == RTL8852A) ++ val &= B_PHY_STS_BITMAP_MSK_52A; ++ ++ addr = rtw89_phy_get_ie_bitmap_addr(ie_page); ++ rtw89_phy_write32(rtwdev, addr, val); ++} ++ ++static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, ++ enum rtw89_phy_status_bitmap bitmap, ++ enum rtw89_phy_status_ie_type ie, ++ bool enable) ++{ ++ u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); ++ ++ if (enable) ++ val |= BIT(ie); ++ else ++ val &= ~BIT(ie); ++ ++ rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); ++} ++ ++static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, ++ bool enable, ++ enum rtw89_phy_idx phy_idx) ++{ ++ if (enable) { ++ rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, ++ B_STS_DIS_TRIG_BY_FAIL); ++ rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, ++ B_STS_DIS_TRIG_BY_BRK); ++ } else { ++ rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, ++ B_STS_DIS_TRIG_BY_FAIL); ++ rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, ++ B_STS_DIS_TRIG_BY_BRK); ++ } ++} ++ ++static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) ++{ ++ const struct rtw89_chip_info *chip = rtwdev->chip; ++ u8 i; ++ ++ if (chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) ++ rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); ++ ++ for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { ++ if (i >= RTW89_CCK_PKT) ++ rtw89_physts_enable_ie_bitmap(rtwdev, i, ++ RTW89_PHYSTS_IE09_FTR_0, ++ true); ++ if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || ++ (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) ++ continue; ++ rtw89_physts_enable_ie_bitmap(rtwdev, i, ++ RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, ++ true); ++ } ++ rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, ++ RTW89_PHYSTS_IE13_DL_MU_DEF, true); ++ rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, ++ RTW89_PHYSTS_IE13_DL_MU_DEF, true); ++ ++ /* force IE01 for channel index, only channel field is valid */ ++ rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, ++ RTW89_PHYSTS_IE01_CMN_OFDM, true); ++} ++ + static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) + { + const struct rtw89_chip_info *chip = rtwdev->chip; +@@ -2856,6 +2966,7 @@ void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) + rtw89_chip_bb_sethw(rtwdev); + + rtw89_phy_env_monitor_init(rtwdev); ++ rtw89_physts_parsing_init(rtwdev); + rtw89_phy_dig_init(rtwdev); + rtw89_phy_cfo_init(rtwdev); + +diff --git a/drivers/net/wireless/realtek/rtw89/phy.h b/drivers/net/wireless/realtek/rtw89/phy.h +index 370129345e0f..b1f059b725a1 100644 +--- a/drivers/net/wireless/realtek/rtw89/phy.h ++++ b/drivers/net/wireless/realtek/rtw89/phy.h +@@ -134,6 +134,66 @@ enum rtw89_ccx_unit { + RTW89_CCX_32_US = 3 + }; + ++enum rtw89_phy_status_ie_type { ++ RTW89_PHYSTS_IE00_CMN_CCK = 0, ++ RTW89_PHYSTS_IE01_CMN_OFDM = 1, ++ RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, ++ RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, ++ RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, ++ RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, ++ RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, ++ RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, ++ RTW89_PHYSTS_IE08_FTR_CH = 8, ++ RTW89_PHYSTS_IE09_FTR_0 = 9, ++ RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, ++ RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, ++ RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, ++ RTW89_PHYSTS_IE13_DL_MU_DEF = 13, ++ RTW89_PHYSTS_IE14_TB_UL_CQI = 14, ++ RTW89_PHYSTS_IE15_TB_UL_DEF = 15, ++ RTW89_PHYSTS_IE16_RSVD16 = 16, ++ RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, ++ RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, ++ RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, ++ RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, ++ RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, ++ RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, ++ RTW89_PHYSTS_IE23_RSVD23 = 23, ++ RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, ++ RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, ++ RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, ++ RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, ++ RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, ++ RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, ++ RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, ++ RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, ++ ++ /* keep last */ ++ RTW89_PHYSTS_IE_NUM, ++ RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 ++}; ++ ++enum rtw89_phy_status_bitmap { ++ RTW89_TD_SEARCH_FAIL = 0, ++ RTW89_BRK_BY_TX_PKT = 1, ++ RTW89_CCA_SPOOF = 2, ++ RTW89_OFDM_BRK = 3, ++ RTW89_CCK_BRK = 4, ++ RTW89_DL_MU_SPOOFING = 5, ++ RTW89_HE_MU = 6, ++ RTW89_VHT_MU = 7, ++ RTW89_UL_TB_SPOOFING = 8, ++ RTW89_RSVD_9 = 9, ++ RTW89_TRIG_BASE_PPDU = 10, ++ RTW89_CCK_PKT = 11, ++ RTW89_LEGACY_OFDM_PKT = 12, ++ RTW89_HT_PKT = 13, ++ RTW89_VHT_PKT = 14, ++ RTW89_HE_PKT = 15, ++ ++ RTW89_PHYSTS_BITMAP_NUM ++}; ++ + enum rtw89_dig_gain_type { + RTW89_DIG_GAIN_LNA_G = 0, + RTW89_DIG_GAIN_TIA_G = 1, +diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h +index 365d8c8ce57b..b6049009f183 100644 +--- a/drivers/net/wireless/realtek/rtw89/reg.h ++++ b/drivers/net/wireless/realtek/rtw89/reg.h +@@ -1674,6 +1674,29 @@ + #define B_UPD_CLK_ADC_VAL GENMASK(26, 25) + #define R_RSTB_ASYNC 0x0704 + #define B_RSTB_ASYNC_ALL BIT(1) ++#define R_MAC_PIN_SEL 0x0734 ++#define B_CH_IDX_SEG0 GENMASK(23, 16) ++#define R_PLCP_HISTOGRAM 0x0738 ++#define B_STS_DIS_TRIG_BY_BRK BIT(2) ++#define B_STS_DIS_TRIG_BY_FAIL BIT(3) ++#define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL ++#define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2) ++#define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C ++#define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f ++#define R_PHY_STS_BITMAP_R2T 0x0740 ++#define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744 ++#define R_PHY_STS_BITMAP_OFDM_BRK 0x0748 ++#define R_PHY_STS_BITMAP_CCK_BRK 0x074C ++#define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750 ++#define R_PHY_STS_BITMAP_HE_MU 0x0754 ++#define R_PHY_STS_BITMAP_VHT_MU 0x0758 ++#define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C ++#define R_PHY_STS_BITMAP_TRIGBASE 0x0760 ++#define R_PHY_STS_BITMAP_CCK 0x0764 ++#define R_PHY_STS_BITMAP_LEGACY 0x0768 ++#define R_PHY_STS_BITMAP_HT 0x076C ++#define R_PHY_STS_BITMAP_VHT 0x0770 ++#define R_PHY_STS_BITMAP_HE 0x0774 + #define R_PMAC_GNT 0x0980 + #define B_PMAC_GNT_TXEN BIT(0) + #define B_PMAC_GNT_RXEN BIT(16) +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +index 9e25e53f6c4a..5ec13ae0abcd 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -1069,6 +1069,8 @@ static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, + rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); + } + rtw8852a_spur_elimination(rtwdev, param->center_chan); ++ rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, ++ param->primary_chan); + rtw8852a_bb_reset_all(rtwdev, phy_idx); + } + +@@ -1927,6 +1929,21 @@ void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) + rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); + } + ++static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, ++ struct rtw89_rx_phy_ppdu *phy_ppdu, ++ struct ieee80211_rx_status *status) ++{ ++ u16 chan = phy_ppdu->chan_idx; ++ u8 band; ++ ++ if (chan == 0) ++ return; ++ ++ band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; ++ status->freq = ieee80211_channel_to_frequency(chan, band); ++ status->band = band; ++} ++ + static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, + struct rtw89_rx_phy_ppdu *phy_ppdu, + struct ieee80211_rx_status *status) +@@ -1939,6 +1956,8 @@ static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, + status->chains |= BIT(path); + status->chain_signal[path] = rx_power[path]; + } ++ if (phy_ppdu->valid) ++ rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); + } + + static const struct rtw89_chip_ops rtw8852a_chip_ops = { +diff --git a/drivers/net/wireless/realtek/rtw89/txrx.h b/drivers/net/wireless/realtek/rtw89/txrx.h +index 5570d8ccf136..75b11249f306 100644 +--- a/drivers/net/wireless/realtek/rtw89/txrx.h ++++ b/drivers/net/wireless/realtek/rtw89/txrx.h +@@ -168,6 +168,8 @@ + #define RTW89_GET_RXINFO_MACID(rpt, usr) \ + le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) + ++#define RTW89_GET_PHY_STS_IE_MAP(sts) \ ++ le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0)) + #define RTW89_GET_PHY_STS_RSSI_A(sts) \ + le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0)) + #define RTW89_GET_PHY_STS_RSSI_B(sts) \ +@@ -184,7 +186,9 @@ + le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0)) + #define RTW89_GET_PHY_STS_IE_LEN(ie) \ + le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5)) +-#define RTW89_GET_PHY_STS_IE0_CFO(ie) \ ++#define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \ ++ le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16)) ++#define RTW89_GET_PHY_STS_IE01_CFO(ie) \ + le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20)) + + enum rtw89_tx_channel { +@@ -251,45 +255,6 @@ enum rtw89_tx_qsel { + /* reserved */ + }; + +-enum rtw89_phy_status_ie_type { +- RTW89_PHYSTS_IE00_CMN_CCK = 0, +- RTW89_PHYSTS_IE01_CMN_OFDM = 1, +- RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, +- RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, +- RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, +- RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, +- RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, +- RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, +- RTW89_PHYSTS_IE08_FTR_CH = 8, +- RTW89_PHYSTS_IE09_FTR_PLCP_0 = 9, +- RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, +- RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, +- RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, +- RTW89_PHYSTS_IE13_DL_MU_DEF = 13, +- RTW89_PHYSTS_IE14_TB_UL_CQI = 14, +- RTW89_PHYSTS_IE15_TB_UL_DEF = 15, +- RTW89_PHYSTS_IE16_RSVD16 = 16, +- RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, +- RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, +- RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, +- RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, +- RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, +- RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, +- RTW89_PHYSTS_IE23_RSVD23 = 23, +- RTW89_PHYSTS_IE24_DBG_OFDM_TD_PATH_A = 24, +- RTW89_PHYSTS_IE25_DBG_OFDM_TD_PATH_B = 25, +- RTW89_PHYSTS_IE26_DBG_OFDM_TD_PATH_C = 26, +- RTW89_PHYSTS_IE27_DBG_OFDM_TD_PATH_D = 27, +- RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, +- RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, +- RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, +- RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, +- +- /* keep last */ +- RTW89_PHYSTS_IE_NUM, +- RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 +-}; +- + static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) + { + switch (tid) { +-- +2.13.6 + diff --git a/SOURCES/0023-rtw89-fix-sending-wrong-rtwsta-mac_id-to-firmware-to.patch b/SOURCES/0023-rtw89-fix-sending-wrong-rtwsta-mac_id-to-firmware-to.patch new file mode 100644 index 0000000..18d9ed1 --- /dev/null +++ b/SOURCES/0023-rtw89-fix-sending-wrong-rtwsta-mac_id-to-firmware-to.patch @@ -0,0 +1,359 @@ +From 54a696e53e3265ff849635957429da85977bf707 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 23/36] rtw89: fix sending wrong rtwsta->mac_id to firmware to + fill address CAM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 40822e079011ef8704d429c9d8271000159abffe +Author: Ping-Ke Shih +Date: Wed Dec 1 16:06:06 2021 +0800 + + rtw89: fix sending wrong rtwsta->mac_id to firmware to fill address CAM + + With wrong rtwsta->mac_id, it can't send out ack properly when we receive + assoc response occasionally. Then, it failed to connect an AP. + + The cause is that we store 'sta' and use it somewhere. To correct this, + remove the variable and use mac_id in drv_priv of 'sta' or 'vif' passed + by mac80211. + + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211201080607.11211-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/cam.c | 43 ++++++++++++--------------- + drivers/net/wireless/realtek/rtw89/cam.h | 1 + + drivers/net/wireless/realtek/rtw89/core.c | 12 ++++---- + drivers/net/wireless/realtek/rtw89/core.h | 19 ++++++------ + drivers/net/wireless/realtek/rtw89/fw.c | 4 +-- + drivers/net/wireless/realtek/rtw89/fw.h | 2 +- + drivers/net/wireless/realtek/rtw89/mac.c | 4 +-- + drivers/net/wireless/realtek/rtw89/mac80211.c | 6 ++-- + 8 files changed, 43 insertions(+), 48 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/cam.c b/drivers/net/wireless/realtek/rtw89/cam.c +index ce5056ad1e5c..bd34e4bbe107 100644 +--- a/drivers/net/wireless/realtek/rtw89/cam.c ++++ b/drivers/net/wireless/realtek/rtw89/cam.c +@@ -219,6 +219,7 @@ static int rtw89_cam_attach_sec_cam(struct rtw89_dev *rtwdev, + struct ieee80211_key_conf *key, + struct rtw89_sec_cam_entry *sec_cam) + { ++ struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); + struct rtw89_vif *rtwvif; + struct rtw89_addr_cam_entry *addr_cam; + u8 key_idx = 0; +@@ -243,7 +244,7 @@ static int rtw89_cam_attach_sec_cam(struct rtw89_dev *rtwdev, + addr_cam->sec_ent[key_idx] = sec_cam->sec_cam_idx; + addr_cam->sec_entries[key_idx] = sec_cam; + set_bit(key_idx, addr_cam->sec_cam_map); +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); + if (ret) { + rtw89_err(rtwdev, "failed to update addr cam sec entry: %d\n", + ret); +@@ -371,6 +372,7 @@ int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, + struct ieee80211_key_conf *key, + bool inform_fw) + { ++ struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); + struct rtw89_cam_info *cam_info = &rtwdev->cam_info; + struct rtw89_vif *rtwvif; + struct rtw89_addr_cam_entry *addr_cam; +@@ -394,7 +396,7 @@ int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, + clear_bit(key_idx, addr_cam->sec_cam_map); + addr_cam->sec_entries[key_idx] = NULL; + if (inform_fw) { +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); + if (ret) + rtw89_err(rtwdev, "failed to update cam del key: %d\n", ret); + } +@@ -536,12 +538,8 @@ static int rtw89_cam_init_bssid_cam(struct rtw89_dev *rtwdev, + + void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) + { +- struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); +- struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; + struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; + +- if (vif->type == NL80211_IFTYPE_STATION) +- ether_addr_copy(addr_cam->tma, rtwvif->bssid); + ether_addr_copy(bssid_cam->bssid, rtwvif->bssid); + } + +@@ -606,17 +604,18 @@ static u8 rtw89_cam_addr_hash(u8 start, const u8 *addr) + + void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + struct rtw89_vif *rtwvif, ++ struct rtw89_sta *rtwsta, + const u8 *scan_mac_addr, + u8 *cmd) + { + struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); +- struct ieee80211_sta *sta; +- struct rtw89_sta *rtwsta; + struct rtw89_addr_cam_entry *addr_cam = &rtwvif->addr_cam; ++ struct ieee80211_sta *sta = rtwsta_to_sta_safe(rtwsta); + const u8 *sma = scan_mac_addr ? scan_mac_addr : rtwvif->mac_addr; + u8 sma_hash, tma_hash, addr_msk_start; + u8 sma_start = 0; + u8 tma_start = 0; ++ u8 *tma = sta ? sta->addr : rtwvif->bssid; + + if (addr_cam->addr_mask != 0) { + addr_msk_start = __ffs(addr_cam->addr_mask); +@@ -626,7 +625,7 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + tma_start = addr_msk_start; + } + sma_hash = rtw89_cam_addr_hash(sma_start, sma); +- tma_hash = rtw89_cam_addr_hash(tma_start, addr_cam->tma); ++ tma_hash = rtw89_cam_addr_hash(tma_start, tma); + + FWCMD_SET_ADDR_IDX(cmd, addr_cam->addr_cam_idx); + FWCMD_SET_ADDR_OFFSET(cmd, addr_cam->offset); +@@ -651,12 +650,12 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + FWCMD_SET_ADDR_SMA4(cmd, sma[4]); + FWCMD_SET_ADDR_SMA5(cmd, sma[5]); + +- FWCMD_SET_ADDR_TMA0(cmd, addr_cam->tma[0]); +- FWCMD_SET_ADDR_TMA1(cmd, addr_cam->tma[1]); +- FWCMD_SET_ADDR_TMA2(cmd, addr_cam->tma[2]); +- FWCMD_SET_ADDR_TMA3(cmd, addr_cam->tma[3]); +- FWCMD_SET_ADDR_TMA4(cmd, addr_cam->tma[4]); +- FWCMD_SET_ADDR_TMA5(cmd, addr_cam->tma[5]); ++ FWCMD_SET_ADDR_TMA0(cmd, tma[0]); ++ FWCMD_SET_ADDR_TMA1(cmd, tma[1]); ++ FWCMD_SET_ADDR_TMA2(cmd, tma[2]); ++ FWCMD_SET_ADDR_TMA3(cmd, tma[3]); ++ FWCMD_SET_ADDR_TMA4(cmd, tma[4]); ++ FWCMD_SET_ADDR_TMA5(cmd, tma[5]); + + FWCMD_SET_ADDR_PORT_INT(cmd, rtwvif->port); + FWCMD_SET_ADDR_TSF_SYNC(cmd, rtwvif->port); +@@ -664,15 +663,11 @@ void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + FWCMD_SET_ADDR_LSIG_TXOP(cmd, rtwvif->lsig_txop); + FWCMD_SET_ADDR_TGT_IND(cmd, rtwvif->tgt_ind); + FWCMD_SET_ADDR_FRM_TGT_IND(cmd, rtwvif->frm_tgt_ind); +- +- if (vif->type == NL80211_IFTYPE_STATION) { +- sta = rtwvif->mgd.ap; +- if (sta) { +- rtwsta = (struct rtw89_sta *)sta->drv_priv; +- FWCMD_SET_ADDR_MACID(cmd, rtwsta->mac_id); +- FWCMD_SET_ADDR_AID12(cmd, vif->bss_conf.aid & 0xfff); +- } +- } ++ FWCMD_SET_ADDR_MACID(cmd, rtwsta ? rtwsta->mac_id : rtwvif->mac_id); ++ if (rtwvif->net_type == RTW89_NET_TYPE_INFRA) ++ FWCMD_SET_ADDR_AID12(cmd, vif->bss_conf.aid & 0xfff); ++ else if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) ++ FWCMD_SET_ADDR_AID12(cmd, sta ? sta->aid & 0xfff : 0); + FWCMD_SET_ADDR_WOL_PATTERN(cmd, rtwvif->wowlan_pattern); + FWCMD_SET_ADDR_WOL_UC(cmd, rtwvif->wowlan_uc); + FWCMD_SET_ADDR_WOL_MAGIC(cmd, rtwvif->wowlan_magic); +diff --git a/drivers/net/wireless/realtek/rtw89/cam.h b/drivers/net/wireless/realtek/rtw89/cam.h +index c0f9ef12f530..33a3ad582b81 100644 +--- a/drivers/net/wireless/realtek/rtw89/cam.h ++++ b/drivers/net/wireless/realtek/rtw89/cam.h +@@ -348,6 +348,7 @@ int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); + void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); + void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, + struct rtw89_vif *vif, ++ struct rtw89_sta *rtwsta, + const u8 *scan_mac_addr, u8 *cmd); + int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, + struct rtw89_vif *vif, u8 *cmd); +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +index 2c079388a664..8212496ae9ef 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.c ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -1854,7 +1854,8 @@ int rtw89_core_sta_add(struct rtw89_dev *rtwdev, + ewma_rssi_init(&rtwsta->avg_rssi); + + if (vif->type == NL80211_IFTYPE_STATION) { +- rtwvif->mgd.ap = sta; ++ /* for station mode, assign the mac_id from itself */ ++ rtwsta->mac_id = rtwvif->mac_id; + rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, + BTC_ROLE_MSTS_STA_CONN_START); + rtw89_chip_rfk_channel(rtwdev); +@@ -1880,6 +1881,7 @@ int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, + struct ieee80211_sta *sta) + { + struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; ++ struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; + int ret; + + rtw89_mac_bf_monitor_calc(rtwdev, sta, true); +@@ -1901,7 +1903,7 @@ int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, + } + + /* update cam aid mac_id net_type */ +- rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); + if (ret) { + rtw89_warn(rtwdev, "failed to send h2c cam\n"); + return ret; +@@ -1926,10 +1928,6 @@ int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, + return ret; + } + +- /* for station mode, assign the mac_id from itself */ +- if (vif->type == NL80211_IFTYPE_STATION) +- rtwsta->mac_id = rtwvif->mac_id; +- + ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, 0); + if (ret) { + rtw89_warn(rtwdev, "failed to send h2c join info\n"); +@@ -1937,7 +1935,7 @@ int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, + } + + /* update cam aid mac_id net_type */ +- rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); + if (ret) { + rtw89_warn(rtwdev, "failed to send h2c cam\n"); + return ret; +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +index ef3f5de26f13..7066335adcee 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.h ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -1869,7 +1869,6 @@ struct rtw89_addr_cam_entry { + u8 wapi : 1; + u8 mask_sel : 2; + u8 bssid_cam_idx: 6; +- u8 tma[ETH_ALEN]; + u8 sma[ETH_ALEN]; + + u8 sec_ent_mode; +@@ -1938,14 +1937,6 @@ struct rtw89_vif { + bool wowlan_magic; + bool is_hesta; + bool last_a_ctrl; +- union { +- struct { +- struct ieee80211_sta *ap; +- } mgd; +- struct { +- struct list_head sta_list; +- } ap; +- }; + struct rtw89_addr_cam_entry addr_cam; + struct rtw89_bssid_cam_entry bssid_cam; + struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; +@@ -3132,6 +3123,16 @@ static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) + return container_of(p, struct ieee80211_sta, drv_priv); + } + ++static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) ++{ ++ return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; ++} ++ ++static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) ++{ ++ return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; ++} ++ + static inline + void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, + struct rtw89_channel_help_params *p) +diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c +index c9aa86e5d4e4..d4b59fbe7365 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.c ++++ b/drivers/net/wireless/realtek/rtw89/fw.c +@@ -524,7 +524,7 @@ void rtw89_unload_firmware(struct rtw89_dev *rtwdev) + + #define H2C_CAM_LEN 60 + int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, +- const u8 *scan_mac_addr) ++ struct rtw89_sta *rtwsta, const u8 *scan_mac_addr) + { + struct sk_buff *skb; + +@@ -534,7 +534,7 @@ int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, + return -ENOMEM; + } + skb_put(skb, H2C_CAM_LEN); +- rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, scan_mac_addr, skb->data); ++ rtw89_cam_fill_addr_cam_info(rtwdev, rtwvif, rtwsta, scan_mac_addr, skb->data); + rtw89_cam_fill_bssid_cam_info(rtwdev, rtwvif, skb->data); + + rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C, +diff --git a/drivers/net/wireless/realtek/rtw89/fw.h b/drivers/net/wireless/realtek/rtw89/fw.h +index 865170a89c4a..2d36dc27222f 100644 +--- a/drivers/net/wireless/realtek/rtw89/fw.h ++++ b/drivers/net/wireless/realtek/rtw89/fw.h +@@ -1757,7 +1757,7 @@ int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, + int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, + struct rtw89_sta *rtwsta); + int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, +- const u8 *scan_mac_addr); ++ struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); + void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); + void rtw89_fw_c2h_work(struct work_struct *work); + int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index 04c5f9966521..999459489e92 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -2990,7 +2990,7 @@ int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) + if (ret) + return ret; + +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); + if (ret) + return ret; + +@@ -3011,7 +3011,7 @@ int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) + + rtw89_cam_deinit(rtwdev, rtwvif); + +- ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); + if (ret) + return ret; + +diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c +index 16381adf006e..757685de6b07 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -336,7 +336,7 @@ static void rtw89_ops_bss_info_changed(struct ieee80211_hw *hw, + if (changed & BSS_CHANGED_BSSID) { + ether_addr_copy(rtwvif->bssid, conf->bssid); + rtw89_cam_bssid_changed(rtwdev, rtwvif); +- rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); + } + + if (changed & BSS_CHANGED_ERP_SLOT) +@@ -624,7 +624,7 @@ static void rtw89_ops_sw_scan_start(struct ieee80211_hw *hw, + rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, hal->current_band_type); + rtw89_chip_rfk_scan(rtwdev, true); + rtw89_hci_recalc_int_mit(rtwdev); +- rtw89_fw_h2c_cam(rtwdev, rtwvif, mac_addr); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); + mutex_unlock(&rtwdev->mutex); + } + +@@ -635,7 +635,7 @@ static void rtw89_ops_sw_scan_complete(struct ieee80211_hw *hw, + struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; + + mutex_lock(&rtwdev->mutex); +- rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL); ++ rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); + rtw89_chip_rfk_scan(rtwdev, false); + rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); + rtwdev->scanning = false; +-- +2.13.6 + diff --git a/SOURCES/0024-rtw89-remove-cch_by_bw-which-is-not-used.patch b/SOURCES/0024-rtw89-remove-cch_by_bw-which-is-not-used.patch new file mode 100644 index 0000000..8a9ade4 --- /dev/null +++ b/SOURCES/0024-rtw89-remove-cch_by_bw-which-is-not-used.patch @@ -0,0 +1,146 @@ +From 52ad252f9ecc9b83bd17b74280e10ae8fae15e44 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 24/36] rtw89: remove cch_by_bw which is not used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit c2258b29985eac9216a9e55f9d5bead9767f96da +Author: Zong-Zhe Yang +Date: Wed Dec 1 16:09:01 2021 +0800 + + rtw89: remove cch_by_bw which is not used + + Originally, cch_by_bw recorded center channels of each available + bandwidths under current bandwidth. And the plan was to iterate + cch_by_bw as parameters to query other configurations. However, + we have not used it for the time being. Keeping it will disturb + the follow-up things, such as bandwidth 160 MHz, so we remove it + for now. If it's really needed at some point, we will redesign it. + + Signed-off-by: Zong-Zhe Yang + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211201080901.12125-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/core.c | 23 ----------------------- + drivers/net/wireless/realtek/rtw89/core.h | 6 ------ + 2 files changed, 29 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c +index 8212496ae9ef..00ae86807dc2 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.c ++++ b/drivers/net/wireless/realtek/rtw89/core.c +@@ -143,20 +143,15 @@ static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, + { + struct ieee80211_channel *channel = chandef->chan; + enum nl80211_chan_width width = chandef->width; +- u8 *cch_by_bw = chan_param->cch_by_bw; + u32 primary_freq, center_freq; + u8 center_chan; + u8 bandwidth = RTW89_CHANNEL_WIDTH_20; + u8 primary_chan_idx = 0; +- u8 i; + + center_chan = channel->hw_value; + primary_freq = channel->center_freq; + center_freq = chandef->center_freq1; + +- /* assign the center channel used while 20M bw is selected */ +- cch_by_bw[RTW89_CHANNEL_WIDTH_20] = channel->hw_value; +- + switch (width) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: +@@ -183,10 +178,6 @@ static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, + primary_chan_idx = RTW89_SC_20_UPMOST; + center_chan -= 6; + } +- /* assign the center channel used +- * while 40M bw is selected +- */ +- cch_by_bw[RTW89_CHANNEL_WIDTH_40] = center_chan + 4; + } else { + if (center_freq - primary_freq == 10) { + primary_chan_idx = RTW89_SC_20_LOWER; +@@ -195,10 +186,6 @@ static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, + primary_chan_idx = RTW89_SC_20_LOWEST; + center_chan += 6; + } +- /* assign the center channel used +- * while 40M bw is selected +- */ +- cch_by_bw[RTW89_CHANNEL_WIDTH_40] = center_chan - 4; + } + break; + default: +@@ -210,12 +197,6 @@ static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef, + chan_param->primary_chan = channel->hw_value; + chan_param->bandwidth = bandwidth; + chan_param->pri_ch_idx = primary_chan_idx; +- +- /* assign the center channel used while current bw is selected */ +- cch_by_bw[bandwidth] = center_chan; +- +- for (i = bandwidth + 1; i <= RTW89_MAX_CHANNEL_WIDTH; i++) +- cch_by_bw[i] = 0; + } + + void rtw89_set_channel(struct rtw89_dev *rtwdev) +@@ -228,7 +209,6 @@ void rtw89_set_channel(struct rtw89_dev *rtwdev) + u8 center_chan, bandwidth; + u8 band_type; + bool band_changed; +- u8 i; + + rtw89_get_channel_params(&hw->conf.chandef, &ch_param); + if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) +@@ -261,9 +241,6 @@ void rtw89_set_channel(struct rtw89_dev *rtwdev) + break; + } + +- for (i = RTW89_CHANNEL_WIDTH_20; i <= RTW89_MAX_CHANNEL_WIDTH; i++) +- hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; +- + rtw89_chip_set_channel_prepare(rtwdev, &bak); + + chip->ops->set_channel(rtwdev, &ch_param); +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +index 7066335adcee..c03e3a13bd56 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.h ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -547,7 +547,6 @@ enum rtw89_ps_mode { + RTW89_PS_MODE_PWR_GATED = 3, + }; + +-#define RTW89_MAX_CHANNEL_WIDTH RTW89_CHANNEL_WIDTH_80 + #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) + #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) + #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) +@@ -574,7 +573,6 @@ struct rtw89_channel_params { + u8 primary_chan; + u8 bandwidth; + u8 pri_ch_idx; +- u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1]; + }; + + struct rtw89_channel_help_params { +@@ -2354,10 +2352,6 @@ struct rtw89_hal { + enum rtw89_subband current_subband; + u8 current_band_width; + u8 current_band_type; +- /* center channel for different available bandwidth, +- * val of (bw > current_band_width) is invalid +- */ +- u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1]; + u32 sw_amsdu_max_size; + u32 antenna_tx; + u32 antenna_rx; +-- +2.13.6 + diff --git a/SOURCES/0025-rtw89-don-t-kick-off-TX-DMA-if-failed-to-write-skb.patch b/SOURCES/0025-rtw89-don-t-kick-off-TX-DMA-if-failed-to-write-skb.patch new file mode 100644 index 0000000..2cf9577 --- /dev/null +++ b/SOURCES/0025-rtw89-don-t-kick-off-TX-DMA-if-failed-to-write-skb.patch @@ -0,0 +1,49 @@ +From b80a31f2d8debd7681d141b03ce167701549be4f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:03 +0100 +Subject: [PATCH 25/36] rtw89: don't kick off TX DMA if failed to write skb +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit a58fdb7c843a37d6598204c6513961feefdadc6a +Author: Ping-Ke Shih +Date: Wed Dec 1 17:38:16 2021 +0800 + + rtw89: don't kick off TX DMA if failed to write skb + + This is found by Smatch static checker warning: + drivers/net/wireless/realtek/rtw89/mac80211.c:31 rtw89_ops_tx() + error: uninitialized symbol 'qsel'. + + The warning is because 'qsel' isn't filled by rtw89_core_tx_write() due to + failed to write. The way to fix it is to avoid kicking off TX DMA, so add + 'return' to the failure case. + + Reported-by: Dan Carpenter + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211201093816.13806-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/mac80211.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/mac80211.c b/drivers/net/wireless/realtek/rtw89/mac80211.c +index 757685de6b07..a322259f4cc4 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac80211.c ++++ b/drivers/net/wireless/realtek/rtw89/mac80211.c +@@ -27,6 +27,7 @@ static void rtw89_ops_tx(struct ieee80211_hw *hw, + if (ret) { + rtw89_err(rtwdev, "failed to transmit skb: %d\n", ret); + ieee80211_free_txskb(hw, skb); ++ return; + } + rtw89_core_tx_kick_off(rtwdev, qsel); + } +-- +2.13.6 + diff --git a/SOURCES/0026-rtw89-coex-correct-C2H-header-length.patch b/SOURCES/0026-rtw89-coex-correct-C2H-header-length.patch new file mode 100644 index 0000000..abd6801 --- /dev/null +++ b/SOURCES/0026-rtw89-coex-correct-C2H-header-length.patch @@ -0,0 +1,45 @@ +From a0606ee9846a9c9937a46717b18440cf6bad87f8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 26/36] rtw89: coex: correct C2H header length +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit b3131a41ac6fcda0a636b3c7d1e05914107d8840 +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:23 2021 +0800 + + rtw89: coex: correct C2H header length + + To resolve C2H handle length mismatch, or it will parse the c2h content + out of array. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-2-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/coex.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +index abe4b6549ab2..f220229a7a48 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.c ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -4494,6 +4494,8 @@ void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, + struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; + u8 *buf = &skb->data[RTW89_C2H_HEADER_LEN]; + ++ len -= RTW89_C2H_HEADER_LEN; ++ + rtw89_debug(rtwdev, RTW89_DBG_BTC, + "[BTC], %s(): C2H BT len:%d class:%d fun:%d\n", + __func__, len, class, func); +-- +2.13.6 + diff --git a/SOURCES/0027-rtw89-coex-Not-to-send-H2C-when-WL-not-ready-and-cou.patch b/SOURCES/0027-rtw89-coex-Not-to-send-H2C-when-WL-not-ready-and-cou.patch new file mode 100644 index 0000000..8062e50 --- /dev/null +++ b/SOURCES/0027-rtw89-coex-Not-to-send-H2C-when-WL-not-ready-and-cou.patch @@ -0,0 +1,71 @@ +From da03f6e3ed4f6dc74b3f0be2c7f959cea5af6c55 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 27/36] rtw89: coex: Not to send H2C when WL not ready and + count H2C +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit f8028a9a92f2b8653658f2ad9cc1fb849873ba5a +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:24 2021 +0800 + + rtw89: coex: Not to send H2C when WL not ready and count H2C + + Prevent to send H2C request to FW when BTC is not initialized or + WL is under power saving. Add counter to count the H2C success or fail. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-3-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/coex.c | 27 +++++++++++++++++++++++++-- + 1 file changed, 25 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +index f220229a7a48..c8f912e7344d 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.c ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -540,8 +540,31 @@ static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update); + static void _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, + void *param, u16 len) + { +- rtw89_fw_h2c_raw_with_hdr(rtwdev, h2c_class, h2c_func, param, len, +- false, true); ++ struct rtw89_btc *btc = &rtwdev->btc; ++ struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; ++ struct rtw89_btc_cx *cx = &btc->cx; ++ struct rtw89_btc_wl_info *wl = &cx->wl; ++ int ret; ++ ++ if (!wl->status.map.init_ok) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by btc not init!!\n", __func__); ++ pfwinfo->cnt_h2c_fail++; ++ return; ++ } else if ((wl->status.map.rf_off_pre == 1 && wl->status.map.rf_off == 1) || ++ (wl->status.map.lps_pre == 1 && wl->status.map.lps == 1)) { ++ rtw89_debug(rtwdev, RTW89_DBG_BTC, ++ "[BTC], %s(): return by wl off!!\n", __func__); ++ pfwinfo->cnt_h2c_fail++; ++ return; ++ } ++ ++ pfwinfo->cnt_h2c++; ++ ++ ret = rtw89_fw_h2c_raw_with_hdr(rtwdev, h2c_class, h2c_func, param, len, ++ false, true); ++ if (ret != 0) ++ pfwinfo->cnt_h2c_fail++; + } + + static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) +-- +2.13.6 + diff --git a/SOURCES/0028-rtw89-coex-Add-MAC-API-to-get-BT-polluted-counter.patch b/SOURCES/0028-rtw89-coex-Add-MAC-API-to-get-BT-polluted-counter.patch new file mode 100644 index 0000000..d81c512 --- /dev/null +++ b/SOURCES/0028-rtw89-coex-Add-MAC-API-to-get-BT-polluted-counter.patch @@ -0,0 +1,113 @@ +From 28c1d4c167238010c6bfee8c86d9964a889b9acd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 28/36] rtw89: coex: Add MAC API to get BT polluted counter +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 8c7e9ceb5bacec842784e5568c36769e97d96acb +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:25 2021 +0800 + + rtw89: coex: Add MAC API to get BT polluted counter + + Add function to get and parse BT polluted counter. + When WLAN Tx was dropped by BT, the packet will be marked as BT polluted. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-4-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/coex.c | 6 ++++-- + drivers/net/wireless/realtek/rtw89/core.h | 1 + + drivers/net/wireless/realtek/rtw89/mac.c | 12 ++++++++++++ + drivers/net/wireless/realtek/rtw89/mac.h | 1 + + 4 files changed, 18 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +index c8f912e7344d..8763114eab27 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.c ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -1126,6 +1126,9 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, + wl->ver_info.fw_coex = prpt->wl_fw_coex_ver; + wl->ver_info.fw = prpt->wl_fw_ver; + dm->wl_fw_cx_offload = !!(prpt->wl_fw_cx_offload); ++ ++ btc->cx.cnt_bt[BTC_BCNT_POLUT] = ++ rtw89_mac_get_plt_cnt(rtwdev, RTW89_MAC_0); + } + + if (rpt_type >= BTC_RPT_TYPE_BT_VER && +@@ -4798,7 +4801,6 @@ static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) + struct rtw89_btc_module *module = &btc->mdinfo; + struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; + u8 *afh = bt_linfo->afh_map; +- u16 polt_cnt = 0; + + if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT)) + return; +@@ -4884,7 +4886,7 @@ static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) + " %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)\n", + "[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX], + cx->cnt_bt[BTC_BCNT_HIPRI_TX], cx->cnt_bt[BTC_BCNT_LOPRI_RX], +- cx->cnt_bt[BTC_BCNT_LOPRI_TX], polt_cnt); ++ cx->cnt_bt[BTC_BCNT_LOPRI_TX], cx->cnt_bt[BTC_BCNT_POLUT]); + } + + #define CASE_BTC_RSN_STR(e) case BTC_RSN_ ## e: return #e +diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h +index c03e3a13bd56..7c84556ec4ad 100644 +--- a/drivers/net/wireless/realtek/rtw89/core.h ++++ b/drivers/net/wireless/realtek/rtw89/core.h +@@ -805,6 +805,7 @@ enum rtw89_btc_bt_state_cnt { + BTC_BCNT_HIPRI_RX, + BTC_BCNT_LOPRI_TX, + BTC_BCNT_LOPRI_RX, ++ BTC_BCNT_POLUT, + BTC_BCNT_RATECHG, + BTC_BCNT_NUM + }; +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index 999459489e92..b98c47e9ecfe 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -3450,6 +3450,18 @@ bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) + return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); + } + ++u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) ++{ ++ u32 reg; ++ u16 cnt; ++ ++ reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); ++ cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); ++ rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); ++ ++ return cnt; ++} ++ + static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) + { + u32 reg; +diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h +index 94cd29bd83d7..b7d13edf7dd1 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.h ++++ b/drivers/net/wireless/realtek/rtw89/mac.h +@@ -788,6 +788,7 @@ int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex + int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, + const struct rtw89_mac_ax_coex_gnt *gnt_cfg); + int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); ++u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); + void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); + u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); + bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); +-- +2.13.6 + diff --git a/SOURCES/0029-rtw89-coex-Define-LPS-state-for-BTC-using.patch b/SOURCES/0029-rtw89-coex-Define-LPS-state-for-BTC-using.patch new file mode 100644 index 0000000..d65e510 --- /dev/null +++ b/SOURCES/0029-rtw89-coex-Define-LPS-state-for-BTC-using.patch @@ -0,0 +1,82 @@ +From ac6eb6a8bbca1aa358b288ee694c62c740623283 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 29/36] rtw89: coex: Define LPS state for BTC using +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 2200ff3f0d1df9f41d0a5589e4a9572b4f627796 +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:26 2021 +0800 + + rtw89: coex: Define LPS state for BTC using + + To distinguish three types of LPS state. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-5-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/coex.c | 8 ++++---- + drivers/net/wireless/realtek/rtw89/coex.h | 6 ++++++ + 2 files changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +index 8763114eab27..436f5ccb193a 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.c ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -1622,7 +1622,7 @@ static void _set_rf_trx_para(struct rtw89_dev *rtwdev) + _set_bt_rx_gain(rtwdev, para.bt_rx_gain); + + if (bt->enable.now == 0 || wl->status.map.rf_off == 1 || +- wl->status.map.lps == 1) ++ wl->status.map.lps == BTC_LPS_RF_OFF) + wl_stb_chg = 0; + else + wl_stb_chg = 1; +@@ -4225,16 +4225,16 @@ void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_sta + switch (rf_state) { + case BTC_RFCTRL_WL_OFF: + wl->status.map.rf_off = 1; +- wl->status.map.lps = 0; ++ wl->status.map.lps = BTC_LPS_OFF; + break; + case BTC_RFCTRL_FW_CTRL: + wl->status.map.rf_off = 0; +- wl->status.map.lps = 1; ++ wl->status.map.lps = BTC_LPS_RF_OFF; + break; + case BTC_RFCTRL_WL_ON: + default: + wl->status.map.rf_off = 0; +- wl->status.map.lps = 0; ++ wl->status.map.lps = BTC_LPS_OFF; + break; + } + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.h b/drivers/net/wireless/realtek/rtw89/coex.h +index 4b4565d15c9e..c3a722d259d7 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.h ++++ b/drivers/net/wireless/realtek/rtw89/coex.h +@@ -130,6 +130,12 @@ enum btc_rfctrl { + BTC_RFCTRL_MAX + }; + ++enum btc_lps_state { ++ BTC_LPS_OFF = 0, ++ BTC_LPS_RF_OFF = 1, ++ BTC_LPS_RF_ON = 2 ++}; ++ + void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev); + void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev); + void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode); +-- +2.13.6 + diff --git a/SOURCES/0030-rtw89-coex-Update-BT-counters-while-receiving-report.patch b/SOURCES/0030-rtw89-coex-Update-BT-counters-while-receiving-report.patch new file mode 100644 index 0000000..433a26a --- /dev/null +++ b/SOURCES/0030-rtw89-coex-Update-BT-counters-while-receiving-report.patch @@ -0,0 +1,118 @@ +From 1b91f335400f3c9937b7c2b6f396352fc8ecc7f7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 30/36] rtw89: coex: Update BT counters while receiving report +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit eb87d79911c65ab8973ee8292802f0da6b7c67a4 +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:27 2021 +0800 + + rtw89: coex: Update BT counters while receiving report + + Move _chk_btc_err and update_bt_cnt to _chk_btc_report(), + so we can update counter/info to COEX at a proper moment, + instead of relying on a user does cat the debug info periodically. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-6-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/coex.c | 32 +++++++++++++++---------------- + 1 file changed, 15 insertions(+), 17 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +index 436f5ccb193a..929818c3a776 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.c ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -1118,6 +1118,10 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, + diff_t = pcysta->tavg_cycle[CXT_WL] - wl_slot_set; + _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t); + } ++ ++ _chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]); ++ _chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]); ++ _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles); + } + + if (rpt_type == BTC_RPT_TYPE_CTRL) { +@@ -1127,8 +1131,17 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, + wl->ver_info.fw = prpt->wl_fw_ver; + dm->wl_fw_cx_offload = !!(prpt->wl_fw_cx_offload); + +- btc->cx.cnt_bt[BTC_BCNT_POLUT] = +- rtw89_mac_get_plt_cnt(rtwdev, RTW89_MAC_0); ++ _chk_btc_err(rtwdev, BTC_DCNT_RPT_FREEZE, ++ pfwinfo->event[BTF_EVNT_RPT]); ++ ++ /* To avoid I/O if WL LPS or power-off */ ++ if (wl->status.map.lps != BTC_LPS_RF_OFF && !wl->status.map.rf_off) { ++ rtwdev->chip->ops->btc_update_bt_cnt(rtwdev); ++ _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_FREEZE, 0); ++ ++ btc->cx.cnt_bt[BTC_BCNT_POLUT] = ++ rtw89_mac_get_plt_cnt(rtwdev, RTW89_MAC_0); ++ } + } + + if (rpt_type >= BTC_RPT_TYPE_BT_VER && +@@ -4793,7 +4806,6 @@ static void _show_bt_profile_info(struct rtw89_dev *rtwdev, struct seq_file *m) + + static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) + { +- const struct rtw89_chip_info *chip = rtwdev->chip; + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_cx *cx = &btc->cx; + struct rtw89_btc_bt_info *bt = &cx->bt; +@@ -4876,12 +4888,6 @@ static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) + cx->cnt_bt[BTC_BCNT_INFOUPDATE], + cx->cnt_bt[BTC_BCNT_INFOSAME]); + +- if (wl->status.map.lps || wl->status.map.rf_off) +- return; +- +- chip->ops->btc_update_bt_cnt(rtwdev); +- _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_FREEZE, 0); +- + seq_printf(m, + " %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)\n", + "[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX], +@@ -5254,8 +5260,6 @@ static void _show_fbtc_cysta(struct rtw89_dev *rtwdev, struct seq_file *m) + pcysta->bcn_cnt[CXBCN_BT_SLOT], + pcysta->bcn_cnt[CXBCN_BT_OK]); + +- _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_FREEZE, (u32)pcysta->cycles); +- + for (i = 0; i < CXST_MAX; i++) { + if (!pcysta->slot_cnt[i]) + continue; +@@ -5279,9 +5283,6 @@ static void _show_fbtc_cysta(struct rtw89_dev *rtwdev, struct seq_file *m) + } + seq_puts(m, "\n"); + +- _chk_btc_err(rtwdev, BTC_DCNT_W1_FREEZE, pcysta->slot_cnt[CXST_W1]); +- _chk_btc_err(rtwdev, BTC_DCNT_B1_FREEZE, pcysta->slot_cnt[CXST_B1]); +- + seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", + "[cycle_time]", + pcysta->tavg_cycle[CXT_WL], +@@ -5633,9 +5634,6 @@ static void _show_summary(struct rtw89_dev *rtwdev, struct seq_file *m) + pfwinfo->event[BTF_EVNT_RPT], prptctrl->rpt_cnt, + prptctrl->rpt_enable, dm->error.val); + +- _chk_btc_err(rtwdev, BTC_DCNT_RPT_FREEZE, +- pfwinfo->event[BTF_EVNT_RPT]); +- + if (dm->error.map.wl_fw_hang) + seq_puts(m, " (WL FW Hang!!)"); + seq_puts(m, "\n"); +-- +2.13.6 + diff --git a/SOURCES/0031-rtw89-coex-Cancel-PS-leaving-while-C2H-comes.patch b/SOURCES/0031-rtw89-coex-Cancel-PS-leaving-while-C2H-comes.patch new file mode 100644 index 0000000..b52c42e --- /dev/null +++ b/SOURCES/0031-rtw89-coex-Cancel-PS-leaving-while-C2H-comes.patch @@ -0,0 +1,50 @@ +From 3880474c7442b138b17f8009b8a40037bbaf484c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 31/36] rtw89: coex: Cancel PS leaving while C2H comes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit bd309c8b4965b67917d8828c97d1b6741377cb8e +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:28 2021 +0800 + + rtw89: coex: Cancel PS leaving while C2H comes + + It's unnecessary to leave WL PS while C2H comes. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-7-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/coex.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c +index 929818c3a776..9f7d4f8d0c56 100644 +--- a/drivers/net/wireless/realtek/rtw89/coex.c ++++ b/drivers/net/wireless/realtek/rtw89/coex.c +@@ -4553,14 +4553,12 @@ void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, + rtw89_debug(rtwdev, RTW89_DBG_BTC, + "[BTC], handle C2H BT INFO with data %8ph\n", buf); + btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE]++; +- rtw89_leave_ps_mode(rtwdev); + _update_bt_info(rtwdev, buf, len); + break; + case BTF_EVNT_BT_SCBD: + rtw89_debug(rtwdev, RTW89_DBG_BTC, + "[BTC], handle C2H BT SCBD with data %8ph\n", buf); + btc->cx.cnt_bt[BTC_BCNT_SCBDUPDATE]++; +- rtw89_leave_ps_mode(rtwdev); + _update_bt_scbd(rtwdev, false); + break; + case BTF_EVNT_BT_PSD: +-- +2.13.6 + diff --git a/SOURCES/0032-rtw89-coex-Update-COEX-to-5.5.8.patch b/SOURCES/0032-rtw89-coex-Update-COEX-to-5.5.8.patch new file mode 100644 index 0000000..85e2a07 --- /dev/null +++ b/SOURCES/0032-rtw89-coex-Update-COEX-to-5.5.8.patch @@ -0,0 +1,44 @@ +From c5f1d2ed0a760267c6927d3d1670cffe02c51953 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 32/36] rtw89: coex: Update COEX to 5.5.8 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 4c02043c5a5270c5b6e11ca1c695ac17043a3e88 +Author: Ching-Te Ku +Date: Thu Dec 9 16:32:29 2021 +0800 + + rtw89: coex: Update COEX to 5.5.8 + + Update COEX version. + + Signed-off-by: Ching-Te Ku + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211209083229.10815-8-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +index 5ec13ae0abcd..6b75e4bc7352 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -2031,7 +2031,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = { + .limit_efuse_size = 1152, + .phycap_addr = 0x580, + .phycap_size = 128, +- .para_ver = 0x05050764, ++ .para_ver = 0x05050864, + .wlcx_desired = 0x05050000, + .btcx_desired = 0x5, + .scbd = 0x1, +-- +2.13.6 + diff --git a/SOURCES/0033-rtw89-8852a-correct-bit-definition-of-dfs_en.patch b/SOURCES/0033-rtw89-8852a-correct-bit-definition-of-dfs_en.patch new file mode 100644 index 0000000..e62428c --- /dev/null +++ b/SOURCES/0033-rtw89-8852a-correct-bit-definition-of-dfs_en.patch @@ -0,0 +1,45 @@ +From 67e9706f32aa28ec91467d694c72055e3cfe709c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 33/36] rtw89: 8852a: correct bit definition of dfs_en +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 + +commit 5f48d7bbec3775c9388c91c6920a64076f7ae339 +Author: Chung-Hsuan Hung +Date: Tue Dec 21 10:48:00 2021 +0800 + + rtw89: 8852a: correct bit definition of dfs_en + + Since there are other protections in the set channel flow, fortunately old + wrong setting won't affect the performance. + + Signed-off-by: Chung-Hsuan Hung + Signed-off-by: Ping-Ke Shih + Signed-off-by: Kalle Valo + Link: https://lore.kernel.org/r/20211221024800.23814-1-pkshih@realtek.com + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/reg.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h +index b6049009f183..e0a416d37d0e 100644 +--- a/drivers/net/wireless/realtek/rtw89/reg.h ++++ b/drivers/net/wireless/realtek/rtw89/reg.h +@@ -1658,7 +1658,7 @@ + #define R_RSTB_WATCH_DOG 0x000C + #define B_P0_RSTB_WATCH_DOG BIT(0) + #define B_P1_RSTB_WATCH_DOG BIT(1) +-#define B_UPD_P0_EN BIT(30) ++#define B_UPD_P0_EN BIT(31) + #define R_ANAPAR_PW15 0x030C + #define B_ANAPAR_PW15 GENMASK(31, 24) + #define B_ANAPAR_PW15_H GENMASK(27, 24) +-- +2.13.6 + diff --git a/SOURCES/0034-rtw89-fix-maybe-uninitialized-error-RHEL-only.patch b/SOURCES/0034-rtw89-fix-maybe-uninitialized-error-RHEL-only.patch new file mode 100644 index 0000000..eae81ef --- /dev/null +++ b/SOURCES/0034-rtw89-fix-maybe-uninitialized-error-RHEL-only.patch @@ -0,0 +1,46 @@ +From 12844a206de3d543be87b9fbe8af014ca353a974 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 34/36] rtw89: fix maybe-uninitialized error (RHEL only) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 +Upstream-status: RHEL8 only + +Fix build error of "maybe uninitialized variable", refering to _cur +variable in rtw8852a.c, function rtw8852a_btc_set_wl_txpwr_ctrl. +In fact it will never be uninitialized in this case because _reg values +used here are within the acceptable range for rtw89_mac_txpwr_read32 so +it will not return an error in this case. + +Upstream kernel is built with -Wno-maybe-uninitialized so this warning +does not prevent from building. However, that flag was added after RHEL8 +kernel fork, so we build without it. + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/rtw8852a.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852a.c b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +index 6b75e4bc7352..15337c638317 100644 +--- a/drivers/net/wireless/realtek/rtw89/rtw8852a.c ++++ b/drivers/net/wireless/realtek/rtw89/rtw8852a.c +@@ -1806,9 +1806,11 @@ rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) + const u32 _reg = __btc_cr_ ## _case; \ + u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ + u32 _cur, _wrt; \ ++ int ret; \ + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ + "btc ctrl %s: 0x%x\n", #_case, _val); \ +- rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ ++ ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ ++ if (ret) break; \ + rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ + "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ + _wrt = __do_clr(_val) ? \ +-- +2.13.6 + diff --git a/SOURCES/0035-rtw89-enable-driver-and-device-RTL8852AE.patch b/SOURCES/0035-rtw89-enable-driver-and-device-RTL8852AE.patch new file mode 100644 index 0000000..db55531 --- /dev/null +++ b/SOURCES/0035-rtw89-enable-driver-and-device-RTL8852AE.patch @@ -0,0 +1,38 @@ +From 067322075a8cdb1e466da71f7d7560062591ed54 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:04 +0100 +Subject: [PATCH 35/36] rtw89: enable driver and device RTL8852AE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 +Upstream-status: Posted https://gitlab.com/cki-project/kernel-ark/-/merge_requests/1570 + +Enable new driver rtw89 and device RTL8852AE + +Signed-off-by: Íñigo Huguet +--- + redhat/configs/generic/CONFIG_RTW89 | 1 + + redhat/configs/generic/CONFIG_RTW89_8852AE | 1 + + 2 files changed, 2 insertions(+) + create mode 100644 redhat/configs/generic/CONFIG_RTW89 + create mode 100644 redhat/configs/generic/CONFIG_RTW89_8852AE + +diff --git a/redhat/configs/generic/CONFIG_RTW89 b/redhat/configs/generic/CONFIG_RTW89 +new file mode 100644 +index 000000000000..48f9cf9f73e3 +--- /dev/null ++++ b/redhat/configs/generic/CONFIG_RTW89 +@@ -0,0 +1 @@ ++CONFIG_RTW89=m +diff --git a/redhat/configs/generic/CONFIG_RTW89_8852AE b/redhat/configs/generic/CONFIG_RTW89_8852AE +new file mode 100644 +index 000000000000..d8ef20a039eb +--- /dev/null ++++ b/redhat/configs/generic/CONFIG_RTW89_8852AE +@@ -0,0 +1 @@ ++CONFIG_RTW89_8852AE=m +-- +2.13.6 + diff --git a/SOURCES/0036-rtw89-fix-maybe-uninitialized-error.patch b/SOURCES/0036-rtw89-fix-maybe-uninitialized-error.patch new file mode 100644 index 0000000..139d51d --- /dev/null +++ b/SOURCES/0036-rtw89-fix-maybe-uninitialized-error.patch @@ -0,0 +1,44 @@ +From a76d23ad6ef2bf7e7f7f1718d74e799ca7e64c77 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=C3=8D=C3=B1igo=20Huguet?= +Date: Fri, 21 Jan 2022 08:49:05 +0100 +Subject: [PATCH 36/36] rtw89: fix maybe-uninitialized error +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Bugzilla: http://bugzilla.redhat.com/2033291 +Upstream-status: Posted https://patchwork.kernel.org/project/linux-wireless/patch/20220113094253.73370-1-ihuguet@redhat.com/ + +Author: Íñigo Huguet + + rtw89: fix maybe-uninitialized error + + Call to dle_dfi_qempty might fail, leaving qempty.qempty untouched, which + is latter used to control the for loop. If that happens, it's not + initialized anywhere. + + Initialize it so the loop doesn't iterate unless it's modified by the + call to dle_dfi_qempty. + + Signed-off-by: Íñigo Huguet + +Signed-off-by: Íñigo Huguet +--- + drivers/net/wireless/realtek/rtw89/mac.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c +index b98c47e9ecfe..7c3e547006cd 100644 +--- a/drivers/net/wireless/realtek/rtw89/mac.c ++++ b/drivers/net/wireless/realtek/rtw89/mac.c +@@ -172,6 +172,7 @@ static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) + + qempty.dle_type = DLE_CTRL_TYPE_PLE; + qempty.grpsel = 0; ++ qempty.qempty = ~(u32)0; + ret = dle_dfi_qempty(rtwdev, &qempty); + if (ret) + rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); +-- +2.13.6 + diff --git a/SOURCES/9000-force-enable-rtw89.patch b/SOURCES/9000-force-enable-rtw89.patch new file mode 100644 index 0000000..5cd2d3d --- /dev/null +++ b/SOURCES/9000-force-enable-rtw89.patch @@ -0,0 +1,14 @@ +Index: src/drivers/net/wireless/realtek/rtw89/Makefile +=================================================================== +--- src.orig/drivers/net/wireless/realtek/rtw89/Makefile 2022-01-26 22:56:38.152946163 +0100 ++++ src/drivers/net/wireless/realtek/rtw89/Makefile 2022-02-01 03:35:33.804917507 +0100 +@@ -1,5 +1,9 @@ + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause + ++CONFIG_RTW89_CORE := m ++CONFIG_RTW89_PCI := m ++CONFIG_RTW89_8852AE := m ++ + obj-$(CONFIG_RTW89_CORE) += rtw89_core.o + rtw89_core-y += core.o \ + mac80211.o \ diff --git a/SOURCES/9001-add-driver-version.patch b/SOURCES/9001-add-driver-version.patch new file mode 100644 index 0000000..8c6d910 --- /dev/null +++ b/SOURCES/9001-add-driver-version.patch @@ -0,0 +1,18 @@ +Index: src/drivers/net/wireless/realtek/rtw89/core.c +=================================================================== +--- src.orig/drivers/net/wireless/realtek/rtw89/core.c 2022-02-01 03:34:55.998152930 +0100 ++++ src/drivers/net/wireless/realtek/rtw89/core.c 2022-02-01 03:36:17.249725882 +0100 +@@ -2504,3 +2504,4 @@ + MODULE_AUTHOR("Realtek Corporation"); + MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); + MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_VERSION("4.18.0_363_dup8.5"); +Index: src/drivers/net/wireless/realtek/rtw89/pci.c +=================================================================== +--- src.orig/drivers/net/wireless/realtek/rtw89/pci.c 2022-01-26 22:56:38.384944089 +0100 ++++ src/drivers/net/wireless/realtek/rtw89/pci.c 2022-02-01 03:36:39.679626949 +0100 +@@ -3058,3 +3058,4 @@ + MODULE_AUTHOR("Realtek Corporation"); + MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); + MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_VERSION("4.18.0_363_dup8.5"); diff --git a/SOURCES/9002-change-firmware-path.patch b/SOURCES/9002-change-firmware-path.patch new file mode 100644 index 0000000..e290245 --- /dev/null +++ b/SOURCES/9002-change-firmware-path.patch @@ -0,0 +1,19 @@ +Index: src/drivers/net/wireless/realtek/rtw89/rtw8852a.c +=================================================================== +--- src.orig/drivers/net/wireless/realtek/rtw89/rtw8852a.c 2022-02-01 03:51:01.506584795 +0100 ++++ src/drivers/net/wireless/realtek/rtw89/rtw8852a.c 2022-02-01 15:55:44.165428825 +0100 +@@ -2000,7 +2000,7 @@ + const struct rtw89_chip_info rtw8852a_chip_info = { + .chip_id = RTL8852A, + .ops = &rtw8852a_chip_ops, +- .fw_name = "rtw89/rtw8852a_fw.bin", ++ .fw_name = "rtw89/rtw8852a_fw_dup85.bin", + .fifo_size = 458752, + .max_amsdu_limit = 3500, + .dis_2g_40m_ul_ofdma = true, +@@ -2054,4 +2054,4 @@ + }; + EXPORT_SYMBOL(rtw8852a_chip_info); + +-MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); ++MODULE_FIRMWARE("rtw89/rtw8852a_fw_dup85.bin"); diff --git a/SPECS/kmod-redhat-rtw89.spec b/SPECS/kmod-redhat-rtw89.spec new file mode 100644 index 0000000..9e3d081 --- /dev/null +++ b/SPECS/kmod-redhat-rtw89.spec @@ -0,0 +1,402 @@ +%define kmod_name rtw89 +%define kmod_vendor redhat +%define kmod_rpm_name kmod-redhat-rtw89 +%define kmod_driver_version 4.18.0_363_dup8.5 +%define kmod_driver_epoch %{nil} +%define kmod_rpm_release 1 +%define kmod_kernel_version 4.18.0-348.el8 +%define kmod_kernel_version_min %{nil} +%define kmod_kernel_version_dep %{nil} +%define kmod_kbuild_dir drivers/net/wireless/realtek/rtw89 +%define kmod_dependencies %{nil} +%define kmod_dist_build_deps %{nil} +%define kmod_build_dependencies %{nil} +%define kmod_provides %{nil} +%define kmod_devel_package 1 +%define kmod_devel_src_paths %{nil} +%define kmod_install_path extra/kmod-redhat-rtw89 +%define kmod_files_package 0 +%define kmod_files_noarch 1 +%define kernel_pkg kernel +%define kernel_devel_pkg kernel-devel +%define kernel_modules_pkg kernel-modules + +%{!?dist: %define dist .el8_5} +%{!?make_build: %define make_build make} + +%if "%{kmod_kernel_version_dep}" == "" +%define kmod_kernel_version_dep %{kmod_kernel_version} +%endif + +%if "%{kmod_dist_build_deps}" == "" +%if (0%{?rhel} > 7) || (0%{?centos} > 7) +%define kmod_dist_build_deps redhat-rpm-config kernel-abi-whitelists elfutils-libelf-devel kernel-rpm-macros kmod +%else +%define kmod_dist_build_deps redhat-rpm-config kernel-abi-whitelists +%endif +%endif + +Source0: %{kmod_name}-%{kmod_vendor}-%{kmod_driver_version}.tar.bz2 +# Source code patches +Patch0: 0001-rtw89-add-Realtek-802.11ax-driver.patch +Patch1: 0002-rtw89-Fix-two-spelling-mistakes-in-debug-messages.patch +Patch2: 0003-rtw89-Remove-redundant-check-of-ret-after-call-to-rt.patch +Patch3: 0004-rtw89-fix-return-value-check-in-rtw89_cam_send_sec_k.patch +Patch4: 0005-rtw89-remove-unneeded-semicolon.patch +Patch5: 0006-rtw89-fix-error-function-parameter.patch +Patch6: 0007-rtw89-remove-duplicate-register-definitions.patch +Patch7: 0008-rtw89-fix-return-value-in-hfc_pub_cfg_chk.patch +Patch8: 0009-rtw89-Fix-variable-dereferenced-before-check-sta.patch +Patch9: 0010-rtw89-update-partition-size-of-firmware-header-on-sk.patch +Patch10: 0011-rtw89-fill-regd-field-of-limit-limit_ru-tables-by-en.patch +Patch11: 0012-rtw89-update-rtw89-regulation-definition-to-R58-R31.patch +Patch12: 0013-rtw89-update-tx-power-limit-limit_ru-tables-to-R54.patch +Patch13: 0014-rtw89-update-rtw89_regulatory-map-to-R58-R31.patch +Patch14: 0015-rtw89-remove-unnecessary-conditional-operators.patch +Patch15: 0016-rtw89-remove-unneeded-variable.patch +Patch16: 0017-rtw89-fix-potentially-access-out-of-range-of-RF-regi.patch +Patch17: 0018-rtw89-add-AXIDMA-and-TX-FIFO-dump-in-mac_mem_dump.patch +Patch18: 0019-rtw89-add-const-in-the-cast-of-le32_get_bits.patch +Patch19: 0020-rtw89-use-inline-function-instead-macro-to-set-H2C-a.patch +Patch20: 0021-rtw89-update-scan_mac_addr-during-scanning-period.patch +Patch21: 0022-rtw89-fix-incorrect-channel-info-during-scan.patch +Patch22: 0023-rtw89-fix-sending-wrong-rtwsta-mac_id-to-firmware-to.patch +Patch23: 0024-rtw89-remove-cch_by_bw-which-is-not-used.patch +Patch24: 0025-rtw89-don-t-kick-off-TX-DMA-if-failed-to-write-skb.patch +Patch25: 0026-rtw89-coex-correct-C2H-header-length.patch +Patch26: 0027-rtw89-coex-Not-to-send-H2C-when-WL-not-ready-and-cou.patch +Patch27: 0028-rtw89-coex-Add-MAC-API-to-get-BT-polluted-counter.patch +Patch28: 0029-rtw89-coex-Define-LPS-state-for-BTC-using.patch +Patch29: 0030-rtw89-coex-Update-BT-counters-while-receiving-report.patch +Patch30: 0031-rtw89-coex-Cancel-PS-leaving-while-C2H-comes.patch +Patch31: 0032-rtw89-coex-Update-COEX-to-5.5.8.patch +Patch32: 0033-rtw89-8852a-correct-bit-definition-of-dfs_en.patch +Patch33: 0034-rtw89-fix-maybe-uninitialized-error-RHEL-only.patch +Patch34: 0035-rtw89-enable-driver-and-device-RTL8852AE.patch +Patch35: 0036-rtw89-fix-maybe-uninitialized-error.patch +Patch36: 9000-force-enable-rtw89.patch +Patch37: 9001-add-driver-version.patch +Patch38: 9002-change-firmware-path.patch + +%define findpat %( echo "%""P" ) +%define __find_requires /usr/lib/rpm/redhat/find-requires.ksyms +%define __find_provides /usr/lib/rpm/redhat/find-provides.ksyms %{kmod_name} %{?epoch:%{epoch}:}%{version}-%{release} +%define sbindir %( if [ -d "/sbin" -a \! -h "/sbin" ]; then echo "/sbin"; else echo %{_sbindir}; fi ) +%define dup_state_dir %{_localstatedir}/lib/rpm-state/kmod-dups +%define kver_state_dir %{dup_state_dir}/kver +%define kver_state_file %{kver_state_dir}/%{kmod_kernel_version}.%(arch) +%define dup_module_list %{dup_state_dir}/rpm-kmod-%{kmod_name}-modules + +Name: kmod-redhat-rtw89 +Version: %{kmod_driver_version} +Release: %{kmod_rpm_release}%{?dist} +%if "%{kmod_driver_epoch}" != "" +Epoch: %{kmod_driver_epoch} +%endif +Summary: rtw89 kernel module for Driver Update Program +Group: System/Kernel +License: GPLv2 +URL: https://www.kernel.org/ +BuildRoot: %(mktemp -ud %{_tmppath}/%{name}-%{version}-%{release}-XXXXXX) +BuildRequires: %kernel_devel_pkg = %kmod_kernel_version +%if "%{kmod_dist_build_deps}" != "" +BuildRequires: %{kmod_dist_build_deps} +%endif +ExclusiveArch: x86_64 +%global kernel_source() /usr/src/kernels/%{kmod_kernel_version}.$(arch) + +%global _use_internal_dependency_generator 0 +%if "%{?kmod_kernel_version_min}" != "" +Provides: %kernel_modules_pkg >= %{kmod_kernel_version_min}.%{_target_cpu} +%else +Provides: %kernel_modules_pkg = %{kmod_kernel_version_dep}.%{_target_cpu} +%endif +Provides: kmod-%{kmod_name} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires(post): %{sbindir}/weak-modules +Requires(postun): %{sbindir}/weak-modules +Requires: kernel >= 4.18.0-348.el8 + +Requires: kernel < 4.18.0-349.el8 +%if 1 +Requires: firmware(%{kmod_name}) = 20211119_105.gitf5d51956_dup8.5 +%endif +%if "%{kmod_build_dependencies}" != "" +BuildRequires: %{kmod_build_dependencies} +%endif +%if "%{kmod_dependencies}" != "" +Requires: %{kmod_dependencies} +%endif +%if "%{kmod_provides}" != "" +Provides: %{kmod_provides} +%endif +# if there are multiple kmods for the same driver from different vendors, +# they should conflict with each other. +Conflicts: kmod-%{kmod_name} + +%description +rtw89 kernel module for Driver Update Program + +%if 1 + +%package -n kmod-redhat-rtw89-firmware +Version: 20211119_105.gitf5d51956_dup8.5 +Summary: rtw89 firmware for Driver Update Program +Provides: firmware(%{kmod_name}) = 20211119_105.gitf5d51956_dup8.5 +%if "%{kmod_kernel_version_min}" != "" +Provides: %kernel_modules_pkg >= %{kmod_kernel_version_min}.%{_target_cpu} +%else +Provides: %kernel_modules_pkg = %{kmod_kernel_version_dep}.%{_target_cpu} +%endif +%description -n kmod-redhat-rtw89-firmware +rtw89 firmware for Driver Update Program + + +%files -n kmod-redhat-rtw89-firmware +%defattr(644,root,root,755) +/lib/firmware/rtw89/rtw8852a_fw_dup85.bin + + +%endif + +# Development package +%if 0%{kmod_devel_package} +%package -n kmod-redhat-rtw89-devel +Version: %{kmod_driver_version} +Requires: kernel >= 4.18.0-348.el8 + +Requires: kernel < 4.18.0-349.el8 +Summary: rtw89 development files for Driver Update Program + +%description -n kmod-redhat-rtw89-devel +rtw89 development files for Driver Update Program + + +%files -n kmod-redhat-rtw89-devel +%defattr(644,root,root,755) +/lib/modules/%{kmod_rpm_name}-%{kmod_driver_version}/ +%endif + +# Extra files package +%if 0%{kmod_files_package} +%package -n kmod-redhat-rtw89-files +Version: %{kmod_driver_version} +Summary: rtw89 additional files for Driver Update Program +%if 0%{kmod_files_noarch} +BuildArch: noarch +%endif +%if "%{?kmod_kernel_version_min}" != "" +Provides: %kernel_modules_pkg >= %{kmod_kernel_version_min}.%{_target_cpu} +%else +Provides: %kernel_modules_pkg = %{kmod_kernel_version_dep}.%{_target_cpu} +%endif + +%description -n kmod-redhat-rtw89-files +rtw89 additional files for Driver Update Program + + +%files -n kmod-redhat-rtw89-files +%defattr(644,root,root,755) +/etc/dracut.conf.d/kmod-redhat-rtw89_dup85.conf +%endif + +%post +modules=( $(find /lib/modules/%{kmod_kernel_version}.%(arch)/%{kmod_install_path} | grep '\.ko$') ) +printf '%s\n' "${modules[@]}" | %{sbindir}/weak-modules --add-modules --no-initramfs + +mkdir -p "%{kver_state_dir}" +touch "%{kver_state_file}" + +exit 0 + +%posttrans +# We have to re-implement part of weak-modules here because it doesn't allow +# calling initramfs regeneration separately +if [ -f "%{kver_state_file}" ]; then + kver_base="%{kmod_kernel_version_dep}" + kvers=$(ls -d "/lib/modules/${kver_base%%.*}"*) + + for k_dir in $kvers; do + k="${k_dir#/lib/modules/}" + + tmp_initramfs="/boot/initramfs-$k.tmp" + dst_initramfs="/boot/initramfs-$k.img" + + # The same check as in weak-modules: we assume that the kernel present + # if the symvers file exists. + if [ -e "/boot/symvers-$k.gz" ] || [ -e "$k_dir/symvers.gz" ]; then + /usr/bin/dracut -f "$tmp_initramfs" "$k" || exit 1 + cmp -s "$tmp_initramfs" "$dst_initramfs" + if [ "$?" = 1 ]; then + mv "$tmp_initramfs" "$dst_initramfs" + else + rm -f "$tmp_initramfs" + fi + fi + done + + rm -f "%{kver_state_file}" + rmdir "%{kver_state_dir}" 2> /dev/null +fi + +rmdir "%{dup_state_dir}" 2> /dev/null + +exit 0 + +%preun +if rpm -q --filetriggers kmod 2> /dev/null| grep -q "Trigger for weak-modules call on kmod removal"; then + mkdir -p "%{kver_state_dir}" + touch "%{kver_state_file}" +fi + +mkdir -p "%{dup_state_dir}" +rpm -ql kmod-redhat-rtw89-%{kmod_driver_version}-%{kmod_rpm_release}%{?dist}.$(arch) | \ + grep '\.ko$' > "%{dup_module_list}" + +%postun +if rpm -q --filetriggers kmod 2> /dev/null| grep -q "Trigger for weak-modules call on kmod removal"; then + initramfs_opt="--no-initramfs" +else + initramfs_opt="" +fi + +modules=( $(cat "%{dup_module_list}") ) +rm -f "%{dup_module_list}" +printf '%s\n' "${modules[@]}" | %{sbindir}/weak-modules --remove-modules $initramfs_opt + +rmdir "%{dup_state_dir}" 2> /dev/null + +exit 0 + +%files +%defattr(644,root,root,755) +/lib/modules/%{kmod_kernel_version}.%(arch) +/etc/depmod.d/%{kmod_name}.conf +%doc /usr/share/doc/%{kmod_rpm_name}/greylist.txt +%if !0%{kmod_files_package} +/etc/dracut.conf.d/kmod-redhat-rtw89_dup85.conf +%endif + +%prep +%setup -n %{kmod_name}-%{kmod_vendor}-%{kmod_driver_version} + +%patch0 -p1 +%patch1 -p1 +%patch2 -p1 +%patch3 -p1 +%patch4 -p1 +%patch5 -p1 +%patch6 -p1 +%patch7 -p1 +%patch8 -p1 +%patch9 -p1 +%patch10 -p1 +%patch11 -p1 +%patch12 -p1 +%patch13 -p1 +%patch14 -p1 +%patch15 -p1 +%patch16 -p1 +%patch17 -p1 +%patch18 -p1 +%patch19 -p1 +%patch20 -p1 +%patch21 -p1 +%patch22 -p1 +%patch23 -p1 +%patch24 -p1 +%patch25 -p1 +%patch26 -p1 +%patch27 -p1 +%patch28 -p1 +%patch29 -p1 +%patch30 -p1 +%patch31 -p1 +%patch32 -p1 +%patch33 -p1 +%patch34 -p1 +%patch35 -p1 +%patch36 -p1 +%patch37 -p1 +%patch38 -p1 +set -- * +mkdir source +mv "$@" source/ +mkdir obj + +%build +rm -rf obj +cp -r source obj + +PWD_PATH="$PWD" +%if "%{workaround_no_pwd_rel_path}" != "1" +PWD_PATH=$(realpath --relative-to="%{kernel_source}" . 2>/dev/null || echo "$PWD") +%endif +%{make_build} -C %{kernel_source} V=1 M="$PWD_PATH/obj/%{kmod_kbuild_dir}" \ + NOSTDINC_FLAGS="-I$PWD_PATH/obj/include -I$PWD_PATH/obj/include/uapi %{nil}" \ + EXTRA_CFLAGS="%{nil}" \ + %{nil} +# mark modules executable so that strip-to-file can strip them +find obj/%{kmod_kbuild_dir} -name "*.ko" -type f -exec chmod u+x '{}' + + +whitelist="/lib/modules/kabi-current/kabi_whitelist_%{_target_cpu}" +for modules in $( find obj/%{kmod_kbuild_dir} -name "*.ko" -type f -printf "%{findpat}\n" | sed 's|\.ko$||' | sort -u ) ; do + # update depmod.conf + module_weak_path=$(echo "$modules" | sed 's/[\/]*[^\/]*$//') + if [ -z "$module_weak_path" ]; then + module_weak_path=%{name} + else + module_weak_path=%{name}/$module_weak_path + fi + echo "override $(echo $modules | sed 's/.*\///')" \ + "$(echo "%{kmod_kernel_version_dep}" | + sed 's/\.[^\.]*$//; + s/\([.+?^$\/\\|()\[]\|\]\)/\\\0/g').*" \ + "weak-updates/$module_weak_path" >> source/depmod.conf + + # update greylist + nm -u obj/%{kmod_kbuild_dir}/$modules.ko | sed 's/.*U //' | sed 's/^\.//' | sort -u | while read -r symbol; do + grep -q "^\s*$symbol\$" $whitelist || echo "$symbol" >> source/greylist + done +done +sort -u source/greylist | uniq > source/greylist.txt + +%install +export INSTALL_MOD_PATH=$RPM_BUILD_ROOT +export INSTALL_MOD_DIR=%{kmod_install_path} +PWD_PATH="$PWD" +%if "%{workaround_no_pwd_rel_path}" != "1" +PWD_PATH=$(realpath --relative-to="%{kernel_source}" . 2>/dev/null || echo "$PWD") +%endif +make -C %{kernel_source} modules_install \ + M=$PWD_PATH/obj/%{kmod_kbuild_dir} +# Cleanup unnecessary kernel-generated module dependency files. +find $INSTALL_MOD_PATH/lib/modules -iname 'modules.*' -exec rm {} \; + +install -m 644 -D source/depmod.conf $RPM_BUILD_ROOT/etc/depmod.d/%{kmod_name}.conf +install -m 644 -D source/greylist.txt $RPM_BUILD_ROOT/usr/share/doc/%{kmod_rpm_name}/greylist.txt +%if 1 +install -m 644 -D source/firmware/rtw89/rtw8852a_fw_dup85.bin $RPM_BUILD_ROOT/lib/firmware/rtw89/rtw8852a_fw_dup85.bin + +%endif +%if 0%{kmod_devel_package} +install -m 644 -D $PWD/obj/%{kmod_kbuild_dir}/Module.symvers $RPM_BUILD_ROOT/lib/modules/%{kmod_rpm_name}-%{kmod_driver_version}/build/Module.symvers + +if [ -n "%{kmod_devel_src_paths}" ]; then + for i in %{kmod_devel_src_paths}; do + mkdir -p "$RPM_BUILD_ROOT/lib/modules/%{kmod_rpm_name}-%{kmod_driver_version}/build/$(dirname "$i")" + cp -rv "$PWD/source/$i" \ + "$RPM_BUILD_ROOT/lib/modules/%{kmod_rpm_name}-%{kmod_driver_version}/build/$i" + done +fi +%endif +install -m 664 -D source/extra//etc/dracut.conf.d/kmod-redhat-rtw89_dup85.conf $RPM_BUILD_ROOT//etc/dracut.conf.d/kmod-redhat-rtw89_dup85.conf + + +%clean +rm -rf $RPM_BUILD_ROOT + +%changelog +* Wed Feb 09 2022 Eugene Syromiatnikov 4.18.0_363_dup8.5-1 +- 9dc660bf1362f5a22a908e61004498cf7ec063a8 +- rtw89 kernel module for Driver Update Program +- Resolves: #bz2051886