From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:16 +0100

Subject: [PATCH 01/19] iommu: Introduce a union to struct iommu_resv_region

A union is introduced to struct iommu_resv_region to hold

any firmware specific data. This is in preparation to add

support for IORT RMR reserve regions and the union now holds

the RMR specific information.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 include/linux/iommu.h | 11 +++++++++++

 1 file changed, 11 insertions(+)

diff --git a/include/linux/iommu.h b/include/linux/iommu.h

index d2f3435e7d17..d5cfd0c6a217 100644

--- a/include/linux/iommu.h

+++ b/include/linux/iommu.h

@@ -126,6 +126,13 @@ enum iommu_resv_type {

 	IOMMU_RESV_SW_MSI,

 };

+struct iommu_iort_rmr_data {

+#define IOMMU_RMR_REMAP_PERMITTED	(1 << 0)

+	u32 flags;

+	u32 sid;	/* Stream Id associated with RMR entry */

+	void *smmu;	/* Associated IORT SMMU node pointer */

+};

+

 /**

  * struct iommu_resv_region - descriptor for a reserved memory region

  * @list: Linked list pointers

@@ -133,6 +140,7 @@ enum iommu_resv_type {

  * @length: Length of the region in bytes

  * @prot: IOMMU Protection flags (READ/WRITE/...)

  * @type: Type of the reserved region

+ * @rmr: ACPI IORT RMR specific data

  */

 struct iommu_resv_region {

 	struct list_head	list;

@@ -140,6 +148,9 @@ struct iommu_resv_region {

 	size_t			length;

 	int			prot;

 	enum iommu_resv_type	type;

+	union {

+		struct iommu_iort_rmr_data rmr;

+	} fw_data;

 };

 /**

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:17 +0100

Subject: [PATCH 02/19] ACPI/IORT: Add support for RMR node parsing

Add support for parsing RMR node information from ACPI.

Find the associated streamid and smmu node info from the

RMR node and populate a linked list with RMR memory

descriptors.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/acpi/arm64/iort.c | 134 +++++++++++++++++++++++++++++++++++++-

 1 file changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c

index f2f8f05662de..7df83d80819b 100644

--- a/drivers/acpi/arm64/iort.c

+++ b/drivers/acpi/arm64/iort.c

@@ -40,6 +40,8 @@ struct iort_fwnode {

 static LIST_HEAD(iort_fwnode_list);

 static DEFINE_SPINLOCK(iort_fwnode_lock);

+static LIST_HEAD(iort_rmr_list);	/* list of RMR regions from ACPI */

+

 /**

  * iort_set_fwnode() - Create iort_fwnode and use it to register

  *		       iommu data in the iort_fwnode_list

@@ -393,7 +395,8 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,

 		if (node->type == ACPI_IORT_NODE_NAMED_COMPONENT ||

 		    node->type == ACPI_IORT_NODE_PCI_ROOT_COMPLEX ||

 		    node->type == ACPI_IORT_NODE_SMMU_V3 ||

-		    node->type == ACPI_IORT_NODE_PMCG) {

+		    node->type == ACPI_IORT_NODE_PMCG ||

+		    node->type == ACPI_IORT_NODE_RMR) {

 			*id_out = map->output_base;

 			return parent;

 		}

@@ -1574,6 +1577,134 @@ static void __init iort_enable_acs(struct acpi_iort_node *iort_node)

 #else

 static inline void iort_enable_acs(struct acpi_iort_node *iort_node) { }

 #endif

+static void iort_rmr_desc_check_overlap(struct acpi_iort_rmr_desc *desc, u32 count)

+{

+	int i, j;

+

+	for (i = 0; i < count; i++) {

+		u64 end, start = desc[i].base_address, length = desc[i].length;

+

+		end = start + length - 1;

+

+		/* Check for address overlap */

+		for (j = i + 1; j < count; j++) {

+			u64 e_start = desc[j].base_address;

+			u64 e_end = e_start + desc[j].length - 1;

+

+			if (start <= e_end && end >= e_start)

+				pr_err(FW_BUG "RMR descriptor[0x%llx - 0x%llx] overlaps, continue anyway\n",

+				       start, end);

+		}

+	}

+}

+

+static void __init iort_node_get_rmr_info(struct acpi_iort_node *iort_node)

+{

+	struct acpi_iort_node *smmu;

+	struct acpi_iort_rmr *rmr;

+	struct acpi_iort_rmr_desc *rmr_desc;

+	u32 map_count = iort_node->mapping_count;

+	u32 sid;

+	int i;

+

+	if (!iort_node->mapping_offset || map_count != 1) {

+		pr_err(FW_BUG "Invalid ID mapping, skipping RMR node %p\n",

+		       iort_node);

+		return;

+	}

+

+	/* Retrieve associated smmu and stream id */

+	smmu = iort_node_get_id(iort_node, &sid, 0);

+	if (!smmu) {

+		pr_err(FW_BUG "Invalid SMMU reference, skipping RMR node %p\n",

+		       iort_node);

+		return;

+	}

+

+	/* Retrieve RMR data */

+	rmr = (struct acpi_iort_rmr *)iort_node->node_data;

+	if (!rmr->rmr_offset || !rmr->rmr_count) {

+		pr_err(FW_BUG "Invalid RMR descriptor array, skipping RMR node %p\n",

+		       iort_node);

+		return;

+	}

+

+	rmr_desc = ACPI_ADD_PTR(struct acpi_iort_rmr_desc, iort_node,

+				rmr->rmr_offset);

+

+	iort_rmr_desc_check_overlap(rmr_desc, rmr->rmr_count);

+

+	for (i = 0; i < rmr->rmr_count; i++, rmr_desc++) {

+		struct iommu_resv_region *region;

+		enum iommu_resv_type type;

+		int prot = IOMMU_READ | IOMMU_WRITE;

+		u64 addr = rmr_desc->base_address, size = rmr_desc->length;

+

+		if (!IS_ALIGNED(addr, SZ_64K) || !IS_ALIGNED(size, SZ_64K)) {

+			/* PAGE align base addr and size */

+			addr &= PAGE_MASK;

+			size = PAGE_ALIGN(size + offset_in_page(rmr_desc->base_address));

+

+			pr_err(FW_BUG "RMR descriptor[0x%llx - 0x%llx] not aligned to 64K, continue with [0x%llx - 0x%llx]\n",

+			       rmr_desc->base_address,

+			       rmr_desc->base_address + rmr_desc->length - 1,

+			       addr, addr + size - 1);

+		}

+		if (rmr->flags & IOMMU_RMR_REMAP_PERMITTED) {

+			type = IOMMU_RESV_DIRECT_RELAXABLE;

+			/*

+			 * Set IOMMU_CACHE as IOMMU_RESV_DIRECT_RELAXABLE is

+			 * normally used for allocated system memory that is

+			 * then used for device specific reserved regions.

+			 */

+			prot |= IOMMU_CACHE;

+		} else {

+			type = IOMMU_RESV_DIRECT;

+			/*

+			 * Set IOMMU_MMIO as IOMMU_RESV_DIRECT is normally used

+			 * for device memory like MSI doorbell.

+			 */

+			prot |= IOMMU_MMIO;

+		}

+

+		region = iommu_alloc_resv_region(addr, size, prot, type);

+		if (region) {

+			region->fw_data.rmr.flags = rmr->flags;

+			region->fw_data.rmr.sid = sid;

+			region->fw_data.rmr.smmu = smmu;

+			list_add_tail(&region->list, &iort_rmr_list);

+		}

+	}

+}

+

+static void __init iort_parse_rmr(void)

+{

+	struct acpi_iort_node *iort_node, *iort_end;

+	struct acpi_table_iort *iort;

+	int i;

+

+	if (iort_table->revision < 3)

+		return;

+

+	iort = (struct acpi_table_iort *)iort_table;

+

+	iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort,

+				 iort->node_offset);

+	iort_end = ACPI_ADD_PTR(struct acpi_iort_node, iort,

+				iort_table->length);

+

+	for (i = 0; i < iort->node_count; i++) {

+		if (WARN_TAINT(iort_node >= iort_end, TAINT_FIRMWARE_WORKAROUND,

+			       "IORT node pointer overflows, bad table!\n"))

+			return;

+

+		if (iort_node->type == ACPI_IORT_NODE_RMR)

+			iort_node_get_rmr_info(iort_node);

+

+		iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort_node,

+					 iort_node->length);

+	}

+}

 static void __init iort_init_platform_devices(void)

 {

@@ -1644,6 +1775,7 @@ void __init acpi_iort_init(void)

 	}

 	iort_init_platform_devices();

+	iort_parse_rmr();

 }

 #ifdef CONFIG_ZONE_DMA

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:18 +0100

Subject: [PATCH 03/19] iommu/dma: Introduce generic helper to retrieve RMR

 info

Reserved Memory Regions(RMR) associated with an IOMMU can be

described through ACPI IORT tables in systems with devices

that require a unity mapping or bypass for those

regions.

Introduce a generic interface so that IOMMU drivers can retrieve

and set up necessary mappings.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/iommu/dma-iommu.c | 29 +++++++++++++++++++++++++++++

 include/linux/dma-iommu.h | 13 +++++++++++++

 2 files changed, 42 insertions(+)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c

index 48c6f7ff4aef..72d801a5a5f7 100644

--- a/drivers/iommu/dma-iommu.c

+++ b/drivers/iommu/dma-iommu.c

@@ -174,6 +174,35 @@ void iommu_put_dma_cookie(struct iommu_domain *domain)

 }

 EXPORT_SYMBOL(iommu_put_dma_cookie);

+/**

+ *

+ * iommu_dma_get_rmrs - Retrieve Reserved Memory Regions(RMRs) associated

+ *                      with a given IOMMU

+ * @iommu_fwnode: fwnode associated with IOMMU

+ * @list: RMR list to be populated

+ *

+ */

+int iommu_dma_get_rmrs(struct fwnode_handle *iommu_fwnode,

+		       struct list_head *list)

+{

+	return -EINVAL;

+}

+EXPORT_SYMBOL(iommu_dma_get_rmrs);

+

+/**

+ *

+ * iommu_dma_put_rmrs - Release Reserved Memory Regions(RMRs) associated

+ *                      with a given IOMMU

+ * @iommu_fwnode: fwnode associated with IOMMU

+ * @list: RMR list

+ *

+ */

+void iommu_dma_put_rmrs(struct fwnode_handle *iommu_fwnode,

+			struct list_head *list)

+{

+}

+EXPORT_SYMBOL(iommu_dma_put_rmrs);

+

 /**

  * iommu_dma_get_resv_regions - Reserved region driver helper

  * @dev: Device from iommu_get_resv_regions()

diff --git a/include/linux/dma-iommu.h b/include/linux/dma-iommu.h

index 24607dc3c2ac..7579c014e274 100644

--- a/include/linux/dma-iommu.h

+++ b/include/linux/dma-iommu.h

@@ -43,12 +43,16 @@ void iommu_dma_free_cpu_cached_iovas(unsigned int cpu,

 extern bool iommu_dma_forcedac;

+int iommu_dma_get_rmrs(struct fwnode_handle *iommu, struct list_head *list);

+void iommu_dma_put_rmrs(struct fwnode_handle *iommu, struct list_head *list);

+

 #else /* CONFIG_IOMMU_DMA */

 struct iommu_domain;

 struct msi_desc;

 struct msi_msg;

 struct device;

+struct fwnode_handle;

 static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base,

 				       u64 dma_limit)

@@ -89,5 +93,14 @@ static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_he

 {

 }

+static int iommu_dma_get_rmrs(struct fwnode_handle *iommu, struct list_head *list)

+{

+	return -ENODEV;

+}

+

+static void iommu_dma_put_rmrs(struct fwnode_handle *iommu, struct list_head *list)

+{

+}

+

 #endif	/* CONFIG_IOMMU_DMA */

 #endif	/* __DMA_IOMMU_H */

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:19 +0100

Subject: [PATCH 04/19] ACPI/IORT: Add a helper to retrieve RMR memory regions

Add a helper function (iort_iommu_get_rmrs()) that retrieves RMR

memory descriptors associated with a given IOMMU. This will be used

by IOMMU drivers to setup necessary mappings.

Invoke it from the generic helper iommu_dma_get_rmrs().

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/acpi/arm64/iort.c | 38 ++++++++++++++++++++++++++++++++++++++

 drivers/iommu/dma-iommu.c |  4 ++++

 include/linux/acpi_iort.h |  7 +++++++

 3 files changed, 49 insertions(+)

diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c

index 7df83d80819b..66d200e577cb 100644

--- a/drivers/acpi/arm64/iort.c

+++ b/drivers/acpi/arm64/iort.c

@@ -809,6 +809,42 @@ static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev)

 	return NULL;

 }

+/**

+ * iort_iommu_get_rmrs() - Helper to retrieve RMR info associated with IOMMU

+ * @iommu_fwnode: fwnode for the IOMMU

+ * @head: RMR list head to be populated

+ *

+ * Returns: 0 on success, <0 failure. Please note, we will keep the already

+ *          allocated RMR reserve regions in case of a kmemdup()

+ *          failure.

+ */

+int iort_iommu_get_rmrs(struct fwnode_handle *iommu_fwnode,

+			struct list_head *head)

+{

+	struct iommu_resv_region *e;

+	struct acpi_iort_node *iommu;

+	int rmrs = 0;

+

+	iommu = iort_get_iort_node(iommu_fwnode);

+	if (!iommu || list_empty(&iort_rmr_list))

+		return -ENODEV;

+

+	list_for_each_entry(e, &iort_rmr_list, list) {

+		struct iommu_resv_region *region;

+

+		if (e->fw_data.rmr.smmu != iommu)

+			continue;

+

+		region = kmemdup(e, sizeof(*region), GFP_KERNEL);

+		if (region) {

+			list_add_tail(&region->list, head);

+			rmrs++;

+		}

+	}

+

+	return (rmrs == 0) ? -ENODEV : 0;

+}

+

 /**

  * iort_iommu_msi_get_resv_regions - Reserved region driver helper

  * @dev: Device from iommu_get_resv_regions()

@@ -1041,6 +1077,8 @@ int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)

 { return 0; }

 int iort_iommu_configure_id(struct device *dev, const u32 *input_id)

 { return -ENODEV; }

+int iort_iommu_get_rmrs(struct fwnode_handle *fwnode, struct list_head *head)

+{ return -ENODEV; }

 #endif

 static int nc_dma_get_range(struct device *dev, u64 *size)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c

index 72d801a5a5f7..4e4d00a3adaf 100644

--- a/drivers/iommu/dma-iommu.c

+++ b/drivers/iommu/dma-iommu.c

@@ -185,6 +185,9 @@ EXPORT_SYMBOL(iommu_put_dma_cookie);

 int iommu_dma_get_rmrs(struct fwnode_handle *iommu_fwnode,

 		       struct list_head *list)

 {

+	if (!is_of_node(iommu_fwnode))

+		return iort_iommu_get_rmrs(iommu_fwnode, list);

+

 	return -EINVAL;

 }

 EXPORT_SYMBOL(iommu_dma_get_rmrs);

@@ -200,6 +203,7 @@ EXPORT_SYMBOL(iommu_dma_get_rmrs);

 void iommu_dma_put_rmrs(struct fwnode_handle *iommu_fwnode,

 			struct list_head *list)

 {

+	generic_iommu_put_resv_regions(iommu_fwnode->dev, list);

 }

 EXPORT_SYMBOL(iommu_dma_put_rmrs);

diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h

index f1f0842a2cb2..d8c030c103f5 100644

--- a/include/linux/acpi_iort.h

+++ b/include/linux/acpi_iort.h

@@ -38,6 +38,8 @@ int iort_dma_get_ranges(struct device *dev, u64 *size);

 int iort_iommu_configure_id(struct device *dev, const u32 *id_in);

 int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head);

 phys_addr_t acpi_iort_dma_get_max_cpu_address(void);

+int iort_iommu_get_rmrs(struct fwnode_handle *iommu_fwnode,

+			struct list_head *list);

 #else

 static inline void acpi_iort_init(void) { }

 static inline u32 iort_msi_map_id(struct device *dev, u32 id)

@@ -57,6 +59,11 @@ int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)

 static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void)

 { return PHYS_ADDR_MAX; }

+

+static inline

+int iort_iommu_get_rmrs(struct fwnode_handle *iommu_fwnode,

+			struct list_head *list)

+{ return -ENODEV; }

 #endif

 #endif /* __ACPI_IORT_H__ */

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:20 +0100

Subject: [PATCH 05/19] iommu/arm-smmu-v3: Introduce strtab init helper

Introduce a helper to check the sid range and to init the l2 strtab

entries(bypass). This will be useful when we have to initialize the

l2 strtab with bypass for RMR SIDs.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++----------

 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

index e7da4a47ce52..4a8c2f5158ea 100644

--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

@@ -2530,6 +2530,19 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)

 	return sid < limit;

 }

+static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid)

+{

+	/* Check the SIDs are in range of the SMMU and our stream table */

+	if (!arm_smmu_sid_in_range(smmu, sid))

+		return -ERANGE;

+

+	/* Ensure l2 strtab is initialised */

+	if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)

+		return arm_smmu_init_l2_strtab(smmu, sid);

+

+	return 0;

+}

+

 static int arm_smmu_insert_master(struct arm_smmu_device *smmu,

 				  struct arm_smmu_master *master)

 {

@@ -2553,20 +2566,9 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu,

 		new_stream->id = sid;

 		new_stream->master = master;

-		/*

-		 * Check the SIDs are in range of the SMMU and our stream table

-		 */

-		if (!arm_smmu_sid_in_range(smmu, sid)) {

-			ret = -ERANGE;

+		ret = arm_smmu_init_sid_strtab(smmu, sid);

+		if (ret)

 			break;

-		}

-

-		/* Ensure l2 strtab is initialised */

-		if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {

-			ret = arm_smmu_init_l2_strtab(smmu, sid);

-			if (ret)

-				break;

-		}

 		/* Insert into SID tree */

 		new_node = &(smmu->streams.rb_node);

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:21 +0100

Subject: [PATCH 06/19] =?UTF-8?q?iommu/arm-smmu-v3:=20Refactor=C2=A0arm=5F?=

 =?UTF-8?q?smmu=5Finit=5Fbypass=5Fstes()=20to=20force=20bypass?=

MIME-Version: 1.0

Content-Type: text/plain; charset=UTF-8

Content-Transfer-Encoding: 8bit

By default, disable_bypass flag is set and any dev without

an iommu domain installs STE with CFG_ABORT during

arm_smmu_init_bypass_stes(). Introduce a "force" flag and

move the STE update logic to arm_smmu_init_bypass_stes()

so that we can force it to install CFG_BYPASS STE for specific

SIDs.

This will be useful in follow-up patch to install bypass

for IORT RMR SIDs.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 +++++++++++++----

 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

index 4a8c2f5158ea..ce47559cfca7 100644

--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

@@ -1374,12 +1374,21 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,

 		arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);

 }

-static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)

+static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent, bool force)

 {

 	unsigned int i;

+	u64 val = STRTAB_STE_0_V;

+

+	if (disable_bypass && !force)

+		val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);

+	else

+		val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);

 	for (i = 0; i < nent; ++i) {

-		arm_smmu_write_strtab_ent(NULL, -1, strtab);

+		strtab[0] = cpu_to_le64(val);

+		strtab[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,

+						   STRTAB_STE_1_SHCFG_INCOMING));

+		strtab[2] = 0;

 		strtab += STRTAB_STE_DWORDS;

 	}

 }

@@ -1407,7 +1416,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)

 		return -ENOMEM;

 	}

-	arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT);

+	arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT, false);

 	arm_smmu_write_strtab_l1_desc(strtab, desc);

 	return 0;

 }

@@ -3075,7 +3084,7 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)

 	reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);

 	cfg->strtab_base_cfg = reg;

-	arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents);

+	arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents, false);

 	return 0;

 }

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:22 +0100

Subject: [PATCH 07/19] iommu/arm-smmu-v3: Get associated RMR info and install

 bypass STE

MIME-Version: 1.0

Content-Type: text/plain; charset=UTF-8

Content-Transfer-Encoding: 8bit

Check if there is any RMR info associated with the devices behind

the SMMUv3 and if any, install bypass STEs for them. This is to

keep any ongoing traffic associated with these devices alive

when we enable/reset SMMUv3 during probe().

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 31 +++++++++++++++++++++

 1 file changed, 31 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

index ce47559cfca7..dbddb5ea2321 100644

--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

@@ -3791,6 +3791,34 @@ static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start,

 	return devm_ioremap_resource(dev, &res;;

 }

+static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu)

+{

+	struct list_head rmr_list;

+	struct iommu_resv_region *e;

+	int ret;

+

+	INIT_LIST_HEAD(&rmr_list);

+	if (iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &rmr_list))

+		return;

+

+	list_for_each_entry(e, &rmr_list, list) {

+		__le64 *step;

+		u32 sid = e->fw_data.rmr.sid;

+

+		ret = arm_smmu_init_sid_strtab(smmu, sid);

+		if (ret) {

+			dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n",

+				sid);

+			continue;

+		}

+

+		step = arm_smmu_get_step_for_sid(smmu, sid);

+		arm_smmu_init_bypass_stes(step, 1, true);

+	}

+

+	iommu_dma_put_rmrs(dev_fwnode(smmu->dev), &rmr_list);

+}

+

 static int arm_smmu_device_probe(struct platform_device *pdev)

 {

 	int irq, ret;

@@ -3874,6 +3902,9 @@ static int arm_smmu_device_probe(struct platform_device *pdev)

 	/* Record our private device structure */

 	platform_set_drvdata(pdev, smmu);

+	/* Check for RMRs and install bypass STEs if any */

+	arm_smmu_rmr_install_bypass_ste(smmu);

+

 	/* Reset the device */

 	ret = arm_smmu_device_reset(smmu, bypass);

 	if (ret)

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Jon Nettleton <jon@solid-run.com>

Date: Thu, 5 Aug 2021 09:07:23 +0100

Subject: [PATCH 08/19] iommu/arm-smmu: Get associated RMR info and install

 bypass SMR

Check if there is any RMR info associated with the devices behind

the SMMU and if any, install bypass SMRs for them. This is to

keep any ongoing traffic associated with these devices alive

when we enable/reset SMMU during probe().

Signed-off-by: Jon Nettleton <jon@solid-run.com>

Signed-off-by: Steven Price <steven.price@arm.com>

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/iommu/arm/arm-smmu/arm-smmu.c | 48 +++++++++++++++++++++++++++

 1 file changed, 48 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c

index 324e8f32962a..1d65dd243fee 100644

--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c

+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c

@@ -2066,6 +2066,50 @@ err_reset_platform_ops: __maybe_unused;

 	return err;

 }

+static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu)

+{

+	struct list_head rmr_list;

+	struct iommu_resv_region *e;

+	int i, cnt = 0;

+	u32 reg;

+

+	INIT_LIST_HEAD(&rmr_list);

+	if (iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &rmr_list))

+		return;

+

+	/*

+	 * Rather than trying to look at existing mappings that

+	 * are setup by the firmware and then invalidate the ones

+	 * that do no have matching RMR entries, just disable the

+	 * SMMU until it gets enabled again in the reset routine.

+	 */

+	reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0);

+	reg |= ARM_SMMU_sCR0_CLIENTPD;

+	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg);

+

+	list_for_each_entry(e, &rmr_list, list) {

+		u32 sid = e->fw_data.rmr.sid;

+

+		i = arm_smmu_find_sme(smmu, sid, ~0);

+		if (i < 0)

+			continue;

+		if (smmu->s2crs[i].count == 0) {

+			smmu->smrs[i].id = sid;

+			smmu->smrs[i].mask = 0;

+			smmu->smrs[i].valid = true;

+		}

+		smmu->s2crs[i].count++;

+		smmu->s2crs[i].type = S2CR_TYPE_BYPASS;

+		smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;

+

+		cnt++;

+	}

+

+	dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt,

+		   cnt == 1 ? "" : "s");

+	iommu_dma_put_rmrs(dev_fwnode(smmu->dev), &rmr_list);

+}

+

 static int arm_smmu_device_probe(struct platform_device *pdev)

 {

 	struct resource *res;

@@ -2191,6 +2235,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev)

 	}

 	platform_set_drvdata(pdev, smmu);

+

+	/* Check for RMRs and install bypass SMRs if any */

+	arm_smmu_rmr_install_bypass_smr(smmu);

+

 	arm_smmu_device_reset(smmu);

 	arm_smmu_test_smr_masks(smmu);

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Thu, 5 Aug 2021 09:07:24 +0100

Subject: [PATCH 09/19] iommu/dma: Reserve any RMR regions associated with a

 dev

Get ACPI IORT RMR regions associated with a dev reserved

so that there is a unity mapping for them in SMMU.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/iommu/dma-iommu.c | 56 +++++++++++++++++++++++++++++++++++----

 1 file changed, 51 insertions(+), 5 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c

index 4e4d00a3adaf..0014a70597ef 100644

--- a/drivers/iommu/dma-iommu.c

+++ b/drivers/iommu/dma-iommu.c

@@ -207,22 +207,68 @@ void iommu_dma_put_rmrs(struct fwnode_handle *iommu_fwnode,

 }

 EXPORT_SYMBOL(iommu_dma_put_rmrs);

+static bool iommu_dma_dev_has_rmr(struct iommu_fwspec *fwspec,

+				  struct iommu_resv_region *e)

+{

+	int i;

+

+	for (i = 0; i < fwspec->num_ids; i++) {

+		if (e->fw_data.rmr.sid == fwspec->ids[i])

+			return true;

+	}

+

+	return false;

+}

+

+static void iommu_dma_get_rmr_resv_regions(struct device *dev,

+					   struct list_head *list)

+{

+	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);

+	struct list_head rmr_list;

+	struct iommu_resv_region *rmr, *tmp;

+

+	INIT_LIST_HEAD(&rmr_list);

+	if (iommu_dma_get_rmrs(fwspec->iommu_fwnode, &rmr_list))

+		return;

+

+	if (dev_is_pci(dev)) {

+		struct pci_dev *pdev = to_pci_dev(dev);

+		struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);

+

+		if (!host->preserve_config)

+			return;

+	}

+

+	list_for_each_entry_safe(rmr, tmp, &rmr_list, list) {

+		if (!iommu_dma_dev_has_rmr(fwspec, rmr))

+			continue;

+

+		/* Remove from iommu RMR list and add to dev resv_regions */

+		list_del_init(&rmr->list);

+		list_add_tail(&rmr->list, list);

+	}

+

+	iommu_dma_put_rmrs(fwspec->iommu_fwnode, &rmr_list);

+}

+

 /**

  * iommu_dma_get_resv_regions - Reserved region driver helper

  * @dev: Device from iommu_get_resv_regions()

  * @list: Reserved region list from iommu_get_resv_regions()

  *

  * IOMMU drivers can use this to implement their .get_resv_regions callback

- * for general non-IOMMU-specific reservations. Currently, this covers GICv3

- * ITS region reservation on ACPI based ARM platforms that may require HW MSI

- * reservation.

+ * for general non-IOMMU-specific reservations. Currently this covers,

+ *  -GICv3 ITS region reservation on ACPI based ARM platforms that may

+ *   require HW MSI reservation.

+ *  -Any ACPI IORT RMR memory range reservations (IORT spec rev E.b)

  */

 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)

 {

-	if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))

+	if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) {

 		iort_iommu_msi_get_resv_regions(dev, list);

-

+		iommu_dma_get_rmr_resv_regions(dev, list);

+	}

 }

 EXPORT_SYMBOL(iommu_dma_get_resv_regions);

-- 

2.39.0

From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001

From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

Date: Fri, 17 Sep 2021 12:07:26 +0100

Subject: [PATCH 10/19] iommu/dma: Update RMR mem attributes

Since we dont have enough information from the IORT spec,

make use of ACPI table and EFI memory map to set the RMR

reserved region prot value.

[Not tested]

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>

---

 drivers/acpi/arm64/iort.c | 24 +++++++++++++-----------

 drivers/iommu/dma-iommu.c |  1 +

 include/linux/acpi_iort.h |  8 ++++++++