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commit 0f09154c64005e78b61484ae87b5ea2028051ea0
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Author: H.J. Lu <hjl.tools@gmail.com>
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Date:   Sat Jul 4 06:35:49 2020 -0700
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    x86: Initialize CPU info via IFUNC relocation [BZ 26203]
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    X86 CPU features in ld.so are initialized by init_cpu_features, which is
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    invoked by DL_PLATFORM_INIT from _dl_sysdep_start.  But when ld.so is
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    loaded by static executable, DL_PLATFORM_INIT is never called.  Also
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    x86 cache info in libc.o and libc.a is initialized by a constructor
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    which may be called too late.  Since some fields in _rtld_global_ro
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    in ld.so are initialized by dynamic relocation, we can also initialize
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    x86 CPU features in _rtld_global_ro in ld.so and cache info in libc.so
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    by initializing dummy function pointers in ld.so and libc.so via IFUNC
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    relocation.
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    Key points:
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    1. IFUNC is always supported, independent of --enable-multi-arch or
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    --disable-multi-arch.  Linker generates IFUNC relocations from input
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    IFUNC objects and ld.so performs IFUNC relocations.
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    2. There are no IFUNC dependencies in ld.so before dynamic relocation
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    have been performed,
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    3. The x86 CPU features in ld.so is initialized by DL_PLATFORM_INIT
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    in dynamic executable and by IFUNC relocation in dlopen in static
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    executable.
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    4. The x86 cache info in libc.o is initialized by IFUNC relocation.
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    5. In libc.a, both x86 CPU features and cache info are initialized from
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    ARCH_INIT_CPU_FEATURES, not by IFUNC relocation, before __libc_early_init
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    is called.
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    Note: _dl_x86_init_cpu_features can be called more than once from
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    DL_PLATFORM_INIT and during relocation in ld.so.
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Conflicts:
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	sysdeps/x86/cacheinfo.c
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	  (Copyright year difference, and AMD Zen cache computation
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	   backports downstream.  These changes were reapplied to
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	   sysdeps/x86/cacheinfo.h, mirroring the upstream refactoring
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	   in the backported commit.)
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	sysdeps/x86/dl-get-cpu-features.c
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	  (Copyright year difference.)
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diff --git a/sysdeps/i386/dl-machine.h b/sysdeps/i386/dl-machine.h
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index 8c959e39457c8c41..e5776ef7bc8ad749 100644
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--- a/sysdeps/i386/dl-machine.h
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+++ b/sysdeps/i386/dl-machine.h
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@@ -25,7 +25,6 @@
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 #include <sysdep.h>
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 #include <tls.h>
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 #include <dl-tlsdesc.h>
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-#include <cpu-features.c>
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 /* Return nonzero iff ELF header is compatible with the running host.  */
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 static inline int __attribute__ ((unused))
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@@ -248,9 +247,9 @@ static inline void __attribute__ ((unused))
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 dl_platform_init (void)
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 {
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 #if IS_IN (rtld)
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-  /* init_cpu_features has been called early from __libc_start_main in
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-     static executable.  */
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-  init_cpu_features (&GLRO(dl_x86_cpu_features));
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+  /* _dl_x86_init_cpu_features is a wrapper for init_cpu_features which
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+     has been called early from __libc_start_main in static executable.  */
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+  _dl_x86_init_cpu_features ();
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 #else
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   if (GLRO(dl_platform) != NULL && *GLRO(dl_platform) == '\0')
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     /* Avoid an empty string which would disturb us.  */
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diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
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index fdfe2684759d968c..84b10f6dd8d23a51 100644
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--- a/sysdeps/x86/cacheinfo.c
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+++ b/sysdeps/x86/cacheinfo.c
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@@ -1,5 +1,5 @@
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-/* x86_64 cache info.
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-   Copyright (C) 2003-2018 Free Software Foundation, Inc.
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+/* x86 cache info.
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+   Copyright (C) 2003-2020 Free Software Foundation, Inc.
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    This file is part of the GNU C Library.
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    The GNU C Library is free software; you can redistribute it and/or
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@@ -19,473 +19,10 @@
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 #if IS_IN (libc)
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 #include <assert.h>
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-#include <stdbool.h>
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-#include <stdlib.h>
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 #include <unistd.h>
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 #include <cpuid.h>
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-#include <init-arch.h>
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-
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-static const struct intel_02_cache_info
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-{
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-  unsigned char idx;
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-  unsigned char assoc;
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-  unsigned char linesize;
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-  unsigned char rel_name;
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-  unsigned int size;
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-} intel_02_known [] =
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-  {
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-#define M(sc) ((sc) - _SC_LEVEL1_ICACHE_SIZE)
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-    { 0x06,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),    8192 },
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-    { 0x08,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   16384 },
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-    { 0x09,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
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-    { 0x0a,  2, 32, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
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-    { 0x0c,  4, 32, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
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-    { 0x0d,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
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-    { 0x0e,  6, 64, M(_SC_LEVEL1_DCACHE_SIZE),   24576 },
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-    { 0x21,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
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-    { 0x22,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
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-    { 0x23,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
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-    { 0x25,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
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-    { 0x29,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
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-    { 0x2c,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
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-    { 0x30,  8, 64, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
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-    { 0x39,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
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-    { 0x3a,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   196608 },
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-    { 0x3b,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
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-    { 0x3c,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
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-    { 0x3d,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   393216 },
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-    { 0x3e,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x3f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
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-    { 0x41,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
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-    { 0x42,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
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-    { 0x43,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x44,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
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-    { 0x45,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
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-    { 0x46,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
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-    { 0x47,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
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-    { 0x48, 12, 64, M(_SC_LEVEL2_CACHE_SIZE),  3145728 },
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-    { 0x49, 16, 64, M(_SC_LEVEL2_CACHE_SIZE),  4194304 },
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-    { 0x4a, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  6291456 },
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-    { 0x4b, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
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-    { 0x4c, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
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-    { 0x4d, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 16777216 },
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-    { 0x4e, 24, 64, M(_SC_LEVEL2_CACHE_SIZE),  6291456 },
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-    { 0x60,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
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-    { 0x66,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
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-    { 0x67,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
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-    { 0x68,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
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-    { 0x78,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
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-    { 0x79,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
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-    { 0x7a,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
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-    { 0x7b,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x7c,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
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-    { 0x7d,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
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-    { 0x7f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x80,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x82,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
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-    { 0x83,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x84,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
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-    { 0x85,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
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-    { 0x86,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
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-    { 0x87,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
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-    { 0xd0,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
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-    { 0xd1,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
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-    { 0xd2,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
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-    { 0xd6,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
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-    { 0xd7,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
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-    { 0xd8,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
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-    { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
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-    { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
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-    { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
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-    { 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
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-    { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
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-    { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
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-    { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
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-    { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
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-    { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
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-  };
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-
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-#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0]))
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-
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-static int
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-intel_02_known_compare (const void *p1, const void *p2)
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-{
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-  const struct intel_02_cache_info *i1;
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-  const struct intel_02_cache_info *i2;
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-
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-  i1 = (const struct intel_02_cache_info *) p1;
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-  i2 = (const struct intel_02_cache_info *) p2;
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-
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-  if (i1->idx == i2->idx)
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-    return 0;
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-
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-  return i1->idx < i2->idx ? -1 : 1;
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-}
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-
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-
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-static long int
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-__attribute__ ((noinline))
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-intel_check_word (int name, unsigned int value, bool *has_level_2,
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-		  bool *no_level_2_or_3,
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-		  const struct cpu_features *cpu_features)
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-{
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-  if ((value & 0x80000000) != 0)
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-    /* The register value is reserved.  */
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-    return 0;
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-
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-  /* Fold the name.  The _SC_ constants are always in the order SIZE,
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-     ASSOC, LINESIZE.  */
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-  int folded_rel_name = (M(name) / 3) * 3;
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-
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-  while (value != 0)
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-    {
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-      unsigned int byte = value & 0xff;
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-
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-      if (byte == 0x40)
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-	{
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-	  *no_level_2_or_3 = true;
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-
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-	  if (folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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-	    /* No need to look further.  */
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-	    break;
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-	}
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-      else if (byte == 0xff)
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-	{
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-	  /* CPUID leaf 0x4 contains all the information.  We need to
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-	     iterate over it.  */
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-	  unsigned int eax;
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-	  unsigned int ebx;
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-	  unsigned int ecx;
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-	  unsigned int edx;
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-
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-	  unsigned int round = 0;
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-	  while (1)
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-	    {
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-	      __cpuid_count (4, round, eax, ebx, ecx, edx);
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-
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-	      enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
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-	      if (type == null)
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-		/* That was the end.  */
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-		break;
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-
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-	      unsigned int level = (eax >> 5) & 0x7;
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-
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-	      if ((level == 1 && type == data
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-		   && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
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-		  || (level == 1 && type == inst
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-		      && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
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-		  || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
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-		  || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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-		  || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
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-		{
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-		  unsigned int offset = M(name) - folded_rel_name;
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-
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-		  if (offset == 0)
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-		    /* Cache size.  */
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-		    return (((ebx >> 22) + 1)
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-			    * (((ebx >> 12) & 0x3ff) + 1)
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-			    * ((ebx & 0xfff) + 1)
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-			    * (ecx + 1));
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-		  if (offset == 1)
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-		    return (ebx >> 22) + 1;
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-
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-		  assert (offset == 2);
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-		  return (ebx & 0xfff) + 1;
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-		}
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-
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-	      ++round;
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-	    }
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-	  /* There is no other cache information anywhere else.  */
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-	  break;
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-	}
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-      else
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-	{
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-	  if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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-	    {
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-	      /* Intel reused this value.  For family 15, model 6 it
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-		 specifies the 3rd level cache.  Otherwise the 2nd
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-		 level cache.  */
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-	      unsigned int family = cpu_features->basic.family;
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-	      unsigned int model = cpu_features->basic.model;
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-
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-	      if (family == 15 && model == 6)
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-		{
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-		  /* The level 3 cache is encoded for this model like
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-		     the level 2 cache is for other models.  Pretend
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-		     the caller asked for the level 2 cache.  */
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-		  name = (_SC_LEVEL2_CACHE_SIZE
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-			  + (name - _SC_LEVEL3_CACHE_SIZE));
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-		  folded_rel_name = M(_SC_LEVEL2_CACHE_SIZE);
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-		}
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-	    }
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-
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-	  struct intel_02_cache_info *found;
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-	  struct intel_02_cache_info search;
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-
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-	  search.idx = byte;
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-	  found = bsearch (&search, intel_02_known, nintel_02_known,
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-			   sizeof (intel_02_known[0]), intel_02_known_compare);
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-	  if (found != NULL)
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-	    {
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-	      if (found->rel_name == folded_rel_name)
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-		{
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-		  unsigned int offset = M(name) - folded_rel_name;
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-
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-		  if (offset == 0)
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-		    /* Cache size.  */
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-		    return found->size;
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-		  if (offset == 1)
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-		    return found->assoc;
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-
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-		  assert (offset == 2);
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-		  return found->linesize;
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-		}
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-
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-	      if (found->rel_name == M(_SC_LEVEL2_CACHE_SIZE))
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-		*has_level_2 = true;
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-	    }
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-	}
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-
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-      /* Next byte for the next round.  */
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-      value >>= 8;
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-    }
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-
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-  /* Nothing found.  */
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-  return 0;
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-}
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-
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-
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-static long int __attribute__ ((noinline))
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-handle_intel (int name, const struct cpu_features *cpu_features)
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-{
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-  unsigned int maxidx = cpu_features->basic.max_cpuid;
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-
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-  /* Return -1 for older CPUs.  */
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-  if (maxidx < 2)
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-    return -1;
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-
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-  /* OK, we can use the CPUID instruction to get all info about the
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-     caches.  */
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-  unsigned int cnt = 0;
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-  unsigned int max = 1;
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-  long int result = 0;
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-  bool no_level_2_or_3 = false;
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-  bool has_level_2 = false;
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-
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-  while (cnt++ < max)
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-    {
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-      unsigned int eax;
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-      unsigned int ebx;
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-      unsigned int ecx;
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-      unsigned int edx;
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-      __cpuid (2, eax, ebx, ecx, edx);
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-
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-      /* The low byte of EAX in the first round contain the number of
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-	 rounds we have to make.  At least one, the one we are already
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-	 doing.  */
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-      if (cnt == 1)
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-	{
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-	  max = eax & 0xff;
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-	  eax &= 0xffffff00;
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-	}
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-
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-      /* Process the individual registers' value.  */
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-      result = intel_check_word (name, eax, &has_level_2,
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-				 &no_level_2_or_3, cpu_features);
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-      if (result != 0)
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-	return result;
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-
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-      result = intel_check_word (name, ebx, &has_level_2,
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-				 &no_level_2_or_3, cpu_features);
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-      if (result != 0)
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-	return result;
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-
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-      result = intel_check_word (name, ecx, &has_level_2,
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-				 &no_level_2_or_3, cpu_features);
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-      if (result != 0)
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-	return result;
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-
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-      result = intel_check_word (name, edx, &has_level_2,
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-				 &no_level_2_or_3, cpu_features);
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-      if (result != 0)
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-	return result;
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-    }
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-
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-  if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
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-      && no_level_2_or_3)
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-    return -1;
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-
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-  return 0;
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-}
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-
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-
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-static long int __attribute__ ((noinline))
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-handle_amd (int name)
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-{
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-  unsigned int eax;
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-  unsigned int ebx;
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-  unsigned int ecx;
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-  unsigned int edx;
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-  __cpuid (0x80000000, eax, ebx, ecx, edx);
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-
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-  /* No level 4 cache (yet).  */
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-  if (name > _SC_LEVEL3_CACHE_LINESIZE)
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-    return 0;
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-
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-  unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
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-  if (eax < fn)
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-    return 0;
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-
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-  __cpuid (fn, eax, ebx, ecx, edx);
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-
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-  if (name < _SC_LEVEL1_DCACHE_SIZE)
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-    {
446cf2
-      name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
446cf2
-      ecx = edx;
446cf2
-    }
446cf2
-
446cf2
-  switch (name)
446cf2
-    {
446cf2
-    case _SC_LEVEL1_DCACHE_SIZE:
446cf2
-      return (ecx >> 14) & 0x3fc00;
446cf2
-
446cf2
-    case _SC_LEVEL1_DCACHE_ASSOC:
446cf2
-      ecx >>= 16;
446cf2
-      if ((ecx & 0xff) == 0xff)
446cf2
-	/* Fully associative.  */
446cf2
-	return (ecx << 2) & 0x3fc00;
446cf2
-      return ecx & 0xff;
446cf2
-
446cf2
-    case _SC_LEVEL1_DCACHE_LINESIZE:
446cf2
-      return ecx & 0xff;
446cf2
-
446cf2
-    case _SC_LEVEL2_CACHE_SIZE:
446cf2
-      return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
446cf2
-
446cf2
-    case _SC_LEVEL2_CACHE_ASSOC:
446cf2
-      switch ((ecx >> 12) & 0xf)
446cf2
-	{
446cf2
-	case 0:
446cf2
-	case 1:
446cf2
-	case 2:
446cf2
-	case 4:
446cf2
-	  return (ecx >> 12) & 0xf;
446cf2
-	case 6:
446cf2
-	  return 8;
446cf2
-	case 8:
446cf2
-	  return 16;
446cf2
-	case 10:
446cf2
-	  return 32;
446cf2
-	case 11:
446cf2
-	  return 48;
446cf2
-	case 12:
446cf2
-	  return 64;
446cf2
-	case 13:
446cf2
-	  return 96;
446cf2
-	case 14:
446cf2
-	  return 128;
446cf2
-	case 15:
446cf2
-	  return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
446cf2
-	default:
446cf2
-	  return 0;
446cf2
-	}
446cf2
-      /* NOTREACHED */
446cf2
-
446cf2
-    case _SC_LEVEL2_CACHE_LINESIZE:
446cf2
-      return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
446cf2
-
446cf2
-    case _SC_LEVEL3_CACHE_SIZE:
446cf2
-      return (edx & 0xf000) == 0 ? 0 : (edx & 0x3ffc0000) << 1;
446cf2
-
446cf2
-    case _SC_LEVEL3_CACHE_ASSOC:
446cf2
-      switch ((edx >> 12) & 0xf)
446cf2
-	{
446cf2
-	case 0:
446cf2
-	case 1:
446cf2
-	case 2:
446cf2
-	case 4:
446cf2
-	  return (edx >> 12) & 0xf;
446cf2
-	case 6:
446cf2
-	  return 8;
446cf2
-	case 8:
446cf2
-	  return 16;
446cf2
-	case 10:
446cf2
-	  return 32;
446cf2
-	case 11:
446cf2
-	  return 48;
446cf2
-	case 12:
446cf2
-	  return 64;
446cf2
-	case 13:
446cf2
-	  return 96;
446cf2
-	case 14:
446cf2
-	  return 128;
446cf2
-	case 15:
446cf2
-	  return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
446cf2
-	default:
446cf2
-	  return 0;
446cf2
-	}
446cf2
-      /* NOTREACHED */
446cf2
-
446cf2
-    case _SC_LEVEL3_CACHE_LINESIZE:
446cf2
-      return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
446cf2
-
446cf2
-    default:
446cf2
-      assert (! "cannot happen");
446cf2
-    }
446cf2
-  return -1;
446cf2
-}
446cf2
-
446cf2
-
446cf2
-static long int __attribute__ ((noinline))
446cf2
-handle_zhaoxin (int name)
446cf2
-{
446cf2
-  unsigned int eax;
446cf2
-  unsigned int ebx;
446cf2
-  unsigned int ecx;
446cf2
-  unsigned int edx;
446cf2
-
446cf2
-  int folded_rel_name = (M(name) / 3) * 3;
446cf2
-
446cf2
-  unsigned int round = 0;
446cf2
-  while (1)
446cf2
-    {
446cf2
-      __cpuid_count (4, round, eax, ebx, ecx, edx);
446cf2
-
446cf2
-      enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
446cf2
-      if (type == null)
446cf2
-        break;
446cf2
-
446cf2
-      unsigned int level = (eax >> 5) & 0x7;
446cf2
-
446cf2
-      if ((level == 1 && type == data
446cf2
-        && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
446cf2
-        || (level == 1 && type == inst
446cf2
-            && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
446cf2
-        || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
446cf2
-        || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)))
446cf2
-        {
446cf2
-          unsigned int offset = M(name) - folded_rel_name;
446cf2
-
446cf2
-          if (offset == 0)
446cf2
-            /* Cache size.  */
446cf2
-            return (((ebx >> 22) + 1)
446cf2
-                * (((ebx >> 12) & 0x3ff) + 1)
446cf2
-                * ((ebx & 0xfff) + 1)
446cf2
-                * (ecx + 1));
446cf2
-          if (offset == 1)
446cf2
-            return (ebx >> 22) + 1;
446cf2
-
446cf2
-          assert (offset == 2);
446cf2
-          return (ebx & 0xfff) + 1;
446cf2
-        }
446cf2
-
446cf2
-      ++round;
446cf2
-    }
446cf2
-
446cf2
-  /* Nothing found.  */
446cf2
-  return 0;
446cf2
-}
446cf2
-
446cf2
+#include <ldsodefs.h>
446cf2
+#include <dl-cacheinfo.h>
446cf2
 
446cf2
 /* Get the value of the system variable NAME.  */
446cf2
 long int
446cf2
@@ -509,409 +46,18 @@ __cache_sysconf (int name)
446cf2
   return 0;
446cf2
 }
446cf2
 
446cf2
+# ifdef SHARED
446cf2
+/* NB: In libc.a, cacheinfo.h is included in libc-start.c.  In libc.so,
446cf2
+   cacheinfo.h is included here and call init_cacheinfo by initializing
446cf2
+   a dummy function pointer via IFUNC relocation after CPU features in
446cf2
+   ld.so have been initialized by DL_PLATFORM_INIT or IFUNC relocation.  */
446cf2
+# include <cacheinfo.h>
446cf2
+# include <ifunc-init.h>
446cf2
 
446cf2
-/* Data cache size for use in memory and string routines, typically
446cf2
-   L1 size, rounded to multiple of 256 bytes.  */
446cf2
-long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
446cf2
-long int __x86_data_cache_size attribute_hidden = 32 * 1024;
446cf2
-/* Similar to __x86_data_cache_size_half, but not rounded.  */
446cf2
-long int __x86_raw_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
446cf2
-/* Similar to __x86_data_cache_size, but not rounded.  */
446cf2
-long int __x86_raw_data_cache_size attribute_hidden = 32 * 1024;
446cf2
-/* Shared cache size for use in memory and string routines, typically
446cf2
-   L2 or L3 size, rounded to multiple of 256 bytes.  */
446cf2
-long int __x86_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
446cf2
-long int __x86_shared_cache_size attribute_hidden = 1024 * 1024;
446cf2
-/* Similar to __x86_shared_cache_size_half, but not rounded.  */
446cf2
-long int __x86_raw_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
446cf2
-/* Similar to __x86_shared_cache_size, but not rounded.  */
446cf2
-long int __x86_raw_shared_cache_size attribute_hidden = 1024 * 1024;
446cf2
-
446cf2
-/* Threshold to use non temporal store.  */
446cf2
-long int __x86_shared_non_temporal_threshold attribute_hidden;
446cf2
-
446cf2
-/* Threshold to use Enhanced REP MOVSB.  */
446cf2
-long int __x86_rep_movsb_threshold attribute_hidden = 2048;
446cf2
-
446cf2
-/* Threshold to use Enhanced REP STOSB.  */
446cf2
-long int __x86_rep_stosb_threshold attribute_hidden = 2048;
446cf2
-
446cf2
-
446cf2
-static void
446cf2
-get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr,
446cf2
-                long int core)
446cf2
-{
446cf2
-  unsigned int eax;
446cf2
-  unsigned int ebx;
446cf2
-  unsigned int ecx;
446cf2
-  unsigned int edx;
446cf2
-
446cf2
-  /* Number of logical processors sharing L2 cache.  */
446cf2
-  int threads_l2;
446cf2
-
446cf2
-  /* Number of logical processors sharing L3 cache.  */
446cf2
-  int threads_l3;
446cf2
-
446cf2
-  const struct cpu_features *cpu_features = __get_cpu_features ();
446cf2
-  int max_cpuid = cpu_features->basic.max_cpuid;
446cf2
-  unsigned int family = cpu_features->basic.family;
446cf2
-  unsigned int model = cpu_features->basic.model;
446cf2
-  long int shared = *shared_ptr;
446cf2
-  unsigned int threads = *threads_ptr;
446cf2
-  bool inclusive_cache = true;
446cf2
-  bool support_count_mask = true;
446cf2
-
446cf2
-  /* Try L3 first.  */
446cf2
-  unsigned int level = 3;
446cf2
-
446cf2
-  if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6)
446cf2
-    support_count_mask = false;
446cf2
-
446cf2
-  if (shared <= 0)
446cf2
-    {
446cf2
-      /* Try L2 otherwise.  */
446cf2
-      level  = 2;
446cf2
-      shared = core;
446cf2
-      threads_l2 = 0;
446cf2
-      threads_l3 = -1;
446cf2
-    }
446cf2
-  else
446cf2
-    {
446cf2
-      threads_l2 = 0;
446cf2
-      threads_l3 = 0;
446cf2
-    }
446cf2
-
446cf2
-  /* A value of 0 for the HTT bit indicates there is only a single
446cf2
-     logical processor.  */
446cf2
-  if (CPU_FEATURE_USABLE (HTT))
446cf2
-    {
446cf2
-      /* Figure out the number of logical threads that share the
446cf2
-         highest cache level.  */
446cf2
-      if (max_cpuid >= 4)
446cf2
-        {
446cf2
-          int i = 0;
446cf2
-
446cf2
-          /* Query until cache level 2 and 3 are enumerated.  */
446cf2
-          int check = 0x1 | (threads_l3 == 0) << 1;
446cf2
-          do
446cf2
-            {
446cf2
-              __cpuid_count (4, i++, eax, ebx, ecx, edx);
446cf2
-
446cf2
-              /* There seems to be a bug in at least some Pentium Ds
446cf2
-                 which sometimes fail to iterate all cache parameters.
446cf2
-                 Do not loop indefinitely here, stop in this case and
446cf2
-                 assume there is no such information.  */
446cf2
-              if (cpu_features->basic.kind == arch_kind_intel
446cf2
-                  && (eax & 0x1f) == 0 )
446cf2
-                goto intel_bug_no_cache_info;
446cf2
-
446cf2
-              switch ((eax >> 5) & 0x7)
446cf2
-                {
446cf2
-                  default:
446cf2
-                    break;
446cf2
-                  case 2:
446cf2
-                    if ((check & 0x1))
446cf2
-                      {
446cf2
-                        /* Get maximum number of logical processors
446cf2
-                           sharing L2 cache.  */
446cf2
-                        threads_l2 = (eax >> 14) & 0x3ff;
446cf2
-                        check &= ~0x1;
446cf2
-                      }
446cf2
-                    break;
446cf2
-                  case 3:
446cf2
-                    if ((check & (0x1 << 1)))
446cf2
-                      {
446cf2
-                        /* Get maximum number of logical processors
446cf2
-                           sharing L3 cache.  */
446cf2
-                        threads_l3 = (eax >> 14) & 0x3ff;
446cf2
-
446cf2
-                        /* Check if L2 and L3 caches are inclusive.  */
446cf2
-                        inclusive_cache = (edx & 0x2) != 0;
446cf2
-                        check &= ~(0x1 << 1);
446cf2
-                      }
446cf2
-                    break;
446cf2
-                }
446cf2
-            }
446cf2
-          while (check);
446cf2
-
446cf2
-          /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum
446cf2
-             numbers of addressable IDs for logical processors sharing
446cf2
-             the cache, instead of the maximum number of threads
446cf2
-             sharing the cache.  */
446cf2
-          if (max_cpuid >= 11 && support_count_mask)
446cf2
-            {
446cf2
-              /* Find the number of logical processors shipped in
446cf2
-                 one core and apply count mask.  */
446cf2
-              i = 0;
446cf2
-
446cf2
-              /* Count SMT only if there is L3 cache.  Always count
446cf2
-                 core if there is no L3 cache.  */
446cf2
-              int count = ((threads_l2 > 0 && level == 3)
446cf2
-                           | ((threads_l3 > 0
446cf2
-                               || (threads_l2 > 0 && level == 2)) << 1));
446cf2
-
446cf2
-              while (count)
446cf2
-                {
446cf2
-                  __cpuid_count (11, i++, eax, ebx, ecx, edx);
446cf2
-
446cf2
-                  int shipped = ebx & 0xff;
446cf2
-                  int type = ecx & 0xff00;
446cf2
-                  if (shipped == 0 || type == 0)
446cf2
-                    break;
446cf2
-                  else if (type == 0x100)
446cf2
-                    {
446cf2
-                      /* Count SMT.  */
446cf2
-                      if ((count & 0x1))
446cf2
-                        {
446cf2
-                          int count_mask;
446cf2
-
446cf2
-                          /* Compute count mask.  */
446cf2
-                          asm ("bsr %1, %0"
446cf2
-                               : "=r" (count_mask) : "g" (threads_l2));
446cf2
-                          count_mask = ~(-1 << (count_mask + 1));
446cf2
-                          threads_l2 = (shipped - 1) & count_mask;
446cf2
-                          count &= ~0x1;
446cf2
-                        }
446cf2
-                    }
446cf2
-                  else if (type == 0x200)
446cf2
-                    {
446cf2
-                      /* Count core.  */
446cf2
-                      if ((count & (0x1 << 1)))
446cf2
-                        {
446cf2
-                          int count_mask;
446cf2
-                          int threads_core
446cf2
-                            = (level == 2 ? threads_l2 : threads_l3);
446cf2
-
446cf2
-                          /* Compute count mask.  */
446cf2
-                          asm ("bsr %1, %0"
446cf2
-                               : "=r" (count_mask) : "g" (threads_core));
446cf2
-                          count_mask = ~(-1 << (count_mask + 1));
446cf2
-                          threads_core = (shipped - 1) & count_mask;
446cf2
-                          if (level == 2)
446cf2
-                            threads_l2 = threads_core;
446cf2
-                          else
446cf2
-                            threads_l3 = threads_core;
446cf2
-                          count &= ~(0x1 << 1);
446cf2
-                        }
446cf2
-                    }
446cf2
-                }
446cf2
-            }
446cf2
-          if (threads_l2 > 0)
446cf2
-            threads_l2 += 1;
446cf2
-          if (threads_l3 > 0)
446cf2
-            threads_l3 += 1;
446cf2
-          if (level == 2)
446cf2
-            {
446cf2
-              if (threads_l2)
446cf2
-                {
446cf2
-                  threads = threads_l2;
446cf2
-                  if (cpu_features->basic.kind == arch_kind_intel
446cf2
-                      && threads > 2
446cf2
-                      && family == 6)
446cf2
-                    switch (model)
446cf2
-                      {
446cf2
-                        case 0x37:
446cf2
-                        case 0x4a:
446cf2
-                        case 0x4d:
446cf2
-                        case 0x5a:
446cf2
-                        case 0x5d:
446cf2
-                          /* Silvermont has L2 cache shared by 2 cores.  */
446cf2
-                          threads = 2;
446cf2
-                          break;
446cf2
-                        default:
446cf2
-                          break;
446cf2
-                      }
446cf2
-                }
446cf2
-            }
446cf2
-          else if (threads_l3)
446cf2
-            threads = threads_l3;
446cf2
-        }
446cf2
-      else
446cf2
-        {
446cf2
-intel_bug_no_cache_info:
446cf2
-          /* Assume that all logical threads share the highest cache
446cf2
-             level.  */
446cf2
-          threads
446cf2
-            = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx
446cf2
-                >> 16) & 0xff);
446cf2
-        }
446cf2
-
446cf2
-        /* Cap usage of highest cache level to the number of supported
446cf2
-           threads.  */
446cf2
-        if (shared > 0 && threads > 0)
446cf2
-          shared /= threads;
446cf2
-    }
446cf2
-
446cf2
-  /* Account for non-inclusive L2 and L3 caches.  */
446cf2
-  if (!inclusive_cache)
446cf2
-    {
446cf2
-      if (threads_l2 > 0)
446cf2
-        core /= threads_l2;
446cf2
-      shared += core;
446cf2
-    }
446cf2
-
446cf2
-  *shared_ptr = shared;
446cf2
-  *threads_ptr = threads;
446cf2
-}
446cf2
-
446cf2
-
446cf2
-static void
446cf2
-__attribute__((constructor))
446cf2
-init_cacheinfo (void)
446cf2
-{
446cf2
-  /* Find out what brand of processor.  */
446cf2
-  unsigned int ebx;
446cf2
-  unsigned int ecx;
446cf2
-  unsigned int edx;
446cf2
-  int max_cpuid_ex;
446cf2
-  long int data = -1;
446cf2
-  long int shared = -1;
446cf2
-  long int core;
446cf2
-  unsigned int threads = 0;
446cf2
-  const struct cpu_features *cpu_features = __get_cpu_features ();
446cf2
-
446cf2
-  if (cpu_features->basic.kind == arch_kind_intel)
446cf2
-    {
446cf2
-      data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
446cf2
-      core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
446cf2
-      shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
446cf2
-
446cf2
-      get_common_cache_info (&shared, &threads, core);
446cf2
-    }
446cf2
-  else if (cpu_features->basic.kind == arch_kind_zhaoxin)
446cf2
-    {
446cf2
-      data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE);
446cf2
-      core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
446cf2
-      shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
446cf2
-
446cf2
-      get_common_cache_info (&shared, &threads, core);
446cf2
-    }
446cf2
-  else if (cpu_features->basic.kind == arch_kind_amd)
446cf2
-    {
446cf2
-      data   = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
446cf2
-      long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
446cf2
-      shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
446cf2
+extern void __x86_cacheinfo (void) attribute_hidden;
446cf2
+const void (*__x86_cacheinfo_p) (void) attribute_hidden
446cf2
+  = __x86_cacheinfo;
446cf2
 
446cf2
-      /* Get maximum extended function. */
446cf2
-      __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx);
446cf2
-
446cf2
-      if (shared <= 0)
446cf2
-	/* No shared L3 cache.  All we have is the L2 cache.  */
446cf2
-	shared = core;
446cf2
-      else
446cf2
-	{
446cf2
-	  /* Figure out the number of logical threads that share L3.  */
446cf2
-	  if (max_cpuid_ex >= 0x80000008)
446cf2
-	    {
446cf2
-	      /* Get width of APIC ID.  */
446cf2
-	      __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx);
446cf2
-	      threads = 1 << ((ecx >> 12) & 0x0f);
446cf2
-	    }
446cf2
-
446cf2
-	  if (threads == 0 || cpu_features->basic.family >= 0x17)
446cf2
-	    {
446cf2
-	      /* If APIC ID width is not available, use logical
446cf2
-		 processor count.  */
446cf2
-	      __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx);
446cf2
-
446cf2
-	      if ((edx & (1 << 28)) != 0)
446cf2
-		threads = (ebx >> 16) & 0xff;
446cf2
-	    }
446cf2
-
446cf2
-	  /* Cap usage of highest cache level to the number of
446cf2
-	     supported threads.  */
446cf2
-	  if (threads > 0)
446cf2
-	    shared /= threads;
446cf2
-
446cf2
-	  /* Get shared cache per ccx for Zen architectures.  */
446cf2
-	  if (cpu_features->basic.family >= 0x17)
446cf2
-	    {
446cf2
-	      unsigned int eax;
446cf2
-
446cf2
-	      /* Get number of threads share the L3 cache in CCX.  */
446cf2
-	      __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
446cf2
-
446cf2
-	      unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
446cf2
-	      shared *= threads_per_ccx;
446cf2
-	    }
446cf2
-	  else
446cf2
-	    {
446cf2
-	      /* Account for exclusive L2 and L3 caches.  */
446cf2
-	      shared += core;
446cf2
-            }
446cf2
-	}
446cf2
-    }
446cf2
-
446cf2
-  if (cpu_features->data_cache_size != 0)
446cf2
-    data = cpu_features->data_cache_size;
446cf2
-
446cf2
-  if (data > 0)
446cf2
-    {
446cf2
-      __x86_raw_data_cache_size_half = data / 2;
446cf2
-      __x86_raw_data_cache_size = data;
446cf2
-      /* Round data cache size to multiple of 256 bytes.  */
446cf2
-      data = data & ~255L;
446cf2
-      __x86_data_cache_size_half = data / 2;
446cf2
-      __x86_data_cache_size = data;
446cf2
-    }
446cf2
-
446cf2
-  if (cpu_features->shared_cache_size != 0)
446cf2
-    shared = cpu_features->shared_cache_size;
446cf2
-
446cf2
-  if (shared > 0)
446cf2
-    {
446cf2
-      __x86_raw_shared_cache_size_half = shared / 2;
446cf2
-      __x86_raw_shared_cache_size = shared;
446cf2
-      /* Round shared cache size to multiple of 256 bytes.  */
446cf2
-      shared = shared & ~255L;
446cf2
-      __x86_shared_cache_size_half = shared / 2;
446cf2
-      __x86_shared_cache_size = shared;
446cf2
-    }
446cf2
-
446cf2
-  /* The default setting for the non_temporal threshold is 3/4 of one
446cf2
-     thread's share of the chip's cache. For most Intel and AMD processors
446cf2
-     with an initial release date between 2017 and 2020, a thread's typical
446cf2
-     share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4
446cf2
-     threshold leaves 125 KBytes to 500 KBytes of the thread's data
446cf2
-     in cache after a maximum temporal copy, which will maintain
446cf2
-     in cache a reasonable portion of the thread's stack and other
446cf2
-     active data. If the threshold is set higher than one thread's
446cf2
-     share of the cache, it has a substantial risk of negatively
446cf2
-     impacting the performance of other threads running on the chip. */
446cf2
-  __x86_shared_non_temporal_threshold
446cf2
-    = (cpu_features->non_temporal_threshold != 0
446cf2
-       ? cpu_features->non_temporal_threshold
446cf2
-       : __x86_shared_cache_size * 3 / 4);
446cf2
-
446cf2
-  /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8.  */
446cf2
-  unsigned int minimum_rep_movsb_threshold;
446cf2
-  /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16).  */
446cf2
-  unsigned int rep_movsb_threshold;
446cf2
-  if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F)
446cf2
-      && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512))
446cf2
-    {
446cf2
-      rep_movsb_threshold = 2048 * (64 / 16);
446cf2
-      minimum_rep_movsb_threshold = 64 * 8;
446cf2
-    }
446cf2
-  else if (CPU_FEATURE_PREFERRED_P (cpu_features,
446cf2
-				    AVX_Fast_Unaligned_Load))
446cf2
-    {
446cf2
-      rep_movsb_threshold = 2048 * (32 / 16);
446cf2
-      minimum_rep_movsb_threshold = 32 * 8;
446cf2
-    }
446cf2
-  else
446cf2
-    {
446cf2
-      rep_movsb_threshold = 2048 * (16 / 16);
446cf2
-      minimum_rep_movsb_threshold = 16 * 8;
446cf2
-    }
446cf2
-  if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold)
446cf2
-    __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold;
446cf2
-  else
446cf2
-    __x86_rep_movsb_threshold = rep_movsb_threshold;
446cf2
-
446cf2
-# if HAVE_TUNABLES
446cf2
-  __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold;
446cf2
+__ifunc (__x86_cacheinfo, __x86_cacheinfo, NULL, void, init_cacheinfo);
446cf2
 # endif
446cf2
-}
446cf2
-
446cf2
 #endif
446cf2
diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h
446cf2
new file mode 100644
446cf2
index 0000000000000000..0255696163b7b8ff
446cf2
--- /dev/null
446cf2
+++ b/sysdeps/x86/cacheinfo.h
446cf2
@@ -0,0 +1,427 @@
446cf2
+/* x86 cache info.
446cf2
+   Copyright (C) 2020 Free Software Foundation, Inc.
446cf2
+   This file is part of the GNU C Library.
446cf2
+
446cf2
+   The GNU C Library is free software; you can redistribute it and/or
446cf2
+   modify it under the terms of the GNU Lesser General Public
446cf2
+   License as published by the Free Software Foundation; either
446cf2
+   version 2.1 of the License, or (at your option) any later version.
446cf2
+
446cf2
+   The GNU C Library is distributed in the hope that it will be useful,
446cf2
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
446cf2
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
446cf2
+   Lesser General Public License for more details.
446cf2
+
446cf2
+   You should have received a copy of the GNU Lesser General Public
446cf2
+   License along with the GNU C Library; if not, see
446cf2
+   <https://www.gnu.org/licenses/>.  */
446cf2
+
446cf2
+#include <assert.h>
446cf2
+#include <unistd.h>
446cf2
+
446cf2
+/* Data cache size for use in memory and string routines, typically
446cf2
+   L1 size, rounded to multiple of 256 bytes.  */
446cf2
+long int __x86_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
446cf2
+long int __x86_data_cache_size attribute_hidden = 32 * 1024;
446cf2
+/* Similar to __x86_data_cache_size_half, but not rounded.  */
446cf2
+long int __x86_raw_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
446cf2
+/* Similar to __x86_data_cache_size, but not rounded.  */
446cf2
+long int __x86_raw_data_cache_size attribute_hidden = 32 * 1024;
446cf2
+/* Shared cache size for use in memory and string routines, typically
446cf2
+   L2 or L3 size, rounded to multiple of 256 bytes.  */
446cf2
+long int __x86_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
446cf2
+long int __x86_shared_cache_size attribute_hidden = 1024 * 1024;
446cf2
+/* Similar to __x86_shared_cache_size_half, but not rounded.  */
446cf2
+long int __x86_raw_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
446cf2
+/* Similar to __x86_shared_cache_size, but not rounded.  */
446cf2
+long int __x86_raw_shared_cache_size attribute_hidden = 1024 * 1024;
446cf2
+
446cf2
+/* Threshold to use non temporal store.  */
446cf2
+long int __x86_shared_non_temporal_threshold attribute_hidden;
446cf2
+
446cf2
+/* Threshold to use Enhanced REP MOVSB.  */
446cf2
+long int __x86_rep_movsb_threshold attribute_hidden = 2048;
446cf2
+
446cf2
+/* Threshold to use Enhanced REP STOSB.  */
446cf2
+long int __x86_rep_stosb_threshold attribute_hidden = 2048;
446cf2
+
446cf2
+static void
446cf2
+get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr,
446cf2
+		       long int core)
446cf2
+{
446cf2
+  unsigned int eax;
446cf2
+  unsigned int ebx;
446cf2
+  unsigned int ecx;
446cf2
+  unsigned int edx;
446cf2
+
446cf2
+  /* Number of logical processors sharing L2 cache.  */
446cf2
+  int threads_l2;
446cf2
+
446cf2
+  /* Number of logical processors sharing L3 cache.  */
446cf2
+  int threads_l3;
446cf2
+
446cf2
+  const struct cpu_features *cpu_features = __get_cpu_features ();
446cf2
+  int max_cpuid = cpu_features->basic.max_cpuid;
446cf2
+  unsigned int family = cpu_features->basic.family;
446cf2
+  unsigned int model = cpu_features->basic.model;
446cf2
+  long int shared = *shared_ptr;
446cf2
+  unsigned int threads = *threads_ptr;
446cf2
+  bool inclusive_cache = true;
446cf2
+  bool support_count_mask = true;
446cf2
+
446cf2
+  /* Try L3 first.  */
446cf2
+  unsigned int level = 3;
446cf2
+
446cf2
+  if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6)
446cf2
+    support_count_mask = false;
446cf2
+
446cf2
+  if (shared <= 0)
446cf2
+    {
446cf2
+      /* Try L2 otherwise.  */
446cf2
+      level  = 2;
446cf2
+      shared = core;
446cf2
+      threads_l2 = 0;
446cf2
+      threads_l3 = -1;
446cf2
+    }
446cf2
+  else
446cf2
+    {
446cf2
+      threads_l2 = 0;
446cf2
+      threads_l3 = 0;
446cf2
+    }
446cf2
+
446cf2
+  /* A value of 0 for the HTT bit indicates there is only a single
446cf2
+     logical processor.  */
446cf2
+  if (HAS_CPU_FEATURE (HTT))
446cf2
+    {
446cf2
+      /* Figure out the number of logical threads that share the
446cf2
+         highest cache level.  */
446cf2
+      if (max_cpuid >= 4)
446cf2
+        {
446cf2
+          int i = 0;
446cf2
+
446cf2
+          /* Query until cache level 2 and 3 are enumerated.  */
446cf2
+          int check = 0x1 | (threads_l3 == 0) << 1;
446cf2
+          do
446cf2
+            {
446cf2
+              __cpuid_count (4, i++, eax, ebx, ecx, edx);
446cf2
+
446cf2
+              /* There seems to be a bug in at least some Pentium Ds
446cf2
+                 which sometimes fail to iterate all cache parameters.
446cf2
+                 Do not loop indefinitely here, stop in this case and
446cf2
+                 assume there is no such information.  */
446cf2
+              if (cpu_features->basic.kind == arch_kind_intel
446cf2
+                  && (eax & 0x1f) == 0 )
446cf2
+                goto intel_bug_no_cache_info;
446cf2
+
446cf2
+              switch ((eax >> 5) & 0x7)
446cf2
+                {
446cf2
+                  default:
446cf2
+                    break;
446cf2
+                  case 2:
446cf2
+                    if ((check & 0x1))
446cf2
+                      {
446cf2
+                        /* Get maximum number of logical processors
446cf2
+                           sharing L2 cache.  */
446cf2
+                        threads_l2 = (eax >> 14) & 0x3ff;
446cf2
+                        check &= ~0x1;
446cf2
+                      }
446cf2
+                    break;
446cf2
+                  case 3:
446cf2
+                    if ((check & (0x1 << 1)))
446cf2
+                      {
446cf2
+                        /* Get maximum number of logical processors
446cf2
+                           sharing L3 cache.  */
446cf2
+                        threads_l3 = (eax >> 14) & 0x3ff;
446cf2
+
446cf2
+                        /* Check if L2 and L3 caches are inclusive.  */
446cf2
+                        inclusive_cache = (edx & 0x2) != 0;
446cf2
+                        check &= ~(0x1 << 1);
446cf2
+                      }
446cf2
+                    break;
446cf2
+                }
446cf2
+            }
446cf2
+          while (check);
446cf2
+
446cf2
+          /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum
446cf2
+             numbers of addressable IDs for logical processors sharing
446cf2
+             the cache, instead of the maximum number of threads
446cf2
+             sharing the cache.  */
446cf2
+          if (max_cpuid >= 11 && support_count_mask)
446cf2
+            {
446cf2
+              /* Find the number of logical processors shipped in
446cf2
+                 one core and apply count mask.  */
446cf2
+              i = 0;
446cf2
+
446cf2
+              /* Count SMT only if there is L3 cache.  Always count
446cf2
+                 core if there is no L3 cache.  */
446cf2
+              int count = ((threads_l2 > 0 && level == 3)
446cf2
+                           | ((threads_l3 > 0
446cf2
+                               || (threads_l2 > 0 && level == 2)) << 1));
446cf2
+
446cf2
+              while (count)
446cf2
+                {
446cf2
+                  __cpuid_count (11, i++, eax, ebx, ecx, edx);
446cf2
+
446cf2
+                  int shipped = ebx & 0xff;
446cf2
+                  int type = ecx & 0xff00;
446cf2
+                  if (shipped == 0 || type == 0)
446cf2
+                    break;
446cf2
+                  else if (type == 0x100)
446cf2
+                    {
446cf2
+                      /* Count SMT.  */
446cf2
+                      if ((count & 0x1))
446cf2
+                        {
446cf2
+                          int count_mask;
446cf2
+
446cf2
+                          /* Compute count mask.  */
446cf2
+                          asm ("bsr %1, %0"
446cf2
+                               : "=r" (count_mask) : "g" (threads_l2));
446cf2
+                          count_mask = ~(-1 << (count_mask + 1));
446cf2
+                          threads_l2 = (shipped - 1) & count_mask;
446cf2
+                          count &= ~0x1;
446cf2
+                        }
446cf2
+                    }
446cf2
+                  else if (type == 0x200)
446cf2
+                    {
446cf2
+                      /* Count core.  */
446cf2
+                      if ((count & (0x1 << 1)))
446cf2
+                        {
446cf2
+                          int count_mask;
446cf2
+                          int threads_core
446cf2
+                            = (level == 2 ? threads_l2 : threads_l3);
446cf2
+
446cf2
+                          /* Compute count mask.  */
446cf2
+                          asm ("bsr %1, %0"
446cf2
+                               : "=r" (count_mask) : "g" (threads_core));
446cf2
+                          count_mask = ~(-1 << (count_mask + 1));
446cf2
+                          threads_core = (shipped - 1) & count_mask;
446cf2
+                          if (level == 2)
446cf2
+                            threads_l2 = threads_core;
446cf2
+                          else
446cf2
+                            threads_l3 = threads_core;
446cf2
+                          count &= ~(0x1 << 1);
446cf2
+                        }
446cf2
+                    }
446cf2
+                }
446cf2
+            }
446cf2
+          if (threads_l2 > 0)
446cf2
+            threads_l2 += 1;
446cf2
+          if (threads_l3 > 0)
446cf2
+            threads_l3 += 1;
446cf2
+          if (level == 2)
446cf2
+            {
446cf2
+              if (threads_l2)
446cf2
+                {
446cf2
+                  threads = threads_l2;
446cf2
+                  if (cpu_features->basic.kind == arch_kind_intel
446cf2
+                      && threads > 2
446cf2
+                      && family == 6)
446cf2
+                    switch (model)
446cf2
+                      {
446cf2
+                        case 0x37:
446cf2
+                        case 0x4a:
446cf2
+                        case 0x4d:
446cf2
+                        case 0x5a:
446cf2
+                        case 0x5d:
446cf2
+                          /* Silvermont has L2 cache shared by 2 cores.  */
446cf2
+                          threads = 2;
446cf2
+                          break;
446cf2
+                        default:
446cf2
+                          break;
446cf2
+                      }
446cf2
+                }
446cf2
+            }
446cf2
+          else if (threads_l3)
446cf2
+            threads = threads_l3;
446cf2
+        }
446cf2
+      else
446cf2
+        {
446cf2
+intel_bug_no_cache_info:
446cf2
+          /* Assume that all logical threads share the highest cache
446cf2
+             level.  */
446cf2
+          threads
446cf2
+            = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx
446cf2
+                >> 16) & 0xff);
446cf2
+        }
446cf2
+
446cf2
+        /* Cap usage of highest cache level to the number of supported
446cf2
+           threads.  */
446cf2
+        if (shared > 0 && threads > 0)
446cf2
+          shared /= threads;
446cf2
+    }
446cf2
+
446cf2
+  /* Account for non-inclusive L2 and L3 caches.  */
446cf2
+  if (!inclusive_cache)
446cf2
+    {
446cf2
+      if (threads_l2 > 0)
446cf2
+        core /= threads_l2;
446cf2
+      shared += core;
446cf2
+    }
446cf2
+
446cf2
+  *shared_ptr = shared;
446cf2
+  *threads_ptr = threads;
446cf2
+}
446cf2
+
446cf2
+static void
446cf2
+init_cacheinfo (void)
446cf2
+{
446cf2
+  /* Find out what brand of processor.  */
446cf2
+  unsigned int ebx;
446cf2
+  unsigned int ecx;
446cf2
+  unsigned int edx;
446cf2
+  int max_cpuid_ex;
446cf2
+  long int data = -1;
446cf2
+  long int shared = -1;
446cf2
+  long int core;
446cf2
+  unsigned int threads = 0;
446cf2
+  const struct cpu_features *cpu_features = __get_cpu_features ();
446cf2
+
446cf2
+  /* NB: In libc.so, cpu_features is defined in ld.so and is initialized
446cf2
+     by DL_PLATFORM_INIT or IFUNC relocation before init_cacheinfo is
446cf2
+     called by IFUNC relocation.  In libc.a, init_cacheinfo is called
446cf2
+     from init_cpu_features by ARCH_INIT_CPU_FEATURES.  */
446cf2
+  assert (cpu_features->basic.kind != arch_kind_unknown);
446cf2
+
446cf2
+  if (cpu_features->basic.kind == arch_kind_intel)
446cf2
+    {
446cf2
+      data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
446cf2
+      core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
446cf2
+      shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
446cf2
+
446cf2
+      get_common_cache_info (&shared, &threads, core);
446cf2
+    }
446cf2
+  else if (cpu_features->basic.kind == arch_kind_zhaoxin)
446cf2
+    {
446cf2
+      data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE);
446cf2
+      core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
446cf2
+      shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
446cf2
+
446cf2
+      get_common_cache_info (&shared, &threads, core);
446cf2
+    }
446cf2
+  else if (cpu_features->basic.kind == arch_kind_amd)
446cf2
+    {
446cf2
+      data   = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
446cf2
+      long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
446cf2
+      shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
446cf2
+
446cf2
+      /* Get maximum extended function. */
446cf2
+      __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx);
446cf2
+
446cf2
+      if (shared <= 0)
446cf2
+	/* No shared L3 cache.  All we have is the L2 cache.  */
446cf2
+	shared = core;
446cf2
+      else
446cf2
+	{
446cf2
+	  /* Figure out the number of logical threads that share L3.  */
446cf2
+	  if (max_cpuid_ex >= 0x80000008)
446cf2
+	    {
446cf2
+	      /* Get width of APIC ID.  */
446cf2
+	      __cpuid (0x80000008, max_cpuid_ex, ebx, ecx, edx);
446cf2
+	      threads = 1 << ((ecx >> 12) & 0x0f);
446cf2
+	    }
446cf2
+
446cf2
+	  if (threads == 0 || cpu_features->basic.family >= 0x17)
446cf2
+	    {
446cf2
+	      /* If APIC ID width is not available, use logical
446cf2
+		 processor count.  */
446cf2
+	      __cpuid (0x00000001, max_cpuid_ex, ebx, ecx, edx);
446cf2
+
446cf2
+	      if ((edx & (1 << 28)) != 0)
446cf2
+		threads = (ebx >> 16) & 0xff;
446cf2
+	    }
446cf2
+
446cf2
+	  /* Cap usage of highest cache level to the number of
446cf2
+	     supported threads.  */
446cf2
+	  if (threads > 0)
446cf2
+	    shared /= threads;
446cf2
+
446cf2
+	  /* Get shared cache per ccx for Zen architectures.  */
446cf2
+	  if (cpu_features->basic.family >= 0x17)
446cf2
+	    {
446cf2
+	      unsigned int eax;
446cf2
+
446cf2
+	      /* Get number of threads share the L3 cache in CCX.  */
446cf2
+	      __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
446cf2
+
446cf2
+	      unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
446cf2
+	      shared *= threads_per_ccx;
446cf2
+	    }
446cf2
+	  else
446cf2
+	    {
446cf2
+	      /* Account for exclusive L2 and L3 caches.  */
446cf2
+	      shared += core;
446cf2
+            }
446cf2
+	}
446cf2
+    }
446cf2
+
446cf2
+  if (cpu_features->data_cache_size != 0)
446cf2
+    data = cpu_features->data_cache_size;
446cf2
+
446cf2
+  if (data > 0)
446cf2
+    {
446cf2
+      __x86_raw_data_cache_size_half = data / 2;
446cf2
+      __x86_raw_data_cache_size = data;
446cf2
+      /* Round data cache size to multiple of 256 bytes.  */
446cf2
+      data = data & ~255L;
446cf2
+      __x86_data_cache_size_half = data / 2;
446cf2
+      __x86_data_cache_size = data;
446cf2
+    }
446cf2
+
446cf2
+  if (cpu_features->shared_cache_size != 0)
446cf2
+    shared = cpu_features->shared_cache_size;
446cf2
+
446cf2
+  if (shared > 0)
446cf2
+    {
446cf2
+      __x86_raw_shared_cache_size_half = shared / 2;
446cf2
+      __x86_raw_shared_cache_size = shared;
446cf2
+      /* Round shared cache size to multiple of 256 bytes.  */
446cf2
+      shared = shared & ~255L;
446cf2
+      __x86_shared_cache_size_half = shared / 2;
446cf2
+      __x86_shared_cache_size = shared;
446cf2
+    }
446cf2
+
446cf2
+  /* The default setting for the non_temporal threshold is 3/4 of one
446cf2
+     thread's share of the chip's cache. For most Intel and AMD processors
446cf2
+     with an initial release date between 2017 and 2020, a thread's typical
446cf2
+     share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4
446cf2
+     threshold leaves 125 KBytes to 500 KBytes of the thread's data
446cf2
+     in cache after a maximum temporal copy, which will maintain
446cf2
+     in cache a reasonable portion of the thread's stack and other
446cf2
+     active data. If the threshold is set higher than one thread's
446cf2
+     share of the cache, it has a substantial risk of negatively
446cf2
+     impacting the performance of other threads running on the chip. */
446cf2
+  __x86_shared_non_temporal_threshold
446cf2
+    = (cpu_features->non_temporal_threshold != 0
446cf2
+       ? cpu_features->non_temporal_threshold
446cf2
+       : __x86_shared_cache_size * 3 / 4);
446cf2
+
446cf2
+  /* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8.  */
446cf2
+  unsigned int minimum_rep_movsb_threshold;
446cf2
+  /* NB: The default REP MOVSB threshold is 2048 * (VEC_SIZE / 16).  */
446cf2
+  unsigned int rep_movsb_threshold;
446cf2
+  if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F)
446cf2
+      && !CPU_FEATURE_PREFERRED_P (cpu_features, Prefer_No_AVX512))
446cf2
+    {
446cf2
+      rep_movsb_threshold = 2048 * (64 / 16);
446cf2
+      minimum_rep_movsb_threshold = 64 * 8;
446cf2
+    }
446cf2
+  else if (CPU_FEATURE_PREFERRED_P (cpu_features,
446cf2
+				    AVX_Fast_Unaligned_Load))
446cf2
+    {
446cf2
+      rep_movsb_threshold = 2048 * (32 / 16);
446cf2
+      minimum_rep_movsb_threshold = 32 * 8;
446cf2
+    }
446cf2
+  else
446cf2
+    {
446cf2
+      rep_movsb_threshold = 2048 * (16 / 16);
446cf2
+      minimum_rep_movsb_threshold = 16 * 8;
446cf2
+    }
446cf2
+  if (cpu_features->rep_movsb_threshold > minimum_rep_movsb_threshold)
446cf2
+    __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold;
446cf2
+  else
446cf2
+    __x86_rep_movsb_threshold = rep_movsb_threshold;
446cf2
+
446cf2
+# if HAVE_TUNABLES
446cf2
+  __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold;
446cf2
+# endif
446cf2
+}
446cf2
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
446cf2
index 5f0548fe08134236..4c9c15a44b618fed 100644
446cf2
--- a/sysdeps/x86/cpu-features.c
446cf2
+++ b/sysdeps/x86/cpu-features.c
446cf2
@@ -17,9 +17,14 @@
446cf2
    <http://www.gnu.org/licenses/>.  */
446cf2
 
446cf2
 #include <cpuid.h>
446cf2
-#include <cpu-features.h>
446cf2
 #include <dl-hwcap.h>
446cf2
 #include <libc-pointer-arith.h>
446cf2
+#if IS_IN (libc) && !defined SHARED
446cf2
+# include <assert.h>
446cf2
+# include <unistd.h>
446cf2
+# include <dl-cacheinfo.h>
446cf2
+# include <cacheinfo.h>
446cf2
+#endif
446cf2
 
446cf2
 #if HAVE_TUNABLES
446cf2
 # define TUNABLE_NAMESPACE cpu
446cf2
@@ -752,4 +757,9 @@ no_cpuid:
446cf2
 # endif
446cf2
     }
446cf2
 #endif
446cf2
+
446cf2
+#ifndef SHARED
446cf2
+  /* NB: In libc.a, call init_cacheinfo.  */
446cf2
+  init_cacheinfo ();
446cf2
+#endif
446cf2
 }
446cf2
diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
446cf2
new file mode 100644
446cf2
index 0000000000000000..b2b90074b0e98a60
446cf2
--- /dev/null
446cf2
+++ b/sysdeps/x86/dl-cacheinfo.h
446cf2
@@ -0,0 +1,478 @@
446cf2
+/* Initialize x86 cache info.
446cf2
+   Copyright (C) 2020 Free Software Foundation, Inc.
446cf2
+   This file is part of the GNU C Library.
446cf2
+
446cf2
+   The GNU C Library is free software; you can redistribute it and/or
446cf2
+   modify it under the terms of the GNU Lesser General Public
446cf2
+   License as published by the Free Software Foundation; either
446cf2
+   version 2.1 of the License, or (at your option) any later version.
446cf2
+
446cf2
+   The GNU C Library is distributed in the hope that it will be useful,
446cf2
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
446cf2
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
446cf2
+   Lesser General Public License for more details.
446cf2
+
446cf2
+   You should have received a copy of the GNU Lesser General Public
446cf2
+   License along with the GNU C Library; if not, see
446cf2
+   <https://www.gnu.org/licenses/>.  */
446cf2
+
446cf2
+static const struct intel_02_cache_info
446cf2
+{
446cf2
+  unsigned char idx;
446cf2
+  unsigned char assoc;
446cf2
+  unsigned char linesize;
446cf2
+  unsigned char rel_name;
446cf2
+  unsigned int size;
446cf2
+} intel_02_known [] =
446cf2
+  {
446cf2
+#define M(sc) ((sc) - _SC_LEVEL1_ICACHE_SIZE)
446cf2
+    { 0x06,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),    8192 },
446cf2
+    { 0x08,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   16384 },
446cf2
+    { 0x09,  4, 32, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
446cf2
+    { 0x0a,  2, 32, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
446cf2
+    { 0x0c,  4, 32, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
446cf2
+    { 0x0d,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
446cf2
+    { 0x0e,  6, 64, M(_SC_LEVEL1_DCACHE_SIZE),   24576 },
446cf2
+    { 0x21,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
446cf2
+    { 0x22,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
446cf2
+    { 0x23,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
446cf2
+    { 0x25,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
446cf2
+    { 0x29,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
446cf2
+    { 0x2c,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
446cf2
+    { 0x30,  8, 64, M(_SC_LEVEL1_ICACHE_SIZE),   32768 },
446cf2
+    { 0x39,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
446cf2
+    { 0x3a,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   196608 },
446cf2
+    { 0x3b,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
446cf2
+    { 0x3c,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
446cf2
+    { 0x3d,  6, 64, M(_SC_LEVEL2_CACHE_SIZE),   393216 },
446cf2
+    { 0x3e,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x3f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
446cf2
+    { 0x41,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
446cf2
+    { 0x42,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
446cf2
+    { 0x43,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x44,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
446cf2
+    { 0x45,  4, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
446cf2
+    { 0x46,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
446cf2
+    { 0x47,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
446cf2
+    { 0x48, 12, 64, M(_SC_LEVEL2_CACHE_SIZE),  3145728 },
446cf2
+    { 0x49, 16, 64, M(_SC_LEVEL2_CACHE_SIZE),  4194304 },
446cf2
+    { 0x4a, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  6291456 },
446cf2
+    { 0x4b, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
446cf2
+    { 0x4c, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
446cf2
+    { 0x4d, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 16777216 },
446cf2
+    { 0x4e, 24, 64, M(_SC_LEVEL2_CACHE_SIZE),  6291456 },
446cf2
+    { 0x60,  8, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
446cf2
+    { 0x66,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),    8192 },
446cf2
+    { 0x67,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   16384 },
446cf2
+    { 0x68,  4, 64, M(_SC_LEVEL1_DCACHE_SIZE),   32768 },
446cf2
+    { 0x78,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
446cf2
+    { 0x79,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   131072 },
446cf2
+    { 0x7a,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
446cf2
+    { 0x7b,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x7c,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
446cf2
+    { 0x7d,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
446cf2
+    { 0x7f,  2, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x80,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x82,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   262144 },
446cf2
+    { 0x83,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x84,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
446cf2
+    { 0x85,  8, 32, M(_SC_LEVEL2_CACHE_SIZE),  2097152 },
446cf2
+    { 0x86,  4, 64, M(_SC_LEVEL2_CACHE_SIZE),   524288 },
446cf2
+    { 0x87,  8, 64, M(_SC_LEVEL2_CACHE_SIZE),  1048576 },
446cf2
+    { 0xd0,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),   524288 },
446cf2
+    { 0xd1,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
446cf2
+    { 0xd2,  4, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
446cf2
+    { 0xd6,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  1048576 },
446cf2
+    { 0xd7,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
446cf2
+    { 0xd8,  8, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
446cf2
+    { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
446cf2
+    { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
446cf2
+    { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
446cf2
+    { 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  2097152 },
446cf2
+    { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  4194304 },
446cf2
+    { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE),  8388608 },
446cf2
+    { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
446cf2
+    { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
446cf2
+    { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
446cf2
+  };
446cf2
+
446cf2
+#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0]))
446cf2
+
446cf2
+static int
446cf2
+intel_02_known_compare (const void *p1, const void *p2)
446cf2
+{
446cf2
+  const struct intel_02_cache_info *i1;
446cf2
+  const struct intel_02_cache_info *i2;
446cf2
+
446cf2
+  i1 = (const struct intel_02_cache_info *) p1;
446cf2
+  i2 = (const struct intel_02_cache_info *) p2;
446cf2
+
446cf2
+  if (i1->idx == i2->idx)
446cf2
+    return 0;
446cf2
+
446cf2
+  return i1->idx < i2->idx ? -1 : 1;
446cf2
+}
446cf2
+
446cf2
+
446cf2
+static long int
446cf2
+__attribute__ ((noinline))
446cf2
+intel_check_word (int name, unsigned int value, bool *has_level_2,
446cf2
+		  bool *no_level_2_or_3,
446cf2
+		  const struct cpu_features *cpu_features)
446cf2
+{
446cf2
+  if ((value & 0x80000000) != 0)
446cf2
+    /* The register value is reserved.  */
446cf2
+    return 0;
446cf2
+
446cf2
+  /* Fold the name.  The _SC_ constants are always in the order SIZE,
446cf2
+     ASSOC, LINESIZE.  */
446cf2
+  int folded_rel_name = (M(name) / 3) * 3;
446cf2
+
446cf2
+  while (value != 0)
446cf2
+    {
446cf2
+      unsigned int byte = value & 0xff;
446cf2
+
446cf2
+      if (byte == 0x40)
446cf2
+	{
446cf2
+	  *no_level_2_or_3 = true;
446cf2
+
446cf2
+	  if (folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
446cf2
+	    /* No need to look further.  */
446cf2
+	    break;
446cf2
+	}
446cf2
+      else if (byte == 0xff)
446cf2
+	{
446cf2
+	  /* CPUID leaf 0x4 contains all the information.  We need to
446cf2
+	     iterate over it.  */
446cf2
+	  unsigned int eax;
446cf2
+	  unsigned int ebx;
446cf2
+	  unsigned int ecx;
446cf2
+	  unsigned int edx;
446cf2
+
446cf2
+	  unsigned int round = 0;
446cf2
+	  while (1)
446cf2
+	    {
446cf2
+	      __cpuid_count (4, round, eax, ebx, ecx, edx);
446cf2
+
446cf2
+	      enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
446cf2
+	      if (type == null)
446cf2
+		/* That was the end.  */
446cf2
+		break;
446cf2
+
446cf2
+	      unsigned int level = (eax >> 5) & 0x7;
446cf2
+
446cf2
+	      if ((level == 1 && type == data
446cf2
+		   && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
446cf2
+		  || (level == 1 && type == inst
446cf2
+		      && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
446cf2
+		  || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
446cf2
+		  || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
446cf2
+		  || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
446cf2
+		{
446cf2
+		  unsigned int offset = M(name) - folded_rel_name;
446cf2
+
446cf2
+		  if (offset == 0)
446cf2
+		    /* Cache size.  */
446cf2
+		    return (((ebx >> 22) + 1)
446cf2
+			    * (((ebx >> 12) & 0x3ff) + 1)
446cf2
+			    * ((ebx & 0xfff) + 1)
446cf2
+			    * (ecx + 1));
446cf2
+		  if (offset == 1)
446cf2
+		    return (ebx >> 22) + 1;
446cf2
+
446cf2
+		  assert (offset == 2);
446cf2
+		  return (ebx & 0xfff) + 1;
446cf2
+		}
446cf2
+
446cf2
+	      ++round;
446cf2
+	    }
446cf2
+	  /* There is no other cache information anywhere else.  */
446cf2
+	  break;
446cf2
+	}
446cf2
+      else
446cf2
+	{
446cf2
+	  if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
446cf2
+	    {
446cf2
+	      /* Intel reused this value.  For family 15, model 6 it
446cf2
+		 specifies the 3rd level cache.  Otherwise the 2nd
446cf2
+		 level cache.  */
446cf2
+	      unsigned int family = cpu_features->basic.family;
446cf2
+	      unsigned int model = cpu_features->basic.model;
446cf2
+
446cf2
+	      if (family == 15 && model == 6)
446cf2
+		{
446cf2
+		  /* The level 3 cache is encoded for this model like
446cf2
+		     the level 2 cache is for other models.  Pretend
446cf2
+		     the caller asked for the level 2 cache.  */
446cf2
+		  name = (_SC_LEVEL2_CACHE_SIZE
446cf2
+			  + (name - _SC_LEVEL3_CACHE_SIZE));
446cf2
+		  folded_rel_name = M(_SC_LEVEL2_CACHE_SIZE);
446cf2
+		}
446cf2
+	    }
446cf2
+
446cf2
+	  struct intel_02_cache_info *found;
446cf2
+	  struct intel_02_cache_info search;
446cf2
+
446cf2
+	  search.idx = byte;
446cf2
+	  found = bsearch (&search, intel_02_known, nintel_02_known,
446cf2
+			   sizeof (intel_02_known[0]), intel_02_known_compare);
446cf2
+	  if (found != NULL)
446cf2
+	    {
446cf2
+	      if (found->rel_name == folded_rel_name)
446cf2
+		{
446cf2
+		  unsigned int offset = M(name) - folded_rel_name;
446cf2
+
446cf2
+		  if (offset == 0)
446cf2
+		    /* Cache size.  */
446cf2
+		    return found->size;
446cf2
+		  if (offset == 1)
446cf2
+		    return found->assoc;
446cf2
+
446cf2
+		  assert (offset == 2);
446cf2
+		  return found->linesize;
446cf2
+		}
446cf2
+
446cf2
+	      if (found->rel_name == M(_SC_LEVEL2_CACHE_SIZE))
446cf2
+		*has_level_2 = true;
446cf2
+	    }
446cf2
+	}
446cf2
+
446cf2
+      /* Next byte for the next round.  */
446cf2
+      value >>= 8;
446cf2
+    }
446cf2
+
446cf2
+  /* Nothing found.  */
446cf2
+  return 0;
446cf2
+}
446cf2
+
446cf2
+
446cf2
+static long int __attribute__ ((noinline))
446cf2
+handle_intel (int name, const struct cpu_features *cpu_features)
446cf2
+{
446cf2
+  unsigned int maxidx = cpu_features->basic.max_cpuid;
446cf2
+
446cf2
+  /* Return -1 for older CPUs.  */
446cf2
+  if (maxidx < 2)
446cf2
+    return -1;
446cf2
+
446cf2
+  /* OK, we can use the CPUID instruction to get all info about the
446cf2
+     caches.  */
446cf2
+  unsigned int cnt = 0;
446cf2
+  unsigned int max = 1;
446cf2
+  long int result = 0;
446cf2
+  bool no_level_2_or_3 = false;
446cf2
+  bool has_level_2 = false;
446cf2
+
446cf2
+  while (cnt++ < max)
446cf2
+    {
446cf2
+      unsigned int eax;
446cf2
+      unsigned int ebx;
446cf2
+      unsigned int ecx;
446cf2
+      unsigned int edx;
446cf2
+      __cpuid (2, eax, ebx, ecx, edx);
446cf2
+
446cf2
+      /* The low byte of EAX in the first round contain the number of
446cf2
+	 rounds we have to make.  At least one, the one we are already
446cf2
+	 doing.  */
446cf2
+      if (cnt == 1)
446cf2
+	{
446cf2
+	  max = eax & 0xff;
446cf2
+	  eax &= 0xffffff00;
446cf2
+	}
446cf2
+
446cf2
+      /* Process the individual registers' value.  */
446cf2
+      result = intel_check_word (name, eax, &has_level_2,
446cf2
+				 &no_level_2_or_3, cpu_features);
446cf2
+      if (result != 0)
446cf2
+	return result;
446cf2
+
446cf2
+      result = intel_check_word (name, ebx, &has_level_2,
446cf2
+				 &no_level_2_or_3, cpu_features);
446cf2
+      if (result != 0)
446cf2
+	return result;
446cf2
+
446cf2
+      result = intel_check_word (name, ecx, &has_level_2,
446cf2
+				 &no_level_2_or_3, cpu_features);
446cf2
+      if (result != 0)
446cf2
+	return result;
446cf2
+
446cf2
+      result = intel_check_word (name, edx, &has_level_2,
446cf2
+				 &no_level_2_or_3, cpu_features);
446cf2
+      if (result != 0)
446cf2
+	return result;
446cf2
+    }
446cf2
+
446cf2
+  if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
446cf2
+      && no_level_2_or_3)
446cf2
+    return -1;
446cf2
+
446cf2
+  return 0;
446cf2
+}
446cf2
+
446cf2
+
446cf2
+static long int __attribute__ ((noinline))
446cf2
+handle_amd (int name)
446cf2
+{
446cf2
+  unsigned int eax;
446cf2
+  unsigned int ebx;
446cf2
+  unsigned int ecx;
446cf2
+  unsigned int edx;
446cf2
+  __cpuid (0x80000000, eax, ebx, ecx, edx);
446cf2
+
446cf2
+  /* No level 4 cache (yet).  */
446cf2
+  if (name > _SC_LEVEL3_CACHE_LINESIZE)
446cf2
+    return 0;
446cf2
+
446cf2
+  unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
446cf2
+  if (eax < fn)
446cf2
+    return 0;
446cf2
+
446cf2
+  __cpuid (fn, eax, ebx, ecx, edx);
446cf2
+
446cf2
+  if (name < _SC_LEVEL1_DCACHE_SIZE)
446cf2
+    {
446cf2
+      name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
446cf2
+      ecx = edx;
446cf2
+    }
446cf2
+
446cf2
+  switch (name)
446cf2
+    {
446cf2
+    case _SC_LEVEL1_DCACHE_SIZE:
446cf2
+      return (ecx >> 14) & 0x3fc00;
446cf2
+
446cf2
+    case _SC_LEVEL1_DCACHE_ASSOC:
446cf2
+      ecx >>= 16;
446cf2
+      if ((ecx & 0xff) == 0xff)
446cf2
+	/* Fully associative.  */
446cf2
+	return (ecx << 2) & 0x3fc00;
446cf2
+      return ecx & 0xff;
446cf2
+
446cf2
+    case _SC_LEVEL1_DCACHE_LINESIZE:
446cf2
+      return ecx & 0xff;
446cf2
+
446cf2
+    case _SC_LEVEL2_CACHE_SIZE:
446cf2
+      return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
446cf2
+
446cf2
+    case _SC_LEVEL2_CACHE_ASSOC:
446cf2
+      switch ((ecx >> 12) & 0xf)
446cf2
+	{
446cf2
+	case 0:
446cf2
+	case 1:
446cf2
+	case 2:
446cf2
+	case 4:
446cf2
+	  return (ecx >> 12) & 0xf;
446cf2
+	case 6:
446cf2
+	  return 8;
446cf2
+	case 8:
446cf2
+	  return 16;
446cf2
+	case 10:
446cf2
+	  return 32;
446cf2
+	case 11:
446cf2
+	  return 48;
446cf2
+	case 12:
446cf2
+	  return 64;
446cf2
+	case 13:
446cf2
+	  return 96;
446cf2
+	case 14:
446cf2
+	  return 128;
446cf2
+	case 15:
446cf2
+	  return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
446cf2
+	default:
446cf2
+	  return 0;
446cf2
+	}
446cf2
+      /* NOTREACHED */
446cf2
+
446cf2
+    case _SC_LEVEL2_CACHE_LINESIZE:
446cf2
+      return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
446cf2
+
446cf2
+    case _SC_LEVEL3_CACHE_SIZE:
446cf2
+      return (edx & 0xf000) == 0 ? 0 : (edx & 0x3ffc0000) << 1;
446cf2
+
446cf2
+    case _SC_LEVEL3_CACHE_ASSOC:
446cf2
+      switch ((edx >> 12) & 0xf)
446cf2
+	{
446cf2
+	case 0:
446cf2
+	case 1:
446cf2
+	case 2:
446cf2
+	case 4:
446cf2
+	  return (edx >> 12) & 0xf;
446cf2
+	case 6:
446cf2
+	  return 8;
446cf2
+	case 8:
446cf2
+	  return 16;
446cf2
+	case 10:
446cf2
+	  return 32;
446cf2
+	case 11:
446cf2
+	  return 48;
446cf2
+	case 12:
446cf2
+	  return 64;
446cf2
+	case 13:
446cf2
+	  return 96;
446cf2
+	case 14:
446cf2
+	  return 128;
446cf2
+	case 15:
446cf2
+	  return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
446cf2
+	default:
446cf2
+	  return 0;
446cf2
+	}
446cf2
+      /* NOTREACHED */
446cf2
+
446cf2
+    case _SC_LEVEL3_CACHE_LINESIZE:
446cf2
+      return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
446cf2
+
446cf2
+    default:
446cf2
+      assert (! "cannot happen");
446cf2
+    }
446cf2
+  return -1;
446cf2
+}
446cf2
+
446cf2
+
446cf2
+static long int __attribute__ ((noinline))
446cf2
+handle_zhaoxin (int name)
446cf2
+{
446cf2
+  unsigned int eax;
446cf2
+  unsigned int ebx;
446cf2
+  unsigned int ecx;
446cf2
+  unsigned int edx;
446cf2
+
446cf2
+  int folded_rel_name = (M(name) / 3) * 3;
446cf2
+
446cf2
+  unsigned int round = 0;
446cf2
+  while (1)
446cf2
+    {
446cf2
+      __cpuid_count (4, round, eax, ebx, ecx, edx);
446cf2
+
446cf2
+      enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
446cf2
+      if (type == null)
446cf2
+        break;
446cf2
+
446cf2
+      unsigned int level = (eax >> 5) & 0x7;
446cf2
+
446cf2
+      if ((level == 1 && type == data
446cf2
+        && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
446cf2
+        || (level == 1 && type == inst
446cf2
+            && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
446cf2
+        || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
446cf2
+        || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)))
446cf2
+        {
446cf2
+          unsigned int offset = M(name) - folded_rel_name;
446cf2
+
446cf2
+          if (offset == 0)
446cf2
+            /* Cache size.  */
446cf2
+            return (((ebx >> 22) + 1)
446cf2
+                * (((ebx >> 12) & 0x3ff) + 1)
446cf2
+                * ((ebx & 0xfff) + 1)
446cf2
+                * (ecx + 1));
446cf2
+          if (offset == 1)
446cf2
+            return (ebx >> 22) + 1;
446cf2
+
446cf2
+          assert (offset == 2);
446cf2
+          return (ebx & 0xfff) + 1;
446cf2
+        }
446cf2
+
446cf2
+      ++round;
446cf2
+    }
446cf2
+
446cf2
+  /* Nothing found.  */
446cf2
+  return 0;
446cf2
+}
446cf2
diff --git a/sysdeps/x86/dl-get-cpu-features.c b/sysdeps/x86/dl-get-cpu-features.c
446cf2
index 2aba0d167129b336..82772cc12f0c7e54 100644
446cf2
--- a/sysdeps/x86/dl-get-cpu-features.c
446cf2
+++ b/sysdeps/x86/dl-get-cpu-features.c
446cf2
@@ -1,5 +1,5 @@
446cf2
-/* This file is part of the GNU C Library.
446cf2
-   Copyright (C) 2015-2018 Free Software Foundation, Inc.
446cf2
+/* Initialize CPU feature data via IFUNC relocation.
446cf2
+   Copyright (C) 2015-2020 Free Software Foundation, Inc.
446cf2
 
446cf2
    The GNU C Library is free software; you can redistribute it and/or
446cf2
    modify it under the terms of the GNU Lesser General Public
446cf2
@@ -18,6 +18,31 @@
446cf2
 
446cf2
 #include <ldsodefs.h>
446cf2
 
446cf2
+#ifdef SHARED
446cf2
+# include <cpu-features.c>
446cf2
+
446cf2
+/* NB: Normally, DL_PLATFORM_INIT calls init_cpu_features to initialize
446cf2
+   CPU features in dynamic executable.  But when loading ld.so inside of
446cf2
+   static executable, DL_PLATFORM_INIT isn't called and IFUNC relocation
446cf2
+   is used to call init_cpu_features.  In static executable, it is called
446cf2
+   once by IFUNC relocation.  In dynamic executable, it is called twice
446cf2
+   by DL_PLATFORM_INIT and by IFUNC relocation.  */
446cf2
+extern void __x86_cpu_features (void) attribute_hidden;
446cf2
+const void (*__x86_cpu_features_p) (void) attribute_hidden
446cf2
+  = __x86_cpu_features;
446cf2
+
446cf2
+void
446cf2
+_dl_x86_init_cpu_features (void)
446cf2
+{
446cf2
+  struct cpu_features *cpu_features = __get_cpu_features ();
446cf2
+  if (cpu_features->basic.kind == arch_kind_unknown)
446cf2
+    init_cpu_features (cpu_features);
446cf2
+}
446cf2
+
446cf2
+__ifunc (__x86_cpu_features, __x86_cpu_features, NULL, void,
446cf2
+	 _dl_x86_init_cpu_features);
446cf2
+#endif
446cf2
+
446cf2
 #undef __x86_get_cpu_features
446cf2
 
446cf2
 const struct cpu_features *
446cf2
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
446cf2
index dcf29b6fe8578078..f62be0b9b3746675 100644
446cf2
--- a/sysdeps/x86/include/cpu-features.h
446cf2
+++ b/sysdeps/x86/include/cpu-features.h
446cf2
@@ -159,6 +159,7 @@ struct cpu_features
446cf2
 /* Unused for x86.  */
446cf2
 #  define INIT_ARCH()
446cf2
 #  define __x86_get_cpu_features(max) (&GLRO(dl_x86_cpu_features))
446cf2
+extern void _dl_x86_init_cpu_features (void) attribute_hidden;
446cf2
 # endif
446cf2
 
446cf2
 # ifdef __x86_64__
446cf2
diff --git a/sysdeps/x86/libc-start.c b/sysdeps/x86/libc-start.c
446cf2
index eb5335c154096384..60f2c34ab5511350 100644
446cf2
--- a/sysdeps/x86/libc-start.c
446cf2
+++ b/sysdeps/x86/libc-start.c
446cf2
@@ -20,7 +20,6 @@
446cf2
    PIE.  */
446cf2
 # include <startup.h>
446cf2
 # include <ldsodefs.h>
446cf2
-# include <cpu-features.h>
446cf2
 # include <cpu-features.c>
446cf2
 
446cf2
 extern struct cpu_features _dl_x86_cpu_features;
446cf2
diff --git a/sysdeps/x86_64/dl-machine.h b/sysdeps/x86_64/dl-machine.h
446cf2
index d58298d787ef352c..e308b662d245cc63 100644
446cf2
--- a/sysdeps/x86_64/dl-machine.h
446cf2
+++ b/sysdeps/x86_64/dl-machine.h
446cf2
@@ -26,7 +26,6 @@
446cf2
 #include <sysdep.h>
446cf2
 #include <tls.h>
446cf2
 #include <dl-tlsdesc.h>
446cf2
-#include <cpu-features.c>
446cf2
 
446cf2
 /* Return nonzero iff ELF header is compatible with the running host.  */
446cf2
 static inline int __attribute__ ((unused))
446cf2
@@ -223,9 +222,9 @@ static inline void __attribute__ ((unused))
446cf2
 dl_platform_init (void)
446cf2
 {
446cf2
 #if IS_IN (rtld)
446cf2
-  /* init_cpu_features has been called early from __libc_start_main in
446cf2
-     static executable.  */
446cf2
-  init_cpu_features (&GLRO(dl_x86_cpu_features));
446cf2
+  /* _dl_x86_init_cpu_features is a wrapper for init_cpu_features which
446cf2
+     has been called early from __libc_start_main in static executable.  */
446cf2
+  _dl_x86_init_cpu_features ();
446cf2
 #else
446cf2
   if (GLRO(dl_platform) != NULL && *GLRO(dl_platform) == '\0')
446cf2
     /* Avoid an empty string which would disturb us.  */