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We add back Prefer_SSE_for_memop since we still need it for all of the
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existing era implementations for RHEL 7.3. To remove it would require
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a more wholesale backport of optmized routines.
00db10
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commit e2e4f56056adddc3c1efe676b40a4b4f2453103b
00db10
Author: H.J. Lu <hjl.tools@gmail.com>
00db10
Date:   Thu Aug 13 03:37:47 2015 -0700
00db10
00db10
    Add _dl_x86_cpu_features to rtld_global
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    This patch adds _dl_x86_cpu_features to rtld_global in x86 ld.so
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    and initializes it early before __libc_start_main is called so that
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    cpu_features is always available when it is used and we can avoid
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    calling __init_cpu_features in IFUNC selectors.
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00db10
Index: glibc-2.17-c758a686/sysdeps/i386/dl-machine.h
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/dl-machine.h
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+++ glibc-2.17-c758a686/sysdeps/i386/dl-machine.h
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@@ -25,6 +25,7 @@
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 #include <sysdep.h>
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 #include <tls.h>
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 #include <dl-tlsdesc.h>
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+#include <cpu-features.c>
00db10
 
00db10
 /* Return nonzero iff ELF header is compatible with the running host.  */
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 static inline int __attribute__ ((unused))
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@@ -266,6 +267,8 @@ dl_platform_init (void)
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   if (GLRO(dl_platform) != NULL && *GLRO(dl_platform) == '\0')
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     /* Avoid an empty string which would disturb us.  */
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     GLRO(dl_platform) = NULL;
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+
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+  init_cpu_features (&GLRO(dl_x86_cpu_features));
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 }
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 static inline Elf32_Addr
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Index: glibc-2.17-c758a686/sysdeps/i386/dl-procinfo.c
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/dl-procinfo.c
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+++ glibc-2.17-c758a686/sysdeps/i386/dl-procinfo.c
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@@ -43,6 +43,22 @@
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 # define PROCINFO_CLASS
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 #endif
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+#if !IS_IN (ldconfig)
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+# if !defined PROCINFO_DECL && defined SHARED
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+  ._dl_x86_cpu_features
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+# else
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+PROCINFO_CLASS struct cpu_features _dl_x86_cpu_features
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+# endif
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+# ifndef PROCINFO_DECL
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+= { }
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+# endif
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+# if !defined SHARED || defined PROCINFO_DECL
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+;
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+# else
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+,
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+# endif
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+#endif
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+
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 #if !defined PROCINFO_DECL && defined SHARED
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   ._dl_x86_cap_flags
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 #else
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Index: glibc-2.17-c758a686/sysdeps/i386/i686/cacheinfo.c
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/i686/cacheinfo.c
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+++ glibc-2.17-c758a686/sysdeps/i386/i686/cacheinfo.c
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@@ -8,6 +8,5 @@
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 #define __x86_64_raw_shared_cache_size_half __x86_raw_shared_cache_size_half
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 #define DISABLE_PREFETCHW
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-#define DISABLE_PREFERRED_MEMORY_INSTRUCTION
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 #include <sysdeps/x86_64/cacheinfo.c>
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Index: glibc-2.17-c758a686/sysdeps/i386/i686/multiarch/Makefile
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/i686/multiarch/Makefile
00db10
+++ glibc-2.17-c758a686/sysdeps/i386/i686/multiarch/Makefile
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@@ -1,5 +1,4 @@
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 ifeq ($(subdir),csu)
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-aux += init-arch
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 tests += test-multiarch
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 gen-as-const-headers += ifunc-defines.sym
00db10
 endif
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Index: glibc-2.17-c758a686/sysdeps/i386/i686/multiarch/Versions
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/i686/multiarch/Versions
00db10
+++ /dev/null
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@@ -1,5 +0,0 @@
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-libc {
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-  GLIBC_PRIVATE {
00db10
-    __get_cpu_features;
00db10
-  }
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-}
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Index: glibc-2.17-c758a686/sysdeps/i386/i686/multiarch/ifunc-defines.sym
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/i686/multiarch/ifunc-defines.sym
00db10
+++ glibc-2.17-c758a686/sysdeps/i386/i686/multiarch/ifunc-defines.sym
00db10
@@ -4,7 +4,6 @@
00db10
 --
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 CPU_FEATURES_SIZE	sizeof (struct cpu_features)
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-KIND_OFFSET		offsetof (struct cpu_features, kind)
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 CPUID_OFFSET		offsetof (struct cpu_features, cpuid)
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 CPUID_SIZE		sizeof (struct cpuid_registers)
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 CPUID_EAX_OFFSET	offsetof (struct cpuid_registers, eax)
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Index: glibc-2.17-c758a686/sysdeps/i386/ldsodefs.h
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/i386/ldsodefs.h
00db10
+++ glibc-2.17-c758a686/sysdeps/i386/ldsodefs.h
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@@ -20,6 +20,7 @@
00db10
 #define	_I386_LDSODEFS_H	1
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 #include <elf.h>
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+#include <cpu-features.h>
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 struct La_i86_regs;
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 struct La_i86_retval;
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Index: glibc-2.17-c758a686/sysdeps/unix/sysv/linux/x86_64/dl-procinfo.c
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/unix/sysv/linux/x86_64/dl-procinfo.c
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+++ glibc-2.17-c758a686/sysdeps/unix/sysv/linux/x86_64/dl-procinfo.c
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@@ -1,5 +1,5 @@
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 #if IS_IN (ldconfig)
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 # include <sysdeps/i386/dl-procinfo.c>
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 #else
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-# include <sysdeps/generic/dl-procinfo.c>
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+# include <sysdeps/x86_64/dl-procinfo.c>
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 #endif
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Index: glibc-2.17-c758a686/sysdeps/x86/Makefile
00db10
===================================================================
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--- glibc-2.17-c758a686.orig/sysdeps/x86/Makefile
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+++ glibc-2.17-c758a686/sysdeps/x86/Makefile
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@@ -7,3 +7,14 @@ $(objpfx)tst-xmmymmzmm.out: ../sysdeps/x
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 	@echo "Checking ld.so for SSE register use.  This will take a few seconds..."
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 	$(SHELL) $< $(objpfx) '$(NM)' '$(OBJDUMP)' '$(READELF)' > $@
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 endif
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+
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+ifeq ($(subdir),csu)
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+gen-as-const-headers += cpu-features-offsets.sym rtld-global-offsets.sym
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+endif
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+
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+ifeq ($(subdir),elf)
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+sysdep-dl-routines += dl-get-cpu-features
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+
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+tests += tst-get-cpu-features
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+tests-static += tst-get-cpu-features-static
00db10
+endif
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Index: glibc-2.17-c758a686/sysdeps/x86/Versions
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/Versions
00db10
@@ -0,0 +1,5 @@
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+ld {
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+  GLIBC_PRIVATE {
00db10
+    __get_cpu_features;
00db10
+  }
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+}
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Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features-offsets.sym
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features-offsets.sym
00db10
@@ -0,0 +1,7 @@
00db10
+#define SHARED 1
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+
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+#include <ldsodefs.h>
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+
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+#define rtld_global_ro_offsetof(mem) offsetof (struct rtld_global_ro, mem)
00db10
+
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+RTLD_GLOBAL_RO_DL_X86_CPU_FEATURES_OFFSET rtld_global_ro_offsetof (_dl_x86_cpu_features)
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Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.c
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.c
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@@ -0,0 +1,213 @@
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+/* Initialize CPU feature data.
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+   This file is part of the GNU C Library.
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+   Copyright (C) 2008-2015 Free Software Foundation, Inc.
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+
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+   The GNU C Library is free software; you can redistribute it and/or
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+   modify it under the terms of the GNU Lesser General Public
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+   License as published by the Free Software Foundation; either
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+   version 2.1 of the License, or (at your option) any later version.
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+
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+   The GNU C Library is distributed in the hope that it will be useful,
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+   but WITHOUT ANY WARRANTY; without even the implied warranty of
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+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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+   Lesser General Public License for more details.
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+
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+   You should have received a copy of the GNU Lesser General Public
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+   License along with the GNU C Library; if not, see
00db10
+   <http://www.gnu.org/licenses/>.  */
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+
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+#include <cpuid.h>
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+#include <cpu-features.h>
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+
00db10
+static inline void
00db10
+get_common_indeces (struct cpu_features *cpu_features,
00db10
+		    unsigned int *family, unsigned int *model)
00db10
+{
00db10
+  unsigned int eax;
00db10
+  __cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
00db10
+	   cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
00db10
+	   cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
00db10
+  GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].eax = eax;
00db10
+  *family = (eax >> 8) & 0x0f;
00db10
+  *model = (eax >> 4) & 0x0f;
00db10
+}
00db10
+
00db10
+static inline void
00db10
+init_cpu_features (struct cpu_features *cpu_features)
00db10
+{
00db10
+  unsigned int ebx, ecx, edx;
00db10
+  unsigned int family = 0;
00db10
+  unsigned int model = 0;
00db10
+  enum cpu_features_kind kind;
00db10
+
00db10
+  __cpuid (0, cpu_features->max_cpuid, ebx, ecx, edx);
00db10
+
00db10
+  /* This spells out "GenuineIntel".  */
00db10
+  if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
00db10
+    {
00db10
+      kind = arch_kind_intel;
00db10
+
00db10
+      get_common_indeces (cpu_features, &family, &model);
00db10
+
00db10
+      /* Intel processors prefer SSE instruction for memory/string
00db10
+        routines if they are available.  */
00db10
+      cpu_features->feature[index_Prefer_SSE_for_memop]
00db10
+        |= bit_Prefer_SSE_for_memop;
00db10
+
00db10
+      unsigned int eax = cpu_features->cpuid[COMMON_CPUID_INDEX_1].eax;
00db10
+      unsigned int extended_family = (eax >> 20) & 0xff;
00db10
+      unsigned int extended_model = (eax >> 12) & 0xf0;
00db10
+      if (family == 0x0f)
00db10
+	{
00db10
+	  family += extended_family;
00db10
+	  model += extended_model;
00db10
+	}
00db10
+      else if (family == 0x06)
00db10
+	{
00db10
+	  ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
00db10
+	  model += extended_model;
00db10
+	  switch (model)
00db10
+	    {
00db10
+	    case 0x1c:
00db10
+	    case 0x26:
00db10
+	      /* BSF is slow on Atom.  */
00db10
+	      cpu_features->feature[index_Slow_BSF] |= bit_Slow_BSF;
00db10
+	      break;
00db10
+
00db10
+	    case 0x37:
00db10
+	    case 0x4a:
00db10
+	    case 0x4d:
00db10
+	    case 0x5a:
00db10
+	    case 0x5d:
00db10
+	      /* Unaligned load versions are faster than SSSE3
00db10
+		 on Silvermont.  */
00db10
+#if index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop
00db10
+# error index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop
00db10
+#endif
00db10
+#if index_Fast_Unaligned_Load != index_Slow_SSE4_2
00db10
+# error index_Fast_Unaligned_Load != index_Slow_SSE4_2
00db10
+#endif
00db10
+	      cpu_features->feature[index_Fast_Unaligned_Load]
00db10
+		|= (bit_Fast_Unaligned_Load
00db10
+		    | bit_Prefer_PMINUB_for_stringop
00db10
+		    | bit_Slow_SSE4_2);
00db10
+	      break;
00db10
+
00db10
+	    default:
00db10
+	      /* Unknown family 0x06 processors.  Assuming this is one
00db10
+		 of Core i3/i5/i7 processors if AVX is available.  */
00db10
+	      if ((ecx & bit_AVX) == 0)
00db10
+		break;
00db10
+
00db10
+	    case 0x1a:
00db10
+	    case 0x1e:
00db10
+	    case 0x1f:
00db10
+	    case 0x25:
00db10
+	    case 0x2c:
00db10
+	    case 0x2e:
00db10
+	    case 0x2f:
00db10
+	      /* Rep string instructions, copy backward, unaligned loads
00db10
+		 and pminub are fast on Intel Core i3, i5 and i7.  */
00db10
+#if index_Fast_Rep_String != index_Fast_Copy_Backward
00db10
+# error index_Fast_Rep_String != index_Fast_Copy_Backward
00db10
+#endif
00db10
+#if index_Fast_Rep_String != index_Fast_Unaligned_Load
00db10
+# error index_Fast_Rep_String != index_Fast_Unaligned_Load
00db10
+#endif
00db10
+#if index_Fast_Rep_String != index_Prefer_PMINUB_for_stringop
00db10
+# error index_Fast_Rep_String != index_Prefer_PMINUB_for_stringop
00db10
+#endif
00db10
+	      cpu_features->feature[index_Fast_Rep_String]
00db10
+		|= (bit_Fast_Rep_String
00db10
+		    | bit_Fast_Copy_Backward
00db10
+		    | bit_Fast_Unaligned_Load
00db10
+		    | bit_Prefer_PMINUB_for_stringop);
00db10
+	      break;
00db10
+	    }
00db10
+	}
00db10
+    }
00db10
+  /* This spells out "AuthenticAMD".  */
00db10
+  else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
00db10
+    {
00db10
+      kind = arch_kind_amd;
00db10
+
00db10
+      get_common_indeces (cpu_features, &family, &model);
00db10
+
00db10
+      ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
00db10
+
00db10
+      /* AMD processors prefer SSE instructions for memory/string routines
00db10
+        if they are available, otherwise they prefer integer instructions.  */
00db10
+      if ((ecx & 0x200))
00db10
+	cpu_features->feature[index_Prefer_SSE_for_memop]
00db10
+	  |= bit_Prefer_SSE_for_memop;
00db10
+
00db10
+      unsigned int eax;
00db10
+      __cpuid (0x80000000, eax, ebx, ecx, edx);
00db10
+      if (eax >= 0x80000001)
00db10
+	__cpuid (0x80000001,
00db10
+		 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].eax,
00db10
+		 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ebx,
00db10
+		 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ecx,
00db10
+		 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].edx);
00db10
+    }
00db10
+  else
00db10
+    kind = arch_kind_other;
00db10
+
00db10
+  if (cpu_features->max_cpuid >= 7)
00db10
+    __cpuid_count (7, 0,
00db10
+		   cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
00db10
+		   cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
00db10
+		   cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
00db10
+		   cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
00db10
+
00db10
+  /* Can we call xgetbv?  */
00db10
+  if (HAS_CPU_FEATURE (OSXSAVE))
00db10
+    {
00db10
+      unsigned int xcrlow;
00db10
+      unsigned int xcrhigh;
00db10
+      asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
00db10
+      /* Is YMM and XMM state usable?  */
00db10
+      if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
00db10
+	  (bit_YMM_state | bit_XMM_state))
00db10
+	{
00db10
+	  /* Determine if AVX is usable.  */
00db10
+	  if (HAS_CPU_FEATURE (AVX))
00db10
+	    cpu_features->feature[index_AVX_Usable] |= bit_AVX_Usable;
00db10
+#if index_AVX2_Usable != index_AVX_Fast_Unaligned_Load
00db10
+# error index_AVX2_Usable != index_AVX_Fast_Unaligned_Load
00db10
+#endif
00db10
+	  /* Determine if AVX2 is usable.  Unaligned load with 256-bit
00db10
+	     AVX registers are faster on processors with AVX2.  */
00db10
+	  if (HAS_CPU_FEATURE (AVX2))
00db10
+	    cpu_features->feature[index_AVX2_Usable]
00db10
+	      |= bit_AVX2_Usable | bit_AVX_Fast_Unaligned_Load;
00db10
+	  /* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
00db10
+	     ZMM16-ZMM31 state are enabled.  */
00db10
+	  if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
00db10
+			 | bit_ZMM16_31_state)) ==
00db10
+	      (bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
00db10
+	    {
00db10
+	      /* Determine if AVX512F is usable.  */
00db10
+	      if (HAS_CPU_FEATURE (AVX512F))
00db10
+		{
00db10
+		  cpu_features->feature[index_AVX512F_Usable]
00db10
+		    |= bit_AVX512F_Usable;
00db10
+		  /* Determine if AVX512DQ is usable.  */
00db10
+		  if (HAS_CPU_FEATURE (AVX512DQ))
00db10
+		    cpu_features->feature[index_AVX512DQ_Usable]
00db10
+		      |= bit_AVX512DQ_Usable;
00db10
+		}
00db10
+	    }
00db10
+	  /* Determine if FMA is usable.  */
00db10
+	  if (HAS_CPU_FEATURE (FMA))
00db10
+	    cpu_features->feature[index_FMA_Usable] |= bit_FMA_Usable;
00db10
+	  /* Determine if FMA4 is usable.  */
00db10
+	  if (HAS_CPU_FEATURE (FMA4))
00db10
+	    cpu_features->feature[index_FMA4_Usable] |= bit_FMA4_Usable;
00db10
+	}
00db10
+    }
00db10
+
00db10
+  cpu_features->family = family;
00db10
+  cpu_features->model = model;
00db10
+  cpu_features->kind = kind;
00db10
+}
00db10
Index: glibc-2.17-c758a686/sysdeps/x86/cpu-features.h
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/cpu-features.h
00db10
@@ -0,0 +1,273 @@
00db10
+/* This file is part of the GNU C Library.
00db10
+   Copyright (C) 2008-2015 Free Software Foundation, Inc.
00db10
+
00db10
+   The GNU C Library is free software; you can redistribute it and/or
00db10
+   modify it under the terms of the GNU Lesser General Public
00db10
+   License as published by the Free Software Foundation; either
00db10
+   version 2.1 of the License, or (at your option) any later version.
00db10
+
00db10
+   The GNU C Library is distributed in the hope that it will be useful,
00db10
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
00db10
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00db10
+   Lesser General Public License for more details.
00db10
+
00db10
+   You should have received a copy of the GNU Lesser General Public
00db10
+   License along with the GNU C Library; if not, see
00db10
+   <http://www.gnu.org/licenses/>.  */
00db10
+
00db10
+#ifndef cpu_features_h
00db10
+#define cpu_features_h
00db10
+
00db10
+#define bit_Fast_Rep_String		(1 << 0)
00db10
+#define bit_Fast_Copy_Backward		(1 << 1)
00db10
+#define bit_Slow_BSF			(1 << 2)
00db10
+#define bit_Prefer_SSE_for_memop	(1 << 3)
00db10
+#define bit_Fast_Unaligned_Load		(1 << 4)
00db10
+#define bit_Prefer_PMINUB_for_stringop	(1 << 5)
00db10
+#define bit_AVX_Usable			(1 << 6)
00db10
+#define bit_FMA_Usable			(1 << 7)
00db10
+#define bit_FMA4_Usable			(1 << 8)
00db10
+#define bit_Slow_SSE4_2			(1 << 9)
00db10
+#define bit_AVX2_Usable			(1 << 10)
00db10
+#define bit_AVX_Fast_Unaligned_Load	(1 << 11)
00db10
+#define bit_AVX512F_Usable		(1 << 12)
00db10
+#define bit_AVX512DQ_Usable		(1 << 13)
00db10
+
00db10
+/* CPUID Feature flags.  */
00db10
+
00db10
+/* COMMON_CPUID_INDEX_1.  */
00db10
+#define bit_SSE2	(1 << 26)
00db10
+#define bit_SSSE3	(1 << 9)
00db10
+#define bit_SSE4_1	(1 << 19)
00db10
+#define bit_SSE4_2	(1 << 20)
00db10
+#define bit_OSXSAVE	(1 << 27)
00db10
+#define bit_AVX		(1 << 28)
00db10
+#define bit_POPCOUNT	(1 << 23)
00db10
+#define bit_FMA		(1 << 12)
00db10
+#define bit_FMA4	(1 << 16)
00db10
+
00db10
+/* COMMON_CPUID_INDEX_7.  */
00db10
+#define bit_RTM		(1 << 11)
00db10
+#define bit_AVX2	(1 << 5)
00db10
+#define bit_AVX512F	(1 << 16)
00db10
+#define bit_AVX512DQ	(1 << 17)
00db10
+
00db10
+/* XCR0 Feature flags.  */
00db10
+#define bit_XMM_state  (1 << 1)
00db10
+#define bit_YMM_state  (2 << 1)
00db10
+#define bit_Opmask_state	(1 << 5)
00db10
+#define bit_ZMM0_15_state	(1 << 6)
00db10
+#define bit_ZMM16_31_state	(1 << 7)
00db10
+
00db10
+/* The integer bit array index for the first set of internal feature bits.  */
00db10
+#define FEATURE_INDEX_1 0
00db10
+
00db10
+/* The current maximum size of the feature integer bit array.  */
00db10
+#define FEATURE_INDEX_MAX 1
00db10
+
00db10
+#ifdef	__ASSEMBLER__
00db10
+
00db10
+# include <ifunc-defines.h>
00db10
+# include <rtld-global-offsets.h>
00db10
+
00db10
+# define index_SSE2	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
00db10
+# define index_SSSE3	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
+# define index_SSE4_1	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
+# define index_SSE4_2	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
+# define index_AVX	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
+# define index_AVX2	COMMON_CPUID_INDEX_7*CPUID_SIZE+CPUID_EBX_OFFSET
00db10
+
00db10
+# define index_Fast_Rep_String		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_Fast_Copy_Backward	FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_Slow_BSF			FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_Prefer_SSE_for_memop	FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_Fast_Unaligned_Load	FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_Prefer_PMINUB_for_stringop FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_AVX_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_FMA_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_FMA4_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_Slow_SSE4_2		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_AVX2_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_AVX_Fast_Unaligned_Load	FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_AVX512F_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+# define index_AVX512DQ_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
+
00db10
+# if defined (_LIBC) && !IS_IN (nonlib)
00db10
+#  ifdef __x86_64__
00db10
+#   ifdef SHARED
00db10
+#    if IS_IN (rtld)
00db10
+#     define LOAD_RTLD_GLOBAL_RO_RDX
00db10
+#     define HAS_FEATURE(offset, name) \
00db10
+  testl $(bit_##name), _rtld_local_ro+offset+(index_##name)(%rip)
00db10
+#    else
00db10
+#      define LOAD_RTLD_GLOBAL_RO_RDX \
00db10
+  mov _rtld_global_ro@GOTPCREL(%rip), %RDX_LP
00db10
+#     define HAS_FEATURE(offset, name) \
00db10
+  testl $(bit_##name), \
00db10
+	RTLD_GLOBAL_RO_DL_X86_CPU_FEATURES_OFFSET+offset+(index_##name)(%rdx)
00db10
+#    endif
00db10
+#   else /* SHARED */
00db10
+#    define LOAD_RTLD_GLOBAL_RO_RDX
00db10
+#    define HAS_FEATURE(offset, name) \
00db10
+  testl $(bit_##name), _dl_x86_cpu_features+offset+(index_##name)(%rip)
00db10
+#   endif /* !SHARED */
00db10
+#  else  /* __x86_64__ */
00db10
+#   ifdef SHARED
00db10
+#    define LOAD_FUNC_GOT_EAX(func) \
00db10
+  leal func@GOTOFF(%edx), %eax
00db10
+#    if IS_IN (rtld)
00db10
+#    define LOAD_GOT_AND_RTLD_GLOBAL_RO \
00db10
+  LOAD_PIC_REG(dx)
00db10
+#     define HAS_FEATURE(offset, name) \
00db10
+  testl $(bit_##name), offset+(index_##name)+_rtld_local_ro@GOTOFF(%edx)
00db10
+#    else
00db10
+#     define LOAD_GOT_AND_RTLD_GLOBAL_RO \
00db10
+  LOAD_PIC_REG(dx); \
00db10
+  mov _rtld_global_ro@GOT(%edx), %ecx
00db10
+#     define HAS_FEATURE(offset, name) \
00db10
+  testl $(bit_##name), \
00db10
+	RTLD_GLOBAL_RO_DL_X86_CPU_FEATURES_OFFSET+offset+(index_##name)(%ecx)
00db10
+#    endif
00db10
+#   else  /* SHARED */
00db10
+#    define LOAD_FUNC_GOT_EAX(func) \
00db10
+  leal func, %eax
00db10
+#    define LOAD_GOT_AND_RTLD_GLOBAL_RO
00db10
+#    define HAS_FEATURE(offset, name) \
00db10
+  testl $(bit_##name), _dl_x86_cpu_features+offset+(index_##name)
00db10
+#   endif /* !SHARED */
00db10
+#  endif /* !__x86_64__ */
00db10
+# else /* _LIBC && !nonlib */
00db10
+#  error "Sorry, <cpu-features.h> is unimplemented for assembler"
00db10
+# endif /* !_LIBC || nonlib */
00db10
+
00db10
+/* HAS_* evaluates to true if we may use the feature at runtime.  */
00db10
+# define HAS_CPU_FEATURE(name)	HAS_FEATURE (CPUID_OFFSET, name)
00db10
+# define HAS_ARCH_FEATURE(name) HAS_FEATURE (FEATURE_OFFSET, name)
00db10
+
00db10
+#else	/* __ASSEMBLER__ */
00db10
+
00db10
+# include <sys/param.h>
00db10
+# include <sys/types.h>
00db10
+# include <sysdep.h>
00db10
+# include <stdbool.h>
00db10
+
00db10
+/* Ugly hack to make it possible to select a strstr and strcasestr
00db10
+   implementation that avoids using the stack for 16-byte aligned
00db10
+   SSE temporaries.  Doing so makes it possible to call the functions
00db10
+   with a stack that's not 16-byte aligned as can happen, for example,
00db10
+   as a result of compiling the functions' callers with the GCC
00db10
+   -mpreferred-stack-boubdary=2 or =3 option, or with the ICC
00db10
+   -falign-stack=assume-4-byte option.  See rhbz 1150282 for details.
00db10
+
00db10
+   The ifunc selector uses the unaligned version by default if this
00db10
+   file exists and is accessible.  */
00db10
+# define ENABLE_STRSTR_UNALIGNED_PATHNAME \
00db10
+    "/etc/sysconfig/64bit_strstr_via_64bit_strstr_sse2_unaligned"
00db10
+
00db10
+static bool __attribute__ ((unused))
00db10
+use_unaligned_strstr (void)
00db10
+{
00db10
+  struct stat unaligned_strstr_etc_sysconfig_file;
00db10
+
00db10
+  /* TLS may not have been set up yet, so avoid using stat since it tries to
00db10
+     set errno.  */
00db10
+  return INTERNAL_SYSCALL (stat, , 2,
00db10
+			   ENABLE_STRSTR_UNALIGNED_PATHNAME,
00db10
+			   &unaligned_strstr_etc_sysconfig_file) == 0;
00db10
+}
00db10
+
00db10
+enum
00db10
+  {
00db10
+    COMMON_CPUID_INDEX_1 = 0,
00db10
+    COMMON_CPUID_INDEX_7,
00db10
+    COMMON_CPUID_INDEX_80000001,	/* for AMD */
00db10
+    /* Keep the following line at the end.  */
00db10
+    COMMON_CPUID_INDEX_MAX
00db10
+  };
00db10
+
00db10
+struct cpu_features
00db10
+{
00db10
+  enum cpu_features_kind
00db10
+    {
00db10
+      arch_kind_unknown = 0,
00db10
+      arch_kind_intel,
00db10
+      arch_kind_amd,
00db10
+      arch_kind_other
00db10
+    } kind;
00db10
+  int max_cpuid;
00db10
+  struct cpuid_registers
00db10
+  {
00db10
+    unsigned int eax;
00db10
+    unsigned int ebx;
00db10
+    unsigned int ecx;
00db10
+    unsigned int edx;
00db10
+  } cpuid[COMMON_CPUID_INDEX_MAX];
00db10
+  unsigned int family;
00db10
+  unsigned int model;
00db10
+  unsigned int feature[FEATURE_INDEX_MAX];
00db10
+};
00db10
+
00db10
+/* Used from outside of glibc to get access to the CPU features
00db10
+   structure.  */
00db10
+extern const struct cpu_features *__get_cpu_features (void)
00db10
+     __attribute__ ((const));
00db10
+
00db10
+# if defined (_LIBC) && !IS_IN (nonlib)
00db10
+/* Unused for x86.  */
00db10
+#  define INIT_ARCH()
00db10
+#  define __get_cpu_features()	(&GLRO(dl_x86_cpu_features))
00db10
+# endif
00db10
+
00db10
+
00db10
+/* HAS_* evaluates to true if we may use the feature at runtime.  */
00db10
+# define HAS_CPU_FEATURE(name) \
00db10
+  ((__get_cpu_features ()->cpuid[index_##name].reg_##name & (bit_##name)) != 0)
00db10
+# define HAS_ARCH_FEATURE(name) \
00db10
+  ((__get_cpu_features ()->feature[index_##name] & (bit_##name)) != 0)
00db10
+
00db10
+# define index_SSE2		COMMON_CPUID_INDEX_1
00db10
+# define index_SSSE3		COMMON_CPUID_INDEX_1
00db10
+# define index_SSE4_1		COMMON_CPUID_INDEX_1
00db10
+# define index_SSE4_2		COMMON_CPUID_INDEX_1
00db10
+# define index_AVX		COMMON_CPUID_INDEX_1
00db10
+# define index_AVX2		COMMON_CPUID_INDEX_7
00db10
+# define index_AVX512F		COMMON_CPUID_INDEX_7
00db10
+# define index_AVX512DQ		COMMON_CPUID_INDEX_7
00db10
+# define index_RTM		COMMON_CPUID_INDEX_7
00db10
+# define index_FMA		COMMON_CPUID_INDEX_1
00db10
+# define index_FMA4		COMMON_CPUID_INDEX_80000001
00db10
+# define index_POPCOUNT		COMMON_CPUID_INDEX_1
00db10
+# define index_OSXSAVE		COMMON_CPUID_INDEX_1
00db10
+
00db10
+# define reg_SSE2		edx
00db10
+# define reg_SSSE3		ecx
00db10
+# define reg_SSE4_1		ecx
00db10
+# define reg_SSE4_2		ecx
00db10
+# define reg_AVX		ecx
00db10
+# define reg_AVX2		ebx
00db10
+# define reg_AVX512F		ebx
00db10
+# define reg_AVX512DQ		ebx
00db10
+# define reg_RTM		ebx
00db10
+# define reg_FMA		ecx
00db10
+# define reg_FMA4		ecx
00db10
+# define reg_POPCOUNT		ecx
00db10
+# define reg_OSXSAVE		ecx
00db10
+
00db10
+# define index_Fast_Rep_String		FEATURE_INDEX_1
00db10
+# define index_Fast_Copy_Backward	FEATURE_INDEX_1
00db10
+# define index_Slow_BSF			FEATURE_INDEX_1
00db10
+# define index_Prefer_SSE_for_memop	FEATURE_INDEX_1
00db10
+# define index_Fast_Unaligned_Load	FEATURE_INDEX_1
00db10
+# define index_Prefer_PMINUB_for_stringop FEATURE_INDEX_1
00db10
+# define index_AVX_Usable		FEATURE_INDEX_1
00db10
+# define index_FMA_Usable		FEATURE_INDEX_1
00db10
+# define index_FMA4_Usable		FEATURE_INDEX_1
00db10
+# define index_Slow_SSE4_2		FEATURE_INDEX_1
00db10
+# define index_AVX2_Usable		FEATURE_INDEX_1
00db10
+# define index_AVX_Fast_Unaligned_Load	FEATURE_INDEX_1
00db10
+# define index_AVX512F_Usable		FEATURE_INDEX_1
00db10
+# define index_AVX512DQ_Usable		FEATURE_INDEX_1
00db10
+
00db10
+#endif	/* !__ASSEMBLER__ */
00db10
+
00db10
+#endif  /* cpu_features_h */
00db10
Index: glibc-2.17-c758a686/sysdeps/x86/dl-get-cpu-features.c
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/dl-get-cpu-features.c
00db10
@@ -0,0 +1,27 @@
00db10
+/* This file is part of the GNU C Library.
00db10
+   Copyright (C) 2015 Free Software Foundation, Inc.
00db10
+
00db10
+   The GNU C Library is free software; you can redistribute it and/or
00db10
+   modify it under the terms of the GNU Lesser General Public
00db10
+   License as published by the Free Software Foundation; either
00db10
+   version 2.1 of the License, or (at your option) any later version.
00db10
+
00db10
+   The GNU C Library is distributed in the hope that it will be useful,
00db10
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
00db10
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00db10
+   Lesser General Public License for more details.
00db10
+
00db10
+   You should have received a copy of the GNU Lesser General Public
00db10
+   License along with the GNU C Library; if not, see
00db10
+   <http://www.gnu.org/licenses/>.  */
00db10
+
00db10
+
00db10
+#include <ldsodefs.h>
00db10
+
00db10
+#undef __get_cpu_features
00db10
+
00db10
+const struct cpu_features *
00db10
+__get_cpu_features (void)
00db10
+{
00db10
+  return &GLRO(dl_x86_cpu_features);
00db10
+}
00db10
Index: glibc-2.17-c758a686/sysdeps/x86/libc-start.c
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/libc-start.c
00db10
@@ -0,0 +1,41 @@
00db10
+/* Copyright (C) 2015 Free Software Foundation, Inc.
00db10
+   This file is part of the GNU C Library.
00db10
+
00db10
+   The GNU C Library is free software; you can redistribute it and/or
00db10
+   modify it under the terms of the GNU Lesser General Public
00db10
+   License as published by the Free Software Foundation; either
00db10
+   version 2.1 of the License, or (at your option) any later version.
00db10
+
00db10
+   The GNU C Library is distributed in the hope that it will be useful,
00db10
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
00db10
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00db10
+   Lesser General Public License for more details.
00db10
+
00db10
+   You should have received a copy of the GNU Lesser General Public
00db10
+   License along with the GNU C Library; if not, see
00db10
+   <http://www.gnu.org/licenses/>.  */
00db10
+
00db10
+#ifdef SHARED
00db10
+# include <csu/libc-start.c>
00db10
+# else
00db10
+/* The main work is done in the generic function.  */
00db10
+# define LIBC_START_DISABLE_INLINE
00db10
+# define LIBC_START_MAIN generic_start_main
00db10
+# include <csu/libc-start.c>
00db10
+# include <cpu-features.h>
00db10
+# include <cpu-features.c>
00db10
+
00db10
+extern struct cpu_features _dl_x86_cpu_features;
00db10
+
00db10
+int
00db10
+__libc_start_main (int (*main) (int, char **, char ** MAIN_AUXVEC_DECL),
00db10
+		   int argc, char **argv,
00db10
+		   __typeof (main) init,
00db10
+		   void (*fini) (void),
00db10
+		   void (*rtld_fini) (void), void *stack_end)
00db10
+{
00db10
+  init_cpu_features (&_dl_x86_cpu_features);
00db10
+  return generic_start_main (main, argc, argv, init, fini, rtld_fini,
00db10
+			     stack_end);
00db10
+}
00db10
+#endif
00db10
Index: glibc-2.17-c758a686/sysdeps/x86/rtld-global-offsets.sym
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/rtld-global-offsets.sym
00db10
@@ -0,0 +1,7 @@
00db10
+#define SHARED 1
00db10
+
00db10
+#include <ldsodefs.h>
00db10
+
00db10
+#define rtld_global_ro_offsetof(mem) offsetof (struct rtld_global_ro, mem)
00db10
+
00db10
+RTLD_GLOBAL_RO_DL_X86_CPU_FEATURES_OFFSET rtld_global_ro_offsetof (_dl_x86_cpu_features)
00db10
Index: glibc-2.17-c758a686/sysdeps/x86/tst-get-cpu-features-static.c
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/tst-get-cpu-features-static.c
00db10
@@ -0,0 +1 @@
00db10
+#include "tst-get-cpu-features.c"
00db10
Index: glibc-2.17-c758a686/sysdeps/x86/tst-get-cpu-features.c
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86/tst-get-cpu-features.c
00db10
@@ -0,0 +1,31 @@
00db10
+/* Test case for x86 __get_cpu_features interface
00db10
+   Copyright (C) 2015 Free Software Foundation, Inc.
00db10
+   This file is part of the GNU C Library.
00db10
+
00db10
+   The GNU C Library is free software; you can redistribute it and/or
00db10
+   modify it under the terms of the GNU Lesser General Public
00db10
+   License as published by the Free Software Foundation; either
00db10
+   version 2.1 of the License, or (at your option) any later version.
00db10
+
00db10
+   The GNU C Library is distributed in the hope that it will be useful,
00db10
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
00db10
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00db10
+   Lesser General Public License for more details.
00db10
+
00db10
+   You should have received a copy of the GNU Lesser General Public
00db10
+   License along with the GNU C Library; if not, see
00db10
+   <http://www.gnu.org/licenses/>.  */
00db10
+
00db10
+#include <stdlib.h>
00db10
+#include <cpu-features.h>
00db10
+
00db10
+static int
00db10
+do_test (void)
00db10
+{
00db10
+  if (__get_cpu_features ()->kind == arch_kind_unknown)
00db10
+    abort ();
00db10
+  return 0;
00db10
+}
00db10
+
00db10
+#define TEST_FUNCTION do_test ()
00db10
+#include "../../test-skeleton.c"
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/cacheinfo.c
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/cacheinfo.c
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/cacheinfo.c
00db10
@@ -21,40 +21,11 @@
00db10
 #include <stdlib.h>
00db10
 #include <unistd.h>
00db10
 #include <cpuid.h>
00db10
+#include "multiarch/init-arch.h"
00db10
 
00db10
-#ifndef __cpuid_count
00db10
-/* FIXME: Provide __cpuid_count if it isn't defined.  Copied from gcc
00db10
-   4.4.0.  Remove this if gcc 4.4 is the minimum requirement.  */
00db10
-# if defined(__i386__) && defined(__PIC__)
00db10
-/* %ebx may be the PIC register.  */
00db10
-#  define __cpuid_count(level, count, a, b, c, d)		\
00db10
-  __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"			\
00db10
-	   "cpuid\n\t"					\
00db10
-	   "xchg{l}\t{%%}ebx, %1\n\t"			\
00db10
-	   : "=a" (a), "=r" (b), "=c" (c), "=d" (d)	\
00db10
-	   : "0" (level), "2" (count))
00db10
-# else
00db10
-#  define __cpuid_count(level, count, a, b, c, d)		\
00db10
-  __asm__ ("cpuid\n\t"					\
00db10
-	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
00db10
-	   : "0" (level), "2" (count))
00db10
-# endif
00db10
-#endif
00db10
-
00db10
-#ifdef USE_MULTIARCH
00db10
-# include "multiarch/init-arch.h"
00db10
-
00db10
-# define is_intel __cpu_features.kind == arch_kind_intel
00db10
-# define is_amd __cpu_features.kind == arch_kind_amd
00db10
-# define max_cpuid __cpu_features.max_cpuid
00db10
-#else
00db10
-  /* This spells out "GenuineIntel".  */
00db10
-# define is_intel \
00db10
-  ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69
00db10
-  /* This spells out "AuthenticAMD".  */
00db10
-# define is_amd \
00db10
-  ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65
00db10
-#endif
00db10
+#define is_intel GLRO(dl_x86_cpu_features).kind == arch_kind_intel
00db10
+#define is_amd GLRO(dl_x86_cpu_features).kind == arch_kind_amd
00db10
+#define max_cpuid GLRO(dl_x86_cpu_features).max_cpuid
00db10
 
00db10
 static const struct intel_02_cache_info
00db10
 {
00db10
@@ -237,21 +208,8 @@ intel_check_word (int name, unsigned int
00db10
 	      /* Intel reused this value.  For family 15, model 6 it
00db10
 		 specifies the 3rd level cache.  Otherwise the 2nd
00db10
 		 level cache.  */
00db10
-	      unsigned int family;
00db10
-	      unsigned int model;
00db10
-#ifdef USE_MULTIARCH
00db10
-	      family = __cpu_features.family;
00db10
-	      model = __cpu_features.model;
00db10
-#else
00db10
-	      unsigned int eax;
00db10
-	      unsigned int ebx;
00db10
-	      unsigned int ecx;
00db10
-	      unsigned int edx;
00db10
-	      __cpuid (1, eax, ebx, ecx, edx);
00db10
-
00db10
-	      family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
00db10
-	      model = (((eax >>16) & 0xf) << 4) + ((eax >> 4) & 0xf);
00db10
-#endif
00db10
+	      unsigned int family = GLRO(dl_x86_cpu_features).family;
00db10
+	      unsigned int model = GLRO(dl_x86_cpu_features).model;
00db10
 
00db10
 	      if (family == 15 && model == 6)
00db10
 		{
00db10
@@ -478,18 +436,6 @@ long int
00db10
 attribute_hidden
00db10
 __cache_sysconf (int name)
00db10
 {
00db10
-#ifdef USE_MULTIARCH
00db10
-  if (__cpu_features.kind == arch_kind_unknown)
00db10
-    __init_cpu_features ();
00db10
-#else
00db10
-  /* Find out what brand of processor.  */
00db10
-  unsigned int max_cpuid;
00db10
-  unsigned int ebx;
00db10
-  unsigned int ecx;
00db10
-  unsigned int edx;
00db10
-  __cpuid (0, max_cpuid, ebx, ecx, edx);
00db10
-#endif
00db10
-
00db10
   if (is_intel)
00db10
     return handle_intel (name, max_cpuid);
00db10
 
00db10
@@ -525,18 +471,6 @@ long int __x86_64_raw_shared_cache_size
00db10
 int __x86_64_prefetchw attribute_hidden;
00db10
 #endif
00db10
 
00db10
-#ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
00db10
-/* Instructions preferred for memory and string routines.
00db10
-
00db10
-  0: Regular instructions
00db10
-  1: MMX instructions
00db10
-  2: SSE2 instructions
00db10
-  3: SSSE3 instructions
00db10
-
00db10
-  */
00db10
-int __x86_64_preferred_memory_instruction attribute_hidden;
00db10
-#endif
00db10
-
00db10
 
00db10
 static void
00db10
 __attribute__((constructor))
00db10
@@ -553,14 +487,6 @@ init_cacheinfo (void)
00db10
   unsigned int level;
00db10
   unsigned int threads = 0;
00db10
 
00db10
-#ifdef USE_MULTIARCH
00db10
-  if (__cpu_features.kind == arch_kind_unknown)
00db10
-    __init_cpu_features ();
00db10
-#else
00db10
-  int max_cpuid;
00db10
-  __cpuid (0, max_cpuid, ebx, ecx, edx);
00db10
-#endif
00db10
-
00db10
   if (is_intel)
00db10
     {
00db10
       data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
00db10
@@ -576,34 +502,13 @@ init_cacheinfo (void)
00db10
 	  shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
00db10
 	}
00db10
 
00db10
-      unsigned int ebx_1;
00db10
-
00db10
-#ifdef USE_MULTIARCH
00db10
-      eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
00db10
-      ebx_1 = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx;
00db10
-      ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
00db10
-      edx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].edx;
00db10
-#else
00db10
-      __cpuid (1, eax, ebx_1, ecx, edx);
00db10
-#endif
00db10
-
00db10
-      unsigned int family = (eax >> 8) & 0x0f;
00db10
-      unsigned int model = (eax >> 4) & 0x0f;
00db10
-      unsigned int extended_model = (eax >> 12) & 0xf0;
00db10
-
00db10
-#ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
00db10
-      /* Intel prefers SSSE3 instructions for memory/string routines
00db10
-	 if they are available.  */
00db10
-      if ((ecx & 0x200))
00db10
-	__x86_64_preferred_memory_instruction = 3;
00db10
-      else
00db10
-	__x86_64_preferred_memory_instruction = 2;
00db10
-#endif
00db10
-
00db10
       /* Figure out the number of logical threads that share the
00db10
 	 highest cache level.  */
00db10
       if (max_cpuid >= 4)
00db10
 	{
00db10
+	  unsigned int family = GLRO(dl_x86_cpu_features).family;
00db10
+	  unsigned int model = GLRO(dl_x86_cpu_features).model;
00db10
+
00db10
 	  int i = 0;
00db10
 
00db10
 	  /* Query until desired cache level is enumerated.  */
00db10
@@ -655,7 +560,6 @@ init_cacheinfo (void)
00db10
 	  threads += 1;
00db10
 	  if (threads > 2 && level == 2 && family == 6)
00db10
 	    {
00db10
-	      model += extended_model;
00db10
 	      switch (model)
00db10
 		{
00db10
 		case 0x57:
00db10
@@ -678,7 +582,9 @@ init_cacheinfo (void)
00db10
 	intel_bug_no_cache_info:
00db10
 	  /* Assume that all logical threads share the highest cache level.  */
00db10
 
00db10
-	  threads = (ebx_1 >> 16) & 0xff;
00db10
+	  threads
00db10
+	    = ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx
00db10
+		>> 16) & 0xff);
00db10
 	}
00db10
 
00db10
       /* Cap usage of highest cache level to the number of supported
00db10
@@ -693,25 +599,6 @@ init_cacheinfo (void)
00db10
       long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
00db10
       shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
00db10
 
00db10
-#ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION
00db10
-# ifdef USE_MULTIARCH
00db10
-      eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
00db10
-      ebx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx;
00db10
-      ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
00db10
-      edx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].edx;
00db10
-# else
00db10
-      __cpuid (1, eax, ebx, ecx, edx);
00db10
-# endif
00db10
-
00db10
-      /* AMD prefers SSSE3 instructions for memory/string routines
00db10
-	 if they are avaiable, otherwise it prefers integer
00db10
-	 instructions.  */
00db10
-      if ((ecx & 0x200))
00db10
-	__x86_64_preferred_memory_instruction = 3;
00db10
-      else
00db10
-	__x86_64_preferred_memory_instruction = 0;
00db10
-#endif
00db10
-
00db10
       /* Get maximum extended function. */
00db10
       __cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx);
00db10
 
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/dl-machine.h
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/dl-machine.h
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/dl-machine.h
00db10
@@ -26,6 +26,7 @@
00db10
 #include <sysdep.h>
00db10
 #include <tls.h>
00db10
 #include <dl-tlsdesc.h>
00db10
+#include <cpu-features.c>
00db10
 
00db10
 /* Return nonzero iff ELF header is compatible with the running host.  */
00db10
 static inline int __attribute__ ((unused))
00db10
@@ -200,6 +201,8 @@ dl_platform_init (void)
00db10
   if (GLRO(dl_platform) != NULL && *GLRO(dl_platform) == '\0')
00db10
     /* Avoid an empty string which would disturb us.  */
00db10
     GLRO(dl_platform) = NULL;
00db10
+
00db10
+  init_cpu_features (&GLRO(dl_x86_cpu_features));
00db10
 }
00db10
 
00db10
 static inline ElfW(Addr)
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/dl-procinfo.c
00db10
===================================================================
00db10
--- /dev/null
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/dl-procinfo.c
00db10
@@ -0,0 +1,57 @@
00db10
+/* Data for x86-64 version of processor capability information.
00db10
+   Copyright (C) 2015 Free Software Foundation, Inc.
00db10
+   This file is part of the GNU C Library.
00db10
+
00db10
+   The GNU C Library is free software; you can redistribute it and/or
00db10
+   modify it under the terms of the GNU Lesser General Public
00db10
+   License as published by the Free Software Foundation; either
00db10
+   version 2.1 of the License, or (at your option) any later version.
00db10
+
00db10
+   The GNU C Library is distributed in the hope that it will be useful,
00db10
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
00db10
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00db10
+   Lesser General Public License for more details.
00db10
+
00db10
+   You should have received a copy of the GNU Lesser General Public
00db10
+   License along with the GNU C Library; if not, see
00db10
+   <http://www.gnu.org/licenses/>.  */
00db10
+
00db10
+/* If anything should be added here check whether the size of each string
00db10
+   is still ok with the given array size.
00db10
+
00db10
+   All the #ifdefs in the definitions are quite irritating but
00db10
+   necessary if we want to avoid duplicating the information.  There
00db10
+   are three different modes:
00db10
+
00db10
+   - PROCINFO_DECL is defined.  This means we are only interested in
00db10
+     declarations.
00db10
+
00db10
+   - PROCINFO_DECL is not defined:
00db10
+
00db10
+     + if SHARED is defined the file is included in an array
00db10
+       initializer.  The .element = { ... } syntax is needed.
00db10
+
00db10
+     + if SHARED is not defined a normal array initialization is
00db10
+       needed.
00db10
+  */
00db10
+
00db10
+#ifndef PROCINFO_CLASS
00db10
+# define PROCINFO_CLASS
00db10
+#endif
00db10
+
00db10
+#if !defined PROCINFO_DECL && defined SHARED
00db10
+  ._dl_x86_cpu_features
00db10
+#else
00db10
+PROCINFO_CLASS struct cpu_features _dl_x86_cpu_features
00db10
+#endif
00db10
+#ifndef PROCINFO_DECL
00db10
+= { }
00db10
+#endif
00db10
+#if !defined SHARED || defined PROCINFO_DECL
00db10
+;
00db10
+#else
00db10
+,
00db10
+#endif
00db10
+
00db10
+#undef PROCINFO_DECL
00db10
+#undef PROCINFO_CLASS
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/ldsodefs.h
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/ldsodefs.h
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/ldsodefs.h
00db10
@@ -20,6 +20,7 @@
00db10
 #define	_X86_64_LDSODEFS_H	1
00db10
 
00db10
 #include <elf.h>
00db10
+#include <cpu-features.h>
00db10
 
00db10
 struct La_x86_64_regs;
00db10
 struct La_x86_64_retval;
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/Makefile
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/Makefile
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/Makefile
00db10
@@ -1,5 +1,4 @@
00db10
 ifeq ($(subdir),csu)
00db10
-aux += init-arch
00db10
 tests += test-multiarch
00db10
 gen-as-const-headers += ifunc-defines.sym
00db10
 endif
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/Versions
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/Versions
00db10
+++ /dev/null
00db10
@@ -1,5 +0,0 @@
00db10
-libc {
00db10
-  GLIBC_PRIVATE {
00db10
-    __get_cpu_features;
00db10
-  }
00db10
-}
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/cacheinfo.c
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/cacheinfo.c
00db10
+++ /dev/null
00db10
@@ -1,2 +0,0 @@
00db10
-#define DISABLE_PREFERRED_MEMORY_INSTRUCTION
00db10
-#include "../cacheinfo.c"
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/ifunc-defines.sym
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/ifunc-defines.sym
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/ifunc-defines.sym
00db10
@@ -4,7 +4,6 @@
00db10
 --
00db10
 
00db10
 CPU_FEATURES_SIZE	sizeof (struct cpu_features)
00db10
-KIND_OFFSET		offsetof (struct cpu_features, kind)
00db10
 CPUID_OFFSET		offsetof (struct cpu_features, cpuid)
00db10
 CPUID_SIZE		sizeof (struct cpuid_registers)
00db10
 CPUID_EAX_OFFSET	offsetof (struct cpuid_registers, eax)
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/init-arch.c
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/init-arch.c
00db10
+++ /dev/null
00db10
@@ -1,183 +0,0 @@
00db10
-/* Initialize CPU feature data.
00db10
-   This file is part of the GNU C Library.
00db10
-   Copyright (C) 2008-2012 Free Software Foundation, Inc.
00db10
-   Contributed by Ulrich Drepper <drepper@redhat.com>.
00db10
-
00db10
-   The GNU C Library is free software; you can redistribute it and/or
00db10
-   modify it under the terms of the GNU Lesser General Public
00db10
-   License as published by the Free Software Foundation; either
00db10
-   version 2.1 of the License, or (at your option) any later version.
00db10
-
00db10
-   The GNU C Library is distributed in the hope that it will be useful,
00db10
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
00db10
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00db10
-   Lesser General Public License for more details.
00db10
-
00db10
-   You should have received a copy of the GNU Lesser General Public
00db10
-   License along with the GNU C Library; if not, see
00db10
-   <http://www.gnu.org/licenses/>.  */
00db10
-
00db10
-#include <atomic.h>
00db10
-#include <cpuid.h>
00db10
-#include "init-arch.h"
00db10
-
00db10
-
00db10
-struct cpu_features __cpu_features attribute_hidden;
00db10
-
00db10
-
00db10
-static void
00db10
-get_common_indeces (unsigned int *family, unsigned int *model)
00db10
-{
00db10
-  __cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
00db10
-	   __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,
00db10
-	   __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx,
00db10
-	   __cpu_features.cpuid[COMMON_CPUID_INDEX_1].edx);
00db10
-
00db10
-  unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
00db10
-  *family = (eax >> 8) & 0x0f;
00db10
-  *model = (eax >> 4) & 0x0f;
00db10
-}
00db10
-
00db10
-
00db10
-void
00db10
-__init_cpu_features (void)
00db10
-{
00db10
-  unsigned int ebx;
00db10
-  unsigned int ecx;
00db10
-  unsigned int edx;
00db10
-  unsigned int family = 0;
00db10
-  unsigned int model = 0;
00db10
-  enum cpu_features_kind kind;
00db10
-
00db10
-  __cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);
00db10
-
00db10
-  /* This spells out "GenuineIntel".  */
00db10
-  if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
00db10
-    {
00db10
-      kind = arch_kind_intel;
00db10
-
00db10
-      get_common_indeces (&family, &model);
00db10
-
00db10
-      /* Intel processors prefer SSE instruction for memory/string
00db10
-	 routines if they are available.  */
00db10
-      __cpu_features.feature[index_Prefer_SSE_for_memop]
00db10
-	|= bit_Prefer_SSE_for_memop;
00db10
-
00db10
-      unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
00db10
-      unsigned int extended_family = (eax >> 20) & 0xff;
00db10
-      unsigned int extended_model = (eax >> 12) & 0xf0;
00db10
-      if (family == 0x0f)
00db10
-	{
00db10
-	  family += extended_family;
00db10
-	  model += extended_model;
00db10
-	}
00db10
-      else if (family == 0x06)
00db10
-	{
00db10
-	  ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
00db10
-	  model += extended_model;
00db10
-	  switch (model)
00db10
-	    {
00db10
-	    case 0x1c:
00db10
-	    case 0x26:
00db10
-	      /* BSF is slow on Atom.  */
00db10
-	      __cpu_features.feature[index_Slow_BSF] |= bit_Slow_BSF;
00db10
-	      break;
00db10
-
00db10
-	    default:
00db10
-	      /* Unknown family 0x06 processors.  Assuming this is one
00db10
-		 of Core i3/i5/i7 processors if AVX is available.  */
00db10
-	      if ((ecx & bit_AVX) == 0)
00db10
-		break;
00db10
-
00db10
-	    case 0x1a:
00db10
-	    case 0x1e:
00db10
-	    case 0x1f:
00db10
-	    case 0x25:
00db10
-	    case 0x2c:
00db10
-	    case 0x2e:
00db10
-	    case 0x2f:
00db10
-	      /* Rep string instructions, copy backward, unaligned loads
00db10
-		 and pminub are fast on Intel Core i3, i5 and i7.  */
00db10
-#if index_Fast_Rep_String != index_Fast_Copy_Backward
00db10
-# error index_Fast_Rep_String != index_Fast_Copy_Backward
00db10
-#endif
00db10
-#if index_Fast_Rep_String != index_Fast_Unaligned_Load
00db10
-# error index_Fast_Rep_String != index_Fast_Unaligned_Load
00db10
-#endif
00db10
-#if index_Fast_Rep_String != index_Prefer_PMINUB_for_stringop
00db10
-# error index_Fast_Rep_String != index_Prefer_PMINUB_for_stringop
00db10
-#endif
00db10
-	      __cpu_features.feature[index_Fast_Rep_String]
00db10
-		|= (bit_Fast_Rep_String
00db10
-		    | bit_Fast_Copy_Backward
00db10
-		    | bit_Fast_Unaligned_Load
00db10
-		    | bit_Prefer_PMINUB_for_stringop);
00db10
-	      break;
00db10
-	    }
00db10
-	}
00db10
-    }
00db10
-  /* This spells out "AuthenticAMD".  */
00db10
-  else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
00db10
-    {
00db10
-      kind = arch_kind_amd;
00db10
-
00db10
-      get_common_indeces (&family, &model);
00db10
-
00db10
-      ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
00db10
-
00db10
-      /* AMD processors prefer SSE instructions for memory/string routines
00db10
-	 if they are available, otherwise they prefer integer instructions.  */
00db10
-      if ((ecx & 0x200))
00db10
-	__cpu_features.feature[index_Prefer_SSE_for_memop]
00db10
-	  |= bit_Prefer_SSE_for_memop;
00db10
-
00db10
-      unsigned int eax;
00db10
-      __cpuid (0x80000000, eax, ebx, ecx, edx);
00db10
-      if (eax >= 0x80000001)
00db10
-	__cpuid (0x80000001,
00db10
-		 __cpu_features.cpuid[COMMON_CPUID_INDEX_80000001].eax,
00db10
-		 __cpu_features.cpuid[COMMON_CPUID_INDEX_80000001].ebx,
00db10
-		 __cpu_features.cpuid[COMMON_CPUID_INDEX_80000001].ecx,
00db10
-		 __cpu_features.cpuid[COMMON_CPUID_INDEX_80000001].edx);
00db10
-    }
00db10
-  else
00db10
-    kind = arch_kind_other;
00db10
-
00db10
-  /* Can we call xgetbv?  */
00db10
-  if (CPUID_OSXSAVE)
00db10
-    {
00db10
-      unsigned int xcrlow;
00db10
-      unsigned int xcrhigh;
00db10
-      asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
00db10
-      /* Is YMM and XMM state usable?  */
00db10
-      if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
00db10
-	  (bit_YMM_state | bit_XMM_state))
00db10
-	{
00db10
-	  /* Determine if AVX is usable.  */
00db10
-	  if (CPUID_AVX)
00db10
-	    __cpu_features.feature[index_AVX_Usable] |= bit_AVX_Usable;
00db10
-	  /* Determine if FMA is usable.  */
00db10
-	  if (CPUID_FMA)
00db10
-	    __cpu_features.feature[index_FMA_Usable] |= bit_FMA_Usable;
00db10
-	  /* Determine if FMA4 is usable.  */
00db10
-	  if (CPUID_FMA4)
00db10
-	    __cpu_features.feature[index_FMA4_Usable] |= bit_FMA4_Usable;
00db10
-	}
00db10
-    }
00db10
-
00db10
-  __cpu_features.family = family;
00db10
-  __cpu_features.model = model;
00db10
-  atomic_write_barrier ();
00db10
-  __cpu_features.kind = kind;
00db10
-}
00db10
-
00db10
-#undef __get_cpu_features
00db10
-
00db10
-const struct cpu_features *
00db10
-__get_cpu_features (void)
00db10
-{
00db10
-  if (__cpu_features.kind == arch_kind_unknown)
00db10
-    __init_cpu_features ();
00db10
-
00db10
-  return &__cpu_features;
00db10
-}
00db10
Index: glibc-2.17-c758a686/sysdeps/x86_64/multiarch/init-arch.h
00db10
===================================================================
00db10
--- glibc-2.17-c758a686.orig/sysdeps/x86_64/multiarch/init-arch.h
00db10
+++ glibc-2.17-c758a686/sysdeps/x86_64/multiarch/init-arch.h
00db10
@@ -15,183 +15,8 @@
00db10
    License along with the GNU C Library; if not, see
00db10
    <http://www.gnu.org/licenses/>.  */
00db10
 
00db10
-#define bit_Fast_Rep_String		(1 << 0)
00db10
-#define bit_Fast_Copy_Backward		(1 << 1)
00db10
-#define bit_Slow_BSF			(1 << 2)
00db10
-#define bit_Prefer_SSE_for_memop	(1 << 3)
00db10
-#define bit_Fast_Unaligned_Load		(1 << 4)
00db10
-#define bit_Prefer_PMINUB_for_stringop	(1 << 5)
00db10
-#define bit_AVX_Usable			(1 << 6)
00db10
-#define bit_FMA_Usable			(1 << 7)
00db10
-#define bit_FMA4_Usable			(1 << 8)
00db10
-
00db10
-/* CPUID Feature flags.  */
00db10
-#define bit_SSE2	(1 << 26)
00db10
-#define bit_SSSE3	(1 << 9)
00db10
-#define bit_SSE4_1	(1 << 19)
00db10
-#define bit_SSE4_2	(1 << 20)
00db10
-#define bit_OSXSAVE	(1 << 27)
00db10
-#define bit_AVX		(1 << 28)
00db10
-#define bit_POPCOUNT	(1 << 23)
00db10
-#define bit_FMA		(1 << 12)
00db10
-#define bit_FMA4	(1 << 16)
00db10
-
00db10
-/* XCR0 Feature flags.  */
00db10
-#define bit_XMM_state  (1 << 1)
00db10
-#define bit_YMM_state  (2 << 1)
00db10
-
00db10
-#ifdef	__ASSEMBLER__
00db10
-
00db10
-# include <ifunc-defines.h>
00db10
-
00db10
-# define index_SSE2	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
00db10
-# define index_SSSE3	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
-# define index_SSE4_1	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
-# define index_SSE4_2	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
-# define index_AVX	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
00db10
-
00db10
-# define index_Fast_Rep_String		FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_Fast_Copy_Backward	FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_Slow_BSF			FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_Prefer_SSE_for_memop	FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_Fast_Unaligned_Load	FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_Prefer_PMINUB_for_stringop FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_AVX_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_FMA_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
-# define index_FMA4_Usable		FEATURE_INDEX_1*FEATURE_SIZE
00db10
-
00db10
-#else	/* __ASSEMBLER__ */
00db10
-
00db10
-# include <sys/param.h>
00db10
-# include <sys/types.h>
00db10
-# include <sysdep.h>
00db10
-# include <stdbool.h>
00db10
-
00db10
-/* Ugly hack to make it possible to select a strstr and strcasestr
00db10
-   implementation that avoids using the stack for 16-byte aligned
00db10
-   SSE temporaries.  Doing so makes it possible to call the functions
00db10
-   with a stack that's not 16-byte aligned as can happen, for example,
00db10
-   as a result of compiling the functions' callers with the GCC
00db10
-   -mpreferred-stack-boubdary=2 or =3 option, or with the ICC
00db10
-   -falign-stack=assume-4-byte option.  See rhbz 1150282 for details.
00db10
-
00db10
-   The ifunc selector uses the unaligned version by default if this
00db10
-   file exists and is accessible.  */
00db10
-# define ENABLE_STRSTR_UNALIGNED_PATHNAME \
00db10
-    "/etc/sysconfig/64bit_strstr_via_64bit_strstr_sse2_unaligned"
00db10
-
00db10
-static bool __attribute__ ((unused))
00db10
-use_unaligned_strstr (void)
00db10
-{
00db10
-  struct stat unaligned_strstr_etc_sysconfig_file;
00db10
-
00db10
-  /* TLS may not have been set up yet, so avoid using stat since it tries to
00db10
-     set errno.  */
00db10
-  return INTERNAL_SYSCALL (stat, , 2,
00db10
-                           ENABLE_STRSTR_UNALIGNED_PATHNAME,
00db10
-                           &unaligned_strstr_etc_sysconfig_file) == 0;
00db10
-}
00db10
-
00db10
-enum
00db10
-  {
00db10
-    COMMON_CPUID_INDEX_1 = 0,
00db10
-    COMMON_CPUID_INDEX_80000001,	/* for AMD */
00db10
-    /* Keep the following line at the end.  */
00db10
-    COMMON_CPUID_INDEX_MAX
00db10
-  };
00db10
-
00db10
-enum
00db10
-  {
00db10
-    FEATURE_INDEX_1 = 0,
00db10
-    /* Keep the following line at the end.  */
00db10
-    FEATURE_INDEX_MAX
00db10
-  };
00db10
-
00db10
-extern struct cpu_features
00db10
-{
00db10
-  enum cpu_features_kind
00db10
-    {
00db10
-      arch_kind_unknown = 0,
00db10
-      arch_kind_intel,
00db10
-      arch_kind_amd,
00db10
-      arch_kind_other
00db10
-    } kind;
00db10
-  int max_cpuid;
00db10
-  struct cpuid_registers
00db10
-  {
00db10
-    unsigned int eax;
00db10
-    unsigned int ebx;
00db10
-    unsigned int ecx;
00db10
-    unsigned int edx;
00db10
-  } cpuid[COMMON_CPUID_INDEX_MAX];
00db10
-  unsigned int family;
00db10
-  unsigned int model;
00db10
-  unsigned int feature[FEATURE_INDEX_MAX];
00db10
-} __cpu_features attribute_hidden;
00db10
-
00db10
-
00db10
-extern void __init_cpu_features (void) attribute_hidden;
00db10
-# define INIT_ARCH() \
00db10
-  do							\
00db10
-    if (__cpu_features.kind == arch_kind_unknown)	\
00db10
-      __init_cpu_features ();				\
00db10
-  while (0)
00db10
-
00db10
-/* Used from outside libc.so to get access to the CPU features structure.  */
00db10
-extern const struct cpu_features *__get_cpu_features (void)
00db10
-     __attribute__ ((const));
00db10
-
00db10
-# if IS_IN (libc)
00db10
-#  define __get_cpu_features()	(&__cpu_features)
00db10
-# endif
00db10
-
00db10
-# define HAS_CPU_FEATURE(idx, reg, bit) \
00db10
-  ((__get_cpu_features ()->cpuid[idx].reg & (bit)) != 0)
00db10
-
00db10
-/* Following are the feature tests used throughout libc.  */
00db10
-
00db10
-/* CPUID_* evaluates to true if the feature flag is enabled.
00db10
-   We always use &__cpu_features because the HAS_CPUID_* macros
00db10
-   are called only within __init_cpu_features, where we can't
00db10
-   call __get_cpu_features without infinite recursion.  */
00db10
-# define HAS_CPUID_FLAG(idx, reg, bit) \
00db10
-  (((&__cpu_features)->cpuid[idx].reg & (bit)) != 0)
00db10
-
00db10
-# define CPUID_OSXSAVE \
00db10
-  HAS_CPUID_FLAG (COMMON_CPUID_INDEX_1, ecx, bit_OSXSAVE)
00db10
-# define CPUID_AVX \
00db10
-  HAS_CPUID_FLAG (COMMON_CPUID_INDEX_1, ecx, bit_AVX)
00db10
-# define CPUID_FMA \
00db10
-  HAS_CPUID_FLAG (COMMON_CPUID_INDEX_1, ecx, bit_FMA)
00db10
-# define CPUID_FMA4 \
00db10
-  HAS_CPUID_FLAG (COMMON_CPUID_INDEX_80000001, ecx, bit_FMA4)
00db10
-
00db10
-/* HAS_* evaluates to true if we may use the feature at runtime.  */
00db10
-# define HAS_SSE2	HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, edx, bit_SSE2)
00db10
-# define HAS_POPCOUNT	HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, bit_POPCOUNT)
00db10
-# define HAS_SSSE3	HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, bit_SSSE3)
00db10
-# define HAS_SSE4_1	HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, bit_SSE4_1)
00db10
-# define HAS_SSE4_2	HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, bit_SSE4_2)
00db10
-
00db10
-# define index_Fast_Rep_String		FEATURE_INDEX_1
00db10
-# define index_Fast_Copy_Backward	FEATURE_INDEX_1
00db10
-# define index_Slow_BSF			FEATURE_INDEX_1
00db10
-# define index_Prefer_SSE_for_memop	FEATURE_INDEX_1
00db10
-# define index_Fast_Unaligned_Load	FEATURE_INDEX_1
00db10
-# define index_AVX_Usable		FEATURE_INDEX_1
00db10
-# define index_FMA_Usable		FEATURE_INDEX_1
00db10
-# define index_FMA4_Usable		FEATURE_INDEX_1
00db10
-
00db10
-# define HAS_ARCH_FEATURE(name) \
00db10
-  ((__get_cpu_features ()->feature[index_##name] & (bit_##name)) != 0)
00db10
-
00db10
-# define HAS_FAST_REP_STRING		HAS_ARCH_FEATURE (Fast_Rep_String)
00db10
-# define HAS_FAST_COPY_BACKWARD		HAS_ARCH_FEATURE (Fast_Copy_Backward)
00db10
-# define HAS_SLOW_BSF			HAS_ARCH_FEATURE (Slow_BSF)
00db10
-# define HAS_PREFER_SSE_FOR_MEMOP	HAS_ARCH_FEATURE (Prefer_SSE_for_memop)
00db10
-# define HAS_FAST_UNALIGNED_LOAD	HAS_ARCH_FEATURE (Fast_Unaligned_Load)
00db10
-# define HAS_AVX			HAS_ARCH_FEATURE (AVX_Usable)
00db10
-# define HAS_FMA			HAS_ARCH_FEATURE (FMA_Usable)
00db10
-# define HAS_FMA4			HAS_ARCH_FEATURE (FMA4_Usable)
00db10
-
00db10
-#endif	/* __ASSEMBLER__ */
00db10
+#ifdef  __ASSEMBLER__
00db10
+# include <cpu-features.h>
00db10
+#else
00db10
+# include <ldsodefs.h>
00db10
+#endif