Blame SOURCES/gdb-rhbz2019936-gdbserver-avx512-m32.patch

f31ff6
From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
f31ff6
From: Tom de Vries <tdevries@suse.de>
f31ff6
Date: Mon, 6 Dec 2021 15:39:03 -0500
f31ff6
Subject: gdb-rhbz2019936-gdbserver-avx512-m32.patch
f31ff6
f31ff6
;; Backport "Fix avx512 -m32 support in gdbserver"
f31ff6
;; (Tom de Vries, RHBZ 2019936)
f31ff6
f31ff6
    PR27257 reports a problem that can be reproduced as follows:
f31ff6
    - use x86_64 machine with avx512 support
f31ff6
    - compile a hello world with -m32 to a.out
f31ff6
    - start a gdbserver session with a.out
f31ff6
    - use gdb to connect to the gdbserver session
f31ff6
f31ff6
    This makes us run into:
f31ff6
    ...
f31ff6
    Listening on port 2346
f31ff6
    Remote debugging from host ::1, port 34940
f31ff6
    src/gdbserver/regcache.cc:257: \
f31ff6
      A problem internal to GDBserver has been detected.
f31ff6
    Unknown register zmm16h requested
f31ff6
    ...
f31ff6
f31ff6
    The problem is that i387_xsave_to_cache in gdbserver/i387-fp.cc can't find a
f31ff6
    register zmm16h in the register cache.
f31ff6
f31ff6
    To understand how this happens, first some background.
f31ff6
f31ff6
    SSE has 16 128-bit wide xmm registers.
f31ff6
f31ff6
    AVX extends the SSE registers set as follows:
f31ff6
    - it extends the 16 existing 128-bit wide xmm registers to 256-bit wide ymm
f31ff6
      registers.
f31ff6
f31ff6
    AVX512 extends the AVX register set as follows:
f31ff6
    - it extends the 16 existing 256-bit wide ymm registers to 512-bit wide zmm
f31ff6
      registers.
f31ff6
    - it adds 16 additional 512-bit wide zmm registers (with corresponding ymm and
f31ff6
      xmm subregisters added as well)
f31ff6
f31ff6
    However, in 32-bit mode, there are only 8 xmm/ymm/zmm registers.
f31ff6
f31ff6
    The problem we're running into is that gdbserver/i387-fp.cc uses these
f31ff6
    constants to describe the size of the register file:
f31ff6
    ...
f31ff6
    static const int num_avx512_zmmh_low_registers = 16;
f31ff6
    static const int num_avx512_zmmh_high_registers = 16;
f31ff6
    static const int num_avx512_ymmh_registers = 16;
f31ff6
    static const int num_avx512_xmm_registers = 16;
f31ff6
    ...
f31ff6
    which are all incorrect for the 32-bit case.
f31ff6
f31ff6
    Fix this by replacing the constants with variables that have the appropriate
f31ff6
    values in 64-bit and 32-bit mode.
f31ff6
f31ff6
    Tested on x86_64-linux with native and unix/-m32.
f31ff6
f31ff6
diff --git a/gdbserver/i387-fp.cc b/gdbserver/i387-fp.cc
f31ff6
--- a/gdbserver/i387-fp.cc
f31ff6
+++ b/gdbserver/i387-fp.cc
f31ff6
@@ -23,10 +23,6 @@
f31ff6
 static const int num_mpx_bnd_registers = 4;
f31ff6
 static const int num_mpx_cfg_registers = 2;
f31ff6
 static const int num_avx512_k_registers = 8;
f31ff6
-static const int num_avx512_zmmh_low_registers = 16;
f31ff6
-static const int num_avx512_zmmh_high_registers = 16;
f31ff6
-static const int num_avx512_ymmh_registers = 16;
f31ff6
-static const int num_avx512_xmm_registers = 16;
f31ff6
 static const int num_pkeys_registers = 1;
f31ff6
 
f31ff6
 /* Note: These functions preserve the reserved bits in control registers.
f31ff6
@@ -256,14 +252,22 @@ void
f31ff6
 i387_cache_to_xsave (struct regcache *regcache, void *buf)
f31ff6
 {
f31ff6
   struct i387_xsave *fp = (struct i387_xsave *) buf;
f31ff6
+  bool amd64 = register_size (regcache->tdesc, 0) == 8;
f31ff6
   int i;
f31ff6
   unsigned long val, val2;
f31ff6
   unsigned long long xstate_bv = 0;
f31ff6
   unsigned long long clear_bv = 0;
f31ff6
   char raw[64];
f31ff6
   char *p;
f31ff6
+
f31ff6
   /* Amd64 has 16 xmm regs; I386 has 8 xmm regs.  */
f31ff6
-  int num_xmm_registers = register_size (regcache->tdesc, 0) == 8 ? 16 : 8;
f31ff6
+  int num_xmm_registers = amd64 ? 16 : 8;
f31ff6
+  /* AVX512 extends the existing xmm/ymm registers to a wider mode: zmm.  */
f31ff6
+  int num_avx512_zmmh_low_registers = num_xmm_registers;
f31ff6
+  /* AVX512 adds 16 extra regs in Amd64 mode, but none in I386 mode.*/
f31ff6
+  int num_avx512_zmmh_high_registers = amd64 ? 16 : 0;
f31ff6
+  int num_avx512_ymmh_registers = amd64 ? 16 : 0;
f31ff6
+  int num_avx512_xmm_registers = amd64 ? 16 : 0;
f31ff6
 
f31ff6
   /* The supported bits in `xstat_bv' are 8 bytes.  Clear part in
f31ff6
      vector registers if its bit in xstat_bv is zero.  */
f31ff6
@@ -452,7 +456,9 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf)
f31ff6
   /* Check if any of ZMM16H-ZMM31H registers are changed.  */
f31ff6
   if ((x86_xcr0 & X86_XSTATE_ZMM))
f31ff6
     {
f31ff6
-      int zmm16h_regnum = find_regno (regcache->tdesc, "zmm16h");
f31ff6
+      int zmm16h_regnum = (num_avx512_zmmh_high_registers == 0
f31ff6
+			   ? -1
f31ff6
+			   : find_regno (regcache->tdesc, "zmm16h"));
f31ff6
 
f31ff6
       for (i = 0; i < num_avx512_zmmh_high_registers; i++)
f31ff6
 	{
f31ff6
@@ -469,7 +475,9 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf)
f31ff6
   /* Check if any XMM_AVX512 registers are changed.  */
f31ff6
   if ((x86_xcr0 & X86_XSTATE_ZMM))
f31ff6
     {
f31ff6
-      int xmm_avx512_regnum = find_regno (regcache->tdesc, "xmm16");
f31ff6
+      int xmm_avx512_regnum = (num_avx512_xmm_registers == 0
f31ff6
+			       ? -1
f31ff6
+			       : find_regno (regcache->tdesc, "xmm16"));
f31ff6
 
f31ff6
       for (i = 0; i < num_avx512_xmm_registers; i++)
f31ff6
 	{
f31ff6
@@ -486,7 +494,9 @@ i387_cache_to_xsave (struct regcache *regcache, void *buf)
f31ff6
   /* Check if any YMMH_AVX512 registers are changed.  */
f31ff6
   if ((x86_xcr0 & X86_XSTATE_ZMM))
f31ff6
     {
f31ff6
-      int ymmh_avx512_regnum = find_regno (regcache->tdesc, "ymm16h");
f31ff6
+      int ymmh_avx512_regnum = (num_avx512_ymmh_registers == 0
f31ff6
+				? -1
f31ff6
+				: find_regno (regcache->tdesc, "ymm16h"));
f31ff6
 
f31ff6
       for (i = 0; i < num_avx512_ymmh_registers; i++)
f31ff6
 	{
f31ff6
@@ -710,12 +720,20 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf)
f31ff6
 {
f31ff6
   struct i387_xsave *fp = (struct i387_xsave *) buf;
f31ff6
   struct i387_fxsave *fxp = (struct i387_fxsave *) buf;
f31ff6
+  bool amd64 = register_size (regcache->tdesc, 0) == 8;
f31ff6
   int i, top;
f31ff6
   unsigned long val;
f31ff6
   unsigned long long clear_bv;
f31ff6
   gdb_byte *p;
f31ff6
-  /* Amd64 has 16 xmm regs; I386 has 8 xmm regs.  */
f31ff6
-  int num_xmm_registers = register_size (regcache->tdesc, 0) == 8 ? 16 : 8;
f31ff6
+
f31ff6
+   /* Amd64 has 16 xmm regs; I386 has 8 xmm regs.  */
f31ff6
+  int num_xmm_registers = amd64 ? 16 : 8;
f31ff6
+  /* AVX512 extends the existing xmm/ymm registers to a wider mode: zmm.  */
f31ff6
+  int num_avx512_zmmh_low_registers = num_xmm_registers;
f31ff6
+  /* AVX512 adds 16 extra regs in Amd64 mode, but none in I386 mode.*/
f31ff6
+  int num_avx512_zmmh_high_registers = amd64 ? 16 : 0;
f31ff6
+  int num_avx512_ymmh_registers = amd64 ? 16 : 0;
f31ff6
+  int num_avx512_xmm_registers = amd64 ? 16 : 0;
f31ff6
 
f31ff6
   /* The supported bits in `xstat_bv' are 8 bytes.  Clear part in
f31ff6
      vector registers if its bit in xstat_bv is zero.  */
f31ff6
@@ -845,9 +863,15 @@ i387_xsave_to_cache (struct regcache *regcache, const void *buf)
f31ff6
 
f31ff6
   if ((x86_xcr0 & X86_XSTATE_ZMM) != 0)
f31ff6
     {
f31ff6
-      int zmm16h_regnum = find_regno (regcache->tdesc, "zmm16h");
f31ff6
-      int ymm16h_regnum = find_regno (regcache->tdesc, "ymm16h");
f31ff6
-      int xmm16_regnum = find_regno (regcache->tdesc, "xmm16");
f31ff6
+      int zmm16h_regnum = (num_avx512_zmmh_high_registers == 0
f31ff6
+			   ? -1
f31ff6
+			   : find_regno (regcache->tdesc, "zmm16h"));
f31ff6
+      int ymm16h_regnum = (num_avx512_ymmh_registers == 0
f31ff6
+			   ? -1
f31ff6
+			   : find_regno (regcache->tdesc, "ymm16h"));
f31ff6
+      int xmm16_regnum = (num_avx512_xmm_registers == 0
f31ff6
+			  ? -1
f31ff6
+			  : find_regno (regcache->tdesc, "xmm16"));
f31ff6
 
f31ff6
       if ((clear_bv & X86_XSTATE_ZMM) != 0)
f31ff6
 	{