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From 21367ae2b8ebbe5173cbed22dfa51680a3fe48d2 Mon Sep 17 00:00:00 2001
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From: Ido Schimmel <idosch@nvidia.com>
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Date: Tue, 23 Nov 2021 19:40:58 +0200
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Subject: [PATCH 30/35] cmis: Initialize Banked Page 11h in memory map
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Banked Page 11h stores, among other things, lane-specific flags and
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monitors that are going to be parsed and displayed in subsequent
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patches.
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Request it via the 'MODULE_EEPROM_GET' netlink message and initialize it
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in the memory map.
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Only initialize it in supported Banks.
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Signed-off-by: Ido Schimmel <idosch@nvidia.com>
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---
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cmis.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
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cmis.h | 7 +++++++
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2 files changed, 54 insertions(+), 2 deletions(-)
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diff --git a/cmis.c b/cmis.c
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index 55b9d1b959cd..83ced4d253ae 100644
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--- a/cmis.c
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+++ b/cmis.c
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@@ -15,9 +15,17 @@
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#include "cmis.h"
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#include "netlink/extapi.h"
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+/* The maximum number of supported Banks. Relevant documents:
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+ * [1] CMIS Rev. 5, page. 128, section 8.4.4, Table 8-40
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+ */
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+#define CMIS_MAX_BANKS 4
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+
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+/* We are not parsing further than Page 11h. */
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+#define CMIS_MAX_PAGES 18
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+
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struct cmis_memory_map {
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const __u8 *lower_memory;
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- const __u8 *upper_memory[1][3]; /* Bank, Page */
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+ const __u8 *upper_memory[CMIS_MAX_BANKS][CMIS_MAX_PAGES];
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#define page_00h upper_memory[0x0][0x0]
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#define page_01h upper_memory[0x0][0x1]
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#define page_02h upper_memory[0x0][0x2]
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@@ -399,12 +407,33 @@ static void cmis_request_init(struct ethtool_module_eeprom *request, u8 bank,
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request->data = NULL;
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}
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+static int cmis_num_banks_get(const struct cmis_memory_map *map,
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+ int *p_num_banks)
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+{
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+ switch (map->page_01h[CMIS_PAGES_ADVER_OFFSET] &
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+ CMIS_BANKS_SUPPORTED_MASK) {
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+ case CMIS_BANK_0_SUPPORTED:
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+ *p_num_banks = 1;
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+ break;
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+ case CMIS_BANK_0_1_SUPPORTED:
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+ *p_num_banks = 2;
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+ break;
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+ case CMIS_BANK_0_3_SUPPORTED:
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+ *p_num_banks = 4;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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static int
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cmis_memory_map_init_pages(struct cmd_context *ctx,
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struct cmis_memory_map *map)
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{
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struct ethtool_module_eeprom request;
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- int ret;
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+ int num_banks, i, ret;
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/* Lower Memory and Page 00h are always present.
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*
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@@ -443,6 +472,22 @@ cmis_memory_map_init_pages(struct cmd_context *ctx,
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return ret;
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map->page_02h = request.data - CMIS_PAGE_SIZE;
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+ /* Bank 0 of Page 11h provides lane-specific registers for the first 8
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+ * lanes, and each additional Banks provides support for an additional
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+ * 8 lanes. Only initialize supported Banks.
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+ */
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+ ret = cmis_num_banks_get(map, &num_banks);
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+ if (ret < 0)
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+ return ret;
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+
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+ for (i = 0; i < num_banks; i++) {
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+ cmis_request_init(&request, i, 0x11, CMIS_PAGE_SIZE);
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+ ret = nl_get_eeprom_page(ctx, &request);
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+ if (ret < 0)
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+ return ret;
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+ map->upper_memory[i][0x11] = request.data - CMIS_PAGE_SIZE;
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+ }
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+
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return 0;
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}
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diff --git a/cmis.h b/cmis.h
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index 911491dc5c8f..8d90a04756ad 100644
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--- a/cmis.h
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+++ b/cmis.h
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@@ -114,6 +114,13 @@
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#define CMIS_WAVELENGTH_TOL_MSB 0x8C
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#define CMIS_WAVELENGTH_TOL_LSB 0x8D
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+/* Supported Pages Advertising (Page 1) */
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+#define CMIS_PAGES_ADVER_OFFSET 0x8E
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+#define CMIS_BANKS_SUPPORTED_MASK 0x03
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+#define CMIS_BANK_0_SUPPORTED 0x00
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+#define CMIS_BANK_0_1_SUPPORTED 0x01
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+#define CMIS_BANK_0_3_SUPPORTED 0x02
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+
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/* Signal integrity controls */
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#define CMIS_SIG_INTEG_TX_OFFSET 0xA1
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#define CMIS_SIG_INTEG_RX_OFFSET 0xA2
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--
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2.35.1
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