|
 |
2a1b01 |
From 21367ae2b8ebbe5173cbed22dfa51680a3fe48d2 Mon Sep 17 00:00:00 2001
|
|
|
2a1b01 |
From: Ido Schimmel <idosch@nvidia.com>
|
|
|
2a1b01 |
Date: Tue, 23 Nov 2021 19:40:58 +0200
|
|
|
2a1b01 |
Subject: [PATCH 30/35] cmis: Initialize Banked Page 11h in memory map
|
|
|
2a1b01 |
|
|
|
2a1b01 |
Banked Page 11h stores, among other things, lane-specific flags and
|
|
|
2a1b01 |
monitors that are going to be parsed and displayed in subsequent
|
|
|
2a1b01 |
patches.
|
|
|
2a1b01 |
|
|
|
2a1b01 |
Request it via the 'MODULE_EEPROM_GET' netlink message and initialize it
|
|
|
2a1b01 |
in the memory map.
|
|
|
2a1b01 |
|
|
|
2a1b01 |
Only initialize it in supported Banks.
|
|
|
2a1b01 |
|
|
|
2a1b01 |
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
|
|
|
2a1b01 |
---
|
|
|
2a1b01 |
cmis.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
|
|
|
2a1b01 |
cmis.h | 7 +++++++
|
|
|
2a1b01 |
2 files changed, 54 insertions(+), 2 deletions(-)
|
|
|
2a1b01 |
|
|
|
2a1b01 |
diff --git a/cmis.c b/cmis.c
|
|
|
2a1b01 |
index 55b9d1b959cd..83ced4d253ae 100644
|
|
|
2a1b01 |
--- a/cmis.c
|
|
|
2a1b01 |
+++ b/cmis.c
|
|
|
2a1b01 |
@@ -15,9 +15,17 @@
|
|
|
2a1b01 |
#include "cmis.h"
|
|
|
2a1b01 |
#include "netlink/extapi.h"
|
|
|
2a1b01 |
|
|
|
2a1b01 |
+/* The maximum number of supported Banks. Relevant documents:
|
|
|
2a1b01 |
+ * [1] CMIS Rev. 5, page. 128, section 8.4.4, Table 8-40
|
|
|
2a1b01 |
+ */
|
|
|
2a1b01 |
+#define CMIS_MAX_BANKS 4
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
+/* We are not parsing further than Page 11h. */
|
|
|
2a1b01 |
+#define CMIS_MAX_PAGES 18
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
struct cmis_memory_map {
|
|
|
2a1b01 |
const __u8 *lower_memory;
|
|
|
2a1b01 |
- const __u8 *upper_memory[1][3]; /* Bank, Page */
|
|
|
2a1b01 |
+ const __u8 *upper_memory[CMIS_MAX_BANKS][CMIS_MAX_PAGES];
|
|
|
2a1b01 |
#define page_00h upper_memory[0x0][0x0]
|
|
|
2a1b01 |
#define page_01h upper_memory[0x0][0x1]
|
|
|
2a1b01 |
#define page_02h upper_memory[0x0][0x2]
|
|
|
2a1b01 |
@@ -399,12 +407,33 @@ static void cmis_request_init(struct ethtool_module_eeprom *request, u8 bank,
|
|
|
2a1b01 |
request->data = NULL;
|
|
|
2a1b01 |
}
|
|
|
2a1b01 |
|
|
|
2a1b01 |
+static int cmis_num_banks_get(const struct cmis_memory_map *map,
|
|
|
2a1b01 |
+ int *p_num_banks)
|
|
|
2a1b01 |
+{
|
|
|
2a1b01 |
+ switch (map->page_01h[CMIS_PAGES_ADVER_OFFSET] &
|
|
|
2a1b01 |
+ CMIS_BANKS_SUPPORTED_MASK) {
|
|
|
2a1b01 |
+ case CMIS_BANK_0_SUPPORTED:
|
|
|
2a1b01 |
+ *p_num_banks = 1;
|
|
|
2a1b01 |
+ break;
|
|
|
2a1b01 |
+ case CMIS_BANK_0_1_SUPPORTED:
|
|
|
2a1b01 |
+ *p_num_banks = 2;
|
|
|
2a1b01 |
+ break;
|
|
|
2a1b01 |
+ case CMIS_BANK_0_3_SUPPORTED:
|
|
|
2a1b01 |
+ *p_num_banks = 4;
|
|
|
2a1b01 |
+ break;
|
|
|
2a1b01 |
+ default:
|
|
|
2a1b01 |
+ return -EINVAL;
|
|
|
2a1b01 |
+ }
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
+ return 0;
|
|
|
2a1b01 |
+}
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
static int
|
|
|
2a1b01 |
cmis_memory_map_init_pages(struct cmd_context *ctx,
|
|
|
2a1b01 |
struct cmis_memory_map *map)
|
|
|
2a1b01 |
{
|
|
|
2a1b01 |
struct ethtool_module_eeprom request;
|
|
|
2a1b01 |
- int ret;
|
|
|
2a1b01 |
+ int num_banks, i, ret;
|
|
|
2a1b01 |
|
|
|
2a1b01 |
/* Lower Memory and Page 00h are always present.
|
|
|
2a1b01 |
*
|
|
|
2a1b01 |
@@ -443,6 +472,22 @@ cmis_memory_map_init_pages(struct cmd_context *ctx,
|
|
|
2a1b01 |
return ret;
|
|
|
2a1b01 |
map->page_02h = request.data - CMIS_PAGE_SIZE;
|
|
|
2a1b01 |
|
|
|
2a1b01 |
+ /* Bank 0 of Page 11h provides lane-specific registers for the first 8
|
|
|
2a1b01 |
+ * lanes, and each additional Banks provides support for an additional
|
|
|
2a1b01 |
+ * 8 lanes. Only initialize supported Banks.
|
|
|
2a1b01 |
+ */
|
|
|
2a1b01 |
+ ret = cmis_num_banks_get(map, &num_banks);
|
|
|
2a1b01 |
+ if (ret < 0)
|
|
|
2a1b01 |
+ return ret;
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
+ for (i = 0; i < num_banks; i++) {
|
|
|
2a1b01 |
+ cmis_request_init(&request, i, 0x11, CMIS_PAGE_SIZE);
|
|
|
2a1b01 |
+ ret = nl_get_eeprom_page(ctx, &request);
|
|
|
2a1b01 |
+ if (ret < 0)
|
|
|
2a1b01 |
+ return ret;
|
|
|
2a1b01 |
+ map->upper_memory[i][0x11] = request.data - CMIS_PAGE_SIZE;
|
|
|
2a1b01 |
+ }
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
return 0;
|
|
|
2a1b01 |
}
|
|
|
2a1b01 |
|
|
|
2a1b01 |
diff --git a/cmis.h b/cmis.h
|
|
|
2a1b01 |
index 911491dc5c8f..8d90a04756ad 100644
|
|
|
2a1b01 |
--- a/cmis.h
|
|
|
2a1b01 |
+++ b/cmis.h
|
|
|
2a1b01 |
@@ -114,6 +114,13 @@
|
|
|
2a1b01 |
#define CMIS_WAVELENGTH_TOL_MSB 0x8C
|
|
|
2a1b01 |
#define CMIS_WAVELENGTH_TOL_LSB 0x8D
|
|
|
2a1b01 |
|
|
|
2a1b01 |
+/* Supported Pages Advertising (Page 1) */
|
|
|
2a1b01 |
+#define CMIS_PAGES_ADVER_OFFSET 0x8E
|
|
|
2a1b01 |
+#define CMIS_BANKS_SUPPORTED_MASK 0x03
|
|
|
2a1b01 |
+#define CMIS_BANK_0_SUPPORTED 0x00
|
|
|
2a1b01 |
+#define CMIS_BANK_0_1_SUPPORTED 0x01
|
|
|
2a1b01 |
+#define CMIS_BANK_0_3_SUPPORTED 0x02
|
|
|
2a1b01 |
+
|
|
|
2a1b01 |
/* Signal integrity controls */
|
|
|
2a1b01 |
#define CMIS_SIG_INTEG_TX_OFFSET 0xA1
|
|
|
2a1b01 |
#define CMIS_SIG_INTEG_RX_OFFSET 0xA2
|
|
|
2a1b01 |
--
|
|
|
2a1b01 |
2.35.1
|
|
|
2a1b01 |
|