Blame otp-0010-Quickfix-for-cmpxchg8b-inline-asm-when-pic-and-gcc-5.patch

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From: Rickard Green <rickard@erlang.org>
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Date: Tue, 9 Feb 2016 18:23:26 +0100
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Subject: [PATCH] Quickfix for cmpxchg8b inline asm when pic and gcc >= 5.0 is
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 used
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diff --git a/erts/include/internal/i386/ethr_dw_atomic.h b/erts/include/internal/i386/ethr_dw_atomic.h
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index e8c4119..caba633 100644
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--- a/erts/include/internal/i386/ethr_dw_atomic.h
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+++ b/erts/include/internal/i386/ethr_dw_atomic.h
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@@ -115,6 +115,8 @@ ethr_native_dw_atomic_addr(ethr_native_dw_atomic_t *var)
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     return (ethr_sint_t *) ETHR_DW_NATMC_MEM__(var);
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 }
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+#if !ETHR_AT_LEAST_GCC_VSN__(5, 0, 0)
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+
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 #if ETHR_SIZEOF_PTR == 4 && defined(__PIC__) && __PIC__
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 /*
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  * When position independent code is used in 32-bit mode, the EBX register
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@@ -138,6 +140,7 @@ ethr_native_dw_atomic_addr(ethr_native_dw_atomic_t *var)
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 #  endif
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 #endif
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+#endif /* < gcc-5.0 */
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 #define ETHR_HAVE_ETHR_NATIVE_DW_ATOMIC_CMPXCHG_MB
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