|
|
d76f50 |
From 781bb36add9e43907a16a1303a13808ae53cfa31 Mon Sep 17 00:00:00 2001
|
|
|
d76f50 |
From: Maxime Coquelin <maxime.coquelin@redhat.com>
|
|
|
d76f50 |
Date: Fri, 12 Jan 2018 11:22:20 +0100
|
|
|
d76f50 |
Subject: [PATCH] bus/pci: forbid IOVA mode if IOMMU address width too small
|
|
|
d76f50 |
|
|
|
d76f50 |
[ upstream commit 54a328f552ff2e0098c3f96f9e32302675f2bcf4 ]
|
|
|
d76f50 |
|
|
|
d76f50 |
Intel VT-d supports different address widths for the IOVAs, from
|
|
|
d76f50 |
39 bits to 56 bits.
|
|
|
d76f50 |
|
|
|
d76f50 |
While recent processors support at least 48 bits, VT-d emulation
|
|
|
d76f50 |
currently only supports 39 bits. It makes DMA mapping to fail in this
|
|
|
d76f50 |
case when using VA as IOVA mode, as user-space virtual addresses uses
|
|
|
d76f50 |
up to 47 bits (see kernel's Documentation/x86/x86_64/mm.txt).
|
|
|
d76f50 |
|
|
|
d76f50 |
This patch parses VT-d CAP register value available in sysfs, and
|
|
|
d76f50 |
forbid VA as IOVA mode if the GAW is 39 bits or unknown.
|
|
|
d76f50 |
|
|
|
d76f50 |
Fixes: f37dfab21c98 ("drivers/net: enable IOVA mode for Intel PMDs")
|
|
|
d76f50 |
|
|
|
d76f50 |
Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
|
|
|
d76f50 |
Tested-by: Chas Williams <chas3@att.com>
|
|
|
d76f50 |
---
|
|
|
d76f50 |
drivers/bus/pci/linux/pci.c | 90 ++++++++++++++++++++++++++++++++++++++++-----
|
|
|
d76f50 |
1 file changed, 81 insertions(+), 9 deletions(-)
|
|
|
d76f50 |
|
|
|
d76f50 |
diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c
|
|
|
d76f50 |
index ec31216..74deef3 100644
|
|
|
d76f50 |
--- a/drivers/bus/pci/linux/pci.c
|
|
|
d76f50 |
+++ b/drivers/bus/pci/linux/pci.c
|
|
|
d76f50 |
@@ -577,4 +577,80 @@
|
|
|
d76f50 |
}
|
|
|
d76f50 |
|
|
|
d76f50 |
+#if defined(RTE_ARCH_X86)
|
|
|
d76f50 |
+static bool
|
|
|
d76f50 |
+pci_one_device_iommu_support_va(struct rte_pci_device *dev)
|
|
|
d76f50 |
+{
|
|
|
d76f50 |
+#define VTD_CAP_MGAW_SHIFT 16
|
|
|
d76f50 |
+#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT)
|
|
|
d76f50 |
+#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */
|
|
|
d76f50 |
+ struct rte_pci_addr *addr = &dev->addr;
|
|
|
d76f50 |
+ char filename[PATH_MAX];
|
|
|
d76f50 |
+ FILE *fp;
|
|
|
d76f50 |
+ uint64_t mgaw, vtd_cap_reg = 0;
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ snprintf(filename, sizeof(filename),
|
|
|
d76f50 |
+ "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
|
|
|
d76f50 |
+ rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,
|
|
|
d76f50 |
+ addr->function);
|
|
|
d76f50 |
+ if (access(filename, F_OK) == -1) {
|
|
|
d76f50 |
+ /* We don't have an Intel IOMMU, assume VA supported*/
|
|
|
d76f50 |
+ return true;
|
|
|
d76f50 |
+ }
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ /* We have an intel IOMMU */
|
|
|
d76f50 |
+ fp = fopen(filename, "r");
|
|
|
d76f50 |
+ if (fp == NULL) {
|
|
|
d76f50 |
+ RTE_LOG(ERR, EAL, "%s(): can't open %s\n", __func__, filename);
|
|
|
d76f50 |
+ return false;
|
|
|
d76f50 |
+ }
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) {
|
|
|
d76f50 |
+ RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
|
|
|
d76f50 |
+ fclose(fp);
|
|
|
d76f50 |
+ return false;
|
|
|
d76f50 |
+ }
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ fclose(fp);
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
|
|
|
d76f50 |
+ if (mgaw < X86_VA_WIDTH)
|
|
|
d76f50 |
+ return false;
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ return true;
|
|
|
d76f50 |
+}
|
|
|
d76f50 |
+#elif defined(RTE_ARCH_PPC_64)
|
|
|
d76f50 |
+static bool
|
|
|
d76f50 |
+pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev)
|
|
|
d76f50 |
+{
|
|
|
d76f50 |
+ return false;
|
|
|
d76f50 |
+}
|
|
|
d76f50 |
+#else
|
|
|
d76f50 |
+static bool
|
|
|
d76f50 |
+pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev)
|
|
|
d76f50 |
+{
|
|
|
d76f50 |
+ return true;
|
|
|
d76f50 |
+}
|
|
|
d76f50 |
+#endif
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+/*
|
|
|
d76f50 |
+ * All devices IOMMUs support VA as IOVA
|
|
|
d76f50 |
+ */
|
|
|
d76f50 |
+static bool
|
|
|
d76f50 |
+pci_devices_iommu_support_va(void)
|
|
|
d76f50 |
+{
|
|
|
d76f50 |
+ struct rte_pci_device *dev = NULL;
|
|
|
d76f50 |
+ struct rte_pci_driver *drv = NULL;
|
|
|
d76f50 |
+
|
|
|
d76f50 |
+ FOREACH_DRIVER_ON_PCIBUS(drv) {
|
|
|
d76f50 |
+ FOREACH_DEVICE_ON_PCIBUS(dev) {
|
|
|
d76f50 |
+ if (!rte_pci_match(drv, dev))
|
|
|
d76f50 |
+ continue;
|
|
|
d76f50 |
+ if (!pci_one_device_iommu_support_va(dev))
|
|
|
d76f50 |
+ return false;
|
|
|
d76f50 |
+ }
|
|
|
d76f50 |
+ }
|
|
|
d76f50 |
+ return true;
|
|
|
d76f50 |
+}
|
|
|
d76f50 |
+
|
|
|
d76f50 |
/*
|
|
|
d76f50 |
* Get iommu class of PCI devices on the bus.
|
|
|
d76f50 |
@@ -587,10 +663,5 @@ enum rte_iova_mode
|
|
|
d76f50 |
bool has_iova_va;
|
|
|
d76f50 |
bool is_bound_uio;
|
|
|
d76f50 |
- bool spapr_iommu =
|
|
|
d76f50 |
-#if defined(RTE_ARCH_PPC_64)
|
|
|
d76f50 |
- true;
|
|
|
d76f50 |
-#else
|
|
|
d76f50 |
- false;
|
|
|
d76f50 |
-#endif
|
|
|
d76f50 |
+ bool iommu_no_va;
|
|
|
d76f50 |
|
|
|
d76f50 |
is_bound = pci_one_device_is_bound();
|
|
|
d76f50 |
@@ -600,4 +671,5 @@ enum rte_iova_mode
|
|
|
d76f50 |
has_iova_va = pci_one_device_has_iova_va();
|
|
|
d76f50 |
is_bound_uio = pci_one_device_bound_uio();
|
|
|
d76f50 |
+ iommu_no_va = !pci_devices_iommu_support_va();
|
|
|
d76f50 |
#ifdef VFIO_PRESENT
|
|
|
d76f50 |
is_vfio_noiommu_enabled = rte_vfio_noiommu_is_enabled() == true ?
|
|
|
d76f50 |
@@ -606,5 +678,5 @@ enum rte_iova_mode
|
|
|
d76f50 |
|
|
|
d76f50 |
if (has_iova_va && !is_bound_uio && !is_vfio_noiommu_enabled &&
|
|
|
d76f50 |
- !spapr_iommu)
|
|
|
d76f50 |
+ !iommu_no_va)
|
|
|
d76f50 |
return RTE_IOVA_VA;
|
|
|
d76f50 |
|
|
|
d76f50 |
@@ -615,6 +687,6 @@ enum rte_iova_mode
|
|
|
d76f50 |
if (is_bound_uio)
|
|
|
d76f50 |
RTE_LOG(WARNING, EAL, "few device bound to UIO\n");
|
|
|
d76f50 |
- if (spapr_iommu)
|
|
|
d76f50 |
- RTE_LOG(WARNING, EAL, "sPAPR IOMMU does not support IOVA as VA\n");
|
|
|
d76f50 |
+ if (iommu_no_va)
|
|
|
d76f50 |
+ RTE_LOG(WARNING, EAL, "IOMMU does not support IOVA as VA\n");
|
|
|
d76f50 |
}
|
|
|
d76f50 |
|
|
|
d76f50 |
--
|
|
|
d76f50 |
1.8.3.1
|
|
|
d76f50 |
|