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From FEDORA_PATCHES Mon Sep 17 00:00:00 2001
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From: Fedora GDB patches <invalid@email.com>
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Date: Fri, 27 Oct 2017 21:07:50 +0200
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Subject: gdb-test-ivy-bridge.patch
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;; Test GDB opcodes/ disassembly of Intel Ivy Bridge instructions (BZ 696890).
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;;=fedoratest
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diff --git a/gdb/testsuite/gdb.arch/amd64-ivy-bridge.S b/gdb/testsuite/gdb.arch/amd64-ivy-bridge.S
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/amd64-ivy-bridge.S
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@@ -0,0 +1,98 @@
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+/* Copyright 2011 Free Software Foundation, Inc.
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 3 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
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+ This file is part of the gdb testsuite. */
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+
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+ .globl _start
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+_start: .text
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+
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+/* gas/i386/x86-64-rdrnd.s */
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+ .att_syntax prefix
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+ rdrand %bx
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+ rdrand %ebx
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+ rdrand %rbx
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+ rdrand %r8w
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+ rdrand %r8d
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+ rdrand %r8
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+
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+ .intel_syntax noprefix
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+ rdrand bx
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+ rdrand ebx
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a1b30c |
+ rdrand rbx
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a1b30c |
+ rdrand r8w
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a1b30c |
+ rdrand r8d
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+ rdrand r8
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+
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+/* gas/i386/x86-64-f16c.s */
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+ .att_syntax prefix
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+ vcvtph2ps %xmm4,%ymm4
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+ vcvtph2ps (%r8),%ymm8
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+ vcvtph2ps %xmm4,%xmm6
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+ vcvtph2ps (%rcx),%xmm4
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+ vcvtps2ph $0x2,%ymm4,%xmm4
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+ vcvtps2ph $0x2,%ymm8,(%r8)
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a1b30c |
+ vcvtps2ph $0x2,%xmm4,%xmm4
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+ vcvtps2ph $0x2,%xmm4,(%rcx)
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+
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+ .intel_syntax noprefix
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+ vcvtph2ps ymm4,xmm4
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+ vcvtph2ps ymm8,XMMWORD PTR [r8]
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+ vcvtph2ps ymm4,[rcx]
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+ vcvtph2ps xmm6,xmm4
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+ vcvtph2ps xmm4,QWORD PTR [rcx]
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+ vcvtph2ps xmm4,[rcx]
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+ vcvtps2ph xmm4,ymm4,0x2
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+ vcvtps2ph XMMWORD PTR [rcx],ymm4,0x2
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+ vcvtps2ph [rcx],ymm4,0x2
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+ vcvtps2ph xmm4,xmm4,0x2
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+ vcvtps2ph QWORD PTR [r8],xmm8,0x2
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+ vcvtps2ph [rcx],xmm4,0x2
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+
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+/* gas/i386/x86-64-fsgs.s */
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+ .att_syntax prefix
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+ rdfsbase %ebx
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+ rdfsbase %rbx
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+ rdfsbase %r8d
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+ rdfsbase %r8
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+ rdgsbase %ebx
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+ rdgsbase %rbx
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+ rdgsbase %r8d
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+ rdgsbase %r8
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+ wrfsbase %ebx
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+ wrfsbase %rbx
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+ wrfsbase %r8d
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+ wrfsbase %r8
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+ wrgsbase %ebx
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+ wrgsbase %rbx
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+ wrgsbase %r8d
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+ wrgsbase %r8
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+
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+ .intel_syntax noprefix
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+ rdfsbase ebx
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+ rdfsbase rbx
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+ rdfsbase r8d
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+ rdfsbase r8
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+ rdgsbase ebx
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+ rdgsbase rbx
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+ rdgsbase r8d
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+ rdgsbase r8
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+ wrfsbase ebx
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+ wrfsbase rbx
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+ wrfsbase r8d
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+ wrfsbase r8
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+ wrgsbase ebx
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+ wrgsbase rbx
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+ wrgsbase r8d
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+ wrgsbase r8
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diff --git a/gdb/testsuite/gdb.arch/amd64-ivy-bridge.exp b/gdb/testsuite/gdb.arch/amd64-ivy-bridge.exp
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new file mode 100644
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--- /dev/null
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+++ b/gdb/testsuite/gdb.arch/amd64-ivy-bridge.exp
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@@ -0,0 +1,170 @@
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+# Copyright 2011 Free Software Foundation, Inc.
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+
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+# This program is free software; you can redistribute it and/or modify
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a1b30c |
+# it under the terms of the GNU General Public License as published by
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a1b30c |
+# the Free Software Foundation; either version 3 of the License, or
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a1b30c |
+# (at your option) any later version.
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a1b30c |
+#
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a1b30c |
+# This program is distributed in the hope that it will be useful,
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a1b30c |
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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a1b30c |
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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a1b30c |
+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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a1b30c |
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
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+
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+if {![istarget "x86_64-*-*"]} then {
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+ return
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+}
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+
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+set testfile amd64-ivy-bridge
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+set test compilation
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+if [prepare_for_testing ${testfile}.exp ${testfile}.x ${testfile}.S [list debug "additional_flags=-m64 -nostdlib"]] {
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+ unsupported $test
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+ return -1
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+}
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+pass $test
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+
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+gdb_test_no_output "set disassembly-flavor att"
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+# gas/i386/x86-64-rdrnd.d
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+# gas/i386/x86-64-f16c.d
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+# gas/i386/x86-64-fsgs.d
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+gdb_test "disassemble/r _start" "\r
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+Dump of assembler code for function _start:\r
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+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand %bx\r
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+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand %ebx\r
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+\[^\r\n\]+:\t48 0f c7 f3\t\( \)?rdrand %rbx\r
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+\[^\r\n\]+:\t66 41 0f c7 f0\t\( \)?rdrand %r8w\r
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+\[^\r\n\]+:\t41 0f c7 f0\t\( \)?rdrand %r8d\r
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+\[^\r\n\]+:\t49 0f c7 f0\t\( \)?rdrand %r8\r
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+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand %bx\r
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+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand %ebx\r
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+\[^\r\n\]+:\t48 0f c7 f3\t\( \)?rdrand %rbx\r
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+\[^\r\n\]+:\t66 41 0f c7 f0\t\( \)?rdrand %r8w\r
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+\[^\r\n\]+:\t41 0f c7 f0\t\( \)?rdrand %r8d\r
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+\[^\r\n\]+:\t49 0f c7 f0\t\( \)?rdrand %r8\r
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+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps %xmm4,%ymm4\r
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+\[^\r\n\]+:\tc4 42 7d 13 00\t\( \)?vcvtph2ps \\(%r8\\),%ymm8\r
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+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps %xmm4,%xmm6\r
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+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps \\(%rcx\\),%xmm4\r
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+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,%xmm4\r
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+\[^\r\n\]+:\tc4 43 7d 1d 00 02\t\( \)?vcvtps2ph \\\$0x2,%ymm8,\\(%r8\\)\r
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+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,%xmm4\r
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+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,\\(%rcx\\)\r
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+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps %xmm4,%ymm4\r
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+\[^\r\n\]+:\tc4 42 7d 13 00\t\( \)?vcvtph2ps \\(%r8\\),%ymm8\r
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+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps \\(%rcx\\),%ymm4\r
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+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps %xmm4,%xmm6\r
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+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps \\(%rcx\\),%xmm4\r
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+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps \\(%rcx\\),%xmm4\r
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+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,%xmm4\r
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+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,\\(%rcx\\)\r
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+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,\\(%rcx\\)\r
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+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,%xmm4\r
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+\[^\r\n\]+:\tc4 43 79 1d 00 02\t\( \)?vcvtps2ph \\\$0x2,%xmm8,\\(%r8\\)\r
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+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,\\(%rcx\\)\r
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+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase %ebx\r
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+\[^\r\n\]+:\tf3 48 0f ae c3\t\( \)?rdfsbase %rbx\r
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+\[^\r\n\]+:\tf3 41 0f ae c0\t\( \)?rdfsbase %r8d\r
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+\[^\r\n\]+:\tf3 49 0f ae c0\t\( \)?rdfsbase %r8\r
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+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase %ebx\r
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+\[^\r\n\]+:\tf3 48 0f ae cb\t\( \)?rdgsbase %rbx\r
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+\[^\r\n\]+:\tf3 41 0f ae c8\t\( \)?rdgsbase %r8d\r
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+\[^\r\n\]+:\tf3 49 0f ae c8\t\( \)?rdgsbase %r8\r
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+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase %ebx\r
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+\[^\r\n\]+:\tf3 48 0f ae d3\t\( \)?wrfsbase %rbx\r
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+\[^\r\n\]+:\tf3 41 0f ae d0\t\( \)?wrfsbase %r8d\r
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+\[^\r\n\]+:\tf3 49 0f ae d0\t\( \)?wrfsbase %r8\r
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+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase %ebx\r
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+\[^\r\n\]+:\tf3 48 0f ae db\t\( \)?wrgsbase %rbx\r
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+\[^\r\n\]+:\tf3 41 0f ae d8\t\( \)?wrgsbase %r8d\r
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a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d8\t\( \)?wrgsbase %r8\r
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a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase %ebx\r
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a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae c3\t\( \)?rdfsbase %rbx\r
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a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae c0\t\( \)?rdfsbase %r8d\r
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a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae c0\t\( \)?rdfsbase %r8\r
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a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase %ebx\r
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a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae cb\t\( \)?rdgsbase %rbx\r
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a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae c8\t\( \)?rdgsbase %r8d\r
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a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae c8\t\( \)?rdgsbase %r8\r
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a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase %ebx\r
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a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae d3\t\( \)?wrfsbase %rbx\r
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a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae d0\t\( \)?wrfsbase %r8d\r
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a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d0\t\( \)?wrfsbase %r8\r
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a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase %ebx\r
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a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae db\t\( \)?wrgsbase %rbx\r
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a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae d8\t\( \)?wrgsbase %r8d\r
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a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d8\t\( \)?wrgsbase %r8\r
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a1b30c |
+End of assembler dump\\." "att"
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a1b30c |
+
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a1b30c |
+gdb_test_no_output "set disassembly-flavor intel"
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a1b30c |
+# gas/i386/x86-64-rdrnd-intel.d
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a1b30c |
+# gas/i386/x86-64-f16c-intel.d
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a1b30c |
+# gas/i386/x86-64-fsgs-intel.d
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a1b30c |
+gdb_test "disassemble/r _start" "\r
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a1b30c |
+Dump of assembler code for function _start:\r
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a1b30c |
+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand bx\r
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a1b30c |
+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand ebx\r
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a1b30c |
+\[^\r\n\]+:\t48 0f c7 f3\t\( \)?rdrand rbx\r
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a1b30c |
+\[^\r\n\]+:\t66 41 0f c7 f0\t\( \)?rdrand r8w\r
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|
|
a1b30c |
+\[^\r\n\]+:\t41 0f c7 f0\t\( \)?rdrand r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t49 0f c7 f0\t\( \)?rdrand r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand bx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t48 0f c7 f3\t\( \)?rdrand rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t66 41 0f c7 f0\t\( \)?rdrand r8w\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t41 0f c7 f0\t\( \)?rdrand r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t49 0f c7 f0\t\( \)?rdrand r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps ymm4,xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 42 7d 13 00\t\( \)?vcvtph2ps ymm8,XMMWORD PTR \\\[r8\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps xmm6,xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps xmm4,QWORD PTR \\\[rcx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph xmm4,ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 43 7d 1d 00 02\t\( \)?vcvtps2ph XMMWORD PTR \\\[r8\\\],ymm8,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph xmm4,xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph QWORD PTR \\\[rcx\\\],xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps ymm4,xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 42 7d 13 00\t\( \)?vcvtph2ps ymm8,XMMWORD PTR \\\[r8\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps ymm4,XMMWORD PTR \\\[rcx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps xmm6,xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps xmm4,QWORD PTR \\\[rcx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps xmm4,QWORD PTR \\\[rcx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph xmm4,ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph XMMWORD PTR \\\[rcx\\\],ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph XMMWORD PTR \\\[rcx\\\],ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph xmm4,xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 43 79 1d 00 02\t\( \)?vcvtps2ph QWORD PTR \\\[r8\\\],xmm8,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph QWORD PTR \\\[rcx\\\],xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae c3\t\( \)?rdfsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae c0\t\( \)?rdfsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae c0\t\( \)?rdfsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae cb\t\( \)?rdgsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae c8\t\( \)?rdgsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae c8\t\( \)?rdgsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae d3\t\( \)?wrfsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae d0\t\( \)?wrfsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d0\t\( \)?wrfsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae db\t\( \)?wrgsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae d8\t\( \)?wrgsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d8\t\( \)?wrgsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae c3\t\( \)?rdfsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae c0\t\( \)?rdfsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae c0\t\( \)?rdfsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae cb\t\( \)?rdgsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae c8\t\( \)?rdgsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae c8\t\( \)?rdgsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae d3\t\( \)?wrfsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae d0\t\( \)?wrfsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d0\t\( \)?wrfsbase r8\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 48 0f ae db\t\( \)?wrgsbase rbx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 41 0f ae d8\t\( \)?wrgsbase r8d\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 49 0f ae d8\t\( \)?wrgsbase r8\r
|
|
|
a1b30c |
+End of assembler dump\\." "intel"
|
|
|
a1b30c |
diff --git a/gdb/testsuite/gdb.arch/i386-ivy-bridge.S b/gdb/testsuite/gdb.arch/i386-ivy-bridge.S
|
|
|
a1b30c |
new file mode 100644
|
|
|
a1b30c |
--- /dev/null
|
|
|
a1b30c |
+++ b/gdb/testsuite/gdb.arch/i386-ivy-bridge.S
|
|
|
a1b30c |
@@ -0,0 +1,66 @@
|
|
|
a1b30c |
+/* Copyright 2011 Free Software Foundation, Inc.
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ This program is free software; you can redistribute it and/or modify
|
|
|
a1b30c |
+ it under the terms of the GNU General Public License as published by
|
|
|
a1b30c |
+ the Free Software Foundation; either version 3 of the License, or
|
|
|
a1b30c |
+ (at your option) any later version.
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ This program is distributed in the hope that it will be useful,
|
|
|
a1b30c |
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
a1b30c |
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
a1b30c |
+ GNU General Public License for more details.
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ You should have received a copy of the GNU General Public License
|
|
|
a1b30c |
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ This file is part of the gdb testsuite. */
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ .globl _start
|
|
|
a1b30c |
+_start: .text
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+/* gas/i386/rdrnd.s */
|
|
|
a1b30c |
+ .att_syntax prefix
|
|
|
a1b30c |
+ rdrand %bx
|
|
|
a1b30c |
+ rdrand %ebx
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ .intel_syntax noprefix
|
|
|
a1b30c |
+ rdrand bx
|
|
|
a1b30c |
+ rdrand ebx
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+/* gas/i386/f16c.s */
|
|
|
a1b30c |
+ .att_syntax prefix
|
|
|
a1b30c |
+ vcvtph2ps %xmm4,%ymm4
|
|
|
a1b30c |
+ vcvtph2ps (%ecx),%ymm4
|
|
|
a1b30c |
+ vcvtph2ps %xmm4,%xmm6
|
|
|
a1b30c |
+ vcvtph2ps (%ecx),%xmm4
|
|
|
a1b30c |
+ vcvtps2ph $0x2,%ymm4,%xmm4
|
|
|
a1b30c |
+ vcvtps2ph $0x2,%ymm4,(%ecx)
|
|
|
a1b30c |
+ vcvtps2ph $0x2,%xmm4,%xmm4
|
|
|
a1b30c |
+ vcvtps2ph $0x2,%xmm4,(%ecx)
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ .intel_syntax noprefix
|
|
|
a1b30c |
+ vcvtph2ps ymm4,xmm4
|
|
|
a1b30c |
+ vcvtph2ps ymm4,XMMWORD PTR [ecx]
|
|
|
a1b30c |
+ vcvtph2ps ymm4,[ecx]
|
|
|
a1b30c |
+ vcvtph2ps xmm6,xmm4
|
|
|
a1b30c |
+ vcvtph2ps xmm4,QWORD PTR [ecx]
|
|
|
a1b30c |
+ vcvtph2ps xmm4,[ecx]
|
|
|
a1b30c |
+ vcvtps2ph xmm4,ymm4,0x2
|
|
|
a1b30c |
+ vcvtps2ph XMMWORD PTR [ecx],ymm4,0x2
|
|
|
a1b30c |
+ vcvtps2ph [ecx],ymm4,0x2
|
|
|
a1b30c |
+ vcvtps2ph xmm4,xmm4,0x2
|
|
|
a1b30c |
+ vcvtps2ph QWORD PTR [ecx],xmm4,0x2
|
|
|
a1b30c |
+ vcvtps2ph [ecx],xmm4,0x2
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+/* gas/i386/fsgs.s */
|
|
|
a1b30c |
+ .att_syntax prefix
|
|
|
a1b30c |
+ rdfsbase %ebx
|
|
|
a1b30c |
+ rdgsbase %ebx
|
|
|
a1b30c |
+ wrfsbase %ebx
|
|
|
a1b30c |
+ wrgsbase %ebx
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+ .intel_syntax noprefix
|
|
|
a1b30c |
+ rdfsbase ebx
|
|
|
a1b30c |
+ rdgsbase ebx
|
|
|
a1b30c |
+ wrfsbase ebx
|
|
|
a1b30c |
+ wrgsbase ebx
|
|
|
a1b30c |
diff --git a/gdb/testsuite/gdb.arch/i386-ivy-bridge.exp b/gdb/testsuite/gdb.arch/i386-ivy-bridge.exp
|
|
|
a1b30c |
new file mode 100644
|
|
|
a1b30c |
--- /dev/null
|
|
|
a1b30c |
+++ b/gdb/testsuite/gdb.arch/i386-ivy-bridge.exp
|
|
|
a1b30c |
@@ -0,0 +1,106 @@
|
|
|
a1b30c |
+# Copyright 2011 Free Software Foundation, Inc.
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+# This program is free software; you can redistribute it and/or modify
|
|
|
a1b30c |
+# it under the terms of the GNU General Public License as published by
|
|
|
a1b30c |
+# the Free Software Foundation; either version 3 of the License, or
|
|
|
a1b30c |
+# (at your option) any later version.
|
|
|
a1b30c |
+#
|
|
|
a1b30c |
+# This program is distributed in the hope that it will be useful,
|
|
|
a1b30c |
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
a1b30c |
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
a1b30c |
+# GNU General Public License for more details.
|
|
|
a1b30c |
+#
|
|
|
a1b30c |
+# You should have received a copy of the GNU General Public License
|
|
|
a1b30c |
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+if {![istarget "x86_64-*-*"] && ![istarget "i?86-*-*"]} then {
|
|
|
a1b30c |
+ return
|
|
|
a1b30c |
+}
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+set testfile i386-ivy-bridge
|
|
|
a1b30c |
+set test compilation
|
|
|
a1b30c |
+if [prepare_for_testing ${testfile}.exp ${testfile}.x ${testfile}.S [list debug "additional_flags=-m32 -nostdlib"]] {
|
|
|
a1b30c |
+ fail $test
|
|
|
a1b30c |
+ return -1
|
|
|
a1b30c |
+}
|
|
|
a1b30c |
+pass $test
|
|
|
a1b30c |
+
|
|
|
a1b30c |
+gdb_test_no_output "set disassembly-flavor att"
|
|
|
a1b30c |
+# gas/i386/rdrnd.d
|
|
|
a1b30c |
+# gas/i386/f16c.d
|
|
|
a1b30c |
+# gas/i386/fsgs.d
|
|
|
a1b30c |
+gdb_test "disassemble/r _start" "\r
|
|
|
a1b30c |
+Dump of assembler code for function _start:\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand %bx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand %bx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps %xmm4,%ymm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps \\(%ecx\\),%ymm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps %xmm4,%xmm6\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps \\(%ecx\\),%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,\\(%ecx\\)\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,\\(%ecx\\)\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps %xmm4,%ymm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps \\(%ecx\\),%ymm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps \\(%ecx\\),%ymm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps %xmm4,%xmm6\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps \\(%ecx\\),%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps \\(%ecx\\),%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,\\(%ecx\\)\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%ymm4,\\(%ecx\\)\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,%xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,\\(%ecx\\)\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph \\\$0x2,%xmm4,\\(%ecx\\)\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase %ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase %ebx\r
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a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase %ebx\r
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a1b30c |
+End of assembler dump\\." "att"
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a1b30c |
+
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a1b30c |
+gdb_test_no_output "set disassembly-flavor intel"
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a1b30c |
+# gas/i386/rdrnd-intel.d
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a1b30c |
+# gas/i386/f16c-intel.d
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a1b30c |
+# gas/i386/fsgs-intel.d
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a1b30c |
+gdb_test "disassemble/r _start" "\r
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a1b30c |
+Dump of assembler code for function _start:\r
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a1b30c |
+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand bx\r
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a1b30c |
+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand ebx\r
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a1b30c |
+\[^\r\n\]+:\t66 0f c7 f3\t\( \)?rdrand bx\r
|
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a1b30c |
+\[^\r\n\]+:\t0f c7 f3\t\( \)?rdrand ebx\r
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a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps ymm4,xmm4\r
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a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps ymm4,XMMWORD PTR \\\[ecx\\\]\r
|
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a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps xmm6,xmm4\r
|
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a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps xmm4,QWORD PTR \\\[ecx\\\]\r
|
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a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph xmm4,ymm4,0x2\r
|
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a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph XMMWORD PTR \\\[ecx\\\],ymm4,0x2\r
|
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|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph xmm4,xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph QWORD PTR \\\[ecx\\\],xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 e4\t\( \)?vcvtph2ps ymm4,xmm4\r
|
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|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps ymm4,XMMWORD PTR \\\[ecx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 7d 13 21\t\( \)?vcvtph2ps ymm4,XMMWORD PTR \\\[ecx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 f4\t\( \)?vcvtph2ps xmm6,xmm4\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps xmm4,QWORD PTR \\\[ecx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e2 79 13 21\t\( \)?vcvtph2ps xmm4,QWORD PTR \\\[ecx\\\]\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d e4 02\t\( \)?vcvtps2ph xmm4,ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph XMMWORD PTR \\\[ecx\\\],ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 7d 1d 21 02\t\( \)?vcvtps2ph XMMWORD PTR \\\[ecx\\\],ymm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d e4 02\t\( \)?vcvtps2ph xmm4,xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph QWORD PTR \\\[ecx\\\],xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tc4 e3 79 1d 21 02\t\( \)?vcvtps2ph QWORD PTR \\\[ecx\\\],xmm4,0x2\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae c3\t\( \)?rdfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae cb\t\( \)?rdgsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae d3\t\( \)?wrfsbase ebx\r
|
|
|
a1b30c |
+\[^\r\n\]+:\tf3 0f ae db\t\( \)?wrgsbase ebx\r
|
|
|
a1b30c |
+End of assembler dump\\." "intel"
|