|
 |
1a405f |
--- binutils-2.25.1/gas/testsuite/gas/ppc/power7.s 2015-07-21 09:20:58.000000000 +0100
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|
|
1a405f |
+++ binutils-2.25.1.new/gas/testsuite/gas/ppc/power7.s 2016-03-01 14:08:17.020136029 +0000
|
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|
1a405f |
@@ -98,4 +98,4 @@ power7:
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|
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1a405f |
mfppr32 11
|
|
|
1a405f |
mtppr 12
|
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|
1a405f |
mtppr32 13
|
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|
1a405f |
- tlbie 10,11
|
|
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1a405f |
+ tlbie 10
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|
|
1a405f |
--- binutils-2.25.1/gas/testsuite/gas/ppc/power7.d 2015-07-21 09:20:58.000000000 +0100
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1a405f |
+++ binutils-2.25.1.new/gas/testsuite/gas/ppc/power7.d 2016-03-01 14:08:17.020136029 +0000
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|
|
1a405f |
@@ -107,5 +107,5 @@ Disassembly of section \.text:
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1a405f |
.*: (7d 62 e2 a6|a6 e2 62 7d) mfppr32 r11
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1a405f |
.*: (7d 80 e3 a6|a6 e3 80 7d) mtppr r12
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1a405f |
.*: (7d a2 e3 a6|a6 e3 a2 7d) mtppr32 r13
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|
|
1a405f |
-.*: (7d 60 52 64|64 52 60 7d) tlbie r10,r11
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1a405f |
+.*: (7c 00 52 64|64 52 00 7c) tlbie r10
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1a405f |
#pass
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1a405f |
--- binutils.orig/opcodes/ppc-opc.c 2017-01-17 09:44:23.341397357 +0000
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1a405f |
+++ binutils-2.27/opcodes/ppc-opc.c 2017-01-17 09:45:24.000684653 +0000
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1a405f |
@@ -5182,8 +5182,7 @@ const struct powerpc_opcode powerpc_opco
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1a405f |
{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
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|
|
1a405f |
|
|
|
1a405f |
{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
|
|
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1a405f |
-{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
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|
|
1a405f |
-{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
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|
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1a405f |
+{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER9|TITAN, {RB, L}},
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|
|
1a405f |
{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
|
|
|
1a405f |
|
|
|
1a405f |
{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
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|
|
1a405f |
--- binutils.orig/gas/testsuite/gas/ppc/e500-ill.s 2017-01-17 10:34:39.821866168 +0000
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|
|
1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/e500-ill.s 2017-01-17 10:56:56.766061777 +0000
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1a405f |
@@ -7,4 +7,4 @@ start:
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1a405f |
mfdcr 5, 234
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1a405f |
mtdcr 432, 8
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|
1a405f |
tlbia
|
|
|
1a405f |
- tlbie 3
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1a405f |
+
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1a405f |
--- binutils.orig/gas/testsuite/gas/ppc/e500-ill.l 2017-01-17 10:34:39.821866168 +0000
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1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/e500-ill.l 2017-01-17 10:57:09.021915557 +0000
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|
|
1a405f |
@@ -5,4 +5,3 @@
|
|
|
1a405f |
.*: Error: unrecognized opcode: `mfdcr'
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|
1a405f |
.*: Error: unrecognized opcode: `mtdcr'
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|
1a405f |
.*: Error: unrecognized opcode: `tlbia'
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|
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1a405f |
-.*: Error: unrecognized opcode: `tlbie'
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|
|
1a405f |
--- binutils.orig/gas/testsuite/gas/ppc/power6.s 2017-01-17 10:34:39.822866157 +0000
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|
1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/power6.s 2017-01-17 10:58:38.316849143 +0000
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|
|
1a405f |
@@ -69,6 +69,5 @@ start:
|
|
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1a405f |
slbia
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|
|
1a405f |
slbia 0
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|
1a405f |
slbia 7
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|
1a405f |
- tlbie 10
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|
|
1a405f |
tlbie 10,0
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|
|
1a405f |
tlbie 10,1
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|
|
1a405f |
--- binutils.orig/gas/testsuite/gas/ppc/power6.d 2017-01-17 10:34:39.822866157 +0000
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|
1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/power6.d 2017-01-17 10:59:24.780294250 +0000
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|
|
1a405f |
@@ -74,7 +74,6 @@ Disassembly of section \.text:
|
|
|
1a405f |
.*: (7c 00 03 e4|e4 03 00 7c) slbia
|
|
|
1a405f |
.*: (7c 00 03 e4|e4 03 00 7c) slbia
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1a405f |
.*: (7c e0 03 e4|e4 03 e0 7c) slbia 7
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1a405f |
-.*: (7c 00 52 64|64 52 00 7c) tlbie r10
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1a405f |
-.*: (7c 00 52 64|64 52 00 7c) tlbie r10
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1a405f |
+.*: (7c 00 52 64|64 52 00 7c) tlbie r10,0
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|
|
1a405f |
.*: (7c 20 52 64|64 52 20 7c) tlbie r10,1
|
|
|
1a405f |
#pass
|
|
|
1a405f |
--- binutils.orig/gas/testsuite/gas/ppc/power7.s 2017-01-17 10:34:39.823866144 +0000
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|
|
1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/power7.s 2017-01-17 11:00:19.835636746 +0000
|
|
|
1a405f |
@@ -98,4 +98,4 @@ power7:
|
|
|
1a405f |
mfppr32 11
|
|
|
1a405f |
mtppr 12
|
|
|
1a405f |
mtppr32 13
|
|
|
1a405f |
- tlbie 10
|
|
|
1a405f |
+
|
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|
1a405f |
--- binutils.orig/gas/testsuite/gas/ppc/power7.d 2017-01-17 10:34:39.822866157 +0000
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|
1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/power7.d 2017-01-17 11:00:27.995539295 +0000
|
|
|
1a405f |
@@ -107,5 +107,4 @@ Disassembly of section \.text:
|
|
|
1a405f |
.*: (7d 62 e2 a6|a6 e2 62 7d) mfppr32 r11
|
|
|
1a405f |
.*: (7d 80 e3 a6|a6 e3 80 7d) mtppr r12
|
|
|
1a405f |
.*: (7d a2 e3 a6|a6 e3 a2 7d) mtppr32 r13
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|
|
1a405f |
-.*: (7c 00 52 64|64 52 00 7c) tlbie r10
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|
|
1a405f |
#pass
|
|
|
1a405f |
diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.27/gas/config/tc-ppc.c
|
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|
1a405f |
--- binutils.orig/gas/config/tc-ppc.c 2017-02-02 12:21:55.246930313 +0000
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|
|
1a405f |
+++ binutils-2.27/gas/config/tc-ppc.c 2017-02-02 12:29:13.568862941 +0000
|
|
|
1a405f |
@@ -2672,7 +2672,7 @@ md_assemble (char *str)
|
|
|
1a405f |
|
|
|
1a405f |
operand = &powerpc_operands[*opindex_ptr];
|
|
|
1a405f |
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
|
|
1a405f |
- && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
|
|
|
1a405f |
+ || (operand->flags & PPC_OPERAND_OPTIONAL32))
|
|
|
1a405f |
{
|
|
|
1a405f |
unsigned int opcount;
|
|
|
1a405f |
unsigned int num_operands_expected;
|
|
|
1a405f |
@@ -2741,8 +2741,8 @@ md_assemble (char *str)
|
|
|
1a405f |
|
|
|
1a405f |
/* If this is an optional operand, and we are skipping it, just
|
|
|
1a405f |
insert a zero. */
|
|
|
1a405f |
- if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
|
|
1a405f |
- && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
|
|
|
1a405f |
+ if (((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
|
|
1a405f |
+ || (operand->flags & PPC_OPERAND_OPTIONAL32) != 0)
|
|
|
1a405f |
&& skip_optional)
|
|
|
1a405f |
{
|
|
|
1a405f |
long val = ppc_optional_operand_value (operand);
|
|
|
1a405f |
diff -rup binutils-2.27.orig/gas/testsuite/gas/ppc/power6.d binutils-2.27/gas/testsuite/gas/ppc/power6.d
|
|
|
1a405f |
--- binutils-2.27.orig/gas/testsuite/gas/ppc/power6.d 2017-02-14 10:17:21.352033787 +0000
|
|
|
1a405f |
+++ binutils-2.27/gas/testsuite/gas/ppc/power6.d 2017-02-14 11:54:36.643091777 +0000
|
|
|
1a405f |
@@ -74,6 +74,6 @@ Disassembly of section \.text:
|
|
|
1a405f |
.*: (7c 00 03 e4|e4 03 00 7c) slbia
|
|
|
1a405f |
.*: (7c 00 03 e4|e4 03 00 7c) slbia
|
|
|
1a405f |
.*: (7c e0 03 e4|e4 03 e0 7c) slbia 7
|
|
|
1a405f |
-.*: (7c 00 52 64|64 52 00 7c) tlbie r10,0
|
|
|
1a405f |
+.*: (7c 00 52 64|64 52 00 7c) tlbie r10
|
|
|
1a405f |
.*: (7c 20 52 64|64 52 20 7c) tlbie r10,1
|
|
|
1a405f |
#pass
|
|
|
1a405f |
diff -rup binutils-2.27.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
|
|
|
1a405f |
--- binutils-2.27.orig/opcodes/ppc-opc.c 2017-02-14 10:17:22.281021961 +0000
|
|
|
1a405f |
+++ binutils-2.27/opcodes/ppc-opc.c 2017-02-14 11:58:50.035840144 +0000
|
|
|
1a405f |
@@ -576,9 +576,12 @@ const struct powerpc_operand powerpc_ope
|
|
|
1a405f |
#define RD RS
|
|
|
1a405f |
{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
|
|
|
1a405f |
|
|
|
1a405f |
+#define RSLL RS + 1
|
|
|
1a405f |
+ { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL32 },
|
|
|
1a405f |
+
|
|
|
1a405f |
/* The RS and RT fields of the DS form stq and DQ form lq instructions,
|
|
|
1a405f |
which have special value restrictions. */
|
|
|
1a405f |
-#define RSQ RS + 1
|
|
|
1a405f |
+#define RSQ RSLL + 1
|
|
|
1a405f |
#define RTQ RSQ
|
|
|
1a405f |
{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
|
|
|
1a405f |
|
|
|
1a405f |
@@ -5132,7 +5135,8 @@ const struct powerpc_opcode powerpc_opco
|
|
|
1a405f |
{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
|
|
|
1a405f |
|
|
|
1a405f |
{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
|
|
|
1a405f |
-{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER9|TITAN, {RB, L}},
|
|
|
1a405f |
+{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RSLL}},
|
|
|
1a405f |
+{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
|
|
|
1a405f |
{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
|
|
|
1a405f |
|
|
|
1a405f |
{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
|