|
|
32dd66 |
Patch carried over from the prior iasl package and updated. This allows
|
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|
32dd66 |
for builds on systems requiring aligned memory access. Please see
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|
32dd66 |
http://lists.acpica.org/pipermail/devel/2010-July/000159.html. Resolves
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|
|
32dd66 |
BZ#865013 and BZ#856856.
|
|
|
32dd66 |
--
|
|
|
32dd66 |
|
|
|
32dd66 |
Add more platforms to the list of the ones requiring aligned memory access.
|
|
|
32dd66 |
Also fix callsites where wrong assumptions where made in terms of aligment.
|
|
|
32dd66 |
|
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|
32dd66 |
Signed-off-by: Mattia Dongili <malattia@linux.it>
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|
32dd66 |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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|
32dd66 |
---
|
|
|
32dd66 |
source/compiler/asltree.c | 15 ++++++++++-----
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|
32dd66 |
source/components/executer/exoparg2.c | 12 +++++++++---
|
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|
32dd66 |
source/include/actypes.h | 26 +++++++++++++-------------
|
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|
32dd66 |
3 file modificati, 32 inserzioni(+), 21 rimozioni(-)
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|
32dd66 |
|
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|
32dd66 |
diff --git a/source/compiler/asltree.c b/source/compiler/asltree.c
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|
|
517133 |
index af67467..b7118b3 100644
|
|
|
32dd66 |
--- a/source/compiler/asltree.c
|
|
|
32dd66 |
+++ b/source/compiler/asltree.c
|
|
|
517133 |
@@ -913,28 +913,31 @@ TrCreateValuedLeafNode (
|
|
|
517133 |
"Op %s Value %8.8X%8.8X ",
|
|
|
32dd66 |
Op->Asl.LineNumber, Op->Asl.Column, Op, UtGetOpName(ParseOpcode),
|
|
|
32dd66 |
ACPI_FORMAT_UINT64 (Value));
|
|
|
32dd66 |
- Op->Asl.Value.Integer = Value;
|
|
|
32dd66 |
|
|
|
32dd66 |
switch (ParseOpcode)
|
|
|
32dd66 |
{
|
|
|
32dd66 |
case PARSEOP_STRING_LITERAL:
|
|
|
305057 |
|
|
|
32dd66 |
- DbgPrint (ASL_PARSE_OUTPUT, "STRING->%s", Value);
|
|
|
32dd66 |
+ Op->Asl.Value.String = (ACPI_STRING) (ACPI_SIZE) Value;
|
|
|
32dd66 |
+ DbgPrint (ASL_PARSE_OUTPUT, "STRING->%s", Op->Asl.Value.String);
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
|
|
|
32dd66 |
case PARSEOP_NAMESEG:
|
|
|
305057 |
|
|
|
32dd66 |
- DbgPrint (ASL_PARSE_OUTPUT, "NAMESEG->%s", Value);
|
|
|
32dd66 |
+ Op->Asl.Value.String = (ACPI_STRING) (ACPI_SIZE) Value;
|
|
|
32dd66 |
+ DbgPrint (ASL_PARSE_OUTPUT, "NAMESEG->%s", Op->Asl.Value.String);
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
|
|
|
32dd66 |
case PARSEOP_NAMESTRING:
|
|
|
305057 |
|
|
|
32dd66 |
- DbgPrint (ASL_PARSE_OUTPUT, "NAMESTRING->%s", Value);
|
|
|
32dd66 |
+ Op->Asl.Value.String = (ACPI_STRING) (ACPI_SIZE) Value;
|
|
|
32dd66 |
+ DbgPrint (ASL_PARSE_OUTPUT, "NAMESTRING->%s", Op->Asl.Value.String);
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
|
|
|
32dd66 |
case PARSEOP_EISAID:
|
|
|
305057 |
|
|
|
32dd66 |
- DbgPrint (ASL_PARSE_OUTPUT, "EISAID->%s", Value);
|
|
|
32dd66 |
+ Op->Asl.Value.String = (ACPI_STRING) (ACPI_SIZE) Value;
|
|
|
32dd66 |
+ DbgPrint (ASL_PARSE_OUTPUT, "EISAID->%s", Op->Asl.Value.String);
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
|
|
|
32dd66 |
case PARSEOP_METHOD:
|
|
|
517133 |
@@ -944,12 +947,14 @@ TrCreateValuedLeafNode (
|
|
|
32dd66 |
|
|
|
32dd66 |
case PARSEOP_INTEGER:
|
|
|
305057 |
|
|
|
32dd66 |
+ Op->Asl.Value.Integer = Value;
|
|
|
305057 |
DbgPrint (ASL_PARSE_OUTPUT, "INTEGER->%8.8X%8.8X",
|
|
|
305057 |
ACPI_FORMAT_UINT64 (Value));
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
|
|
|
32dd66 |
default:
|
|
|
305057 |
|
|
|
32dd66 |
+ Op->Asl.Value.Integer = Value;
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
}
|
|
|
32dd66 |
|
|
|
32dd66 |
diff --git a/source/components/executer/exoparg2.c b/source/components/executer/exoparg2.c
|
|
|
517133 |
index 7fe91a8..5c6af04 100644
|
|
|
32dd66 |
--- a/source/components/executer/exoparg2.c
|
|
|
32dd66 |
+++ b/source/components/executer/exoparg2.c
|
|
|
305057 |
@@ -172,6 +172,8 @@ AcpiExOpcode_2A_2T_1R (
|
|
|
32dd66 |
ACPI_OPERAND_OBJECT **Operand = &WalkState->Operands[0];
|
|
|
32dd66 |
ACPI_OPERAND_OBJECT *ReturnDesc1 = NULL;
|
|
|
32dd66 |
ACPI_OPERAND_OBJECT *ReturnDesc2 = NULL;
|
|
|
32dd66 |
+ UINT64 ReturnValue1 = 0;
|
|
|
32dd66 |
+ UINT64 ReturnValue2 = 0;
|
|
|
32dd66 |
ACPI_STATUS Status;
|
|
|
32dd66 |
|
|
|
32dd66 |
|
|
|
517133 |
@@ -206,8 +208,10 @@ AcpiExOpcode_2A_2T_1R (
|
|
|
517133 |
Status = AcpiUtDivide (
|
|
|
517133 |
Operand[0]->Integer.Value,
|
|
|
517133 |
Operand[1]->Integer.Value,
|
|
|
517133 |
- &ReturnDesc1->Integer.Value,
|
|
|
517133 |
- &ReturnDesc2->Integer.Value);
|
|
|
517133 |
+ &ReturnValue1, &ReturnValue2);
|
|
|
32dd66 |
+ ReturnDesc1->Integer.Value = ReturnValue1;
|
|
|
32dd66 |
+ ReturnDesc2->Integer.Value = ReturnValue2;
|
|
|
32dd66 |
+
|
|
|
32dd66 |
if (ACPI_FAILURE (Status))
|
|
|
32dd66 |
{
|
|
|
32dd66 |
goto Cleanup;
|
|
|
517133 |
@@ -282,6 +286,7 @@ AcpiExOpcode_2A_1T_1R (
|
|
|
32dd66 |
ACPI_OPERAND_OBJECT **Operand = &WalkState->Operands[0];
|
|
|
32dd66 |
ACPI_OPERAND_OBJECT *ReturnDesc = NULL;
|
|
|
32dd66 |
UINT64 Index;
|
|
|
32dd66 |
+ UINT64 ReturnValue = 0;
|
|
|
32dd66 |
ACPI_STATUS Status = AE_OK;
|
|
|
32dd66 |
ACPI_SIZE Length = 0;
|
|
|
32dd66 |
|
|
|
517133 |
@@ -327,7 +332,8 @@ AcpiExOpcode_2A_1T_1R (
|
|
|
517133 |
Operand[0]->Integer.Value,
|
|
|
517133 |
Operand[1]->Integer.Value,
|
|
|
517133 |
NULL,
|
|
|
517133 |
- &ReturnDesc->Integer.Value);
|
|
|
517133 |
+ &ReturnValue);
|
|
|
32dd66 |
+ ReturnDesc->Integer.Value = ReturnValue;
|
|
|
32dd66 |
break;
|
|
|
32dd66 |
|
|
|
32dd66 |
case AML_CONCAT_OP: /* Concatenate (Data1, Data2, Result) */
|
|
|
32dd66 |
diff --git a/source/include/actypes.h b/source/include/actypes.h
|
|
|
517133 |
index 395b915..137d93f 100644
|
|
|
32dd66 |
--- a/source/include/actypes.h
|
|
|
32dd66 |
+++ b/source/include/actypes.h
|
|
|
305057 |
@@ -143,6 +143,19 @@ typedef COMPILER_DEPENDENT_INT64 INT64;
|
|
|
32dd66 |
*/
|
|
|
32dd66 |
#define ACPI_THREAD_ID UINT64
|
|
|
32dd66 |
|
|
|
32dd66 |
+/*
|
|
|
32dd66 |
+ * In the case of the Itanium Processor Family (IPF), the hardware does not
|
|
|
32dd66 |
+ * support misaligned memory transfers. Set the MISALIGNMENT_NOT_SUPPORTED flag
|
|
|
32dd66 |
+ * to indicate that special precautions must be taken to avoid alignment faults.
|
|
|
32dd66 |
+ * (IA64 or ia64 is currently used by existing compilers to indicate IPF.)
|
|
|
32dd66 |
+ *
|
|
|
32dd66 |
+ * Note: EM64T and other X86-64 processors support misaligned transfers,
|
|
|
32dd66 |
+ * so there is no need to define this flag.
|
|
|
32dd66 |
+ */
|
|
|
32dd66 |
+#if defined (__IA64__) || defined (__ia64__) || defined(__alpha__) || defined(__sparc__) || defined(__hppa__) || defined(__arm__)
|
|
|
32dd66 |
+#define ACPI_MISALIGNMENT_NOT_SUPPORTED
|
|
|
32dd66 |
+#endif
|
|
|
32dd66 |
+
|
|
|
32dd66 |
|
|
|
32dd66 |
/*******************************************************************************
|
|
|
32dd66 |
*
|
|
|
482972 |
@@ -169,19 +182,6 @@ typedef UINT64 ACPI_PHYSICAL_ADDRESS;
|
|
|
32dd66 |
#define ACPI_SIZE_MAX ACPI_UINT64_MAX
|
|
|
32dd66 |
#define ACPI_USE_NATIVE_DIVIDE /* Has native 64-bit integer support */
|
|
|
32dd66 |
|
|
|
32dd66 |
-/*
|
|
|
32dd66 |
- * In the case of the Itanium Processor Family (IPF), the hardware does not
|
|
|
32dd66 |
- * support misaligned memory transfers. Set the MISALIGNMENT_NOT_SUPPORTED flag
|
|
|
32dd66 |
- * to indicate that special precautions must be taken to avoid alignment faults.
|
|
|
32dd66 |
- * (IA64 or ia64 is currently used by existing compilers to indicate IPF.)
|
|
|
32dd66 |
- *
|
|
|
32dd66 |
- * Note: EM64T and other X86-64 processors support misaligned transfers,
|
|
|
32dd66 |
- * so there is no need to define this flag.
|
|
|
32dd66 |
- */
|
|
|
32dd66 |
-#if defined (__IA64__) || defined (__ia64__)
|
|
|
32dd66 |
-#define ACPI_MISALIGNMENT_NOT_SUPPORTED
|
|
|
32dd66 |
-#endif
|
|
|
32dd66 |
-
|
|
|
32dd66 |
|
|
|
32dd66 |
/*******************************************************************************
|
|
|
32dd66 |
*
|