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From 655e723a5190206302f6cc4f2e794563b8e1c226 Mon Sep 17 00:00:00 2001
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From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
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Date: Wed, 24 Feb 2021 11:30:36 -0500
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Subject: [PATCH 3/4] x86/cpu: Populate SVM CPUID feature bits
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RH-Author: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Message-id: <20210224113037.15599-4-dgilbert@redhat.com>
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Patchwork-id: 101200
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O-Subject: [RHEL-8.4.0 qemu-kvm PATCH 3/4] x86/cpu: Populate SVM CPUID feature bits
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Bugzilla: 1790620
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Sergio Lopez Pascual <slp@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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From: Wei Huang <wei.huang2@amd.com>
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Newer AMD CPUs will add CPUID_0x8000000A_EDX[28] bit, which indicates
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that SVM instructions (VMRUN/VMSAVE/VMLOAD) will trigger #VMEXIT before
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CPU checking their EAX against reserved memory regions. This change will
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allow the hypervisor to avoid intercepting #GP and emulating SVM
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instructions. KVM turns on this CPUID bit for nested VMs. In order to
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support it, let us populate this bit, along with other SVM feature bits,
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in FEAT_SVM.
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Signed-off-by: Wei Huang <wei.huang2@amd.com>
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Message-Id: <20210126202456.589932-1-wei.huang2@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 5447089c2b3b084b51670af36fc86ee3979e04be)
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 6 +++---
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target/i386/cpu.h | 24 ++++++++++++++----------
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2 files changed, 17 insertions(+), 13 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index f6a9ed84b3..7227c803c3 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1026,11 +1026,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"npt", "lbrv", "svm-lock", "nrip-save",
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"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
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NULL, NULL, "pause-filter", NULL,
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- "pfthreshold", NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ "pfthreshold", "avic", NULL, "v-vmsave-vmload",
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+ "vgif", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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+ "svme-addr-chk", NULL, NULL, NULL,
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},
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.cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
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.tcg_features = TCG_SVM_FEATURES,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index f5a4efcec6..e1b67910c2 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -667,16 +667,20 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_EXT3_PERFCORE (1U << 23)
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#define CPUID_EXT3_PERFNB (1U << 24)
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-#define CPUID_SVM_NPT (1U << 0)
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-#define CPUID_SVM_LBRV (1U << 1)
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-#define CPUID_SVM_SVMLOCK (1U << 2)
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-#define CPUID_SVM_NRIPSAVE (1U << 3)
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-#define CPUID_SVM_TSCSCALE (1U << 4)
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-#define CPUID_SVM_VMCBCLEAN (1U << 5)
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-#define CPUID_SVM_FLUSHASID (1U << 6)
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-#define CPUID_SVM_DECODEASSIST (1U << 7)
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-#define CPUID_SVM_PAUSEFILTER (1U << 10)
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-#define CPUID_SVM_PFTHRESHOLD (1U << 12)
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+#define CPUID_SVM_NPT (1U << 0)
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+#define CPUID_SVM_LBRV (1U << 1)
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+#define CPUID_SVM_SVMLOCK (1U << 2)
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+#define CPUID_SVM_NRIPSAVE (1U << 3)
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+#define CPUID_SVM_TSCSCALE (1U << 4)
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+#define CPUID_SVM_VMCBCLEAN (1U << 5)
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+#define CPUID_SVM_FLUSHASID (1U << 6)
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+#define CPUID_SVM_DECODEASSIST (1U << 7)
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+#define CPUID_SVM_PAUSEFILTER (1U << 10)
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+#define CPUID_SVM_PFTHRESHOLD (1U << 12)
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+#define CPUID_SVM_AVIC (1U << 13)
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+#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
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+#define CPUID_SVM_VGIF (1U << 16)
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+#define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
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/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
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#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
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--
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2.27.0
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