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From 0d087d9d5276866b7a7c17cdb23e71b5636dc529 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 22 Nov 2019 11:53:43 +0000
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Subject: [PATCH 10/16] vmxcap: correct the name of the variables
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <20191122115348.25000-11-pbonzini@redhat.com>
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Patchwork-id: 92607
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O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 10/15] vmxcap: correct the name of the variables
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Bugzilla: 1689270
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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The low bits are 1 if the control must be one, the high bits
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are 1 if the control can be one. Correct the variable names
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as they are very confusing.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 49d51b8927a9ea7267f4677a2e92f5046ce74025)
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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scripts/kvm/vmxcap | 14 +++++++-------
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1 file changed, 7 insertions(+), 7 deletions(-)
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diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap
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index 99a8146..2db6832 100755
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--- a/scripts/kvm/vmxcap
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+++ b/scripts/kvm/vmxcap
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@@ -51,15 +51,15 @@ class Control(object):
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return (val & 0xffffffff, val >> 32)
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def show(self):
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print(self.name)
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- mbz, mb1 = self.read2(self.cap_msr)
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- tmbz, tmb1 = 0, 0
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+ mb1, cb1 = self.read2(self.cap_msr)
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+ tmb1, tcb1 = 0, 0
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if self.true_cap_msr:
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- tmbz, tmb1 = self.read2(self.true_cap_msr)
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+ tmb1, tcb1 = self.read2(self.true_cap_msr)
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for bit in sorted(self.bits.keys()):
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- zero = not (mbz & (1 << bit))
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- one = mb1 & (1 << bit)
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- true_zero = not (tmbz & (1 << bit))
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- true_one = tmb1 & (1 << bit)
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+ zero = not (mb1 & (1 << bit))
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+ one = cb1 & (1 << bit)
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+ true_zero = not (tmb1 & (1 << bit))
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+ true_one = tcb1 & (1 << bit)
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s= '?'
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if (self.true_cap_msr and true_zero and true_one
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and one and not zero):
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--
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1.8.3.1
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