From 3b97963ddb435e25f758032691cb2315570a2093 Mon Sep 17 00:00:00 2001

From: David Gibson <dgibson@redhat.com>

Date: Mon, 12 Nov 2018 01:28:32 +0000

Subject: [PATCH 01/16] target/ppc: add basic support for PTCR on POWER9

MIME-Version: 1.0

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RH-Author: David Gibson <dgibson@redhat.com>

Message-id: <20181112012835.21863-2-dgibson@redhat.com>

Patchwork-id: 82978

O-Subject: [RHEL-8 qemu-kvm PATCH 1/4] target/ppc: add basic support for PTCR on POWER9

Bugzilla: 1639069

RH-Acked-by: Laurent Vivier <lvivier@redhat.com>

RH-Acked-by: Serhii Popovych <spopovyc@redhat.com>

RH-Acked-by: Thomas Huth <thuth@redhat.com>

From: Cédric Le Goater <clg@kaod.org>

The Partition Table Control Register (PTCR) is a hypervisor privileged

SPR. It contains the host real address of the Partition Table and its

size.

Signed-off-by: Cédric Le Goater <clg@kaod.org>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

(cherry picked from commit 4a7518e0fdaa20525730ae0709a4afa0960a6c67)

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1639069

Signed-off-by: David Gibson <dgibson@redhat.com>

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 target/ppc/cpu.h            |  2 ++

 target/ppc/helper.h         |  1 +

 target/ppc/misc_helper.c    | 12 ++++++++++++

 target/ppc/mmu-book3s-v3.h  |  6 ++++++

 target/ppc/mmu_helper.c     | 29 +++++++++++++++++++++++++++++

 target/ppc/translate.c      |  3 +++

 target/ppc/translate_init.c | 18 ++++++++++++++++++

 7 files changed, 71 insertions(+)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h

index 1932c2e..8f3cf44 100644

--- a/target/ppc/cpu.h

+++ b/target/ppc/cpu.h

@@ -1313,6 +1313,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,

 #if !defined(CONFIG_USER_ONLY)

 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);

+void ppc_store_ptcr(CPUPPCState *env, target_ulong value);

 #endif /* !defined(CONFIG_USER_ONLY) */

 void ppc_store_msr (CPUPPCState *env, target_ulong value);

@@ -1604,6 +1605,7 @@ void ppc_compat_add_property(Object *obj, const char *name,

 #define SPR_BOOKE_GIVOR13     (0x1BC)

 #define SPR_BOOKE_GIVOR14     (0x1BD)

 #define SPR_TIR               (0x1BE)

+#define SPR_PTCR              (0x1D0)

 #define SPR_BOOKE_SPEFSCR     (0x200)

 #define SPR_Exxx_BBEAR        (0x201)

 #define SPR_Exxx_BBTAR        (0x202)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h

index 5b73917..19453c6 100644

--- a/target/ppc/helper.h

+++ b/target/ppc/helper.h

@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)

 #if !defined(CONFIG_USER_ONLY)

 #if defined(TARGET_PPC64)

 DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)

+DEF_HELPER_2(store_ptcr, void, env, tl)

 #endif

 DEF_HELPER_2(store_sdr1, void, env, tl)

 DEF_HELPER_2(store_pidr, void, env, tl)

diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c

index 0e42178..8c8cba5 100644

--- a/target/ppc/misc_helper.c

+++ b/target/ppc/misc_helper.c

@@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)

     }

 }

+#if defined(TARGET_PPC64)

+void helper_store_ptcr(CPUPPCState *env, target_ulong val)

+{

+    PowerPCCPU *cpu = ppc_env_get_cpu(env);

+

+    if (env->spr[SPR_PTCR] != val) {

+        ppc_store_ptcr(env, val);

+        tlb_flush(CPU(cpu));

+    }

+}

+#endif /* defined(TARGET_PPC64) */

+

 void helper_store_pidr(CPUPPCState *env, target_ulong val)

 {

     PowerPCCPU *cpu = ppc_env_get_cpu(env);

diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h

index 56095da..fdf8098 100644

--- a/target/ppc/mmu-book3s-v3.h

+++ b/target/ppc/mmu-book3s-v3.h

@@ -22,6 +22,12 @@

 #ifndef CONFIG_USER_ONLY

+/*

+ * Partition table definitions

+ */

+#define PTCR_PATB               0x0FFFFFFFFFFFF000ULL /* Partition Table Base */

+#define PTCR_PATS               0x000000000000001FULL /* Partition Table Size */

+

 /* Partition Table Entry Fields */

 #define PATBE1_GR 0x8000000000000000

diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c

index 5568d16..e2197a5 100644

--- a/target/ppc/mmu_helper.c

+++ b/target/ppc/mmu_helper.c

@@ -2028,6 +2028,35 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)

     env->spr[SPR_SDR1] = value;

 }

+#if defined(TARGET_PPC64)

+void ppc_store_ptcr(CPUPPCState *env, target_ulong value)

+{

+    PowerPCCPU *cpu = ppc_env_get_cpu(env);

+    target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;

+    target_ulong patbsize = value & PTCR_PATS;

+

+    qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);

+

+    assert(!cpu->vhyp);

+    assert(env->mmu_model & POWERPC_MMU_3_00);

+

+    if (value & ~ptcr_mask) {

+        error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",

+                     value & ~ptcr_mask);

+        value &= ptcr_mask;

+    }

+

+    if (patbsize > 24) {

+        error_report("Invalid Partition Table size 0x" TARGET_FMT_lx

+                     " stored in PTCR", patbsize);

+        return;

+    }

+

+    env->spr[SPR_PTCR] = value;

+}

+

+#endif /* defined(TARGET_PPC64) */

+

 /* Segment registers load and store */

 target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)

 {

diff --git a/target/ppc/translate.c b/target/ppc/translate.c

index 3457d29..7da9b67 100644

--- a/target/ppc/translate.c

+++ b/target/ppc/translate.c

@@ -7136,6 +7136,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,

         if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */

             cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);

         }

+        if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */

+            cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);

+        }

         cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",

                     env->spr[SPR_DAR], env->spr[SPR_DSISR]);

         break;

diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c

index 17b06c7..926efbc 100644

--- a/target/ppc/translate_init.c

+++ b/target/ppc/translate_init.c

@@ -420,6 +420,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)

     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));

     tcg_temp_free(t0);

 }

+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)

+{

+    gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);

+}

+

 #endif

 #endif

@@ -8167,6 +8172,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)

 #endif

 }

+static void gen_spr_power9_mmu(CPUPPCState *env)

+{

+#if !defined(CONFIG_USER_ONLY)

+    /* Partition Table Control */

+    spr_register_hv(env, SPR_PTCR, "PTCR",

+                    SPR_NOACCESS, SPR_NOACCESS,

+                    SPR_NOACCESS, SPR_NOACCESS,

+                    &spr_read_generic, &spr_write_ptcr,

+                    0x00000000);

+#endif

+}

+

 static void init_proc_book3s_common(CPUPPCState *env)

 {

     gen_spr_ne_601(env);

@@ -8761,6 +8778,7 @@ static void init_proc_POWER9(CPUPPCState *env)

     gen_spr_power8_ic(env);

     gen_spr_power8_book4(env);

     gen_spr_power8_rpr(env);

+    gen_spr_power9_mmu(env);

     /* POWER9 Specific registers */

     spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,

-- 

1.8.3.1