From 127410386296459cf3eec4b12d7451afc50d2503 Mon Sep 17 00:00:00 2001

From: Paolo Bonzini <pbonzini@redhat.com>

Date: Fri, 22 Nov 2019 11:53:36 +0000

Subject: [PATCH 03/16] target/i386: define a new MSR based feature word -

 FEAT_CORE_CAPABILITY

RH-Author: Paolo Bonzini <pbonzini@redhat.com>

Message-id: <20191122115348.25000-4-pbonzini@redhat.com>

Patchwork-id: 92603

O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 03/15] target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY

Bugzilla: 1689270

RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>

RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>

From: Xiaoyao Li <xiaoyao.li@linux.intel.com>

MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only

enumerates the feature split lock detection (via bit 5) by now.

The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30].

The latest kernel patches about them can be found here:

https://lkml.org/lkml/2019/4/24/1909

Signed-off-by: Xiaoyao Li <xiaoyao.li@linux.intel.com>

Message-Id: <20190617153654.916-1-xiaoyao.li@linux.intel.com>

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

(cherry picked from commit 597360c0d8ebda9ca6f239db724a25bddec62b2f)

RHEL: context

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 target/i386/cpu.c | 22 +++++++++++++++++++++-

 target/i386/cpu.h |  5 +++++

 target/i386/kvm.c |  9 +++++++++

 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c

index 8c1338f..52f1f33 100644

--- a/target/i386/cpu.c

+++ b/target/i386/cpu.c

@@ -1045,7 +1045,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {

             NULL, NULL, NULL, NULL,

             NULL, NULL, NULL, NULL,

             NULL, NULL, "spec-ctrl", "stibp",

-            NULL, "arch-capabilities", NULL, "ssbd",

+            NULL, "arch-capabilities", "core-capability", "ssbd",

         },

         .cpuid = {

             .eax = 7,

@@ -1163,6 +1163,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {

             }

         },

     },

+    [FEAT_CORE_CAPABILITY] = {

+        .type = MSR_FEATURE_WORD,

+        .feat_names = {

+            NULL, NULL, NULL, NULL,

+            NULL, "split-lock-detect", NULL, NULL,

+            NULL, NULL, NULL, NULL,

+            NULL, NULL, NULL, NULL,

+            NULL, NULL, NULL, NULL,

+            NULL, NULL, NULL, NULL,

+            NULL, NULL, NULL, NULL,

+            NULL, NULL, NULL, NULL,

+        },

+        .msr = {

+            .index = MSR_IA32_CORE_CAPABILITY,

+            .cpuid_dep = {

+                FEAT_7_0_EDX,

+                CPUID_7_0_EDX_CORE_CAPABILITY,

+            },

+        },

+    },

 };

 typedef struct X86RegisterInfo32 {

diff --git a/target/i386/cpu.h b/target/i386/cpu.h

index 1ad54bd..f9b93be 100644

--- a/target/i386/cpu.h

+++ b/target/i386/cpu.h

@@ -353,6 +353,7 @@ typedef enum X86Seg {

 #define MSR_IA32_SPEC_CTRL              0x48

 #define MSR_VIRT_SSBD                   0xc001011f

 #define MSR_IA32_PRED_CMD               0x49

+#define MSR_IA32_CORE_CAPABILITY        0xcf

 #define MSR_IA32_ARCH_CAPABILITIES      0x10a

 #define MSR_IA32_TSCDEADLINE            0x6e0

@@ -501,6 +502,7 @@ typedef enum FeatureWord {

     FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */

     FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */

     FEAT_ARCH_CAPABILITIES,

+    FEAT_CORE_CAPABILITY,

     FEATURE_WORDS,

 } FeatureWord;

@@ -690,6 +692,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];

 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

 #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */

 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/

+#define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)  /*Core Capability*/

 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */

 #define KVM_HINTS_DEDICATED (1U << 0)

@@ -744,6 +747,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];

 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)

 #define MSR_ARCH_CAP_SSB_NO     (1U << 4)

+#define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)

+

 #ifndef HYPERV_SPINLOCK_NEVER_RETRY

 #define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF

 #endif

diff --git a/target/i386/kvm.c b/target/i386/kvm.c

index da5f07e..849a11a 100644

--- a/target/i386/kvm.c

+++ b/target/i386/kvm.c

@@ -95,6 +95,7 @@ static bool has_msr_spec_ctrl;

 static bool has_msr_virt_ssbd;

 static bool has_msr_smi_count;

 static bool has_msr_arch_capabs;

+static bool has_msr_core_capabs;

 static uint32_t has_architectural_pmu_version;

 static uint32_t num_architectural_pmu_gp_counters;

@@ -1428,6 +1429,9 @@ static int kvm_get_supported_msrs(KVMState *s)

                 case MSR_IA32_ARCH_CAPABILITIES:

                     has_msr_arch_capabs = true;

                     break;

+                case MSR_IA32_CORE_CAPABILITY:

+                    has_msr_core_capabs = true;

+                    break;

                 }

             }

         }

@@ -1947,6 +1951,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level)

                           env->features[FEAT_ARCH_CAPABILITIES]);

     }

+    if (has_msr_core_capabs) {

+        kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,

+                          env->features[FEAT_CORE_CAPABILITY]);

+    }

+

     /*

      * The following MSRs have side effects on the guest or are too heavy

      * for normal writeback. Limit them to reset or full state updates.

-- 

1.8.3.1