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From 9875f9aaef996083064bf6a7afa1bfa30ff7d953 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Wed, 13 Dec 2017 15:43:40 -0200
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Subject: [PATCH 2/3] target-i386: add support for SPEC_CTRL MSR
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20171213174341.20684-3-ehabkost@redhat.com>
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Patchwork-id: n/a
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O-Subject: [CONFIDENTIAL][RHEL-7.5 qemu-kvm PATCH v2 2/3] target-i386: add
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support for SPEC_CTRL MSR
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Bugzilla: CVE-2017-5715
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target-i386/cpu.h | 4 ++++
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target-i386/kvm.c | 14 ++++++++++++++
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target-i386/machine.c | 21 +++++++++++++++++++++
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3 files changed, 39 insertions(+)
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 1e5c980..7d815cd 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -304,6 +304,7 @@
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_TSC_ADJUST 0x0000003b
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+#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define MSR_P6_PERFCTR0 0xc1
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@@ -963,6 +964,7 @@ typedef struct CPUX86State {
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uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
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uint64_t msr_gp_counters[MAX_GP_COUNTERS];
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uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
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+
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uint64_t msr_hv_hypercall;
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uint64_t msr_hv_guest_os_id;
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uint64_t msr_hv_vapic;
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@@ -1037,6 +1039,8 @@ typedef struct CPUX86State {
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uint32_t pkru;
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+ uint64_t spec_ctrl;
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+
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TPRAccess tpr_access_type;
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} CPUX86State;
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index 0dc0e79..24d17ad 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -77,6 +77,7 @@ static bool has_msr_hv_vapic;
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static bool has_msr_hv_tsc;
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static bool has_msr_mtrr;
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static bool has_msr_xss;
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+static bool has_msr_spec_ctrl;
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static bool has_msr_architectural_pmu;
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static uint32_t num_architectural_pmu_counters;
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@@ -800,6 +801,10 @@ static int kvm_get_supported_msrs(KVMState *s)
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has_msr_xss = true;
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continue;
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}
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+ if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) {
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+ has_msr_spec_ctrl = true;
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+ continue;
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+ }
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}
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}
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@@ -1187,6 +1192,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_xss) {
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
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}
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+ if (has_msr_spec_ctrl) {
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+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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+ }
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#ifdef TARGET_X86_64
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if (lm_capable_kernel) {
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kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
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@@ -1544,6 +1552,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_xss) {
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msrs[n++].index = MSR_IA32_XSS;
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}
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+ if (has_msr_spec_ctrl) {
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+ msrs[n++].index = MSR_IA32_SPEC_CTRL;
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+ }
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if (!env->tsc_valid) {
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@@ -1786,6 +1797,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
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}
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break;
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+ case MSR_IA32_SPEC_CTRL:
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+ env->spec_ctrl = msrs[i].data;
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+ break;
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}
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}
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diff --git a/target-i386/machine.c b/target-i386/machine.c
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index ba34088..d883c86 100644
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--- a/target-i386/machine.c
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+++ b/target-i386/machine.c
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@@ -742,6 +742,24 @@ static const VMStateDescription vmstate_pkru = {
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};
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#endif
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+static bool spec_ctrl_needed(void *opaque)
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+{
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+ X86CPU *cpu = opaque;
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+ CPUX86State *env = &cpu->env;
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+
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+ return env->spec_ctrl != 0;
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+}
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+
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+static const VMStateDescription vmstate_spec_ctrl = {
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+ .name = "cpu/spec_ctrl",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .fields = (VMStateField[]){
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+ VMSTATE_UINT64(env.spec_ctrl, X86CPU),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+
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const VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.version_id = 12,
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@@ -896,6 +914,9 @@ const VMStateDescription vmstate_x86_cpu = {
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.vmsd = &vmstate_pkru,
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.needed = pkru_needed,
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#endif
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+ }, {
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+ .vmsd = &vmstate_spec_ctrl,
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+ .needed = spec_ctrl_needed,
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} , {
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/* empty */
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}
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--
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1.8.3.1
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