From 4009f0bcc8004ce481015d088fe335a16b8d7ce1 Mon Sep 17 00:00:00 2001

From: Paolo Bonzini <pbonzini@redhat.com>

Date: Mon, 17 Feb 2020 16:23:12 +0000

Subject: [PATCH 2/9] target/i386: add a ucode-rev property

RH-Author: Paolo Bonzini <pbonzini@redhat.com>

Message-id: <20200217162316.2464-3-pbonzini@redhat.com>

Patchwork-id: 93909

O-Subject: [RHEL-AV-8.2.0 qemu-kvm PATCH 2/6] target/i386: add a ucode-rev property

Bugzilla: 1791648

RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>

RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>

RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

Add the property and plumb it in TCG and HVF (the latter of which

tried to support returning a constant value but used the wrong MSR).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Message-Id: <1579544504-3616-3-git-send-email-pbonzini@redhat.com>

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

(cherry picked from commit 4e45aff398cd1542c2a384a2a3b8600f23337d86)

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 target/i386/cpu.c         | 10 ++++++++++

 target/i386/cpu.h         |  3 +++

 target/i386/hvf/x86_emu.c |  4 +---

 target/i386/misc_helper.c |  4 ++++

 4 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c

index 863192c..e505d3e 100644

--- a/target/i386/cpu.c

+++ b/target/i386/cpu.c

@@ -6325,6 +6325,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)

         }

     }

+    if (cpu->ucode_rev == 0) {

+        /* The default is the same as KVM's.  */

+        if (IS_AMD_CPU(env)) {

+            cpu->ucode_rev = 0x01000065;

+        } else {

+            cpu->ucode_rev = 0x100000000ULL;

+        }

+    }

+

     /* mwait extended info: needed for Core compatibility */

     /* We always wake on interrupt even if host does not have the capability */

     cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;

@@ -7008,6 +7017,7 @@ static Property x86_cpu_properties[] = {

     DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),

     DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),

     DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),

+    DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),

     DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),

     DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),

     DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),

diff --git a/target/i386/cpu.h b/target/i386/cpu.h

index cde2a16..4441061 100644

--- a/target/i386/cpu.h

+++ b/target/i386/cpu.h

@@ -348,6 +348,7 @@ typedef enum X86Seg {

 #define MSR_IA32_SPEC_CTRL              0x48

 #define MSR_VIRT_SSBD                   0xc001011f

 #define MSR_IA32_PRED_CMD               0x49

+#define MSR_IA32_UCODE_REV              0x8b

 #define MSR_IA32_CORE_CAPABILITY        0xcf

 #define MSR_IA32_ARCH_CAPABILITIES      0x10a

@@ -1621,6 +1622,8 @@ struct X86CPU {

     CPUNegativeOffsetState neg;

     CPUX86State env;

+    uint64_t ucode_rev;

+

     uint32_t hyperv_spinlock_attempts;

     char *hyperv_vendor_id;

     bool hyperv_synic_kvm_only;

diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c

index 3df7672..92ab815 100644

--- a/target/i386/hvf/x86_emu.c

+++ b/target/i386/hvf/x86_emu.c

@@ -664,8 +664,6 @@ static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)

     RIP(env) += decode->len;

 }

-#define MSR_IA32_UCODE_REV 0x00000017

-

 void simulate_rdmsr(struct CPUState *cpu)

 {

     X86CPU *x86_cpu = X86_CPU(cpu);

@@ -681,7 +679,7 @@ void simulate_rdmsr(struct CPUState *cpu)

         val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);

         break;

     case MSR_IA32_UCODE_REV:

-        val = (0x100000000ULL << 32) | 0x100000000ULL;

+        val = x86_cpu->ucode_rev;

         break;

     case MSR_EFER:

         val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);

diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c

index 3eff688..aed16fe 100644

--- a/target/i386/misc_helper.c

+++ b/target/i386/misc_helper.c

@@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env)

 #else

 void helper_wrmsr(CPUX86State *env)

 {

+    X86CPU *x86_cpu = env_archcpu(env);

     uint64_t val;

     cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());

@@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env)

         env->msr_bndcfgs = val;

         cpu_sync_bndcs_hflags(env);

         break;

+     case MSR_IA32_UCODE_REV:

+        val = x86_cpu->ucode_rev;

+        break;

     default:

         if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL

             && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +

-- 

1.8.3.1