|
 |
ddf19c |
From 4009f0bcc8004ce481015d088fe335a16b8d7ce1 Mon Sep 17 00:00:00 2001
|
|
|
ddf19c |
From: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
ddf19c |
Date: Mon, 17 Feb 2020 16:23:12 +0000
|
|
|
ddf19c |
Subject: [PATCH 2/9] target/i386: add a ucode-rev property
|
|
|
ddf19c |
|
|
|
ddf19c |
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
ddf19c |
Message-id: <20200217162316.2464-3-pbonzini@redhat.com>
|
|
|
ddf19c |
Patchwork-id: 93909
|
|
|
ddf19c |
O-Subject: [RHEL-AV-8.2.0 qemu-kvm PATCH 2/6] target/i386: add a ucode-rev property
|
|
|
ddf19c |
Bugzilla: 1791648
|
|
|
ddf19c |
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
ddf19c |
RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
|
|
|
ddf19c |
RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
|
|
|
ddf19c |
|
|
|
ddf19c |
Add the property and plumb it in TCG and HVF (the latter of which
|
|
|
ddf19c |
tried to support returning a constant value but used the wrong MSR).
|
|
|
ddf19c |
|
|
|
ddf19c |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
ddf19c |
Message-Id: <1579544504-3616-3-git-send-email-pbonzini@redhat.com>
|
|
|
ddf19c |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
ddf19c |
(cherry picked from commit 4e45aff398cd1542c2a384a2a3b8600f23337d86)
|
|
|
ddf19c |
Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
|
|
|
ddf19c |
---
|
|
|
ddf19c |
target/i386/cpu.c | 10 ++++++++++
|
|
|
ddf19c |
target/i386/cpu.h | 3 +++
|
|
|
ddf19c |
target/i386/hvf/x86_emu.c | 4 +---
|
|
|
ddf19c |
target/i386/misc_helper.c | 4 ++++
|
|
|
ddf19c |
4 files changed, 18 insertions(+), 3 deletions(-)
|
|
|
ddf19c |
|
|
|
ddf19c |
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
|
|
ddf19c |
index 863192c..e505d3e 100644
|
|
|
ddf19c |
--- a/target/i386/cpu.c
|
|
|
ddf19c |
+++ b/target/i386/cpu.c
|
|
|
ddf19c |
@@ -6325,6 +6325,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
|
ddf19c |
}
|
|
|
ddf19c |
}
|
|
|
ddf19c |
|
|
|
ddf19c |
+ if (cpu->ucode_rev == 0) {
|
|
|
ddf19c |
+ /* The default is the same as KVM's. */
|
|
|
ddf19c |
+ if (IS_AMD_CPU(env)) {
|
|
|
ddf19c |
+ cpu->ucode_rev = 0x01000065;
|
|
|
ddf19c |
+ } else {
|
|
|
ddf19c |
+ cpu->ucode_rev = 0x100000000ULL;
|
|
|
ddf19c |
+ }
|
|
|
ddf19c |
+ }
|
|
|
ddf19c |
+
|
|
|
ddf19c |
/* mwait extended info: needed for Core compatibility */
|
|
|
ddf19c |
/* We always wake on interrupt even if host does not have the capability */
|
|
|
ddf19c |
cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
|
|
|
ddf19c |
@@ -7008,6 +7017,7 @@ static Property x86_cpu_properties[] = {
|
|
|
ddf19c |
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
|
|
|
ddf19c |
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
|
|
|
ddf19c |
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
|
|
|
ddf19c |
+ DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
|
|
|
ddf19c |
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
|
|
|
ddf19c |
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
|
|
|
ddf19c |
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
|
|
|
ddf19c |
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
|
|
ddf19c |
index cde2a16..4441061 100644
|
|
|
ddf19c |
--- a/target/i386/cpu.h
|
|
|
ddf19c |
+++ b/target/i386/cpu.h
|
|
|
ddf19c |
@@ -348,6 +348,7 @@ typedef enum X86Seg {
|
|
|
ddf19c |
#define MSR_IA32_SPEC_CTRL 0x48
|
|
|
ddf19c |
#define MSR_VIRT_SSBD 0xc001011f
|
|
|
ddf19c |
#define MSR_IA32_PRED_CMD 0x49
|
|
|
ddf19c |
+#define MSR_IA32_UCODE_REV 0x8b
|
|
|
ddf19c |
#define MSR_IA32_CORE_CAPABILITY 0xcf
|
|
|
ddf19c |
|
|
|
ddf19c |
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
|
|
|
ddf19c |
@@ -1621,6 +1622,8 @@ struct X86CPU {
|
|
|
ddf19c |
CPUNegativeOffsetState neg;
|
|
|
ddf19c |
CPUX86State env;
|
|
|
ddf19c |
|
|
|
ddf19c |
+ uint64_t ucode_rev;
|
|
|
ddf19c |
+
|
|
|
ddf19c |
uint32_t hyperv_spinlock_attempts;
|
|
|
ddf19c |
char *hyperv_vendor_id;
|
|
|
ddf19c |
bool hyperv_synic_kvm_only;
|
|
|
ddf19c |
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
|
|
|
ddf19c |
index 3df7672..92ab815 100644
|
|
|
ddf19c |
--- a/target/i386/hvf/x86_emu.c
|
|
|
ddf19c |
+++ b/target/i386/hvf/x86_emu.c
|
|
|
ddf19c |
@@ -664,8 +664,6 @@ static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
|
|
|
ddf19c |
RIP(env) += decode->len;
|
|
|
ddf19c |
}
|
|
|
ddf19c |
|
|
|
ddf19c |
-#define MSR_IA32_UCODE_REV 0x00000017
|
|
|
ddf19c |
-
|
|
|
ddf19c |
void simulate_rdmsr(struct CPUState *cpu)
|
|
|
ddf19c |
{
|
|
|
ddf19c |
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
|
ddf19c |
@@ -681,7 +679,7 @@ void simulate_rdmsr(struct CPUState *cpu)
|
|
|
ddf19c |
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
|
|
|
ddf19c |
break;
|
|
|
ddf19c |
case MSR_IA32_UCODE_REV:
|
|
|
ddf19c |
- val = (0x100000000ULL << 32) | 0x100000000ULL;
|
|
|
ddf19c |
+ val = x86_cpu->ucode_rev;
|
|
|
ddf19c |
break;
|
|
|
ddf19c |
case MSR_EFER:
|
|
|
ddf19c |
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
|
|
|
ddf19c |
diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
|
|
|
ddf19c |
index 3eff688..aed16fe 100644
|
|
|
ddf19c |
--- a/target/i386/misc_helper.c
|
|
|
ddf19c |
+++ b/target/i386/misc_helper.c
|
|
|
ddf19c |
@@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env)
|
|
|
ddf19c |
#else
|
|
|
ddf19c |
void helper_wrmsr(CPUX86State *env)
|
|
|
ddf19c |
{
|
|
|
ddf19c |
+ X86CPU *x86_cpu = env_archcpu(env);
|
|
|
ddf19c |
uint64_t val;
|
|
|
ddf19c |
|
|
|
ddf19c |
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
|
|
|
ddf19c |
@@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env)
|
|
|
ddf19c |
env->msr_bndcfgs = val;
|
|
|
ddf19c |
cpu_sync_bndcs_hflags(env);
|
|
|
ddf19c |
break;
|
|
|
ddf19c |
+ case MSR_IA32_UCODE_REV:
|
|
|
ddf19c |
+ val = x86_cpu->ucode_rev;
|
|
|
ddf19c |
+ break;
|
|
|
ddf19c |
default:
|
|
|
ddf19c |
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
|
|
|
ddf19c |
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
|
|
|
ddf19c |
--
|
|
|
ddf19c |
1.8.3.1
|
|
|
ddf19c |
|