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From a958a54a1072e201d209fd54e3fd0b55a331c5da Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 22 Nov 2019 11:53:47 +0000
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Subject: [PATCH 14/16] target/i386: add VMX features to named CPU models
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <20191122115348.25000-15-pbonzini@redhat.com>
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Patchwork-id: 92613
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O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 14/15] target/i386: add VMX features to named CPU models
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Bugzilla: 1689270
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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This allows using "-cpu Haswell,+vmx", which we did not really want to
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support in QEMU but was produced by Libvirt when using the "host-model"
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CPU model. Without this patch, no VMX feature is _actually_ supported
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(only the basic instruction set extensions are) and KVM fails to load
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in the guest.
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This was produced from the output of scripts/kvm/vmxcap using the following
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very ugly Python script:
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bits = {
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'INS/OUTS instruction information': ['FEAT_VMX_BASIC', 'MSR_VMX_BASIC_INS_OUTS'],
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'IA32_VMX_TRUE_*_CTLS support': ['FEAT_VMX_BASIC', 'MSR_VMX_BASIC_TRUE_CTLS'],
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'External interrupt exiting': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_EXT_INTR_MASK'],
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'NMI exiting': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_NMI_EXITING'],
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'Virtual NMIs': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_VIRTUAL_NMIS'],
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'Activate VMX-preemption timer': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_VMX_PREEMPTION_TIMER'],
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'Process posted interrupts': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_POSTED_INTR'],
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'Interrupt window exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_VIRTUAL_INTR_PENDING'],
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'Use TSC offsetting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_USE_TSC_OFFSETING'],
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'HLT exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_HLT_EXITING'],
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'INVLPG exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_INVLPG_EXITING'],
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'MWAIT exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MWAIT_EXITING'],
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'RDPMC exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_RDPMC_EXITING'],
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'RDTSC exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_RDTSC_EXITING'],
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'CR3-load exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR3_LOAD_EXITING'],
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'CR3-store exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR3_STORE_EXITING'],
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'CR8-load exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR8_LOAD_EXITING'],
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'CR8-store exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR8_STORE_EXITING'],
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'Use TPR shadow': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_TPR_SHADOW'],
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'NMI-window exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_VIRTUAL_NMI_PENDING'],
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'MOV-DR exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MOV_DR_EXITING'],
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'Unconditional I/O exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_UNCOND_IO_EXITING'],
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'Use I/O bitmaps': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_USE_IO_BITMAPS'],
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'Monitor trap flag': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MONITOR_TRAP_FLAG'],
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'Use MSR bitmaps': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_USE_MSR_BITMAPS'],
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'MONITOR exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MONITOR_EXITING'],
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'PAUSE exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_PAUSE_EXITING'],
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'Activate secondary control': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS'],
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'Virtualize APIC accesses': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES'],
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'Enable EPT': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_EPT'],
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'Descriptor-table exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_DESC'],
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'Enable RDTSCP': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_RDTSCP'],
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'Virtualize x2APIC mode': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE'],
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'Enable VPID': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_VPID'],
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'WBINVD exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_WBINVD_EXITING'],
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'Unrestricted guest': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST'],
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'APIC register emulation': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT'],
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'Virtual interrupt delivery': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY'],
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'PAUSE-loop exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING'],
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'RDRAND exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_RDRAND_EXITING'],
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'Enable INVPCID': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_INVPCID'],
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'Enable VM functions': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_VMFUNC'],
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'VMCS shadowing': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_SHADOW_VMCS'],
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'RDSEED exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_RDSEED_EXITING'],
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'Enable PML': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_PML'],
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'Enable XSAVES/XRSTORS': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_XSAVES'],
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'Save debug controls': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_DEBUG_CONTROLS'],
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'Load IA32_PERF_GLOBAL_CTRL': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL'],
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'Acknowledge interrupt on exit': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_ACK_INTR_ON_EXIT'],
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'Save IA32_PAT': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_IA32_PAT'],
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'Load IA32_PAT': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_LOAD_IA32_PAT'],
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'Save IA32_EFER': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_IA32_EFER'],
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'Load IA32_EFER': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_LOAD_IA32_EFER'],
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'Save VMX-preemption timer value': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER'],
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'Clear IA32_BNDCFGS': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_CLEAR_BNDCFGS'],
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'Load debug controls': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS'],
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'IA-32e mode guest': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_IA32E_MODE'],
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'Load IA32_PERF_GLOBAL_CTRL': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL'],
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'Load IA32_PAT': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_IA32_PAT'],
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'Load IA32_EFER': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_IA32_EFER'],
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'Load IA32_BNDCFGS': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_BNDCFGS'],
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'Store EFER.LMA into IA-32e mode guest control': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_STORE_LMA'],
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'HLT activity state': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_ACTIVITY_HLT'],
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'VMWRITE to VM-exit information fields': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_VMWRITE_VMEXIT'],
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'Inject event with insn length=0': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_ZERO_LEN_INJECT'],
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'Execute-only EPT translations': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_EXECONLY'],
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'Page-walk length 4': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_PAGE_WALK_LENGTH_4'],
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'Paging-structure memory type WB': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_WB'],
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'2MB EPT pages': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB'],
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'INVEPT supported': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVEPT'],
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'EPT accessed and dirty flags': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_AD_BITS'],
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'Single-context INVEPT': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT'],
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'All-context INVEPT': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVEPT_ALL_CONTEXT'],
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'INVVPID supported': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID'],
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'Individual-address INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_SINGLE_ADDR'],
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'Single-context INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT'],
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'All-context INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_ALL_CONTEXT'],
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'Single-context-retaining-globals INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS'],
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'EPTP Switching': ['FEAT_VMX_VMFUNC', 'MSR_VMX_VMFUNC_EPT_SWITCHING']
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}
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import sys
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import textwrap
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out = {}
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for l in sys.stdin.readlines():
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l = l.rstrip()
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if l.endswith('!!'):
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l = l[:-2].rstrip()
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if l.startswith(' ') and (l.endswith('default') or l.endswith('yes')):
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l = l[4:]
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for key, value in bits.items():
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if l.startswith(key):
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ctl, bit = value
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if ctl in out:
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out[ctl] = out[ctl] + ' | '
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else:
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out[ctl] = ' [%s] = ' % ctl
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out[ctl] = out[ctl] + bit
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for x in sorted(out.keys()):
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print("\n ".join(textwrap.wrap(out[x] + ",")))
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Note that the script has a bug in that some keys apply to both VM entry
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and VM exit controls ("load IA32_PERF_GLOBAL_CTRL", "load IA32_EFER",
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"load IA32_PAT". Those have to be fixed by hand.
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 0723cc8a5558c94388db75ae1f4991314914edd3)
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RHEL: no Denverton and Snowridge
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 617 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 617 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 9074a2e..36c9252 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1689,6 +1689,34 @@ static CPUCaches epyc_cache_info = {
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},
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};
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+/* The following VMX features are not supported by KVM and are left out in the
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+ * CPU definitions:
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+ *
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+ * Dual-monitor support (all processors)
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+ * Entry to SMM
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+ * Deactivate dual-monitor treatment
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+ * Number of CR3-target values
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+ * Shutdown activity state
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+ * Wait-for-SIPI activity state
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+ * PAUSE-loop exiting (Westmere and newer)
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+ * EPT-violation #VE (Broadwell and newer)
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+ * Inject event with insn length=0 (Skylake and newer)
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+ * Conceal non-root operation from PT
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+ * Conceal VM exits from PT
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+ * Conceal VM entries from PT
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+ * Enable ENCLS exiting
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+ * Mode-based execute control (XS/XU)
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+ s TSC scaling (Skylake Server and newer)
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+ * GPA translation for PT (IceLake and newer)
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+ * User wait and pause
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+ * ENCLV exiting
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+ * Load IA32_RTIT_CTL
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+ * Clear IA32_RTIT_CTL
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+ * Advanced VM-exit information for EPT violations
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+ * Sub-page write permissions
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+ * PT in VMX operation
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+ */
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+
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static X86CPUDefinition builtin_x86_defs[] = {
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{
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/* qemu64 is the default CPU model for all *-rhel7.* machine-types.
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@@ -1769,6 +1797,24 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM,
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+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
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+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
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+ .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
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+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
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+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
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+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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+ .features[FEAT_VMX_SECONDARY_CTLS] =
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016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -1796,6 +1842,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
|
|
|
016a62 |
.features[FEAT_8000_0001_ECX] =
|
|
|
016a62 |
0,
|
|
|
016a62 |
+ /* VMX features from Cedar Mill/Prescott */
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Common KVM processor"
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -1827,6 +1887,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT_SSE3,
|
|
|
016a62 |
.features[FEAT_8000_0001_ECX] =
|
|
|
016a62 |
0,
|
|
|
016a62 |
+ /* VMX features from Yonah */
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Common 32-bit KVM processor"
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -1848,6 +1921,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
|
|
|
016a62 |
.features[FEAT_8000_0001_EDX] =
|
|
|
016a62 |
CPUID_EXT2_NX,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -1977,6 +2062,24 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
|
|
016a62 |
.features[FEAT_8000_0001_ECX] =
|
|
|
016a62 |
CPUID_EXT3_LAHF_LM,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2000,6 +2103,27 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
|
|
|
016a62 |
.features[FEAT_8000_0001_ECX] =
|
|
|
016a62 |
CPUID_EXT3_LAHF_LM,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2023,6 +2147,46 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
|
|
|
016a62 |
.features[FEAT_8000_0001_ECX] =
|
|
|
016a62 |
CPUID_EXT3_LAHF_LM,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2074,6 +2238,47 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_EXT3_LAHF_LM,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2133,6 +2338,47 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2200,6 +2446,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2347,6 +2637,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Haswell)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2502,6 +2838,53 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XSAVEOPT,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Broadwell)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2587,6 +2970,51 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XGETBV1,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Skylake)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2682,6 +3110,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XGETBV1,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Xeon Processor (Skylake)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2785,6 +3261,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XGETBV1,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
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016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
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016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
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016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
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016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
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016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
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016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
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016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
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016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
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016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
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016a62 |
.xlevel = 0x80000008,
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016a62 |
.model_id = "Intel Xeon Processor (Cascadelake)",
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016a62 |
},
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016a62 |
@@ -2840,6 +3364,51 @@ static X86CPUDefinition builtin_x86_defs[] = {
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016a62 |
CPUID_XSAVE_XGETBV1,
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016a62 |
.features[FEAT_6_EAX] =
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016a62 |
CPUID_6_EAX_ARAT,
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016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
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016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
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016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
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|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
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|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
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|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Core Processor (Icelake)",
|
|
|
016a62 |
},
|
|
|
016a62 |
@@ -2898,6 +3467,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
|
|
|
016a62 |
CPUID_XSAVE_XGETBV1,
|
|
|
016a62 |
.features[FEAT_6_EAX] =
|
|
|
016a62 |
CPUID_6_EAX_ARAT,
|
|
|
016a62 |
+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
|
|
|
016a62 |
+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
|
|
|
016a62 |
+ MSR_VMX_BASIC_TRUE_CTLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
|
|
|
016a62 |
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
|
|
|
016a62 |
+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
|
|
|
016a62 |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
|
|
|
016a62 |
+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
|
|
|
016a62 |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
|
|
|
016a62 |
+ .features[FEAT_VMX_EXIT_CTLS] =
|
|
|
016a62 |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
|
|
|
016a62 |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
|
|
|
016a62 |
+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
|
|
|
016a62 |
+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
|
|
|
016a62 |
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
|
|
|
016a62 |
+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
|
|
|
016a62 |
+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
|
|
|
016a62 |
+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
|
|
|
016a62 |
+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
|
|
|
016a62 |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
|
|
|
016a62 |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
|
|
|
016a62 |
+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
|
|
|
016a62 |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
|
|
|
016a62 |
+ .features[FEAT_VMX_SECONDARY_CTLS] =
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
|
|
|
016a62 |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
|
|
|
016a62 |
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
|
|
|
016a62 |
.xlevel = 0x80000008,
|
|
|
016a62 |
.model_id = "Intel Xeon Processor (Icelake)",
|
|
|
016a62 |
},
|
|
|
016a62 |
--
|
|
|
016a62 |
1.8.3.1
|
|
|
016a62 |
|