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From 8587278a20283851081d4d282d11ef6bafd17dc2 Mon Sep 17 00:00:00 2001
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From: Julia Suvorova <jusual@redhat.com>
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Date: Tue, 17 Mar 2020 13:56:39 -0400
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Subject: [PATCH 1/2] pcie_root_port: Add hotplug disabling option
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Julia Suvorova <jusual@redhat.com>
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Message-id: <20200317135639.65085-1-jusual@redhat.com>
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Patchwork-id: 94367
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O-Subject: [RHEL-AV-8.2.1 qemu-kvm PATCH 1/1] pcie_root_port: Add hotplug disabling option
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Bugzilla: 1790899
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RH-Acked-by: Stefano Garzarella <sgarzare@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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BZ: https://bugzilla.redhat.com/show_bug.cgi?id=1790899
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BRANCH: rhel-av-8.2.1
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UPSTREAM: merged
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BREW: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=27302449
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Make hot-plug/hot-unplug on PCIe Root Ports optional to allow libvirt
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manage it and restrict unplug for the whole machine. This is going to
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prevent user-initiated unplug in guests (Windows mostly).
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Hotplug is enabled by default.
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Usage:
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-device pcie-root-port,hotplug=off,...
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If you want to disable hot-unplug on some downstream ports of one
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switch, disable hot-unplug on PCIe Root Port connected to the upstream
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port as well as on the selected downstream ports.
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Discussion related:
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https://lists.gnu.org/archive/html/qemu-devel/2020-02/msg00530.html
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Signed-off-by: Julia Suvorova <jusual@redhat.com>
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Message-Id: <20200226174607.205941-1-jusual@redhat.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Reviewed-by: Ján Tomko <jtomko@redhat.com>
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(cherry picked from commit 530a0963184e57e71a5b538e9161f115df533e96)
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Signed-off-by: Jon Maloy <jmaloy.redhat.com>
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---
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hw/pci-bridge/pcie_root_port.c | 2 +-
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hw/pci-bridge/xio3130_downstream.c | 2 +-
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hw/pci/pcie.c | 11 +++++++----
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hw/pci/pcie_port.c | 1 +
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include/hw/pci/pcie.h | 2 +-
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include/hw/pci/pcie_port.h | 3 +++
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6 files changed, 14 insertions(+), 7 deletions(-)
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diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
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index 012c2cb12c..db80e2ec23 100644
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--- a/hw/pci-bridge/pcie_root_port.c
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+++ b/hw/pci-bridge/pcie_root_port.c
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@@ -94,7 +94,7 @@ static void rp_realize(PCIDevice *d, Error **errp)
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pcie_cap_arifwd_init(d);
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pcie_cap_deverr_init(d);
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- pcie_cap_slot_init(d, s->slot);
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+ pcie_cap_slot_init(d, s);
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pcie_cap_root_init(d);
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pcie_chassis_create(s->chassis);
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diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
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index a9f084b863..4489ce4a40 100644
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--- a/hw/pci-bridge/xio3130_downstream.c
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+++ b/hw/pci-bridge/xio3130_downstream.c
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@@ -94,7 +94,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
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}
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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- pcie_cap_slot_init(d, s->slot);
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+ pcie_cap_slot_init(d, s);
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pcie_cap_arifwd_init(d);
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pcie_chassis_create(s->chassis);
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diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
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index 08718188bb..0eb3a2a5d2 100644
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--- a/hw/pci/pcie.c
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+++ b/hw/pci/pcie.c
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@@ -495,7 +495,7 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
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/* pci express slot for pci express root/downstream port
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PCI express capability slot registers */
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-void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
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+void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s)
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{
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uint32_t pos = dev->exp.exp_cap;
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@@ -505,13 +505,16 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
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pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
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~PCI_EXP_SLTCAP_PSN);
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
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- (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
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+ (s->slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
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PCI_EXP_SLTCAP_EIP |
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- PCI_EXP_SLTCAP_HPS |
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- PCI_EXP_SLTCAP_HPC |
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PCI_EXP_SLTCAP_PIP |
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PCI_EXP_SLTCAP_AIP |
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PCI_EXP_SLTCAP_ABP);
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+ if (s->hotplug) {
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+ pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
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+ PCI_EXP_SLTCAP_HPS |
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+ PCI_EXP_SLTCAP_HPC);
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+ }
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if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
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pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
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diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c
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index c19a9be592..36dac33d98 100644
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--- a/hw/pci/pcie_port.c
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+++ b/hw/pci/pcie_port.c
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@@ -147,6 +147,7 @@ static const TypeInfo pcie_port_type_info = {
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static Property pcie_slot_props[] = {
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DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
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DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
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+ DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true),
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DEFINE_PROP_END_OF_LIST()
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};
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diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
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index 7064875835..14c58ebdb6 100644
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--- a/include/hw/pci/pcie.h
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+++ b/include/hw/pci/pcie.h
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@@ -104,7 +104,7 @@ void pcie_cap_deverr_reset(PCIDevice *dev);
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void pcie_cap_lnkctl_init(PCIDevice *dev);
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void pcie_cap_lnkctl_reset(PCIDevice *dev);
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-void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
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+void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s);
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void pcie_cap_slot_reset(PCIDevice *dev);
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void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta);
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void pcie_cap_slot_write_config(PCIDevice *dev,
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diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h
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index 7515430087..7072cc8731 100644
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--- a/include/hw/pci/pcie_port.h
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+++ b/include/hw/pci/pcie_port.h
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@@ -55,6 +55,9 @@ struct PCIESlot {
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/* Disable ACS (really for a pcie_root_port) */
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bool disable_acs;
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+
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+ /* Indicates whether hot-plug is enabled on the slot */
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+ bool hotplug;
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QLIST_ENTRY(PCIESlot) next;
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};
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--
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2.18.2
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