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From e5f76077a47460bcba0bdfc1d70c7b79f84d18b7 Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Tue, 20 Aug 2019 00:24:33 +0100
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Subject: [PATCH 2/9] i386: Add CPUID bit and feature words for
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IA32_ARCH_CAPABILITIES MSR
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RH-Author: plai@redhat.com
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Message-id: <1566260680-20995-3-git-send-email-plai@redhat.com>
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Patchwork-id: 90066
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O-Subject: [RHEL8.0 qemu-kvm PATCH v3 2/9] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
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Bugzilla: 1718235
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: John Snow <jsnow@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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From: Robert Hoo <robert.hu@linux.intel.com>
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Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
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SPEC_CTRL.
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At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
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comment.
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Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
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Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit 3fc7c73139d2d38ae80c3b0bc963b1ac1555924c)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Resolved Conflicts:
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target/i386/cpu.c
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 3 ++-
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target/i386/cpu.h | 1 +
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index c979feb..6d38ac0 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1008,12 +1008,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, "spec-ctrl", "stibp",
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- NULL, NULL, NULL, "ssbd",
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+ NULL, "arch-capabilities", NULL, "ssbd",
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},
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.cpuid_eax = 7,
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.cpuid_needs_ecx = true, .cpuid_ecx = 0,
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.cpuid_reg = R_EDX,
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.tcg_features = TCG_7_0_EDX_FEATURES,
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+ .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
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},
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[FEAT_8000_0007_EDX] = {
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.feat_names = {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 1dc565c..e5e5169 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -687,6 +687,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
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+#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
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#define KVM_HINTS_DEDICATED (1U << 0)
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--
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1.8.3.1
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