From fbfa584e58a560f27081043ad8e90ee9022421c0 Mon Sep 17 00:00:00 2001

From: eperezma <eperezma@redhat.com>

Date: Tue, 12 Jan 2021 14:36:27 -0500

Subject: [PATCH 03/17] hw/arm/smmu-common: Add IOTLB helpers

MIME-Version: 1.0

Content-Type: text/plain; charset=UTF-8

Content-Transfer-Encoding: 8bit

RH-Author: eperezma <eperezma@redhat.com>

Message-id: <20210112143638.374060-3-eperezma@redhat.com>

Patchwork-id: 100595

O-Subject: [RHEL-8.4.0 qemu-kvm PATCH v2 02/13] hw/arm/smmu-common: Add IOTLB helpers

Bugzilla: 1843852

RH-Acked-by: Xiao Wang <jasowang@redhat.com>

RH-Acked-by: Peter Xu <peterx@redhat.com>

RH-Acked-by: Auger Eric <eric.auger@redhat.com>

From: Eric Auger <eric.auger@redhat.com>

Add two helpers: one to lookup for a given IOTLB entry and

one to insert a new entry. We also move the tracing there.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20200728150815.11446-3-eric.auger@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

(cherry picked from commit 6808bca939b8722d98165319ba42366ca80de907)

Signed-off-by: Eugenio Pérez <eperezma@redhat.com>

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 hw/arm/smmu-common.c         | 36 ++++++++++++++++++++++++++++++++++++

 hw/arm/smmuv3.c              | 26 ++------------------------

 hw/arm/trace-events          |  5 +++--

 include/hw/arm/smmu-common.h |  2 ++

 4 files changed, 43 insertions(+), 26 deletions(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c

index d2ba8b224ba..8e01505dbee 100644

--- a/hw/arm/smmu-common.c

+++ b/hw/arm/smmu-common.c

@@ -32,6 +32,42 @@

 /* IOTLB Management */

+IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,

+                                 hwaddr iova)

+{

+    SMMUIOTLBKey key = {.asid = cfg->asid, .iova = iova};

+    IOMMUTLBEntry *entry = g_hash_table_lookup(bs->iotlb, &key);

+

+    if (entry) {

+        cfg->iotlb_hits++;

+        trace_smmu_iotlb_lookup_hit(cfg->asid, iova,

+                                    cfg->iotlb_hits, cfg->iotlb_misses,

+                                    100 * cfg->iotlb_hits /

+                                    (cfg->iotlb_hits + cfg->iotlb_misses));

+    } else {

+        cfg->iotlb_misses++;

+        trace_smmu_iotlb_lookup_miss(cfg->asid, iova,

+                                     cfg->iotlb_hits, cfg->iotlb_misses,

+                                     100 * cfg->iotlb_hits /

+                                     (cfg->iotlb_hits + cfg->iotlb_misses));

+    }

+    return entry;

+}

+

+void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *entry)

+{

+    SMMUIOTLBKey *key = g_new0(SMMUIOTLBKey, 1);

+

+    if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {

+        smmu_iotlb_inv_all(bs);

+    }

+

+    key->asid = cfg->asid;

+    key->iova = entry->iova;

+    trace_smmu_iotlb_insert(cfg->asid, entry->iova);

+    g_hash_table_insert(bs->iotlb, key, entry);

+}

+

 inline void smmu_iotlb_inv_all(SMMUState *s)

 {

     trace_smmu_iotlb_inv_all();

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c

index e2fbb8357ea..34dea4df4da 100644

--- a/hw/arm/smmuv3.c

+++ b/hw/arm/smmuv3.c

@@ -624,7 +624,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

         .addr_mask = ~(hwaddr)0,

         .perm = IOMMU_NONE,

     };

-    SMMUIOTLBKey key, *new_key;

     qemu_mutex_lock(&s->mutex);

@@ -663,16 +662,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

     page_mask = (1ULL << (tt->granule_sz)) - 1;

     aligned_addr = addr & ~page_mask;

-    key.asid = cfg->asid;

-    key.iova = aligned_addr;

-

-    cached_entry = g_hash_table_lookup(bs->iotlb, &key);

+    cached_entry = smmu_iotlb_lookup(bs, cfg, aligned_addr);

     if (cached_entry) {

-        cfg->iotlb_hits++;

-        trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr,

-                                   cfg->iotlb_hits, cfg->iotlb_misses,

-                                   100 * cfg->iotlb_hits /

-                                   (cfg->iotlb_hits + cfg->iotlb_misses));

         if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) {

             status = SMMU_TRANS_ERROR;

             if (event.record_trans_faults) {

@@ -686,16 +677,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

         goto epilogue;

     }

-    cfg->iotlb_misses++;

-    trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask,

-                                cfg->iotlb_hits, cfg->iotlb_misses,

-                                100 * cfg->iotlb_hits /

-                                (cfg->iotlb_hits + cfg->iotlb_misses));

-

-    if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {

-        smmu_iotlb_inv_all(bs);

-    }

-

     cached_entry = g_new0(IOMMUTLBEntry, 1);

     if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {

@@ -741,10 +722,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

         }

         status = SMMU_TRANS_ERROR;

     } else {

-        new_key = g_new0(SMMUIOTLBKey, 1);

-        new_key->asid = cfg->asid;

-        new_key->iova = aligned_addr;

-        g_hash_table_insert(bs->iotlb, new_key, cached_entry);

+        smmu_iotlb_insert(bs, cfg, cached_entry);

         status = SMMU_TRANS_SUCCESS;

     }

diff --git a/hw/arm/trace-events b/hw/arm/trace-events

index 0acedcedc6f..b808a1bfc19 100644

--- a/hw/arm/trace-events

+++ b/hw/arm/trace-events

@@ -14,6 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all"

 smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"

 smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64

 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"

+smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"

+smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"

+smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=%d addr=0x%"PRIx64

 # smmuv3.c

 smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"

@@ -46,8 +49,6 @@ smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d a

 smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64

 smmuv3_cmdq_tlbi_nh(void) ""

 smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"

-smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"

-smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"

 smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"

 smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"

 smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h

index 1f37844e5c9..a28650c9350 100644

--- a/include/hw/arm/smmu-common.h

+++ b/include/hw/arm/smmu-common.h

@@ -153,6 +153,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);

 #define SMMU_IOTLB_MAX_SIZE 256

+IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova);

+void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *entry);

 void smmu_iotlb_inv_all(SMMUState *s);

 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);

 void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova);

-- 

2.27.0