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From 0f918da30dbb71e68e7fad4a2da8983b25536233 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 19 Jun 2015 10:45:29 +0200
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Subject: [PATCH] atomics: add explicit compiler fence in __atomic memory
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barriers
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Message-id: <1434710730-26183-1-git-send-email-pbonzini@redhat.com>
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Patchwork-id: 66333
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O-Subject: [RHEL7.2/7.1.z qemu-kvm PATCH] atomics: add explicit compiler fence in __atomic memory barriers
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Bugzilla: 1233643
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RH-Acked-by: Fam Zheng <famz@redhat.com>
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RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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__atomic_thread_fence does not include a compiler barrier; in the
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C++11 memory model, fences take effect in combination with other
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atomic operations. GCC implements this by making __atomic_load and
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__atomic_store access memory as if the pointer was volatile, and
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leaves no trace whatsoever of acquire and release fences in the
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compiler's intermediate representation.
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In QEMU, we want memory barriers to act on all memory, but at the same
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time we would like to use __atomic_thread_fence for portability reasons.
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Add compiler barriers manually around the __atomic_thread_fence.
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Thanks to Uli and Kevin for analyzing this bug!
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Message-Id: <1433334080-14912-1-git-send-email-pbonzini@redhat.com>
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Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 3bbf572345c65813f86a8fc434ea1b23beb08e16)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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include/qemu/atomic.h | 12 +++++++++---
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1 file changed, 9 insertions(+), 3 deletions(-)
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diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
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index 0aa8913..690d0d6 100644
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--- a/include/qemu/atomic.h
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+++ b/include/qemu/atomic.h
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@@ -99,7 +99,13 @@
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#ifndef smp_wmb
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#ifdef __ATOMIC_RELEASE
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-#define smp_wmb() __atomic_thread_fence(__ATOMIC_RELEASE)
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+/* __atomic_thread_fence does not include a compiler barrier; instead,
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+ * the barrier is part of __atomic_load/__atomic_store's "volatile-like"
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+ * semantics. If smp_wmb() is a no-op, absence of the barrier means that
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+ * the compiler is free to reorder stores on each side of the barrier.
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+ * Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
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+ */
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+#define smp_wmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); barrier(); })
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#else
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#define smp_wmb() __sync_synchronize()
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#endif
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@@ -107,7 +113,7 @@
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#ifndef smp_rmb
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#ifdef __ATOMIC_ACQUIRE
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-#define smp_rmb() __atomic_thread_fence(__ATOMIC_ACQUIRE)
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+#define smp_rmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); barrier(); })
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#else
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#define smp_rmb() __sync_synchronize()
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#endif
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@@ -115,7 +121,7 @@
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#ifndef smp_read_barrier_depends
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#ifdef __ATOMIC_CONSUME
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-#define smp_read_barrier_depends() __atomic_thread_fence(__ATOMIC_CONSUME)
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+#define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); barrier(); })
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#else
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#define smp_read_barrier_depends() barrier()
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#endif
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--
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1.8.3.1
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