render / rpms / qemu

Forked from rpms/qemu 10 months ago
Clone

Blame 0001-tcg-arm-Reduce-vector-alignment-requirement-for-NEON.patch

65ccb9
From 1331e4eec016a295949009b4360c592401b089f7 Mon Sep 17 00:00:00 2001
65ccb9
From: Richard Henderson <richard.henderson@linaro.org>
65ccb9
Date: Sun, 12 Sep 2021 10:49:25 -0700
65ccb9
Subject: [PATCH] tcg/arm: Reduce vector alignment requirement for NEON
65ccb9
65ccb9
With arm32, the ABI gives us 8-byte alignment for the stack.
65ccb9
While it's possible to realign the stack to provide 16-byte alignment,
65ccb9
it's far easier to simply not encode 16-byte alignment in the
65ccb9
VLD1 and VST1 instructions that we emit.
65ccb9
65ccb9
Remove the assertion in temp_allocate_frame, limit natural alignment
65ccb9
to the provided stack alignment, and add a comment.
65ccb9
65ccb9
Reported-by: Richard W.M. Jones <rjones@redhat.com>
65ccb9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
65ccb9
---
65ccb9
 tcg/arm/tcg-target.c.inc | 13 +++++++++----
65ccb9
 tcg/tcg.c                |  8 +++++++-
65ccb9
 2 files changed, 16 insertions(+), 5 deletions(-)
65ccb9
65ccb9
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
65ccb9
index 007ceee68e..34acfb522c 100644
65ccb9
--- a/tcg/arm/tcg-target.c.inc
65ccb9
+++ b/tcg/arm/tcg-target.c.inc
65ccb9
@@ -2477,8 +2477,13 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
65ccb9
         tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
65ccb9
         return;
65ccb9
     case TCG_TYPE_V128:
65ccb9
-        /* regs 2; size 8; align 16 */
65ccb9
-        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
65ccb9
+        /*
65ccb9
+         * We have only 8-byte alignment for the stack per the ABI.
65ccb9
+         * Rather than dynamically re-align the stack, it's easier
65ccb9
+         * to simply not request alignment beyond that.  So:
65ccb9
+         * regs 2; size 8; align 8
65ccb9
+         */
65ccb9
+        tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2);
65ccb9
         return;
65ccb9
     default:
65ccb9
         g_assert_not_reached();
65ccb9
@@ -2497,8 +2502,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
65ccb9
         tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
65ccb9
         return;
65ccb9
     case TCG_TYPE_V128:
65ccb9
-        /* regs 2; size 8; align 16 */
65ccb9
-        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
65ccb9
+        /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */
65ccb9
+        tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2);
65ccb9
         return;
65ccb9
     default:
65ccb9
         g_assert_not_reached();
65ccb9
diff --git a/tcg/tcg.c b/tcg/tcg.c
65ccb9
index 4142d42d77..ca5bcc4635 100644
65ccb9
--- a/tcg/tcg.c
65ccb9
+++ b/tcg/tcg.c
65ccb9
@@ -3060,7 +3060,13 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts)
65ccb9
         g_assert_not_reached();
65ccb9
     }
65ccb9
 
65ccb9
-    assert(align <= TCG_TARGET_STACK_ALIGN);
65ccb9
+    /*
65ccb9
+     * Assume the stack is sufficiently aligned.
65ccb9
+     * This affects e.g. ARM NEON, where we have 8 byte stack alignment
65ccb9
+     * and do not require 16 byte vector alignment.  This seems slightly
65ccb9
+     * easier than fully parameterizing the above switch statement.
65ccb9
+     */
65ccb9
+    align = MIN(TCG_TARGET_STACK_ALIGN, align);
65ccb9
     off = ROUND_UP(s->current_frame_offset, align);
65ccb9
 
65ccb9
     /* If we've exhausted the stack frame, restart with a smaller TB. */
65ccb9
-- 
65ccb9
2.32.0
65ccb9