From bba56fdd91409e93c9597e021481e8a9c089c819 Mon Sep 17 00:00:00 2001 From: CentOS Sources Date: Apr 23 2019 12:37:13 +0000 Subject: import libvirt-4.5.0-10.el7_6.7 --- diff --git a/SOURCES/libvirt-cpu-Don-t-access-invalid-memory-in-virCPUx86Translate.patch b/SOURCES/libvirt-cpu-Don-t-access-invalid-memory-in-virCPUx86Translate.patch new file mode 100644 index 0000000..aaf679b --- /dev/null +++ b/SOURCES/libvirt-cpu-Don-t-access-invalid-memory-in-virCPUx86Translate.patch @@ -0,0 +1,59 @@ +From b470757774a776e2bcbff50c7ae7f40323d10064 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Michal Privoznik +Date: Thu, 7 Mar 2019 14:17:01 +0100 +Subject: [PATCH] cpu: Don't access invalid memory in virCPUx86Translate +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Problem is that if there are no signatures for a CPU, then we +still allocate cpu->signatures (even though with size 0). Later, +we access cpu->signatures[0] if cpu->signatures is not NULL. + + Invalid read of size 4 + at 0x5F439D7: virCPUx86Translate (cpu_x86.c:2930) + by 0x5F3C239: virCPUTranslate (cpu.c:927) + by 0x57CE7A1: qemuProcessUpdateGuestCPU (qemu_process.c:5870) + ... + Address 0xf752d40 is 0 bytes after a block of size 0 alloc'd + at 0x4C30EC6: calloc (vg_replace_malloc.c:711) + by 0x5DBDE4E: virAllocN (viralloc.c:190) + by 0x5F3E4FA: x86ModelCopySignatures (cpu_x86.c:990) + by 0x5F3E60F: x86ModelCopy (cpu_x86.c:1008) + by 0x5F3E7CB: x86ModelFromCPU (cpu_x86.c:1068) + by 0x5F4397E: virCPUx86Translate (cpu_x86.c:2922) + by 0x5F3C239: virCPUTranslate (cpu.c:927) + by 0x57CE7A1: qemuProcessUpdateGuestCPU (qemu_process.c:5870) + ... + +Signed-off-by: Michal Privoznik +Reviewed-by: Jiri Denemark +(cherry picked from commit 62cb9c335c43a722e81ac0a1ed6e1111ba1d428b) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_x86.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c +index f6844aaa0d..466c79031d 100644 +--- a/src/cpu/cpu_x86.c ++++ b/src/cpu/cpu_x86.c +@@ -1021,6 +1021,9 @@ x86ModelCopySignatures(virCPUx86ModelPtr dst, + { + size_t i; + ++ if (src->nsignatures == 0) ++ return 0; ++ + if (VIR_ALLOC_N(dst->signatures, src->nsignatures) < 0) + return -1; + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-hex-representation-of-signatures.patch b/SOURCES/libvirt-cpu_map-Add-hex-representation-of-signatures.patch new file mode 100644 index 0000000..7746a87 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-hex-representation-of-signatures.patch @@ -0,0 +1,301 @@ +From d0fff22c96e56f72e05009b038fc8a80ae35a6ff Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Tue, 26 Feb 2019 09:22:36 +0100 +Subject: [PATCH] cpu_map: Add hex representation of signatures +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The family/model numbers are nice for humans or for comparing with +/proc/cpuinfo, but sometimes there's a need to see the CPUID +representation of the signature. Let's add it into a comment for each +signature in out cpu_map XMLs as the conversion is not exactly +straightforward. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 61be05a00fd383f11070761fac5ae28272b784dd) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu/cpu_map.xml + - the cpu_map split was not backported to RHEL-7.6 + - Icelake-Client and Icelake-Server models are missing + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 58 ++++++++++++++++++++++----------------------- + 1 file changed, 29 insertions(+), 29 deletions(-) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 9d53d4b43a..381068674c 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -789,7 +789,7 @@ + + + +- ++ + + + +@@ -821,7 +821,7 @@ + + + +- ++ + + + +@@ -855,7 +855,7 @@ + + + +- ++ + + + +@@ -891,7 +891,7 @@ + + + +- ++ + + + +@@ -928,7 +928,7 @@ + + + +- ++ + + + +@@ -965,7 +965,7 @@ + + + +- ++ + + + +@@ -1003,7 +1003,7 @@ + + + +- ++ + + + +@@ -1046,7 +1046,7 @@ + + + +- ++ + + + +@@ -1090,7 +1090,7 @@ + + + +- ++ + + + +@@ -1139,7 +1139,7 @@ + + + +- ++ + + + +@@ -1189,7 +1189,7 @@ + + + +- ++ + + + +@@ -1242,7 +1242,7 @@ + + + +- ++ + + + +@@ -1296,7 +1296,7 @@ + + + +- ++ + + + +@@ -1351,7 +1351,7 @@ + + + +- ++ + + + +@@ -1407,7 +1407,7 @@ + + + +- ++ + + + +@@ -1464,7 +1464,7 @@ + + + +- ++ + + + +@@ -1522,7 +1522,7 @@ + + + +- ++ + + + +@@ -1581,7 +1581,7 @@ + + + +- ++ + + + +@@ -1641,7 +1641,7 @@ + + + +- ++ + + + +@@ -1709,7 +1709,7 @@ + + + +- ++ + + + +@@ -1778,7 +1778,7 @@ + + + +- ++ + + + +@@ -1853,7 +1853,7 @@ + + + +- ++ + + + +@@ -1992,7 +1992,7 @@ + + + +- ++ + + + +@@ -2022,7 +2022,7 @@ + + + +- ++ + + + +@@ -2056,7 +2056,7 @@ + + + +- ++ + + + +@@ -2095,7 +2095,7 @@ + + + +- ++ + + + +@@ -2144,7 +2144,7 @@ + + + +- ++ + + + +@@ -2196,7 +2196,7 @@ + + + +- ++ + + + +@@ -2267,7 +2267,7 @@ + + + +- ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Broadwell-CPU-models.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Broadwell-CPU-models.patch new file mode 100644 index 0000000..4a962a1 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Broadwell-CPU-models.patch @@ -0,0 +1,254 @@ +From a4fe8dfb0c2df61f1b903e8858cd6430954f30e2 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Wed, 20 Mar 2019 17:15:16 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Broadwell CPU models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes several CPUs which were incorrectly detected as +Skylake-Client. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 4ff74a806ad42820eef3877c8ec146770914d8df) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Broadwell-IBRS.xml + src/cpu_map/x86_Broadwell-noTSX-IBRS.xml + src/cpu_map/x86_Broadwell-noTSX.xml + src/cpu_map/x86_Broadwell.xml + - cpu_map split not backported + + tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml + - context: intel-pt feature does not exist in RHEL-7.6 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 12 ++++++++++++ + .../x86_64-cpuid-Xeon-E5-2623-v4-guest.xml | 11 +++++++---- + .../x86_64-cpuid-Xeon-E5-2623-v4-json.xml | 11 +++++++---- + .../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 11 +++++++---- + .../x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 11 +++++++---- + .../x86_64-cpuid-Xeon-E5-2650-v4-guest.xml | 11 +++++++---- + .../x86_64-cpuid-Xeon-E5-2650-v4-json.xml | 11 +++++++---- + 7 files changed, 54 insertions(+), 24 deletions(-) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 7c6f70113e..095ea0a839 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -1434,6 +1434,9 @@ + + + ++ ++ ++ + + + +@@ -1491,6 +1494,9 @@ + + + ++ ++ ++ + + + +@@ -1549,6 +1555,9 @@ + + + ++ ++ ++ + + + +@@ -1608,6 +1617,9 @@ + + + ++ ++ ++ + + + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml +index d4f303ecce..e2ad344497 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-guest.xml +@@ -1,6 +1,7 @@ + +- Skylake-Client-IBRS ++ Broadwell-IBRS + Intel ++ + + + +@@ -18,14 +19,16 @@ + + + ++ ++ ++ + + + ++ + + + ++ + +- +- +- + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml +index 167a9028ab..de082dbd93 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2623-v4-json.xml +@@ -1,11 +1,14 @@ + +- Skylake-Client-IBRS ++ Broadwell-IBRS + Intel ++ + ++ ++ + ++ + ++ + +- +- +- ++ + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml +index 2fac54355c..c670b1f4df 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml +@@ -1,6 +1,7 @@ + +- Skylake-Client ++ Broadwell + Intel ++ + + + +@@ -18,13 +19,15 @@ + + + ++ ++ ++ + + ++ + + + ++ + +- +- +- + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml +index 5dfce947b2..5b8891093a 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml +@@ -1,11 +1,14 @@ + +- Skylake-Client ++ Broadwell + Intel ++ + ++ ++ + ++ + ++ + +- +- +- ++ + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml +index 2fac54355c..c670b1f4df 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-guest.xml +@@ -1,6 +1,7 @@ + +- Skylake-Client ++ Broadwell + Intel ++ + + + +@@ -18,13 +19,15 @@ + + + ++ ++ ++ + + ++ + + + ++ + +- +- +- + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml +index 5dfce947b2..5b8891093a 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-v4-json.xml +@@ -1,11 +1,14 @@ + +- Skylake-Client ++ Broadwell + Intel ++ + ++ ++ + ++ + ++ + +- +- +- ++ + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Conroe-CPU-model.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Conroe-CPU-model.patch new file mode 100644 index 0000000..ba9434b --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Conroe-CPU-model.patch @@ -0,0 +1,41 @@ +From 76c38a02c95057563349d6298aa70bde014b75c8 Mon Sep 17 00:00:00 2001 +Message-Id: <76c38a02c95057563349d6298aa70bde014b75c8@dist-git> +From: Jiri Denemark +Date: Tue, 26 Feb 2019 10:45:56 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Conroe CPU model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit c1f6a3269c595e7d3d0c9cf31ef7e6cf88291056) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Conroe.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 381068674c..df2a56ce58 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -790,6 +790,7 @@ + + + ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Haswell-CPU-models.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Haswell-CPU-models.patch new file mode 100644 index 0000000..b4cec74 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Haswell-CPU-models.patch @@ -0,0 +1,76 @@ +From b7208e290e2312156f8efbbffad31316d73d8a42 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Tue, 26 Feb 2019 12:06:05 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Haswell CPU models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit e58ca588cc0deee36c8ae44f2ad75bf9b1680fc5) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Haswell-IBRS.xml + src/cpu_map/x86_Haswell-noTSX-IBRS.xml + src/cpu_map/x86_Haswell-noTSX.xml + src/cpu_map/x86_Haswell.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 68cecf7ac0..7c6f70113e 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -1204,6 +1204,9 @@ + + + ++ ++ ++ + + + +@@ -1257,6 +1260,9 @@ + + + ++ ++ ++ + + + +@@ -1311,6 +1317,9 @@ + + + ++ ++ ++ + + + +@@ -1366,6 +1375,9 @@ + + + ++ ++ ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-IvyBridge-CPU-models.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-IvyBridge-CPU-models.patch new file mode 100644 index 0000000..c622d77 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-IvyBridge-CPU-models.patch @@ -0,0 +1,50 @@ +From 883cfd41ab4b39528ba94f272bd2d78e009aa92d Mon Sep 17 00:00:00 2001 +Message-Id: <883cfd41ab4b39528ba94f272bd2d78e009aa92d@dist-git> +From: Jiri Denemark +Date: Tue, 26 Feb 2019 12:22:00 +0100 +Subject: [PATCH] cpu_map: Add more signatures for IvyBridge CPU models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 194105fef1a3a8645486df3323e460cc4a9b2d4c) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_IvyBridge-IBRS.xml + src/cpu_map/x86_IvyBridge.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 8fe6d7d4f4..68cecf7ac0 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -1103,6 +1103,7 @@ + + + ++ + + + +@@ -1152,6 +1153,7 @@ + + + ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Nehalem-CPU-models.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Nehalem-CPU-models.patch new file mode 100644 index 0000000..df74a44 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Nehalem-CPU-models.patch @@ -0,0 +1,54 @@ +From a520258a7d3d6bf144b2fac4717bccee91d5d0ca Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Tue, 26 Feb 2019 12:59:37 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Nehalem CPU models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit f349f3c53f6427d9955ab7c57900c094f06dfd87) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Nehalem-IBRS.xml + src/cpu_map/x86_Nehalem.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 33994be6a4..8733834071 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -858,6 +858,9 @@ + + + ++ ++ ++ + + + +@@ -894,6 +897,9 @@ + + + ++ ++ ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Penryn-CPU-model.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Penryn-CPU-model.patch new file mode 100644 index 0000000..191ba46 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Penryn-CPU-model.patch @@ -0,0 +1,41 @@ +From 3c834c19e111e5df17ce7c4206d4c8213709e819 Mon Sep 17 00:00:00 2001 +Message-Id: <3c834c19e111e5df17ce7c4206d4c8213709e819@dist-git> +From: Jiri Denemark +Date: Tue, 26 Feb 2019 12:59:50 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Penryn CPU model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 0a09e59457f843b53c2702d1936bca6513868320) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Penryn.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index df2a56ce58..33994be6a4 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -823,6 +823,7 @@ + + + ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-SandyBridge-CPU-models.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-SandyBridge-CPU-models.patch new file mode 100644 index 0000000..97269e7 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-SandyBridge-CPU-models.patch @@ -0,0 +1,50 @@ +From 0b0c3aef9a537d9395d53806ac3695348a47dc09 Mon Sep 17 00:00:00 2001 +Message-Id: <0b0c3aef9a537d9395d53806ac3695348a47dc09@dist-git> +From: Jiri Denemark +Date: Tue, 26 Feb 2019 20:26:35 +0100 +Subject: [PATCH] cpu_map: Add more signatures for SandyBridge CPU models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 4a3c3682f3da4ae1e1036c67db7ddba3dcc66d68) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_SandyBridge-IBRS.xml + src/cpu_map/x86_SandyBridge.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 1435a34bb9..8fe6d7d4f4 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -1014,6 +1014,7 @@ + + + ++ + + + +@@ -1057,6 +1058,7 @@ + + + ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Skylake-Client-CPU-models.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Skylake-Client-CPU-models.patch new file mode 100644 index 0000000..ecdcd66 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Skylake-Client-CPU-models.patch @@ -0,0 +1,58 @@ +From 8760102a2e73747c6ae570c699c3da6752c9efb7 Mon Sep 17 00:00:00 2001 +Message-Id: <8760102a2e73747c6ae570c699c3da6752c9efb7@dist-git> +From: Jiri Denemark +Date: Tue, 26 Feb 2019 21:02:49 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Skylake-Client CPU models +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 367d96a5d6b04bf25d025ed59a7079d71f843c56) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Skylake-Client-IBRS.xml + src/cpu_map/x86_Skylake-Client.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 095ea0a839..1382c29cd1 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -1680,6 +1680,11 @@ + + + ++ ++ ++ ++ + + + +@@ -1748,6 +1753,11 @@ + + + ++ ++ ++ ++ + + + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Westmere-CPU-model.patch b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Westmere-CPU-model.patch new file mode 100644 index 0000000..252acd1 --- /dev/null +++ b/SOURCES/libvirt-cpu_map-Add-more-signatures-for-Westmere-CPU-model.patch @@ -0,0 +1,184 @@ +From c34ca3d596e641381b3397958be5f584f6318777 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Mon, 25 Feb 2019 16:44:11 +0100 +Subject: [PATCH] cpu_map: Add more signatures for Westmere CPU model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes several CPUs which were incorrectly detected as a different +CPU model. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit e89f87721406f6ad6e811ff613a22dc804d69355) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu_map/x86_Westmere.xml + - cpu_map split not backported + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_map.xml | 2 ++ + tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml | 9 +++++---- + tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml | 10 ++++++---- + tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml | 8 ++++---- + tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml | 8 +++++--- + tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml | 9 +++++---- + 6 files changed, 27 insertions(+), 19 deletions(-) + +diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml +index 8733834071..1435a34bb9 100644 +--- a/src/cpu/cpu_map.xml ++++ b/src/cpu/cpu_map.xml +@@ -937,6 +937,8 @@ + + + ++ ++ + + + +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml b/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml +index f5980f53e5..cb21e48a9f 100644 +--- a/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml ++++ b/tests/cputestdata/x86_64-cpuid-Core-i5-650-json.xml +@@ -1,12 +1,13 @@ + +- SandyBridge ++ Westmere + Intel + + ++ ++ ++ + + + +- +- +- ++ + +diff --git a/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml b/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml +index db5e0ae6af..20e2fa363a 100644 +--- a/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml ++++ b/tests/cputestdata/x86_64-cpuid-Pentium-P6100-guest.xml +@@ -1,6 +1,7 @@ + +- core2duo ++ Westmere + Intel ++ + + + +@@ -8,16 +9,17 @@ + + + ++ + + + +- + + + +- + + +- + ++ ++ ++ + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml +index dbf8580a0e..659779687a 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-guest.xml +@@ -1,5 +1,5 @@ + +- SandyBridge ++ Westmere + Intel + + +@@ -8,6 +8,7 @@ + + + ++ + + + +@@ -19,10 +20,9 @@ + + + ++ + + ++ + +- +- +- + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml +index d94a330f37..e8b74c5c30 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4820-json.xml +@@ -1,12 +1,14 @@ + +- SandyBridge ++ Westmere + Intel + + ++ + ++ ++ + + + +- +- ++ + +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml +index aae32bd7e2..da949ad25e 100644 +--- a/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7-4830-json.xml +@@ -1,14 +1,15 @@ + +- SandyBridge ++ Westmere + Intel + + ++ + ++ ++ + + + + +- +- +- ++ + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_x86-Add-x86ModelCopySignatures-helper.patch b/SOURCES/libvirt-cpu_x86-Add-x86ModelCopySignatures-helper.patch new file mode 100644 index 0000000..0b36a89 --- /dev/null +++ b/SOURCES/libvirt-cpu_x86-Add-x86ModelCopySignatures-helper.patch @@ -0,0 +1,83 @@ +From 53cf8a5c5e91132ac3d12bbe2e611594272bb30a Mon Sep 17 00:00:00 2001 +Message-Id: <53cf8a5c5e91132ac3d12bbe2e611594272bb30a@dist-git> +From: Jiri Denemark +Date: Mon, 4 Mar 2019 16:18:42 +0100 +Subject: [PATCH] cpu_x86: Add x86ModelCopySignatures helper +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Introduce a helper for copying CPU signature between two CPU models. + +It's not very useful until the way we store signatures is changed in the +next patch. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 2254c1cfb854dfc52f3b4bfdfca2bd995b0a163c) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu/cpu_x86.c + - other patches separating parts of x86ModelParse into + smaller functions were not backported due to conflicts + with older refactoring which is missing in RHEL-7 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_x86.c | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c +index 668e8aa3f0..e54a3986a1 100644 +--- a/src/cpu/cpu_x86.c ++++ b/src/cpu/cpu_x86.c +@@ -1013,6 +1013,16 @@ x86ModelFree(virCPUx86ModelPtr model) + } + + ++static int ++x86ModelCopySignatures(virCPUx86ModelPtr dst, ++ virCPUx86ModelPtr src) ++{ ++ dst->signature = src->signature; ++ ++ return 0; ++} ++ ++ + static virCPUx86ModelPtr + x86ModelCopy(virCPUx86ModelPtr model) + { +@@ -1020,13 +1030,13 @@ x86ModelCopy(virCPUx86ModelPtr model) + + if (VIR_ALLOC(copy) < 0 || + VIR_STRDUP(copy->name, model->name) < 0 || ++ x86ModelCopySignatures(copy, model) < 0 || + x86DataCopy(©->data, &model->data) < 0) { + x86ModelFree(copy); + return NULL; + } + + copy->vendor = model->vendor; +- copy->signature = model->signature; + + return copy; + } +@@ -1260,8 +1270,8 @@ x86ModelParse(xmlXPathContextPtr ctxt, + VIR_FREE(name); + + model->vendor = ancestor->vendor; +- model->signature = ancestor->signature; +- if (x86DataCopy(&model->data, &ancestor->data) < 0) ++ if (x86ModelCopySignatures(model, ancestor) < 0 || ++ x86DataCopy(&model->data, &ancestor->data) < 0) + goto error; + } + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_x86-Allow-multiple-signatures-for-a-CPU-model.patch b/SOURCES/libvirt-cpu_x86-Allow-multiple-signatures-for-a-CPU-model.patch new file mode 100644 index 0000000..4939755 --- /dev/null +++ b/SOURCES/libvirt-cpu_x86-Allow-multiple-signatures-for-a-CPU-model.patch @@ -0,0 +1,130 @@ +From ac2924813141609b07860a0df5c6bd56eddf0b3e Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Fri, 22 Feb 2019 17:20:59 +0100 +Subject: [PATCH] cpu_x86: Allow multiple signatures for a CPU model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +CPU signatures in the cpu_map serve as a hint for CPUID to CPU model +matching algorithm. If the CPU signatures matches any CPU model in the +cpu_map, this model will be the preferred one. + +This works out well and solved several mismatches, but in real world +CPUs which should match a single CPU model may be produced with several +different signatures. For example, low voltage Broadwell CPUs for +laptops and Broadwell CPUs for servers differ in CPU model numbers while +we should detect them all as Broadwell CPU model. + +This patch adds support for storing several signatures for a single CPU +model to make this hint useful for more CPUs. Later commits will provide +additional signatures for existing CPU models, which will correct some +results in our CPU test suite. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit dfeb3e598438a891a05487c34e6723d1d3ed9256) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu/cpu_x86.c + - most refactoring was not backported + - VIR_AUTOFREE is not in RHEL-7.6 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_x86.c | 44 ++++++++++++++++++++++++++++++-------------- + 1 file changed, 30 insertions(+), 14 deletions(-) + +diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c +index 543533148f..f6844aaa0d 100644 +--- a/src/cpu/cpu_x86.c ++++ b/src/cpu/cpu_x86.c +@@ -1204,41 +1204,57 @@ x86ModelCompare(virCPUx86ModelPtr model1, + + + static int +-x86ModelParseSignature(virCPUx86ModelPtr model, +- xmlXPathContextPtr ctxt) ++x86ModelParseSignatures(virCPUx86ModelPtr model, ++ xmlXPathContextPtr ctxt) + { ++ xmlNodePtr *nodes = NULL; ++ xmlNodePtr root = ctxt->node; ++ size_t i; ++ int n; ++ int ret = -1; ++ ++ if ((n = virXPathNodeSet("./signature", ctxt, &nodes)) <= 0) ++ return n; ++ + /* Remove inherited signatures. */ + VIR_FREE(model->signatures); + +- if (virXPathBoolean("boolean(./signature)", ctxt)) { ++ model->nsignatures = n; ++ if (VIR_ALLOC_N(model->signatures, n) < 0) ++ goto cleanup; ++ ++ for (i = 0; i < n; i++) { + unsigned int sigFamily = 0; + unsigned int sigModel = 0; + int rc; + +- model->nsignatures = 1; +- if (VIR_ALLOC_N(model->signatures, 1) < 0) +- return -1; ++ ctxt->node = nodes[i]; + +- rc = virXPathUInt("string(./signature/@family)", ctxt, &sigFamily); ++ rc = virXPathUInt("string(@family)", ctxt, &sigFamily); + if (rc < 0 || sigFamily == 0) { + virReportError(VIR_ERR_INTERNAL_ERROR, + _("Invalid CPU signature family in model %s"), + model->name); +- return -1; ++ goto cleanup; + } + +- rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel); ++ rc = virXPathUInt("string(@model)", ctxt, &sigModel); + if (rc < 0 || sigModel == 0) { + virReportError(VIR_ERR_INTERNAL_ERROR, + _("Invalid CPU signature model in model %s"), + model->name); +- return -1; ++ goto cleanup; + } + +- model->signatures[0] = x86MakeSignature(sigFamily, sigModel, 0); ++ model->signatures[i] = x86MakeSignature(sigFamily, sigModel, 0); + } + +- return 0; ++ ctxt->node = root; ++ ret = 0; ++ ++ cleanup: ++ VIR_FREE(nodes); ++ return ret; + } + + +@@ -1290,8 +1306,8 @@ x86ModelParse(xmlXPathContextPtr ctxt, + goto error; + } + +- if (x86ModelParseSignature(model, ctxt) < 0) +- goto error; ++ if (x86ModelParseSignatures(model, ctxt) < 0) ++ goto cleanup; + + if (virXPathBoolean("boolean(./vendor)", ctxt)) { + vendor = virXPathString("string(./vendor/@name)", ctxt); +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_x86-Log-decoded-CPU-model-and-signatures.patch b/SOURCES/libvirt-cpu_x86-Log-decoded-CPU-model-and-signatures.patch new file mode 100644 index 0000000..de561c5 --- /dev/null +++ b/SOURCES/libvirt-cpu_x86-Log-decoded-CPU-model-and-signatures.patch @@ -0,0 +1,91 @@ +From 8877885f067aaa87b7ab42de914de5e50f4ef32d Mon Sep 17 00:00:00 2001 +Message-Id: <8877885f067aaa87b7ab42de914de5e50f4ef32d@dist-git> +From: Jiri Denemark +Date: Mon, 4 Mar 2019 16:37:31 +0100 +Subject: [PATCH] cpu_x86: Log decoded CPU model and signatures +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The log message may be useful when debugging why a specific CPU model +was selected for a given set of CPUID data. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 5ced12decea42f1d588f2cb28b10ca7a5772098e) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu/cpu_x86.c + - VIR_AUTOFREE is not in RHEL-7.6 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_x86.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c +index 466c79031d..cf3d80eeb5 100644 +--- a/src/cpu/cpu_x86.c ++++ b/src/cpu/cpu_x86.c +@@ -1821,6 +1821,26 @@ x86ModelHasSignature(virCPUx86ModelPtr model, + } + + ++static char * ++x86FormatSignatures(virCPUx86ModelPtr model) ++{ ++ virBuffer buf = VIR_BUFFER_INITIALIZER; ++ size_t i; ++ ++ for (i = 0; i < model->nsignatures; i++) { ++ virBufferAsprintf(&buf, "%06lx,", ++ (unsigned long)model->signatures[i]); ++ } ++ ++ virBufferTrim(&buf, ",", -1); ++ ++ if (virBufferCheckError(&buf) < 0) ++ return NULL; ++ ++ return virBufferContentAndReset(&buf); ++} ++ ++ + /* + * Checks whether a candidate model is a better fit for the CPU data than the + * current model. +@@ -1944,6 +1964,7 @@ x86Decode(virCPUDefPtr cpu, + virCPUx86Data features = VIR_CPU_X86_DATA_INIT; + virCPUx86VendorPtr vendor; + virDomainCapsCPUModelPtr hvModel = NULL; ++ char *sigs = NULL; + uint32_t signature; + ssize_t i; + int rc; +@@ -2036,6 +2057,11 @@ x86Decode(virCPUDefPtr cpu, + if (vendor && VIR_STRDUP(cpu->vendor, vendor->name) < 0) + goto cleanup; + ++ sigs = x86FormatSignatures(model); ++ ++ VIR_DEBUG("Using CPU model %s (signatures %s) for CPU with signature %06lx", ++ model->name, NULLSTR(sigs), (unsigned long)signature); ++ + VIR_STEAL_PTR(cpu->model, cpuModel->model); + VIR_STEAL_PTR(cpu->features, cpuModel->features); + cpu->nfeatures = cpuModel->nfeatures; +@@ -2050,6 +2076,7 @@ x86Decode(virCPUDefPtr cpu, + virCPUx86DataClear(&data); + virCPUx86DataClear(©); + virCPUx86DataClear(&features); ++ VIR_FREE(sigs); + return ret; + } + +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_x86-Separate-signature-parsing-from-x86ModelParse.patch b/SOURCES/libvirt-cpu_x86-Separate-signature-parsing-from-x86ModelParse.patch new file mode 100644 index 0000000..0ab1498 --- /dev/null +++ b/SOURCES/libvirt-cpu_x86-Separate-signature-parsing-from-x86ModelParse.patch @@ -0,0 +1,112 @@ +From 054fbe2bdd426eb9f3346513ac7d39f0b843a04e Mon Sep 17 00:00:00 2001 +Message-Id: <054fbe2bdd426eb9f3346513ac7d39f0b843a04e@dist-git> +From: Jiri Denemark +Date: Wed, 20 Mar 2019 14:55:20 +0100 +Subject: [PATCH] cpu_x86: Separate signature parsing from x86ModelParse +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The code is separated into a new x86ModelParseSignature function. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit fe78d2fda9f2dd67eb9daa98e48fbffa468d271e) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + src/cpu/cpu_x86.c + - other patches separating parts of x86ModelParse into + smaller functions were not backported due to conflicts + with older refactoring which is missing in RHEL-7 + - commit 118fcdd480ad38a3e8477f466f6a876dce7e9fa6 changing + goto labels from "cleanup" to "error" was not backported + because the goto statement is removed in this patch anyway + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_x86.c | 58 ++++++++++++++++++++++++++++------------------- + 1 file changed, 35 insertions(+), 23 deletions(-) + +diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c +index 809da94117..668e8aa3f0 100644 +--- a/src/cpu/cpu_x86.c ++++ b/src/cpu/cpu_x86.c +@@ -1184,6 +1184,39 @@ x86ModelCompare(virCPUx86ModelPtr model1, + } + + ++static int ++x86ModelParseSignature(virCPUx86ModelPtr model, ++ xmlXPathContextPtr ctxt) ++{ ++ ++ if (virXPathBoolean("boolean(./signature)", ctxt)) { ++ unsigned int sigFamily = 0; ++ unsigned int sigModel = 0; ++ int rc; ++ ++ rc = virXPathUInt("string(./signature/@family)", ctxt, &sigFamily); ++ if (rc < 0 || sigFamily == 0) { ++ virReportError(VIR_ERR_INTERNAL_ERROR, ++ _("Invalid CPU signature family in model %s"), ++ model->name); ++ return -1; ++ } ++ ++ rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel); ++ if (rc < 0 || sigModel == 0) { ++ virReportError(VIR_ERR_INTERNAL_ERROR, ++ _("Invalid CPU signature model in model %s"), ++ model->name); ++ return -1; ++ } ++ ++ model->signature = x86MakeSignature(sigFamily, sigModel, 0); ++ } ++ ++ return 0; ++} ++ ++ + static virCPUx86ModelPtr + x86ModelParse(xmlXPathContextPtr ctxt, + virCPUx86MapPtr map) +@@ -1232,29 +1265,8 @@ x86ModelParse(xmlXPathContextPtr ctxt, + goto error; + } + +- if (virXPathBoolean("boolean(./signature)", ctxt)) { +- unsigned int sigFamily = 0; +- unsigned int sigModel = 0; +- int rc; +- +- rc = virXPathUInt("string(./signature/@family)", ctxt, &sigFamily); +- if (rc < 0 || sigFamily == 0) { +- virReportError(VIR_ERR_INTERNAL_ERROR, +- _("Invalid CPU signature family in model %s"), +- model->name); +- goto cleanup; +- } +- +- rc = virXPathUInt("string(./signature/@model)", ctxt, &sigModel); +- if (rc < 0 || sigModel == 0) { +- virReportError(VIR_ERR_INTERNAL_ERROR, +- _("Invalid CPU signature model in model %s"), +- model->name); +- goto cleanup; +- } +- +- model->signature = x86MakeSignature(sigFamily, sigModel, 0); +- } ++ if (x86ModelParseSignature(model, ctxt) < 0) ++ goto error; + + if (virXPathBoolean("boolean(./vendor)", ctxt)) { + vendor = virXPathString("string(./vendor/@name)", ctxt); +-- +2.21.0 + diff --git a/SOURCES/libvirt-cpu_x86-Store-CPU-signature-in-an-array.patch b/SOURCES/libvirt-cpu_x86-Store-CPU-signature-in-an-array.patch new file mode 100644 index 0000000..0de43e8 --- /dev/null +++ b/SOURCES/libvirt-cpu_x86-Store-CPU-signature-in-an-array.patch @@ -0,0 +1,161 @@ +From 892d1dd5115d91c9ca527a5be954087f390b6159 Mon Sep 17 00:00:00 2001 +Message-Id: <892d1dd5115d91c9ca527a5be954087f390b6159@dist-git> +From: Jiri Denemark +Date: Mon, 4 Mar 2019 16:36:33 +0100 +Subject: [PATCH] cpu_x86: Store CPU signature in an array +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In preparation for storing several CPU signatures in a single CPU model, +we need to turn virCPUx86Model's signature into an array of signatures. + +The parser still hardcodes the number of signatures to 1, but the +following patch will drop this limit. + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit b07b8b7750c6a505d4b00bd272e79ea0305cb610) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + src/cpu/cpu_x86.c | 50 ++++++++++++++++++++++++++++++++++++++--------- + 1 file changed, 41 insertions(+), 9 deletions(-) + +diff --git a/src/cpu/cpu_x86.c b/src/cpu/cpu_x86.c +index e54a3986a1..543533148f 100644 +--- a/src/cpu/cpu_x86.c ++++ b/src/cpu/cpu_x86.c +@@ -136,7 +136,8 @@ typedef virCPUx86Model *virCPUx86ModelPtr; + struct _virCPUx86Model { + char *name; + virCPUx86VendorPtr vendor; +- uint32_t signature; ++ size_t nsignatures; ++ uint32_t *signatures; + virCPUx86Data data; + }; + +@@ -1008,6 +1009,7 @@ x86ModelFree(virCPUx86ModelPtr model) + return; + + VIR_FREE(model->name); ++ VIR_FREE(model->signatures); + virCPUx86DataClear(&model->data); + VIR_FREE(model); + } +@@ -1017,7 +1019,14 @@ static int + x86ModelCopySignatures(virCPUx86ModelPtr dst, + virCPUx86ModelPtr src) + { +- dst->signature = src->signature; ++ size_t i; ++ ++ if (VIR_ALLOC_N(dst->signatures, src->nsignatures) < 0) ++ return -1; ++ ++ dst->nsignatures = src->nsignatures; ++ for (i = 0; i < src->nsignatures; i++) ++ dst->signatures[i] = src->signatures[i]; + + return 0; + } +@@ -1198,12 +1207,18 @@ static int + x86ModelParseSignature(virCPUx86ModelPtr model, + xmlXPathContextPtr ctxt) + { ++ /* Remove inherited signatures. */ ++ VIR_FREE(model->signatures); + + if (virXPathBoolean("boolean(./signature)", ctxt)) { + unsigned int sigFamily = 0; + unsigned int sigModel = 0; + int rc; + ++ model->nsignatures = 1; ++ if (VIR_ALLOC_N(model->signatures, 1) < 0) ++ return -1; ++ + rc = virXPathUInt("string(./signature/@family)", ctxt, &sigFamily); + if (rc < 0 || sigFamily == 0) { + virReportError(VIR_ERR_INTERNAL_ERROR, +@@ -1220,7 +1235,7 @@ x86ModelParseSignature(virCPUx86ModelPtr model, + return -1; + } + +- model->signature = x86MakeSignature(sigFamily, sigModel, 0); ++ model->signatures[0] = x86MakeSignature(sigFamily, sigModel, 0); + } + + return 0; +@@ -1665,7 +1680,8 @@ x86Compute(virCPUDefPtr host, + &host_model->vendor->cpuid) < 0) + goto error; + +- if (x86DataAddSignature(&guest_model->data, host_model->signature) < 0) ++ if (host_model->signatures && ++ x86DataAddSignature(&guest_model->data, *host_model->signatures) < 0) + goto error; + + if (cpu->type == VIR_CPU_TYPE_GUEST +@@ -1771,6 +1787,21 @@ virCPUx86Compare(virCPUDefPtr host, + } + + ++static bool ++x86ModelHasSignature(virCPUx86ModelPtr model, ++ uint32_t signature) ++{ ++ size_t i; ++ ++ for (i = 0; i < model->nsignatures; i++) { ++ if (model->signatures[i] == signature) ++ return true; ++ } ++ ++ return false; ++} ++ ++ + /* + * Checks whether a candidate model is a better fit for the CPU data than the + * current model. +@@ -1812,8 +1843,8 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current, + * consider candidates with matching family/model. + */ + if (signature && +- current->signature == signature && +- candidate->signature != signature) { ++ x86ModelHasSignature(current, signature) && ++ !x86ModelHasSignature(candidate, signature)) { + VIR_DEBUG("%s differs in signature from matching %s", + cpuCandidate->model, cpuCurrent->model); + return 0; +@@ -1829,8 +1860,8 @@ x86DecodeUseCandidate(virCPUx86ModelPtr current, + * result in longer list of features. + */ + if (signature && +- candidate->signature == signature && +- current->signature != signature) { ++ x86ModelHasSignature(candidate, signature) && ++ !x86ModelHasSignature(current, signature)) { + VIR_DEBUG("%s provides matching signature", cpuCandidate->model); + return 1; + } +@@ -2898,7 +2929,8 @@ virCPUx86Translate(virCPUDefPtr cpu, + virCPUx86DataAddCPUIDInt(&model->data, &model->vendor->cpuid) < 0) + goto cleanup; + +- if (x86DataAddSignature(&model->data, model->signature) < 0) ++ if (model->signatures && ++ x86DataAddSignature(&model->data, model->signatures[0]) < 0) + goto cleanup; + + if (!(translated = virCPUDefCopyWithoutModel(cpu))) +-- +2.21.0 + diff --git a/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-7600U.patch b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-7600U.patch new file mode 100644 index 0000000..f45c70a --- /dev/null +++ b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-7600U.patch @@ -0,0 +1,982 @@ +From 7a985e4dbab5d6e71e4371c6c961e9f0773d964e Mon Sep 17 00:00:00 2001 +Message-Id: <7a985e4dbab5d6e71e4371c6c961e9f0773d964e@dist-git> +From: Jiri Denemark +Date: Thu, 21 Feb 2019 22:14:53 +0100 +Subject: [PATCH] cputest: Add data for Intel(R) Core(TM) i7-7600U +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit cd11ea73d01b256437e25bc635c51d08518c8c77) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml + tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml + tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml + - intel-pt and umip features do not exist in RHEL-7.6 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + tests/cputest.c | 1 + + .../x86_64-cpuid-Core-i7-7600U-disabled.xml | 6 + + .../x86_64-cpuid-Core-i7-7600U-enabled.xml | 8 + + .../x86_64-cpuid-Core-i7-7600U-guest.xml | 27 + + .../x86_64-cpuid-Core-i7-7600U-host.xml | 28 + + .../x86_64-cpuid-Core-i7-7600U-json.xml | 12 + + .../x86_64-cpuid-Core-i7-7600U.json | 755 ++++++++++++++++++ + .../x86_64-cpuid-Core-i7-7600U.xml | 47 ++ + 8 files changed, 884 insertions(+) + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml + +diff --git a/tests/cputest.c b/tests/cputest.c +index 8bb801859e..926ae8b533 100644 +--- a/tests/cputest.c ++++ b/tests/cputest.c +@@ -1176,6 +1176,7 @@ mymain(void) + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U-arat", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U-ibrs", JSON_HOST); ++ DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-7600U", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-7700", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-E6850", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-Q9500", JSON_NONE); +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml +new file mode 100644 +index 0000000000..0a567bbfae +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-disabled.xml +@@ -0,0 +1,6 @@ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml +new file mode 100644 +index 0000000000..b1cdaa802a +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-enabled.xml +@@ -0,0 +1,8 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml +new file mode 100644 +index 0000000000..141c01c841 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-guest.xml +@@ -0,0 +1,27 @@ ++ ++ Skylake-Client-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml +new file mode 100644 +index 0000000000..53bfc9728d +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-host.xml +@@ -0,0 +1,28 @@ ++ ++ x86_64 ++ Skylake-Client-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml +new file mode 100644 +index 0000000000..f2c23b6b19 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U-json.xml +@@ -0,0 +1,12 @@ ++ ++ Skylake-Client-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json +new file mode 100644 +index 0000000000..9a258e6be3 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.json +@@ -0,0 +1,755 @@ ++{ ++ "return": { ++ "model": { ++ "name": "base", ++ "props": { ++ "phys-bits": 0, ++ "core-id": -1, ++ "xlevel": 2147483656, ++ "cmov": true, ++ "ia64": false, ++ "ssb-no": false, ++ "aes": true, ++ "mmx": true, ++ "rdpid": false, ++ "arat": true, ++ "gfni": false, ++ "ibrs-all": false, ++ "pause-filter": false, ++ "xsavec": true, ++ "intel-pt": false, ++ "hv-frequencies": false, ++ "tsc-frequency": 0, ++ "xd": true, ++ "hv-vendor-id": "", ++ "kvm-asyncpf": true, ++ "kvm_asyncpf": true, ++ "perfctr_core": false, ++ "perfctr-core": false, ++ "mpx": true, ++ "pbe": false, ++ "decodeassists": false, ++ "avx512cd": false, ++ "sse4_1": true, ++ "sse4.1": true, ++ "sse4-1": true, ++ "family": 6, ++ "legacy-cache": true, ++ "vmware-cpuid-freq": true, ++ "wbnoinvd": false, ++ "avx512f": false, ++ "msr": true, ++ "mce": true, ++ "mca": true, ++ "hv-runtime": false, ++ "xcrypt": false, ++ "thread-id": -1, ++ "min-level": 13, ++ "xgetbv1": true, ++ "cid": false, ++ "hv-relaxed": false, ++ "hv-crash": false, ++ "ds": false, ++ "fxsr": true, ++ "xsaveopt": true, ++ "xtpr": false, ++ "hv-evmcs": false, ++ "avx512vl": false, ++ "avx512-vpopcntdq": false, ++ "phe": false, ++ "extapic": false, ++ "3dnowprefetch": true, ++ "avx512vbmi2": false, ++ "cr8legacy": false, ++ "cpuid-0xb": true, ++ "xcrypt-en": false, ++ "kvm_pv_eoi": true, ++ "apic-id": 4294967295, ++ "rsba": false, ++ "pn": false, ++ "dca": false, ++ "vendor": "GenuineIntel", ++ "hv-ipi": false, ++ "pku": false, ++ "smx": false, ++ "cmp_legacy": false, ++ "cmp-legacy": false, ++ "node-id": -1, ++ "avx512-4fmaps": false, ++ "vmcb_clean": false, ++ "vmcb-clean": false, ++ "3dnowext": false, ++ "amd-no-ssb": false, ++ "hle": true, ++ "npt": false, ++ "rdctl-no": false, ++ "memory": "/machine/unattached/system[0]", ++ "clwb": false, ++ "lbrv": false, ++ "adx": true, ++ "ss": true, ++ "pni": true, ++ "svm_lock": false, ++ "svm-lock": false, ++ "pfthreshold": false, ++ "smep": true, ++ "smap": true, ++ "x2apic": true, ++ "avx512vbmi": false, ++ "avx512vnni": false, ++ "hv-stimer": false, ++ "x-hv-synic-kvm-only": false, ++ "i64": true, ++ "flushbyasid": false, ++ "f16c": true, ++ "ace2-en": false, ++ "pat": true, ++ "pae": true, ++ "sse": true, ++ "phe-en": false, ++ "kvm_nopiodelay": true, ++ "kvm-nopiodelay": true, ++ "tm": false, ++ "kvmclock-stable-bit": true, ++ "hypervisor": true, ++ "socket-id": -1, ++ "pcommit": false, ++ "syscall": true, ++ "level": 13, ++ "avx512dq": false, ++ "x-migrate-smi-count": true, ++ "svm": false, ++ "full-cpuid-auto-level": true, ++ "hv-reset": false, ++ "invtsc": false, ++ "sse3": true, ++ "sse2": true, ++ "ssbd": true, ++ "est": false, ++ "avx512ifma": false, ++ "tm2": false, ++ "kvm-pv-ipi": true, ++ "kvm-pv-eoi": true, ++ "cx8": true, ++ "cldemote": false, ++ "hv-reenlightenment": false, ++ "kvm_mmu": false, ++ "kvm-mmu": false, ++ "sse4_2": true, ++ "sse4.2": true, ++ "sse4-2": true, ++ "pge": true, ++ "fill-mtrr-mask": true, ++ "avx512bitalg": false, ++ "nodeid_msr": false, ++ "pdcm": false, ++ "movbe": true, ++ "model": 142, ++ "nrip_save": false, ++ "nrip-save": false, ++ "kvm_pv_unhalt": true, ++ "ssse3": true, ++ "sse4a": false, ++ "invpcid": true, ++ "pdpe1gb": true, ++ "tsc-deadline": true, ++ "skip-l1dfl-vmentry": true, ++ "fma": true, ++ "cx16": true, ++ "de": true, ++ "pconfig": false, ++ "enforce": false, ++ "stepping": 9, ++ "xsave": true, ++ "clflush": true, ++ "skinit": false, ++ "tsc": true, ++ "tce": false, ++ "fpu": true, ++ "ibs": false, ++ "ds_cpl": false, ++ "ds-cpl": false, ++ "host-phys-bits": false, ++ "fma4": false, ++ "la57": false, ++ "osvw": false, ++ "check": true, ++ "hv-spinlocks": -1, ++ "pmu": false, ++ "pmm": false, ++ "apic": true, ++ "spec-ctrl": true, ++ "min-xlevel2": 0, ++ "tsc-adjust": true, ++ "tsc_adjust": true, ++ "kvm-steal-time": true, ++ "kvm_steal_time": true, ++ "kvmclock": true, ++ "l3-cache": true, ++ "lwp": false, ++ "amd-ssbd": false, ++ "ibpb": false, ++ "xop": false, ++ "avx": true, ++ "ace2": false, ++ "avx512bw": false, ++ "acpi": false, ++ "hv-vapic": false, ++ "fsgsbase": true, ++ "ht": false, ++ "nx": true, ++ "pclmulqdq": true, ++ "mmxext": false, ++ "vaes": false, ++ "popcnt": true, ++ "xsaves": true, ++ "tcg-cpuid": true, ++ "lm": true, ++ "umip": true, ++ "pse": true, ++ "avx2": true, ++ "sep": true, ++ "pclmuldq": true, ++ "virt-ssbd": false, ++ "x-hv-max-vps": -1, ++ "nodeid-msr": false, ++ "kvm": true, ++ "misalignsse": false, ++ "min-xlevel": 2147483656, ++ "kvm-pv-unhalt": true, ++ "bmi2": true, ++ "bmi1": true, ++ "realized": false, ++ "tsc_scale": false, ++ "tsc-scale": false, ++ "topoext": false, ++ "hv-vpindex": false, ++ "xlevel2": 0, ++ "clflushopt": true, ++ "kvm-no-smi-migration": false, ++ "monitor": false, ++ "avx512er": false, ++ "pmm-en": false, ++ "pcid": true, ++ "arch-capabilities": false, ++ "3dnow": false, ++ "erms": true, ++ "lahf-lm": true, ++ "lahf_lm": true, ++ "vpclmulqdq": false, ++ "fxsr-opt": false, ++ "hv-synic": false, ++ "xstore": false, ++ "fxsr_opt": false, ++ "kvm-hint-dedicated": false, ++ "rtm": true, ++ "lmce": true, ++ "hv-time": false, ++ "perfctr-nb": false, ++ "perfctr_nb": false, ++ "ffxsr": false, ++ "hv-tlbflush": false, ++ "rdrand": true, ++ "rdseed": true, ++ "avx512-4vnniw": false, ++ "vmx": true, ++ "vme": true, ++ "dtes64": false, ++ "mtrr": true, ++ "rdtscp": true, ++ "pse36": true, ++ "kvm-pv-tlb-flush": true, ++ "tbm": false, ++ "wdt": false, ++ "pause_filter": false, ++ "sha-ni": false, ++ "model-id": "Intel(R) Core(TM) i7-7600U CPU @ 2.80GHz", ++ "abm": true, ++ "avx512pf": false, ++ "xstore-en": false ++ } ++ } ++ }, ++ "id": "model-expansion" ++} ++ ++ ++{ ++ "return": [ ++ { ++ "name": "max", ++ "typename": "max-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "host", ++ "typename": "host-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "base", ++ "typename": "base-x86_64-cpu", ++ "unavailable-features": [], ++ "static": true, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu64", ++ "typename": "qemu64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu32", ++ "typename": "qemu32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "phenom", ++ "typename": "phenom-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "fxsr-opt", ++ "3dnowext", ++ "3dnow", ++ "sse4a", ++ "npt" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium3", ++ "typename": "pentium3-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium2", ++ "typename": "pentium2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium", ++ "typename": "pentium-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "n270", ++ "typename": "n270-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm64", ++ "typename": "kvm64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm32", ++ "typename": "kvm32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "coreduo", ++ "typename": "coreduo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "core2duo", ++ "typename": "core2duo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "athlon", ++ "typename": "athlon-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "3dnowext", ++ "3dnow" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere-IBRS", ++ "typename": "Westmere-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere", ++ "typename": "Westmere-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server-IBRS", ++ "typename": "Skylake-Server-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512dq", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "pku", ++ "avx512f", ++ "avx512f", ++ "avx512f", ++ "pku" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server", ++ "typename": "Skylake-Server-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512dq", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "pku", ++ "avx512f", ++ "avx512f", ++ "avx512f", ++ "pku" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client-IBRS", ++ "typename": "Skylake-Client-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client", ++ "typename": "Skylake-Client-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge-IBRS", ++ "typename": "SandyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge", ++ "typename": "SandyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Penryn", ++ "typename": "Penryn-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G5", ++ "typename": "Opteron_G5-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse", ++ "xop", ++ "fma4", ++ "tbm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G4", ++ "typename": "Opteron_G4-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse", ++ "xop", ++ "fma4" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G3", ++ "typename": "Opteron_G3-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G2", ++ "typename": "Opteron_G2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G1", ++ "typename": "Opteron_G1-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem-IBRS", ++ "typename": "Nehalem-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem", ++ "typename": "Nehalem-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "KnightsMill", ++ "typename": "KnightsMill-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512pf", ++ "avx512er", ++ "avx512cd", ++ "avx512-vpopcntdq", ++ "avx512-4vnniw", ++ "avx512-4fmaps", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge-IBRS", ++ "typename": "IvyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge", ++ "typename": "IvyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Icelake-Server", ++ "typename": "Icelake-Server-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512dq", ++ "clwb", ++ "intel-pt", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "avx512vbmi", ++ "pku", ++ "", ++ "avx512vbmi2", ++ "gfni", ++ "vaes", ++ "vpclmulqdq", ++ "avx512vnni", ++ "avx512bitalg", ++ "avx512-vpopcntdq", ++ "la57", ++ "pconfig", ++ "wbnoinvd", ++ "avx512f", ++ "avx512f", ++ "avx512f", ++ "pku" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Icelake-Client", ++ "typename": "Icelake-Client-x86_64-cpu", ++ "unavailable-features": [ ++ "intel-pt", ++ "avx512vbmi", ++ "pku", ++ "", ++ "avx512vbmi2", ++ "gfni", ++ "vaes", ++ "vpclmulqdq", ++ "avx512vnni", ++ "avx512bitalg", ++ "avx512-vpopcntdq", ++ "wbnoinvd", ++ "pku" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX-IBRS", ++ "typename": "Haswell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX", ++ "typename": "Haswell-noTSX-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-IBRS", ++ "typename": "Haswell-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell", ++ "typename": "Haswell-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC-IBPB", ++ "typename": "EPYC-IBPB-x86_64-cpu", ++ "unavailable-features": [ ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "cr8legacy", ++ "sse4a", ++ "misalignsse", ++ "osvw", ++ "ibpb" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC", ++ "typename": "EPYC-x86_64-cpu", ++ "unavailable-features": [ ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "cr8legacy", ++ "sse4a", ++ "misalignsse", ++ "osvw" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Conroe", ++ "typename": "Conroe-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Cascadelake-Server", ++ "typename": "Cascadelake-Server-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512dq", ++ "clwb", ++ "intel-pt", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "pku", ++ "", ++ "avx512vnni", ++ "avx512f", ++ "avx512f", ++ "avx512f", ++ "pku" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX-IBRS", ++ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX", ++ "typename": "Broadwell-noTSX-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-IBRS", ++ "typename": "Broadwell-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell", ++ "typename": "Broadwell-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "486", ++ "typename": "486-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ } ++ ], ++ "id": "definitions" ++} +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml +new file mode 100644 +index 0000000000..d46811e3d3 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-7600U.xml +@@ -0,0 +1,47 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +-- +2.21.0 + diff --git a/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-8700.patch b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-8700.patch new file mode 100644 index 0000000..c641d30 --- /dev/null +++ b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-8700.patch @@ -0,0 +1,876 @@ +From 9195e10f017bd06435f8eb0c78f2eecf34391531 Mon Sep 17 00:00:00 2001 +Message-Id: <9195e10f017bd06435f8eb0c78f2eecf34391531@dist-git> +From: Jiri Denemark +Date: Mon, 4 Mar 2019 16:45:48 +0100 +Subject: [PATCH] cputest: Add data for Intel(R) Core(TM) i7-8700 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 87a46f5d8f8b67b22eab8b25cd30a6b9901d6857) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + tests/cputestdata/x86_64-cpuid-Core-i7-8700-guest.xml + tests/cputestdata/x86_64-cpuid-Core-i7-8700-host.xml + tests/cputestdata/x86_64-cpuid-Core-i7-8700-json.xml + - intel-pt and umip features do not exist in RHEL-7.6 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + tests/cputest.c | 1 + + .../x86_64-cpuid-Core-i7-8700-disabled.xml | 6 + + .../x86_64-cpuid-Core-i7-8700-enabled.xml | 8 + + .../x86_64-cpuid-Core-i7-8700-guest.xml | 27 + + .../x86_64-cpuid-Core-i7-8700-host.xml | 28 + + .../x86_64-cpuid-Core-i7-8700-json.xml | 11 + + .../x86_64-cpuid-Core-i7-8700.json | 650 ++++++++++++++++++ + .../cputestdata/x86_64-cpuid-Core-i7-8700.xml | 47 ++ + 8 files changed, 778 insertions(+) + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700-disabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700-enabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700-guest.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700-host.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700-json.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700.json + create mode 100644 tests/cputestdata/x86_64-cpuid-Core-i7-8700.xml + +diff --git a/tests/cputest.c b/tests/cputest.c +index 5ca8d77974..74f84fab6c 100644 +--- a/tests/cputest.c ++++ b/tests/cputest.c +@@ -1178,6 +1178,7 @@ mymain(void) + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-5600U-ibrs", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-7600U", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-7700", JSON_MODELS); ++ DO_TEST_CPUID(VIR_ARCH_X86_64, "Core-i7-8700", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-E6850", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Core2-Q9500", JSON_NONE); + DO_TEST_CPUID(VIR_ARCH_X86_64, "EPYC-7601-32-Core", JSON_HOST); +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700-disabled.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-disabled.xml +new file mode 100644 +index 0000000000..6a7de576f1 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-disabled.xml +@@ -0,0 +1,6 @@ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700-enabled.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-enabled.xml +new file mode 100644 +index 0000000000..f0727d497b +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-enabled.xml +@@ -0,0 +1,8 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700-guest.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-guest.xml +new file mode 100644 +index 0000000000..141c01c841 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-guest.xml +@@ -0,0 +1,27 @@ ++ ++ Skylake-Client-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700-host.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-host.xml +new file mode 100644 +index 0000000000..53bfc9728d +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-host.xml +@@ -0,0 +1,28 @@ ++ ++ x86_64 ++ Skylake-Client-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700-json.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-json.xml +new file mode 100644 +index 0000000000..bf79d435a3 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700-json.xml +@@ -0,0 +1,11 @@ ++ ++ Skylake-Client-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700.json b/tests/cputestdata/x86_64-cpuid-Core-i7-8700.json +new file mode 100644 +index 0000000000..122a1b2985 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700.json +@@ -0,0 +1,650 @@ ++{ ++ "return": { ++ "model": { ++ "name": "base", ++ "props": { ++ "phys-bits": 0, ++ "core-id": -1, ++ "xlevel": 2147483656, ++ "cmov": true, ++ "ia64": false, ++ "aes": true, ++ "mmx": true, ++ "rdpid": false, ++ "arat": true, ++ "gfni": false, ++ "pause-filter": false, ++ "xsavec": true, ++ "intel-pt": false, ++ "osxsave": false, ++ "hv-frequencies": false, ++ "tsc-frequency": 0, ++ "xd": true, ++ "hv-vendor-id": "", ++ "kvm-asyncpf": true, ++ "kvm_asyncpf": true, ++ "perfctr_core": false, ++ "perfctr-core": false, ++ "mpx": true, ++ "pbe": false, ++ "decodeassists": false, ++ "avx512cd": false, ++ "sse4_1": true, ++ "sse4.1": true, ++ "sse4-1": true, ++ "family": 6, ++ "legacy-cache": true, ++ "vmware-cpuid-freq": true, ++ "avx512f": false, ++ "msr": true, ++ "mce": true, ++ "mca": true, ++ "hv-runtime": false, ++ "xcrypt": false, ++ "thread-id": -1, ++ "min-level": 13, ++ "xgetbv1": true, ++ "cid": false, ++ "hv-relaxed": false, ++ "hv-crash": false, ++ "ds": false, ++ "fxsr": true, ++ "xsaveopt": true, ++ "xtpr": false, ++ "avx512vl": false, ++ "avx512-vpopcntdq": false, ++ "phe": false, ++ "extapic": false, ++ "3dnowprefetch": true, ++ "avx512vbmi2": false, ++ "cr8legacy": false, ++ "cpuid-0xb": true, ++ "xcrypt-en": false, ++ "kvm_pv_eoi": true, ++ "apic-id": 4294967295, ++ "pn": false, ++ "dca": false, ++ "vendor": "GenuineIntel", ++ "pku": false, ++ "smx": false, ++ "cmp_legacy": false, ++ "cmp-legacy": false, ++ "node-id": -1, ++ "avx512-4fmaps": false, ++ "vmcb_clean": false, ++ "vmcb-clean": false, ++ "3dnowext": false, ++ "hle": true, ++ "npt": false, ++ "memory": "/machine/unattached/system[0]", ++ "clwb": false, ++ "lbrv": false, ++ "adx": true, ++ "ss": true, ++ "pni": true, ++ "svm_lock": false, ++ "svm-lock": false, ++ "pfthreshold": false, ++ "smep": true, ++ "smap": true, ++ "x2apic": true, ++ "avx512vbmi": false, ++ "avx512vnni": false, ++ "hv-stimer": false, ++ "i64": true, ++ "flushbyasid": false, ++ "f16c": true, ++ "ace2-en": false, ++ "pat": true, ++ "pae": true, ++ "sse": true, ++ "phe-en": false, ++ "kvm_nopiodelay": true, ++ "kvm-nopiodelay": true, ++ "tm": false, ++ "kvmclock-stable-bit": true, ++ "hypervisor": true, ++ "socket-id": -1, ++ "pcommit": false, ++ "syscall": true, ++ "level": 13, ++ "avx512dq": false, ++ "svm": false, ++ "full-cpuid-auto-level": true, ++ "hv-reset": false, ++ "invtsc": false, ++ "sse3": true, ++ "sse2": true, ++ "ssbd": true, ++ "est": false, ++ "avx512ifma": false, ++ "tm2": false, ++ "kvm-pv-eoi": true, ++ "cx8": true, ++ "kvm_mmu": false, ++ "kvm-mmu": false, ++ "sse4_2": true, ++ "sse4.2": true, ++ "sse4-2": true, ++ "pge": true, ++ "fill-mtrr-mask": true, ++ "avx512bitalg": false, ++ "nodeid_msr": false, ++ "pdcm": false, ++ "movbe": true, ++ "model": 158, ++ "nrip_save": false, ++ "nrip-save": false, ++ "kvm_pv_unhalt": true, ++ "ssse3": true, ++ "sse4a": false, ++ "invpcid": true, ++ "pdpe1gb": true, ++ "tsc-deadline": true, ++ "fma": true, ++ "cx16": true, ++ "de": true, ++ "enforce": false, ++ "stepping": 10, ++ "xsave": true, ++ "clflush": true, ++ "skinit": false, ++ "tsc": true, ++ "tce": false, ++ "fpu": true, ++ "ibs": false, ++ "ds_cpl": false, ++ "ds-cpl": false, ++ "host-phys-bits": true, ++ "fma4": false, ++ "la57": false, ++ "osvw": false, ++ "check": true, ++ "hv-spinlocks": -1, ++ "pmu": false, ++ "pmm": false, ++ "apic": true, ++ "spec-ctrl": true, ++ "min-xlevel2": 0, ++ "tsc-adjust": true, ++ "tsc_adjust": true, ++ "kvm-steal-time": true, ++ "kvm_steal_time": true, ++ "kvmclock": true, ++ "l3-cache": true, ++ "lwp": false, ++ "ibpb": false, ++ "xop": false, ++ "avx": true, ++ "ospke": false, ++ "ace2": false, ++ "avx512bw": false, ++ "acpi": false, ++ "hv-vapic": false, ++ "fsgsbase": true, ++ "ht": false, ++ "nx": true, ++ "pclmulqdq": true, ++ "mmxext": false, ++ "vaes": false, ++ "popcnt": true, ++ "xsaves": true, ++ "tcg-cpuid": true, ++ "lm": true, ++ "umip": true, ++ "pse": true, ++ "avx2": true, ++ "sep": true, ++ "pclmuldq": true, ++ "virt-ssbd": false, ++ "x-hv-max-vps": -1, ++ "nodeid-msr": false, ++ "kvm": true, ++ "misalignsse": false, ++ "min-xlevel": 2147483656, ++ "kvm-pv-unhalt": true, ++ "bmi2": true, ++ "bmi1": true, ++ "realized": false, ++ "tsc_scale": false, ++ "tsc-scale": false, ++ "topoext": false, ++ "hv-vpindex": false, ++ "xlevel2": 0, ++ "clflushopt": true, ++ "kvm-no-smi-migration": false, ++ "monitor": false, ++ "avx512er": false, ++ "pmm-en": false, ++ "pcid": true, ++ "3dnow": false, ++ "erms": true, ++ "lahf-lm": true, ++ "lahf_lm": true, ++ "vpclmulqdq": false, ++ "fxsr-opt": false, ++ "hv-synic": false, ++ "xstore": false, ++ "fxsr_opt": false, ++ "kvm-hint-dedicated": false, ++ "rtm": true, ++ "lmce": true, ++ "hv-time": false, ++ "perfctr-nb": false, ++ "perfctr_nb": false, ++ "ffxsr": false, ++ "rdrand": true, ++ "rdseed": true, ++ "avx512-4vnniw": false, ++ "vmx": false, ++ "vme": true, ++ "dtes64": false, ++ "mtrr": true, ++ "rdtscp": true, ++ "pse36": true, ++ "kvm-pv-tlb-flush": true, ++ "tbm": false, ++ "wdt": false, ++ "pause_filter": false, ++ "sha-ni": false, ++ "model-id": "Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz", ++ "abm": true, ++ "avx512pf": false, ++ "xstore-en": false ++ } ++ } ++ }, ++ "id": "model-expansion" ++} ++ ++{ ++ "return": [ ++ { ++ "name": "max", ++ "typename": "max-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "host", ++ "typename": "host-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "base", ++ "typename": "base-x86_64-cpu", ++ "unavailable-features": [], ++ "static": true, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu64", ++ "typename": "qemu64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu32", ++ "typename": "qemu32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "phenom", ++ "typename": "phenom-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "fxsr-opt", ++ "3dnowext", ++ "3dnow", ++ "sse4a", ++ "npt" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium3", ++ "typename": "pentium3-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium2", ++ "typename": "pentium2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium", ++ "typename": "pentium-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "n270", ++ "typename": "n270-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm64", ++ "typename": "kvm64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm32", ++ "typename": "kvm32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "cpu64-rhel6", ++ "typename": "cpu64-rhel6-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "coreduo", ++ "typename": "coreduo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "core2duo", ++ "typename": "core2duo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "athlon", ++ "typename": "athlon-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "3dnowext", ++ "3dnow" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere", ++ "typename": "Westmere-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere-IBRS", ++ "typename": "Westmere-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server", ++ "typename": "Skylake-Server-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512dq", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server-IBRS", ++ "typename": "Skylake-Server-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "avx512f", ++ "avx512dq", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client", ++ "typename": "Skylake-Client-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client-IBRS", ++ "typename": "Skylake-Client-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge", ++ "typename": "SandyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge-IBRS", ++ "typename": "SandyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Penryn", ++ "typename": "Penryn-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G5", ++ "typename": "Opteron_G5-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse", ++ "xop", ++ "fma4", ++ "tbm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G4", ++ "typename": "Opteron_G4-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse", ++ "xop", ++ "fma4" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G3", ++ "typename": "Opteron_G3-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G2", ++ "typename": "Opteron_G2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G1", ++ "typename": "Opteron_G1-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem", ++ "typename": "Nehalem-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem-IBRS", ++ "typename": "Nehalem-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge", ++ "typename": "IvyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge-IBRS", ++ "typename": "IvyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell", ++ "typename": "Haswell-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX", ++ "typename": "Haswell-noTSX-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX-IBRS", ++ "typename": "Haswell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-IBRS", ++ "typename": "Haswell-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC", ++ "typename": "EPYC-x86_64-cpu", ++ "unavailable-features": [ ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "cr8legacy", ++ "sse4a", ++ "misalignsse", ++ "osvw" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC-IBPB", ++ "typename": "EPYC-IBPB-x86_64-cpu", ++ "unavailable-features": [ ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "cr8legacy", ++ "sse4a", ++ "misalignsse", ++ "osvw", ++ "ibpb" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Conroe", ++ "typename": "Conroe-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell", ++ "typename": "Broadwell-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX", ++ "typename": "Broadwell-noTSX-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX-IBRS", ++ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-IBRS", ++ "typename": "Broadwell-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "486", ++ "typename": "486-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ } ++ ], ++ "id": "definitions" ++} +diff --git a/tests/cputestdata/x86_64-cpuid-Core-i7-8700.xml b/tests/cputestdata/x86_64-cpuid-Core-i7-8700.xml +new file mode 100644 +index 0000000000..03ba0a3925 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Core-i7-8700.xml +@@ -0,0 +1,47 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +-- +2.21.0 + diff --git a/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2630-v4.patch b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2630-v4.patch new file mode 100644 index 0000000..089a517 --- /dev/null +++ b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2630-v4.patch @@ -0,0 +1,827 @@ +From c300bfc8b035630e7940a2d3853973c8bc910e72 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Jiri Denemark +Date: Thu, 21 Feb 2019 21:51:58 +0100 +Subject: [PATCH] cputest: Add data for Intel(R) Xeon(R) CPU E5-2630 v4 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 8d068f360183ecd55e3213dbe9ba12f7d6470751) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Conflicts: + tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml + tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml + - intel-pt feature does not exist in RHEL-7.6 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + tests/cputest.c | 1 + + .../x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml | 7 + + .../x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml | 8 + + .../x86_64-cpuid-Xeon-E5-2630-v4-guest.xml | 30 + + .../x86_64-cpuid-Xeon-E5-2630-v4-host.xml | 34 + + .../x86_64-cpuid-Xeon-E5-2630-v4-json.xml | 11 + + .../x86_64-cpuid-Xeon-E5-2630-v4.json | 596 ++++++++++++++++++ + .../x86_64-cpuid-Xeon-E5-2630-v4.xml | 43 ++ + 8 files changed, 730 insertions(+) + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml + +diff --git a/tests/cputest.c b/tests/cputest.c +index baf2b3c648..8bb801859e 100644 +--- a/tests/cputest.c ++++ b/tests/cputest.c +@@ -1194,6 +1194,7 @@ mymain(void) + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2609-v3", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2623-v4", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v3", JSON_HOST); ++ DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v4", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v3", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v4", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", JSON_HOST); +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml +new file mode 100644 +index 0000000000..3ffb246167 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-disabled.xml +@@ -0,0 +1,7 @@ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml +new file mode 100644 +index 0000000000..f2d4f2826d +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-enabled.xml +@@ -0,0 +1,8 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml +new file mode 100644 +index 0000000000..2fac54355c +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-guest.xml +@@ -0,0 +1,30 @@ ++ ++ Skylake-Client ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml +new file mode 100644 +index 0000000000..f482864a98 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-host.xml +@@ -0,0 +1,34 @@ ++ ++ x86_64 ++ Broadwell ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml +new file mode 100644 +index 0000000000..5dfce947b2 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4-json.xml +@@ -0,0 +1,11 @@ ++ ++ Skylake-Client ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json +new file mode 100644 +index 0000000000..ee09950fce +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.json +@@ -0,0 +1,596 @@ ++{ ++ "return": { ++ "model": { ++ "name": "base", ++ "props": { ++ "phys-bits": 0, ++ "core-id": -1, ++ "xlevel": 2147483656, ++ "cmov": true, ++ "ia64": false, ++ "aes": true, ++ "mmx": true, ++ "arat": true, ++ "rdpid": false, ++ "pause-filter": false, ++ "xsavec": false, ++ "osxsave": false, ++ "tsc-frequency": 0, ++ "xd": true, ++ "hv-vendor-id": "", ++ "kvm-asyncpf": true, ++ "kvm_asyncpf": true, ++ "perfctr_core": false, ++ "perfctr-core": false, ++ "mpx": false, ++ "decodeassists": false, ++ "avx512cd": false, ++ "pbe": false, ++ "sse4_1": true, ++ "sse4.1": true, ++ "sse4-1": true, ++ "family": 6, ++ "vmware-cpuid-freq": true, ++ "avx512f": false, ++ "xcrypt": false, ++ "msr": true, ++ "mce": true, ++ "mca": true, ++ "thread-id": -1, ++ "min-level": 13, ++ "xgetbv1": false, ++ "cid": false, ++ "hv-relaxed": false, ++ "fxsr": true, ++ "ds": false, ++ "hv-crash": false, ++ "xsaveopt": true, ++ "xtpr": false, ++ "avx512-vpopcntdq": false, ++ "phe": false, ++ "avx512vl": false, ++ "extapic": false, ++ "3dnowprefetch": true, ++ "cr8legacy": false, ++ "stibp": false, ++ "cpuid-0xb": true, ++ "xcrypt-en": false, ++ "kvm_pv_eoi": true, ++ "apic-id": 4294967295, ++ "pn": false, ++ "dca": false, ++ "vendor": "GenuineIntel", ++ "pku": false, ++ "smx": false, ++ "cmp-legacy": false, ++ "cmp_legacy": false, ++ "avx512-4fmaps": false, ++ "vmcb-clean": false, ++ "vmcb_clean": false, ++ "3dnowext": false, ++ "hle": true, ++ "npt": false, ++ "memory": "/machine/unattached/system[0]", ++ "clwb": false, ++ "lbrv": false, ++ "adx": true, ++ "ss": true, ++ "pni": true, ++ "svm_lock": false, ++ "svm-lock": false, ++ "smep": true, ++ "pfthreshold": false, ++ "smap": true, ++ "x2apic": true, ++ "avx512vbmi": false, ++ "i64": true, ++ "flushbyasid": false, ++ "f16c": true, ++ "ace2-en": false, ++ "pat": true, ++ "pae": true, ++ "sse": true, ++ "phe-en": false, ++ "kvm-nopiodelay": true, ++ "kvm_nopiodelay": true, ++ "tm": false, ++ "kvmclock-stable-bit": true, ++ "hypervisor": true, ++ "socket-id": -1, ++ "pcommit": false, ++ "syscall": true, ++ "level": 13, ++ "avx512dq": false, ++ "svm": false, ++ "full-cpuid-auto-level": true, ++ "invtsc": false, ++ "sse3": true, ++ "sse2": true, ++ "est": false, ++ "avx512ifma": false, ++ "tm2": false, ++ "kvm-pv-eoi": true, ++ "cx8": true, ++ "kvm-mmu": false, ++ "kvm_mmu": false, ++ "sse4_2": true, ++ "sse4.2": true, ++ "sse4-2": true, ++ "pge": true, ++ "fill-mtrr-mask": true, ++ "pdcm": false, ++ "nodeid_msr": false, ++ "model": 79, ++ "movbe": true, ++ "nrip-save": false, ++ "nrip_save": false, ++ "sse4a": false, ++ "ssse3": true, ++ "kvm_pv_unhalt": true, ++ "invpcid": true, ++ "pdpe1gb": true, ++ "tsc-deadline": true, ++ "fma": true, ++ "cx16": true, ++ "de": true, ++ "enforce": false, ++ "stepping": 1, ++ "xsave": true, ++ "clflush": true, ++ "arch-facilities": false, ++ "skinit": false, ++ "tce": false, ++ "tsc": true, ++ "fpu": true, ++ "ds-cpl": false, ++ "ds_cpl": false, ++ "ibs": false, ++ "host-phys-bits": true, ++ "fma4": false, ++ "la57": false, ++ "osvw": false, ++ "check": true, ++ "hv-spinlocks": -1, ++ "pmm": false, ++ "apic": true, ++ "pmu": false, ++ "spec-ctrl": false, ++ "min-xlevel2": 0, ++ "tsc-adjust": true, ++ "tsc_adjust": true, ++ "kvm-steal-time": true, ++ "kvm_steal_time": true, ++ "kvmclock": true, ++ "l3-cache": true, ++ "lwp": false, ++ "xop": false, ++ "ibpb": false, ++ "avx": true, ++ "ospke": false, ++ "ace2": false, ++ "acpi": false, ++ "avx512bw": false, ++ "hv-vapic": false, ++ "fsgsbase": true, ++ "ht": false, ++ "nx": true, ++ "pclmulqdq": true, ++ "mmxext": false, ++ "popcnt": true, ++ "xsaves": false, ++ "lm": true, ++ "umip": false, ++ "avx2": true, ++ "pse": true, ++ "sep": true, ++ "pclmuldq": true, ++ "nodeid-msr": false, ++ "kvm": true, ++ "misalignsse": false, ++ "min-xlevel": 2147483656, ++ "bmi2": true, ++ "bmi1": true, ++ "kvm-pv-unhalt": true, ++ "realized": false, ++ "tsc-scale": false, ++ "tsc_scale": false, ++ "topoext": false, ++ "xlevel2": 0, ++ "clflushopt": false, ++ "kvm-no-smi-migration": false, ++ "monitor": false, ++ "avx512er": false, ++ "pmm-en": false, ++ "pcid": true, ++ "3dnow": false, ++ "erms": true, ++ "lahf-lm": true, ++ "lahf_lm": true, ++ "xstore": false, ++ "fxsr-opt": false, ++ "fxsr_opt": false, ++ "rtm": true, ++ "lmce": true, ++ "hv-time": false, ++ "perfctr-nb": false, ++ "perfctr_nb": false, ++ "ffxsr": false, ++ "rdrand": true, ++ "rdseed": true, ++ "avx512-4vnniw": false, ++ "vme": true, ++ "vmx": false, ++ "dtes64": false, ++ "mtrr": true, ++ "rdtscp": true, ++ "pse36": true, ++ "tbm": false, ++ "wdt": false, ++ "pause_filter": false, ++ "model-id": "Intel(R) Xeon(R) CPU E5-2630 v4 @ 2.20GHz", ++ "sha-ni": false, ++ "abm": true, ++ "avx512pf": false, ++ "xstore-en": false ++ } ++ } ++ }, ++ "id": "model-expansion" ++} ++ ++ ++{ ++ "return": [ ++ { ++ "name": "max", ++ "typename": "max-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "host", ++ "typename": "host-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "base", ++ "typename": "base-x86_64-cpu", ++ "unavailable-features": [], ++ "static": true, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu64", ++ "typename": "qemu64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu32", ++ "typename": "qemu32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "phenom", ++ "typename": "phenom-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "fxsr-opt", ++ "3dnowext", ++ "3dnow", ++ "sse4a", ++ "npt" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium3", ++ "typename": "pentium3-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium2", ++ "typename": "pentium2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium", ++ "typename": "pentium-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "n270", ++ "typename": "n270-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm64", ++ "typename": "kvm64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm32", ++ "typename": "kvm32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "cpu64-rhel6", ++ "typename": "cpu64-rhel6-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "coreduo", ++ "typename": "coreduo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "core2duo", ++ "typename": "core2duo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "athlon", ++ "typename": "athlon-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "3dnowext", ++ "3dnow" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere", ++ "typename": "Westmere-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere-IBRS", ++ "typename": "Westmere-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client", ++ "typename": "Skylake-Client-x86_64-cpu", ++ "unavailable-features": [ ++ "mpx", ++ "xsavec", ++ "xgetbv1", ++ "mpx", ++ "mpx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client-IBRS", ++ "typename": "Skylake-Client-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "mpx", ++ "spec-ctrl", ++ "xsavec", ++ "xgetbv1", ++ "mpx", ++ "mpx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge", ++ "typename": "SandyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge-IBRS", ++ "typename": "SandyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Penryn", ++ "typename": "Penryn-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G5", ++ "typename": "Opteron_G5-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse", ++ "xop", ++ "fma4", ++ "tbm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G4", ++ "typename": "Opteron_G4-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse", ++ "xop", ++ "fma4" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G3", ++ "typename": "Opteron_G3-x86_64-cpu", ++ "unavailable-features": [ ++ "sse4a", ++ "misalignsse" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G2", ++ "typename": "Opteron_G2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G1", ++ "typename": "Opteron_G1-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem", ++ "typename": "Nehalem-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem-IBRS", ++ "typename": "Nehalem-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge", ++ "typename": "IvyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge-IBRS", ++ "typename": "IvyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell", ++ "typename": "Haswell-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX", ++ "typename": "Haswell-noTSX-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX-IBRS", ++ "typename": "Haswell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-IBRS", ++ "typename": "Haswell-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Conroe", ++ "typename": "Conroe-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell", ++ "typename": "Broadwell-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX", ++ "typename": "Broadwell-noTSX-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX-IBRS", ++ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-IBRS", ++ "typename": "Broadwell-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "spec-ctrl" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "486", ++ "typename": "486-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ } ++ ], ++ "id": "definitions" ++} +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml +new file mode 100644 +index 0000000000..d74c207104 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2630-v4.xml +@@ -0,0 +1,43 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +-- +2.21.0 + diff --git a/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2650.patch b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2650.patch new file mode 100644 index 0000000..6cf973d --- /dev/null +++ b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2650.patch @@ -0,0 +1,1144 @@ +From 0330dfbfdac2761a3e29d737bfa1bddd4ad6371f Mon Sep 17 00:00:00 2001 +Message-Id: <0330dfbfdac2761a3e29d737bfa1bddd4ad6371f@dist-git> +From: Jiri Denemark +Date: Wed, 27 Feb 2019 09:49:36 +0100 +Subject: [PATCH] cputest: Add data for Intel(R) Xeon(R) CPU E5-2650 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 483679d48f6b5fb731bdedca3b5d3b33c011d6a3) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + tests/cputest.c | 1 + + .../x86_64-cpuid-Xeon-E5-2650-disabled.xml | 5 + + .../x86_64-cpuid-Xeon-E5-2650-enabled.xml | 8 + + .../x86_64-cpuid-Xeon-E5-2650-guest.xml | 29 + + .../x86_64-cpuid-Xeon-E5-2650-host.xml | 30 + + .../x86_64-cpuid-Xeon-E5-2650-json.xml | 14 + + .../x86_64-cpuid-Xeon-E5-2650.json | 931 ++++++++++++++++++ + .../cputestdata/x86_64-cpuid-Xeon-E5-2650.xml | 34 + + 8 files changed, 1052 insertions(+) + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml + +diff --git a/tests/cputest.c b/tests/cputest.c +index 07fa2359b5..5ca8d77974 100644 +--- a/tests/cputest.c ++++ b/tests/cputest.c +@@ -1196,6 +1196,7 @@ mymain(void) + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2623-v4", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v3", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2630-v4", JSON_MODELS); ++ DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v3", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E5-2650-v4", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", JSON_HOST); +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml +new file mode 100644 +index 0000000000..d9538892eb +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-disabled.xml +@@ -0,0 +1,5 @@ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml +new file mode 100644 +index 0000000000..fcc1e84686 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-enabled.xml +@@ -0,0 +1,8 @@ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml +new file mode 100644 +index 0000000000..e507642df1 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-guest.xml +@@ -0,0 +1,29 @@ ++ ++ SandyBridge-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml +new file mode 100644 +index 0000000000..80ca6c343f +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-host.xml +@@ -0,0 +1,30 @@ ++ ++ x86_64 ++ SandyBridge-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml +new file mode 100644 +index 0000000000..bf587d3ffc +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650-json.xml +@@ -0,0 +1,14 @@ ++ ++ SandyBridge-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json +new file mode 100644 +index 0000000000..a7a8542203 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.json +@@ -0,0 +1,931 @@ ++{ ++ "return": { ++ "model": { ++ "name": "base", ++ "props": { ++ "phys-bits": 0, ++ "core-id": -1, ++ "xlevel": 2147483656, ++ "cmov": true, ++ "ia64": false, ++ "aes": true, ++ "mmx": true, ++ "rdpid": false, ++ "arat": true, ++ "gfni": false, ++ "pause-filter": false, ++ "xsavec": false, ++ "intel-pt": false, ++ "osxsave": false, ++ "hv-frequencies": false, ++ "tsc-frequency": 0, ++ "xd": true, ++ "hv-vendor-id": "", ++ "kvm-asyncpf": true, ++ "kvm_asyncpf": true, ++ "perfctr_core": false, ++ "perfctr-core": false, ++ "mpx": false, ++ "pbe": false, ++ "decodeassists": false, ++ "avx512cd": false, ++ "sse4_1": true, ++ "sse4.1": true, ++ "sse4-1": true, ++ "family": 6, ++ "legacy-cache": true, ++ "vmware-cpuid-freq": true, ++ "avx512f": false, ++ "msr": true, ++ "mce": true, ++ "mca": true, ++ "hv-runtime": false, ++ "xcrypt": false, ++ "thread-id": -1, ++ "min-level": 13, ++ "xgetbv1": false, ++ "cid": false, ++ "hv-relaxed": false, ++ "hv-crash": false, ++ "ds": false, ++ "fxsr": true, ++ "xsaveopt": true, ++ "xtpr": false, ++ "avx512vl": false, ++ "avx512-vpopcntdq": false, ++ "phe": false, ++ "extapic": false, ++ "3dnowprefetch": false, ++ "avx512vbmi2": false, ++ "cr8legacy": false, ++ "stibp": true, ++ "cpuid-0xb": true, ++ "xcrypt-en": false, ++ "kvm_pv_eoi": true, ++ "apic-id": 4294967295, ++ "pn": false, ++ "dca": false, ++ "vendor": "GenuineIntel", ++ "pku": false, ++ "smx": false, ++ "cmp_legacy": false, ++ "cmp-legacy": false, ++ "node-id": -1, ++ "avx512-4fmaps": false, ++ "vmcb_clean": false, ++ "vmcb-clean": false, ++ "3dnowext": false, ++ "hle": false, ++ "npt": false, ++ "memory": "/machine/unattached/system[0]", ++ "clwb": false, ++ "lbrv": false, ++ "adx": false, ++ "ss": true, ++ "pni": true, ++ "svm_lock": false, ++ "svm-lock": false, ++ "pfthreshold": false, ++ "smep": false, ++ "smap": false, ++ "x2apic": true, ++ "avx512vbmi": false, ++ "avx512vnni": false, ++ "hv-stimer": false, ++ "i64": true, ++ "flushbyasid": false, ++ "f16c": false, ++ "ace2-en": false, ++ "pat": true, ++ "pae": true, ++ "sse": true, ++ "phe-en": false, ++ "kvm_nopiodelay": true, ++ "kvm-nopiodelay": true, ++ "tm": false, ++ "kvmclock-stable-bit": true, ++ "hypervisor": true, ++ "socket-id": -1, ++ "pcommit": false, ++ "syscall": true, ++ "level": 13, ++ "avx512dq": false, ++ "svm": false, ++ "full-cpuid-auto-level": true, ++ "hv-reset": false, ++ "invtsc": false, ++ "sse3": true, ++ "sse2": true, ++ "ssbd": true, ++ "est": false, ++ "avx512ifma": false, ++ "tm2": false, ++ "kvm-pv-eoi": true, ++ "cx8": true, ++ "kvm_mmu": false, ++ "kvm-mmu": false, ++ "sse4_2": true, ++ "sse4.2": true, ++ "sse4-2": true, ++ "pge": true, ++ "fill-mtrr-mask": true, ++ "avx512bitalg": false, ++ "nodeid_msr": false, ++ "pdcm": false, ++ "movbe": false, ++ "model": 45, ++ "nrip_save": false, ++ "nrip-save": false, ++ "kvm_pv_unhalt": true, ++ "ssse3": true, ++ "sse4a": false, ++ "invpcid": false, ++ "pdpe1gb": true, ++ "tsc-deadline": true, ++ "fma": false, ++ "cx16": true, ++ "de": true, ++ "enforce": false, ++ "stepping": 7, ++ "xsave": true, ++ "clflush": true, ++ "skinit": false, ++ "tsc": true, ++ "tce": false, ++ "fpu": true, ++ "ibs": false, ++ "ds_cpl": false, ++ "ds-cpl": false, ++ "host-phys-bits": true, ++ "fma4": false, ++ "la57": false, ++ "osvw": false, ++ "check": true, ++ "hv-spinlocks": -1, ++ "pmu": false, ++ "pmm": false, ++ "apic": true, ++ "spec-ctrl": true, ++ "min-xlevel2": 0, ++ "tsc-adjust": true, ++ "tsc_adjust": true, ++ "kvm-steal-time": true, ++ "kvm_steal_time": true, ++ "kvmclock": true, ++ "l3-cache": true, ++ "lwp": false, ++ "ibpb": false, ++ "xop": false, ++ "avx": true, ++ "ospke": false, ++ "ace2": false, ++ "avx512bw": false, ++ "acpi": false, ++ "hv-vapic": false, ++ "fsgsbase": false, ++ "ht": false, ++ "nx": true, ++ "pclmulqdq": true, ++ "mmxext": false, ++ "vaes": false, ++ "popcnt": true, ++ "xsaves": false, ++ "tcg-cpuid": true, ++ "lm": true, ++ "umip": false, ++ "pse": true, ++ "avx2": false, ++ "sep": true, ++ "pclmuldq": true, ++ "virt-ssbd": false, ++ "x-hv-max-vps": -1, ++ "nodeid-msr": false, ++ "kvm": true, ++ "misalignsse": false, ++ "min-xlevel": 2147483656, ++ "kvm-pv-unhalt": true, ++ "bmi2": false, ++ "bmi1": false, ++ "realized": false, ++ "tsc_scale": false, ++ "tsc-scale": false, ++ "topoext": false, ++ "hv-vpindex": false, ++ "xlevel2": 0, ++ "clflushopt": false, ++ "kvm-no-smi-migration": false, ++ "monitor": false, ++ "avx512er": false, ++ "pmm-en": false, ++ "pcid": true, ++ "3dnow": false, ++ "erms": false, ++ "lahf-lm": true, ++ "lahf_lm": true, ++ "vpclmulqdq": false, ++ "fxsr-opt": false, ++ "hv-synic": false, ++ "xstore": false, ++ "fxsr_opt": false, ++ "kvm-hint-dedicated": false, ++ "rtm": false, ++ "lmce": true, ++ "hv-time": false, ++ "perfctr-nb": false, ++ "perfctr_nb": false, ++ "ffxsr": false, ++ "rdrand": false, ++ "rdseed": false, ++ "avx512-4vnniw": false, ++ "vmx": false, ++ "vme": true, ++ "dtes64": false, ++ "mtrr": true, ++ "rdtscp": true, ++ "pse36": true, ++ "kvm-pv-tlb-flush": false, ++ "tbm": false, ++ "wdt": false, ++ "pause_filter": false, ++ "sha-ni": false, ++ "model-id": " Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz", ++ "abm": false, ++ "avx512pf": false, ++ "xstore-en": false ++ } ++ } ++ }, ++ "id": "model-expansion" ++} ++ ++{ ++ "return": [ ++ { ++ "name": "max", ++ "typename": "max-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "host", ++ "typename": "host-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "base", ++ "typename": "base-x86_64-cpu", ++ "unavailable-features": [], ++ "static": true, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu64", ++ "typename": "qemu64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu32", ++ "typename": "qemu32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "phenom", ++ "typename": "phenom-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "fxsr-opt", ++ "3dnowext", ++ "3dnow", ++ "abm", ++ "sse4a", ++ "npt" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium3", ++ "typename": "pentium3-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium2", ++ "typename": "pentium2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium", ++ "typename": "pentium-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "n270", ++ "typename": "n270-x86_64-cpu", ++ "unavailable-features": [ ++ "movbe" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm64", ++ "typename": "kvm64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm32", ++ "typename": "kvm32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "cpu64-rhel6", ++ "typename": "cpu64-rhel6-x86_64-cpu", ++ "unavailable-features": [ ++ "abm", ++ "sse4a" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "coreduo", ++ "typename": "coreduo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "core2duo", ++ "typename": "core2duo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "athlon", ++ "typename": "athlon-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "3dnowext", ++ "3dnow" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere", ++ "typename": "Westmere-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere-IBRS", ++ "typename": "Westmere-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server", ++ "typename": "Skylake-Server-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "avx512f", ++ "avx512dq", ++ "rdseed", ++ "adx", ++ "smap", ++ "clflushopt", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "abm", ++ "3dnowprefetch", ++ "xsavec", ++ "xgetbv1", ++ "mpx", ++ "mpx", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server-IBRS", ++ "typename": "Skylake-Server-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "avx512f", ++ "avx512dq", ++ "rdseed", ++ "adx", ++ "smap", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "abm", ++ "3dnowprefetch", ++ "xsavec", ++ "xgetbv1", ++ "mpx", ++ "mpx", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client", ++ "typename": "Skylake-Client-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsavec", ++ "xgetbv1", ++ "mpx", ++ "mpx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client-IBRS", ++ "typename": "Skylake-Client-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsavec", ++ "xgetbv1", ++ "mpx", ++ "mpx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge", ++ "typename": "SandyBridge-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge-IBRS", ++ "typename": "SandyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Penryn", ++ "typename": "Penryn-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G5", ++ "typename": "Opteron_G5-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "f16c", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "xop", ++ "fma4", ++ "tbm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G4", ++ "typename": "Opteron_G4-x86_64-cpu", ++ "unavailable-features": [ ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "xop", ++ "fma4" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G3", ++ "typename": "Opteron_G3-x86_64-cpu", ++ "unavailable-features": [ ++ "abm", ++ "sse4a", ++ "misalignsse" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G2", ++ "typename": "Opteron_G2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G1", ++ "typename": "Opteron_G1-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem", ++ "typename": "Nehalem-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem-IBRS", ++ "typename": "Nehalem-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge", ++ "typename": "IvyBridge-x86_64-cpu", ++ "unavailable-features": [ ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "smep", ++ "erms" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge-IBRS", ++ "typename": "IvyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "smep", ++ "erms" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell", ++ "typename": "Haswell-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "abm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX", ++ "typename": "Haswell-noTSX-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "abm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX-IBRS", ++ "typename": "Haswell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "abm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-IBRS", ++ "typename": "Haswell-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "abm" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC", ++ "typename": "EPYC-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "rdseed", ++ "adx", ++ "smap", ++ "clflushopt", ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "cr8legacy", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "osvw", ++ "xsavec", ++ "xgetbv1" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC-IBPB", ++ "typename": "EPYC-IBPB-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "rdseed", ++ "adx", ++ "smap", ++ "clflushopt", ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "cr8legacy", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "osvw", ++ "ibpb", ++ "xsavec", ++ "xgetbv1" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Conroe", ++ "typename": "Conroe-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell", ++ "typename": "Broadwell-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX", ++ "typename": "Broadwell-noTSX-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX-IBRS", ++ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-IBRS", ++ "typename": "Broadwell-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "fma", ++ "movbe", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "486", ++ "typename": "486-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ } ++ ], ++ "id": "definitions" ++} +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml +new file mode 100644 +index 0000000000..b7ce0631ca +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E5-2650.xml +@@ -0,0 +1,34 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +-- +2.21.0 + diff --git a/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E7540.patch b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E7540.patch new file mode 100644 index 0000000..80e1ed5 --- /dev/null +++ b/SOURCES/libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E7540.patch @@ -0,0 +1,1317 @@ +From 6c7f91a602ba245f5a73f5788160e89eb82da23d Mon Sep 17 00:00:00 2001 +Message-Id: <6c7f91a602ba245f5a73f5788160e89eb82da23d@dist-git> +From: Jiri Denemark +Date: Tue, 26 Feb 2019 21:22:25 +0100 +Subject: [PATCH] cputest: Add data for Intel(R) Xeon(R) CPU E7540 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +(cherry picked from commit 60046a236583a2f19c0ba6e7ab3a2823d20f177e) + +https://bugzilla.redhat.com/show_bug.cgi?id=1558558 +https://bugzilla.redhat.com/show_bug.cgi?id=1687515 + +Signed-off-by: Jiri Denemark +Reviewed-by: Ján Tomko +--- + tests/cputest.c | 1 + + .../x86_64-cpuid-Xeon-E7540-disabled.xml | 5 + + .../x86_64-cpuid-Xeon-E7540-enabled.xml | 7 + + .../x86_64-cpuid-Xeon-E7540-guest.xml | 25 + + .../x86_64-cpuid-Xeon-E7540-host.xml | 26 + + .../x86_64-cpuid-Xeon-E7540-json.xml | 14 + + .../cputestdata/x86_64-cpuid-Xeon-E7540.json | 1117 +++++++++++++++++ + tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml | 30 + + 8 files changed, 1225 insertions(+) + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.json + create mode 100644 tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml + +diff --git a/tests/cputest.c b/tests/cputest.c +index 926ae8b533..07fa2359b5 100644 +--- a/tests/cputest.c ++++ b/tests/cputest.c +@@ -1201,6 +1201,7 @@ mymain(void) + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4820", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-4830", JSON_MODELS_REQUIRED); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7-8890-v3", JSON_MODELS); ++ DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-E7540", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-Gold-5115", JSON_MODELS); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-Gold-6148", JSON_HOST); + DO_TEST_CPUID(VIR_ARCH_X86_64, "Xeon-W3520", JSON_HOST); +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml +new file mode 100644 +index 0000000000..49737fbdb1 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-disabled.xml +@@ -0,0 +1,5 @@ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml +new file mode 100644 +index 0000000000..8149ac04f0 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-enabled.xml +@@ -0,0 +1,7 @@ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml +new file mode 100644 +index 0000000000..fc3e95253b +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-guest.xml +@@ -0,0 +1,25 @@ ++ ++ Nehalem-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml +new file mode 100644 +index 0000000000..42b43116bd +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-host.xml +@@ -0,0 +1,26 @@ ++ ++ x86_64 ++ Nehalem-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml +new file mode 100644 +index 0000000000..32cd1000c8 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540-json.xml +@@ -0,0 +1,14 @@ ++ ++ Nehalem-IBRS ++ Intel ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540.json b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.json +new file mode 100644 +index 0000000000..ac8452509d +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.json +@@ -0,0 +1,1117 @@ ++{ ++ "return": { ++ "model": { ++ "name": "base", ++ "props": { ++ "phys-bits": 0, ++ "core-id": -1, ++ "xlevel": 2147483656, ++ "cmov": true, ++ "ia64": false, ++ "aes": false, ++ "mmx": true, ++ "rdpid": false, ++ "arat": true, ++ "gfni": false, ++ "pause-filter": false, ++ "xsavec": false, ++ "intel-pt": false, ++ "osxsave": false, ++ "hv-frequencies": false, ++ "tsc-frequency": 0, ++ "xd": true, ++ "hv-vendor-id": "", ++ "kvm-asyncpf": true, ++ "kvm_asyncpf": true, ++ "perfctr_core": false, ++ "perfctr-core": false, ++ "mpx": false, ++ "pbe": false, ++ "decodeassists": false, ++ "avx512cd": false, ++ "sse4_1": true, ++ "sse4.1": true, ++ "sse4-1": true, ++ "family": 6, ++ "legacy-cache": true, ++ "vmware-cpuid-freq": true, ++ "avx512f": false, ++ "msr": true, ++ "mce": true, ++ "mca": true, ++ "hv-runtime": false, ++ "xcrypt": false, ++ "thread-id": -1, ++ "min-level": 11, ++ "xgetbv1": false, ++ "cid": false, ++ "hv-relaxed": false, ++ "hv-crash": false, ++ "ds": false, ++ "fxsr": true, ++ "xsaveopt": false, ++ "xtpr": false, ++ "avx512vl": false, ++ "avx512-vpopcntdq": false, ++ "phe": false, ++ "extapic": false, ++ "3dnowprefetch": false, ++ "avx512vbmi2": false, ++ "cr8legacy": false, ++ "stibp": true, ++ "cpuid-0xb": true, ++ "xcrypt-en": false, ++ "kvm_pv_eoi": true, ++ "apic-id": 4294967295, ++ "pn": false, ++ "dca": false, ++ "vendor": "GenuineIntel", ++ "pku": false, ++ "smx": false, ++ "cmp_legacy": false, ++ "cmp-legacy": false, ++ "node-id": -1, ++ "avx512-4fmaps": false, ++ "vmcb_clean": false, ++ "vmcb-clean": false, ++ "3dnowext": false, ++ "hle": false, ++ "npt": false, ++ "memory": "/machine/unattached/system[0]", ++ "clwb": false, ++ "lbrv": false, ++ "adx": false, ++ "ss": true, ++ "pni": true, ++ "svm_lock": false, ++ "svm-lock": false, ++ "pfthreshold": false, ++ "smep": false, ++ "smap": false, ++ "x2apic": true, ++ "avx512vbmi": false, ++ "avx512vnni": false, ++ "hv-stimer": false, ++ "i64": true, ++ "flushbyasid": false, ++ "f16c": false, ++ "ace2-en": false, ++ "pat": true, ++ "pae": true, ++ "sse": true, ++ "phe-en": false, ++ "kvm_nopiodelay": true, ++ "kvm-nopiodelay": true, ++ "tm": false, ++ "kvmclock-stable-bit": true, ++ "hypervisor": true, ++ "socket-id": -1, ++ "pcommit": false, ++ "syscall": true, ++ "level": 11, ++ "avx512dq": false, ++ "svm": false, ++ "full-cpuid-auto-level": true, ++ "hv-reset": false, ++ "invtsc": false, ++ "sse3": true, ++ "sse2": true, ++ "ssbd": true, ++ "est": false, ++ "avx512ifma": false, ++ "tm2": false, ++ "kvm-pv-eoi": true, ++ "cx8": true, ++ "kvm_mmu": false, ++ "kvm-mmu": false, ++ "sse4_2": true, ++ "sse4.2": true, ++ "sse4-2": true, ++ "pge": true, ++ "fill-mtrr-mask": true, ++ "avx512bitalg": false, ++ "nodeid_msr": false, ++ "pdcm": false, ++ "movbe": false, ++ "model": 46, ++ "nrip_save": false, ++ "nrip-save": false, ++ "kvm_pv_unhalt": true, ++ "ssse3": true, ++ "sse4a": false, ++ "invpcid": false, ++ "pdpe1gb": false, ++ "tsc-deadline": true, ++ "fma": false, ++ "cx16": true, ++ "de": true, ++ "enforce": false, ++ "stepping": 6, ++ "xsave": false, ++ "clflush": true, ++ "skinit": false, ++ "tsc": true, ++ "tce": false, ++ "fpu": true, ++ "ibs": false, ++ "ds_cpl": false, ++ "ds-cpl": false, ++ "host-phys-bits": true, ++ "fma4": false, ++ "la57": false, ++ "osvw": false, ++ "check": true, ++ "hv-spinlocks": -1, ++ "pmu": false, ++ "pmm": false, ++ "apic": true, ++ "spec-ctrl": true, ++ "min-xlevel2": 0, ++ "tsc-adjust": true, ++ "tsc_adjust": true, ++ "kvm-steal-time": true, ++ "kvm_steal_time": true, ++ "kvmclock": true, ++ "l3-cache": true, ++ "lwp": false, ++ "ibpb": false, ++ "xop": false, ++ "avx": false, ++ "ospke": false, ++ "ace2": false, ++ "avx512bw": false, ++ "acpi": false, ++ "hv-vapic": false, ++ "fsgsbase": false, ++ "ht": false, ++ "nx": true, ++ "pclmulqdq": false, ++ "mmxext": false, ++ "vaes": false, ++ "popcnt": true, ++ "xsaves": false, ++ "tcg-cpuid": true, ++ "lm": true, ++ "umip": false, ++ "pse": true, ++ "avx2": false, ++ "sep": true, ++ "pclmuldq": false, ++ "virt-ssbd": false, ++ "x-hv-max-vps": -1, ++ "nodeid-msr": false, ++ "kvm": true, ++ "misalignsse": false, ++ "min-xlevel": 2147483656, ++ "kvm-pv-unhalt": true, ++ "bmi2": false, ++ "bmi1": false, ++ "realized": false, ++ "tsc_scale": false, ++ "tsc-scale": false, ++ "topoext": false, ++ "hv-vpindex": false, ++ "xlevel2": 0, ++ "clflushopt": false, ++ "kvm-no-smi-migration": false, ++ "monitor": false, ++ "avx512er": false, ++ "pmm-en": false, ++ "pcid": false, ++ "3dnow": false, ++ "erms": false, ++ "lahf-lm": true, ++ "lahf_lm": true, ++ "vpclmulqdq": false, ++ "fxsr-opt": false, ++ "hv-synic": false, ++ "xstore": false, ++ "fxsr_opt": false, ++ "kvm-hint-dedicated": false, ++ "rtm": false, ++ "lmce": true, ++ "hv-time": false, ++ "perfctr-nb": false, ++ "perfctr_nb": false, ++ "ffxsr": false, ++ "rdrand": false, ++ "rdseed": false, ++ "avx512-4vnniw": false, ++ "vmx": false, ++ "vme": true, ++ "dtes64": false, ++ "mtrr": true, ++ "rdtscp": true, ++ "pse36": true, ++ "kvm-pv-tlb-flush": false, ++ "tbm": false, ++ "wdt": false, ++ "pause_filter": false, ++ "sha-ni": false, ++ "model-id": "Intel(R) Xeon(R) CPU E7540 @ 2.00GHz", ++ "abm": false, ++ "avx512pf": false, ++ "xstore-en": false ++ } ++ } ++ }, ++ "id": "model-expansion" ++} ++ ++ ++{ ++ "return": [ ++ { ++ "name": "max", ++ "typename": "max-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "host", ++ "typename": "host-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": false ++ }, ++ { ++ "name": "base", ++ "typename": "base-x86_64-cpu", ++ "unavailable-features": [], ++ "static": true, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu64", ++ "typename": "qemu64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "qemu32", ++ "typename": "qemu32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "phenom", ++ "typename": "phenom-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "fxsr-opt", ++ "pdpe1gb", ++ "3dnowext", ++ "3dnow", ++ "abm", ++ "sse4a", ++ "npt" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium3", ++ "typename": "pentium3-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium2", ++ "typename": "pentium2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "pentium", ++ "typename": "pentium-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "n270", ++ "typename": "n270-x86_64-cpu", ++ "unavailable-features": [ ++ "movbe" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm64", ++ "typename": "kvm64-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "kvm32", ++ "typename": "kvm32-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "cpu64-rhel6", ++ "typename": "cpu64-rhel6-x86_64-cpu", ++ "unavailable-features": [ ++ "abm", ++ "sse4a" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "coreduo", ++ "typename": "coreduo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "core2duo", ++ "typename": "core2duo-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "athlon", ++ "typename": "athlon-x86_64-cpu", ++ "unavailable-features": [ ++ "mmxext", ++ "3dnowext", ++ "3dnow" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere", ++ "typename": "Westmere-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Westmere-IBRS", ++ "typename": "Westmere-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server", ++ "typename": "Skylake-Server-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "avx512f", ++ "avx512dq", ++ "rdseed", ++ "adx", ++ "smap", ++ "clflushopt", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "pdpe1gb", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsavec", ++ "xgetbv1", ++ "xsave", ++ "xsave", ++ "avx", ++ "mpx", ++ "mpx", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Server-IBRS", ++ "typename": "Skylake-Server-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "avx512f", ++ "avx512dq", ++ "rdseed", ++ "adx", ++ "smap", ++ "clwb", ++ "avx512cd", ++ "avx512bw", ++ "avx512vl", ++ "pdpe1gb", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsavec", ++ "xgetbv1", ++ "xsave", ++ "xsave", ++ "avx", ++ "mpx", ++ "mpx", ++ "avx512f", ++ "avx512f", ++ "avx512f" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client", ++ "typename": "Skylake-Client-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsavec", ++ "xgetbv1", ++ "xsave", ++ "xsave", ++ "avx", ++ "mpx", ++ "mpx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Skylake-Client-IBRS", ++ "typename": "Skylake-Client-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "mpx", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsavec", ++ "xgetbv1", ++ "xsave", ++ "xsave", ++ "avx", ++ "mpx", ++ "mpx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge", ++ "typename": "SandyBridge-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes", ++ "xsave", ++ "avx", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "SandyBridge-IBRS", ++ "typename": "SandyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes", ++ "xsave", ++ "avx", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Penryn", ++ "typename": "Penryn-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G5", ++ "typename": "Opteron_G5-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "pdpe1gb", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "xop", ++ "fma4", ++ "tbm", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G4", ++ "typename": "Opteron_G4-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes", ++ "xsave", ++ "avx", ++ "pdpe1gb", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "xop", ++ "fma4", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G3", ++ "typename": "Opteron_G3-x86_64-cpu", ++ "unavailable-features": [ ++ "abm", ++ "sse4a", ++ "misalignsse" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G2", ++ "typename": "Opteron_G2-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Opteron_G1", ++ "typename": "Opteron_G1-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem", ++ "typename": "Nehalem-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Nehalem-IBRS", ++ "typename": "Nehalem-IBRS-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge", ++ "typename": "IvyBridge-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "smep", ++ "erms", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "IvyBridge-IBRS", ++ "typename": "IvyBridge-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "smep", ++ "erms", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell", ++ "typename": "Haswell-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "abm", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX", ++ "typename": "Haswell-noTSX-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "abm", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-noTSX-IBRS", ++ "typename": "Haswell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "abm", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Haswell-IBRS", ++ "typename": "Haswell-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "abm", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC", ++ "typename": "EPYC-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "rdseed", ++ "adx", ++ "smap", ++ "clflushopt", ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "pdpe1gb", ++ "cr8legacy", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "osvw", ++ "xsaveopt", ++ "xsavec", ++ "xgetbv1", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "EPYC-IBPB", ++ "typename": "EPYC-IBPB-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "rdseed", ++ "adx", ++ "smap", ++ "clflushopt", ++ "sha-ni", ++ "mmxext", ++ "fxsr-opt", ++ "pdpe1gb", ++ "cr8legacy", ++ "abm", ++ "sse4a", ++ "misalignsse", ++ "3dnowprefetch", ++ "osvw", ++ "ibpb", ++ "xsaveopt", ++ "xsavec", ++ "xgetbv1", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Conroe", ++ "typename": "Conroe-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell", ++ "typename": "Broadwell-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX", ++ "typename": "Broadwell-noTSX-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-noTSX-IBRS", ++ "typename": "Broadwell-noTSX-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "Broadwell-IBRS", ++ "typename": "Broadwell-IBRS-x86_64-cpu", ++ "unavailable-features": [ ++ "pclmulqdq", ++ "fma", ++ "pcid", ++ "movbe", ++ "aes", ++ "xsave", ++ "avx", ++ "f16c", ++ "rdrand", ++ "fsgsbase", ++ "bmi1", ++ "hle", ++ "avx2", ++ "smep", ++ "bmi2", ++ "erms", ++ "invpcid", ++ "rtm", ++ "rdseed", ++ "adx", ++ "smap", ++ "abm", ++ "3dnowprefetch", ++ "xsaveopt", ++ "xsave", ++ "xsave", ++ "avx" ++ ], ++ "static": false, ++ "migration-safe": true ++ }, ++ { ++ "name": "486", ++ "typename": "486-x86_64-cpu", ++ "unavailable-features": [], ++ "static": false, ++ "migration-safe": true ++ } ++ ], ++ "id": "definitions" ++} +diff --git a/tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml +new file mode 100644 +index 0000000000..e80694b5e0 +--- /dev/null ++++ b/tests/cputestdata/x86_64-cpuid-Xeon-E7540.xml +@@ -0,0 +1,30 @@ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +-- +2.21.0 + diff --git a/SOURCES/libvirt-storage-Fetch-a-unique-key-for-vHBA-NPIV-LUNs.patch b/SOURCES/libvirt-storage-Fetch-a-unique-key-for-vHBA-NPIV-LUNs.patch new file mode 100644 index 0000000..05a4638 --- /dev/null +++ b/SOURCES/libvirt-storage-Fetch-a-unique-key-for-vHBA-NPIV-LUNs.patch @@ -0,0 +1,71 @@ +From 5e8bad9479e999bf9dd704ec29f83427b260c587 Mon Sep 17 00:00:00 2001 +Message-Id: <5e8bad9479e999bf9dd704ec29f83427b260c587@dist-git> +From: John Ferlan +Date: Tue, 12 Mar 2019 13:55:59 -0400 +Subject: [PATCH] storage: Fetch a unique key for vHBA/NPIV LUNs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +https://bugzilla.redhat.com/show_bug.cgi?id=1687715 (7.6.z) +https://bugzilla.redhat.com/show_bug.cgi?id=1657468 (7.7.0) + +Commit be1bb6c95 changed the way volumes were stored from a forward +linked list to a hash table. In doing so, it required that each vol +object would have 3 unique values as keys into tables - key, name, +and path. Due to how vHBA/NPIV LUNs are created/used this resulted +in a failure to utilize all the LUN's found during processing. + +During virStorageBackendSCSINewLun processing fetch the key (or +serial value) for NPIV LUN's using virStorageFileGetNPIVKey which +will formulate a more unique key based on the serial value and +the port for the LUN. + +Signed-off-by: John Ferlan +ACKed-by: Michal Privoznik +Reviewed-by: Ján Tomko +(cherry picked from commit 850cfd75beb7872b20439eccda0bcf7b68cab525) +Message-Id: <20190312175559.13583-5-jferlan@redhat.com> +Reviewed-by: Ján Tomko +--- + src/storage/storage_util.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +diff --git a/src/storage/storage_util.c b/src/storage/storage_util.c +index d1659c0c8d..19e6e0544b 100644 +--- a/src/storage/storage_util.c ++++ b/src/storage/storage_util.c +@@ -3694,12 +3694,16 @@ virStorageBackendRefreshLocal(virStoragePoolObjPtr pool) + + + static char * +-virStorageBackendSCSISerial(const char *dev) ++virStorageBackendSCSISerial(const char *dev, ++ bool isNPIV) + { + int rc; + char *serial = NULL; + +- rc = virStorageFileGetSCSIKey(dev, &serial, true); ++ if (isNPIV) ++ rc = virStorageFileGetNPIVKey(dev, &serial); ++ else ++ rc = virStorageFileGetSCSIKey(dev, &serial, true); + if (rc == 0 && serial) + return serial; + +@@ -3796,7 +3800,10 @@ virStorageBackendSCSINewLun(virStoragePoolObjPtr pool, + VIR_STORAGE_VOL_READ_NOERROR)) < 0) + goto cleanup; + +- if (!(vol->key = virStorageBackendSCSISerial(vol->target.path))) ++ vol->key = virStorageBackendSCSISerial(vol->target.path, ++ (def->source.adapter.type == ++ VIR_STORAGE_ADAPTER_TYPE_FC_HOST)); ++ if (!vol->key) + goto cleanup; + + def->capacity += vol->target.capacity; +-- +2.21.0 + diff --git a/SOURCES/libvirt-storage-Rework-virStorageBackendSCSISerial.patch b/SOURCES/libvirt-storage-Rework-virStorageBackendSCSISerial.patch new file mode 100644 index 0000000..c8437b8 --- /dev/null +++ b/SOURCES/libvirt-storage-Rework-virStorageBackendSCSISerial.patch @@ -0,0 +1,151 @@ +From 4b841d996f9e1181e6a0614eb0bc9a35d5f7c372 Mon Sep 17 00:00:00 2001 +Message-Id: <4b841d996f9e1181e6a0614eb0bc9a35d5f7c372@dist-git> +From: John Ferlan +Date: Tue, 12 Mar 2019 13:55:57 -0400 +Subject: [PATCH] storage: Rework virStorageBackendSCSISerial +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +https://bugzilla.redhat.com/show_bug.cgi?id=1687715 (7.6.z) +https://bugzilla.redhat.com/show_bug.cgi?id=1657468 (7.7.0) + +Alter the code to use the virStorageFileGetSCSIKey helper +to fetch the unique key for the SCSI disk. Alter the logic +to follow the former code which would return a duplicate +of @dev when either the virCommandRun succeeded, but returned +an empty string or when WITH_UDEV was not true. + +Signed-off-by: John Ferlan +ACKed-by: Michal Privoznik +Reviewed-by: Ján Tomko +(cherry picked from commit 8bf89dc83729aaa0388f89e972a4847fd1e267c6) + +Managed conflict in src/locking/lock_driver_lockd.c as a result of +commit e9e904b3b70533982954ab39ccb81122e8dad338 which changed from +using "goto error" to using "goto cleanup" by using the error label. + +Signed-off-by: John Ferlan +Message-Id: <20190312175559.13583-3-jferlan@redhat.com> +Reviewed-by: Ján Tomko +--- + src/locking/lock_driver_lockd.c | 2 +- + src/storage/storage_util.c | 33 +++++++-------------------------- + src/util/virstoragefile.c | 10 +++++++--- + src/util/virstoragefile.h | 3 ++- + 4 files changed, 17 insertions(+), 31 deletions(-) + +diff --git a/src/locking/lock_driver_lockd.c b/src/locking/lock_driver_lockd.c +index 957a963a7b..1b9341ceba 100644 +--- a/src/locking/lock_driver_lockd.c ++++ b/src/locking/lock_driver_lockd.c +@@ -517,7 +517,7 @@ static int virLockManagerLockDaemonAddResource(virLockManagerPtr lock, + if (STRPREFIX(name, "/dev") && + driver->scsiLockSpaceDir) { + VIR_DEBUG("Trying to find an SCSI ID for %s", name); +- if (virStorageFileGetSCSIKey(name, &newName) < 0) ++ if (virStorageFileGetSCSIKey(name, &newName, false) < 0) + goto error; + + if (newName) { +diff --git a/src/storage/storage_util.c b/src/storage/storage_util.c +index 5dc22d3182..d1659c0c8d 100644 +--- a/src/storage/storage_util.c ++++ b/src/storage/storage_util.c +@@ -3696,36 +3696,17 @@ virStorageBackendRefreshLocal(virStoragePoolObjPtr pool) + static char * + virStorageBackendSCSISerial(const char *dev) + { ++ int rc; + char *serial = NULL; +-#ifdef WITH_UDEV +- virCommandPtr cmd = virCommandNewArgList( +- "/lib/udev/scsi_id", +- "--replace-whitespace", +- "--whitelisted", +- "--device", dev, +- NULL +- ); + +- /* Run the program and capture its output */ +- virCommandSetOutputBuffer(cmd, &serial); +- if (virCommandRun(cmd, NULL) < 0) +- goto cleanup; +-#endif ++ rc = virStorageFileGetSCSIKey(dev, &serial, true); ++ if (rc == 0 && serial) ++ return serial; + +- if (serial && STRNEQ(serial, "")) { +- char *nl = strchr(serial, '\n'); +- if (nl) +- *nl = '\0'; +- } else { +- VIR_FREE(serial); +- ignore_value(VIR_STRDUP(serial, dev)); +- } +- +-#ifdef WITH_UDEV +- cleanup: +- virCommandFree(cmd); +-#endif ++ if (rc == -2) ++ return NULL; + ++ ignore_value(VIR_STRDUP(serial, dev)); + return serial; + } + +diff --git a/src/util/virstoragefile.c b/src/util/virstoragefile.c +index ed7266619d..56d38b467e 100644 +--- a/src/util/virstoragefile.c ++++ b/src/util/virstoragefile.c +@@ -1438,6 +1438,7 @@ int virStorageFileGetLVMKey(const char *path, + /* virStorageFileGetSCSIKey + * @path: Path to the SCSI device + * @key: Unique key to be returned ++ * @ignoreError: Used to not report ENOSYS + * + * Using a udev specific function, query the @path to get and return a + * unique @key for the caller to use. +@@ -1450,7 +1451,8 @@ int virStorageFileGetLVMKey(const char *path, + */ + int + virStorageFileGetSCSIKey(const char *path, +- char **key) ++ char **key, ++ bool ignoreError ATTRIBUTE_UNUSED) + { + int status; + virCommandPtr cmd = virCommandNewArgList( +@@ -1491,9 +1493,11 @@ virStorageFileGetSCSIKey(const char *path, + } + #else + int virStorageFileGetSCSIKey(const char *path, +- char **key ATTRIBUTE_UNUSED) ++ char **key ATTRIBUTE_UNUSED, ++ bool ignoreError) + { +- virReportSystemError(ENOSYS, _("Unable to get SCSI key for %s"), path); ++ if (!ignoreError) ++ virReportSystemError(ENOSYS, _("Unable to get SCSI key for %s"), path); + return -1; + } + #endif +diff --git a/src/util/virstoragefile.h b/src/util/virstoragefile.h +index 991098e6c6..bbb0b8b3c1 100644 +--- a/src/util/virstoragefile.h ++++ b/src/util/virstoragefile.h +@@ -384,7 +384,8 @@ bool virStorageIsRelative(const char *backing); + int virStorageFileGetLVMKey(const char *path, + char **key); + int virStorageFileGetSCSIKey(const char *path, +- char **key); ++ char **key, ++ bool ignoreError); + + void virStorageAuthDefFree(virStorageAuthDefPtr def); + virStorageAuthDefPtr virStorageAuthDefCopy(const virStorageAuthDef *src); +-- +2.21.0 + diff --git a/SOURCES/libvirt-util-Introduce-virStorageFileGetNPIVKey.patch b/SOURCES/libvirt-util-Introduce-virStorageFileGetNPIVKey.patch new file mode 100644 index 0000000..60a44ef --- /dev/null +++ b/SOURCES/libvirt-util-Introduce-virStorageFileGetNPIVKey.patch @@ -0,0 +1,188 @@ +From 049bb8956ce077d7ea5e8ac613ebb20c7a6b8715 Mon Sep 17 00:00:00 2001 +Message-Id: <049bb8956ce077d7ea5e8ac613ebb20c7a6b8715@dist-git> +From: John Ferlan +Date: Tue, 12 Mar 2019 13:55:58 -0400 +Subject: [PATCH] util: Introduce virStorageFileGetNPIVKey +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +https://bugzilla.redhat.com/show_bug.cgi?id=1687715 (7.6.z) +https://bugzilla.redhat.com/show_bug.cgi?id=1657468 (7.7.0) + +The vHBA/NPIV LUNs created via the udev processing of the +VPORT_CREATE command end up using the same serial value +as seen/generated by the /lib/udev/scsi_id as returned +during virStorageFileGetSCSIKey. Therefore, in order to +generate a unique enough key to be used when adding the +LUN as a volume during virStoragePoolObjAddVol a more +unique key needs to be generated for an NPIV volume. + +The problem is illustrated by the following example, where +scsi_host5 is a vHBA used with the following LUNs: + +$ lsscsi -tg +... +[5:0:4:0] disk fc:0x5006016844602198,0x101f00 /dev/sdh /dev/sg23 +[5:0:5:0] disk fc:0x5006016044602198,0x102000 /dev/sdi /dev/sg24 +... + +Calling virStorageFileGetSCSIKey would return: + +/lib/udev/scsi_id --device /dev/sdh --whitelisted --replace-whitespace /dev/sdh +350060160c460219850060160c4602198 +/lib/udev/scsi_id --device /dev/sdh --whitelisted --replace-whitespace /dev/sdi +350060160c460219850060160c4602198 + +Note that althrough /dev/sdh and /dev/sdi are separate LUNs, they +end up with the same serial number used for the vol->key value. +When virStoragePoolFCRefreshThread calls virStoragePoolObjAddVol +the second LUN fails to be added with the following message +getting logged: + + virHashAddOrUpdateEntry:341 : internal error: Duplicate key + +To resolve this, virStorageFileGetNPIVKey will use a similar call +sequence as virStorageFileGetSCSIKey, except that it will add the +"--export" option to the call. This results in more detailed output +which needs to be parsed in order to formulate a unique enough key +to be used. In order to be unique enough, the returned value will +concatenate the target port as returned in the "ID_TARGET_PORT" +field from the command to the "ID_SERIAL" value. + +Signed-off-by: John Ferlan +ACKed-by: Michal Privoznik +Reviewed-by: Ján Tomko +(cherry picked from commit 5f9e211c9319311fc296cb91ca8e330917ac9494) + +Handled build failure of not having VIR_AUTOFREE in the next-7.6 sources, +by not using VIR_AUTOFREE and using VIR_FREE(outbuf) explicitly. + +Signed-off-by: John Ferlan +Message-Id: <20190312175559.13583-4-jferlan@redhat.com> +Reviewed-by: Ján Tomko +--- + src/libvirt_private.syms | 1 + + src/util/virstoragefile.c | 80 +++++++++++++++++++++++++++++++++++++++ + src/util/virstoragefile.h | 2 + + 3 files changed, 83 insertions(+) + +diff --git a/src/libvirt_private.syms b/src/libvirt_private.syms +index 86846f3b08..636891eabd 100644 +--- a/src/libvirt_private.syms ++++ b/src/libvirt_private.syms +@@ -2820,6 +2820,7 @@ virStorageFileGetMetadata; + virStorageFileGetMetadataFromBuf; + virStorageFileGetMetadataFromFD; + virStorageFileGetMetadataInternal; ++virStorageFileGetNPIVKey; + virStorageFileGetRelativeBackingPath; + virStorageFileGetSCSIKey; + virStorageFileGetUniqueIdentifier; +diff --git a/src/util/virstoragefile.c b/src/util/virstoragefile.c +index 56d38b467e..52c9dc0e1a 100644 +--- a/src/util/virstoragefile.c ++++ b/src/util/virstoragefile.c +@@ -1503,6 +1503,86 @@ int virStorageFileGetSCSIKey(const char *path, + #endif + + ++#ifdef WITH_UDEV ++/* virStorageFileGetNPIVKey ++ * @path: Path to the NPIV device ++ * @key: Unique key to be returned ++ * ++ * Using a udev specific function, query the @path to get and return a ++ * unique @key for the caller to use. Unlike the GetSCSIKey method, an ++ * NPIV LUN is uniquely identified by its ID_TARGET_PORT value. ++ * ++ * Returns: ++ * 0 On success, with the @key filled in or @key=NULL if the ++ * returned output string didn't have the data we need to ++ * formulate a unique key value ++ * -1 When WITH_UDEV is undefined and a system error is reported ++ * -2 When WITH_UDEV is defined, but calling virCommandRun fails ++ */ ++# define ID_SERIAL "ID_SERIAL=" ++# define ID_TARGET_PORT "ID_TARGET_PORT=" ++int ++virStorageFileGetNPIVKey(const char *path, ++ char **key) ++{ ++ int status; ++ char *outbuf = NULL; ++ const char *serial; ++ const char *port; ++ virCommandPtr cmd = virCommandNewArgList("/lib/udev/scsi_id", ++ "--replace-whitespace", ++ "--whitelisted", ++ "--export", ++ "--device", path, ++ NULL ++ ); ++ int ret = -2; ++ ++ *key = NULL; ++ ++ /* Run the program and capture its output */ ++ virCommandSetOutputBuffer(cmd, &outbuf); ++ if (virCommandRun(cmd, &status) < 0) ++ goto cleanup; ++ ++ /* Explicitly check status == 0, rather than passing NULL ++ * to virCommandRun because we don't want to raise an actual ++ * error in this scenario, just return a NULL key. ++ */ ++ if (status == 0 && *outbuf && ++ (serial = strstr(outbuf, ID_SERIAL)) && ++ (port = strstr(outbuf, ID_TARGET_PORT))) { ++ char *tmp; ++ ++ serial += strlen(ID_SERIAL); ++ port += strlen(ID_TARGET_PORT); ++ ++ if ((tmp = strchr(serial, '\n'))) ++ *tmp = '\0'; ++ ++ if ((tmp = strchr(port, '\n'))) ++ *tmp = '\0'; ++ ++ if (*serial != '\0' && *port != '\0') ++ ignore_value(virAsprintf(key, "%s_PORT%s", serial, port)); ++ } ++ ++ ret = 0; ++ ++ cleanup: ++ virCommandFree(cmd); ++ VIR_FREE(outbuf); ++ ++ return ret; ++} ++#else ++int virStorageFileGetNPIVKey(const char *path, ++ char **key ATTRIBUTE_UNUSED) ++{ ++ return -1; ++} ++#endif ++ + /** + * virStorageFileParseBackingStoreStr: + * @str: backing store specifier string to parse +diff --git a/src/util/virstoragefile.h b/src/util/virstoragefile.h +index bbb0b8b3c1..7d28dcfe65 100644 +--- a/src/util/virstoragefile.h ++++ b/src/util/virstoragefile.h +@@ -386,6 +386,8 @@ int virStorageFileGetLVMKey(const char *path, + int virStorageFileGetSCSIKey(const char *path, + char **key, + bool ignoreError); ++int virStorageFileGetNPIVKey(const char *path, ++ char **key); + + void virStorageAuthDefFree(virStorageAuthDefPtr def); + virStorageAuthDefPtr virStorageAuthDefCopy(const virStorageAuthDef *src); +-- +2.21.0 + diff --git a/SOURCES/libvirt-util-Modify-virStorageFileGetSCSIKey-return.patch b/SOURCES/libvirt-util-Modify-virStorageFileGetSCSIKey-return.patch new file mode 100644 index 0000000..0581370 --- /dev/null +++ b/SOURCES/libvirt-util-Modify-virStorageFileGetSCSIKey-return.patch @@ -0,0 +1,73 @@ +From 8c7d0ccfbf1213a2986e8290b90f1b860fd5c3ce Mon Sep 17 00:00:00 2001 +Message-Id: <8c7d0ccfbf1213a2986e8290b90f1b860fd5c3ce@dist-git> +From: John Ferlan +Date: Tue, 12 Mar 2019 13:55:56 -0400 +Subject: [PATCH] util: Modify virStorageFileGetSCSIKey return +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +https://bugzilla.redhat.com/show_bug.cgi?id=1687715 (7.6.z) +https://bugzilla.redhat.com/show_bug.cgi?id=1657468 (7.7.0) + +Alter the "real" code to return -2 on virCommandRun failure. +Alter the comments and function header to describe the function +and its returns. + +Signed-off-by: John Ferlan +ACKed-by: Michal Privoznik +Reviewed-by: Ján Tomko +(cherry picked from commit 9b86bbccb371026d0ce7ab9a2ce685b1fae8a717) + +Managed conflict from commit 34e9c29357ef5c293c8f998ef6911756cbb8b405 +which changed the indention for the virCommandPtr cmd to keep spacing +defined in the next-7.6 tree. + +Signed-off-by: John Ferlan +Message-Id: <20190312175559.13583-2-jferlan@redhat.com> +Reviewed-by: Ján Tomko +--- + src/util/virstoragefile.c | 20 +++++++++++++++++--- + 1 file changed, 17 insertions(+), 3 deletions(-) + +diff --git a/src/util/virstoragefile.c b/src/util/virstoragefile.c +index 0b15219c3e..ed7266619d 100644 +--- a/src/util/virstoragefile.c ++++ b/src/util/virstoragefile.c +@@ -1435,8 +1435,22 @@ int virStorageFileGetLVMKey(const char *path, + #endif + + #ifdef WITH_UDEV +-int virStorageFileGetSCSIKey(const char *path, +- char **key) ++/* virStorageFileGetSCSIKey ++ * @path: Path to the SCSI device ++ * @key: Unique key to be returned ++ * ++ * Using a udev specific function, query the @path to get and return a ++ * unique @key for the caller to use. ++ * ++ * Returns: ++ * 0 On success, with the @key filled in or @key=NULL if the ++ * returned string was empty. ++ * -1 When WITH_UDEV is undefined and a system error is reported ++ * -2 When WITH_UDEV is defined, but calling virCommandRun fails ++ */ ++int ++virStorageFileGetSCSIKey(const char *path, ++ char **key) + { + int status; + virCommandPtr cmd = virCommandNewArgList( +@@ -1446,7 +1460,7 @@ int virStorageFileGetSCSIKey(const char *path, + "--device", path, + NULL + ); +- int ret = -1; ++ int ret = -2; + + *key = NULL; + +-- +2.21.0 + diff --git a/SPECS/libvirt.spec b/SPECS/libvirt.spec index 67d5606..3d5acc9 100644 --- a/SPECS/libvirt.spec +++ b/SPECS/libvirt.spec @@ -253,7 +253,7 @@ Summary: Library providing a simple virtualization API Name: libvirt Version: 4.5.0 -Release: 10%{?dist}.6%{?extra_release} +Release: 10%{?dist}.7%{?extra_release} License: LGPLv2+ URL: https://libvirt.org/ @@ -386,6 +386,31 @@ Patch120: libvirt-RHEL-cpu_map-Mark-arch-facilities-feature-as-non-migratable.pa Patch121: libvirt-virfile-Detect-ceph-as-shared-FS.patch Patch122: libvirt-util-Don-t-overflow-in-virRandomBits.patch Patch123: libvirt-virrandom-Avoid-undefined-behaviour-in-virRandomBits.patch +Patch124: libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2630-v4.patch +Patch125: libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-7600U.patch +Patch126: libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E7540.patch +Patch127: libvirt-cputest-Add-data-for-Intel-R-Xeon-R-CPU-E5-2650.patch +Patch128: libvirt-cputest-Add-data-for-Intel-R-Core-TM-i7-8700.patch +Patch129: libvirt-cpu_x86-Separate-signature-parsing-from-x86ModelParse.patch +Patch130: libvirt-cpu_x86-Add-x86ModelCopySignatures-helper.patch +Patch131: libvirt-cpu_x86-Store-CPU-signature-in-an-array.patch +Patch132: libvirt-cpu_x86-Allow-multiple-signatures-for-a-CPU-model.patch +Patch133: libvirt-cpu_map-Add-hex-representation-of-signatures.patch +Patch134: libvirt-cpu_map-Add-more-signatures-for-Conroe-CPU-model.patch +Patch135: libvirt-cpu_map-Add-more-signatures-for-Penryn-CPU-model.patch +Patch136: libvirt-cpu_map-Add-more-signatures-for-Nehalem-CPU-models.patch +Patch137: libvirt-cpu_map-Add-more-signatures-for-Westmere-CPU-model.patch +Patch138: libvirt-cpu_map-Add-more-signatures-for-SandyBridge-CPU-models.patch +Patch139: libvirt-cpu_map-Add-more-signatures-for-IvyBridge-CPU-models.patch +Patch140: libvirt-cpu_map-Add-more-signatures-for-Haswell-CPU-models.patch +Patch141: libvirt-cpu_map-Add-more-signatures-for-Broadwell-CPU-models.patch +Patch142: libvirt-cpu_map-Add-more-signatures-for-Skylake-Client-CPU-models.patch +Patch143: libvirt-cpu-Don-t-access-invalid-memory-in-virCPUx86Translate.patch +Patch144: libvirt-cpu_x86-Log-decoded-CPU-model-and-signatures.patch +Patch145: libvirt-util-Modify-virStorageFileGetSCSIKey-return.patch +Patch146: libvirt-storage-Rework-virStorageBackendSCSISerial.patch +Patch147: libvirt-util-Introduce-virStorageFileGetNPIVKey.patch +Patch148: libvirt-storage-Fetch-a-unique-key-for-vHBA-NPIV-LUNs.patch Requires: libvirt-daemon = %{version}-%{release} Requires: libvirt-daemon-config-network = %{version}-%{release} @@ -2287,6 +2312,33 @@ exit 0 %changelog +* Tue Mar 26 2019 Jiri Denemark - 4.5.0-10.el7_6.7 +- cputest: Add data for Intel(R) Xeon(R) CPU E5-2630 v4 (rhbz#1687515) +- cputest: Add data for Intel(R) Core(TM) i7-7600U (rhbz#1687515) +- cputest: Add data for Intel(R) Xeon(R) CPU E7540 (rhbz#1687515) +- cputest: Add data for Intel(R) Xeon(R) CPU E5-2650 (rhbz#1687515) +- cputest: Add data for Intel(R) Core(TM) i7-8700 (rhbz#1687515) +- cpu_x86: Separate signature parsing from x86ModelParse (rhbz#1687515) +- cpu_x86: Add x86ModelCopySignatures helper (rhbz#1687515) +- cpu_x86: Store CPU signature in an array (rhbz#1687515) +- cpu_x86: Allow multiple signatures for a CPU model (rhbz#1687515) +- cpu_map: Add hex representation of signatures (rhbz#1687515) +- cpu_map: Add more signatures for Conroe CPU model (rhbz#1687515) +- cpu_map: Add more signatures for Penryn CPU model (rhbz#1687515) +- cpu_map: Add more signatures for Nehalem CPU models (rhbz#1687515) +- cpu_map: Add more signatures for Westmere CPU model (rhbz#1687515) +- cpu_map: Add more signatures for SandyBridge CPU models (rhbz#1687515) +- cpu_map: Add more signatures for IvyBridge CPU models (rhbz#1687515) +- cpu_map: Add more signatures for Haswell CPU models (rhbz#1687515) +- cpu_map: Add more signatures for Broadwell CPU models (rhbz#1687515) +- cpu_map: Add more signatures for Skylake-Client CPU models (rhbz#1687515) +- cpu: Don't access invalid memory in virCPUx86Translate (rhbz#1687515) +- cpu_x86: Log decoded CPU model and signatures (rhbz#1687515) +- util: Modify virStorageFileGetSCSIKey return (rhbz#1687715) +- storage: Rework virStorageBackendSCSISerial (rhbz#1687715) +- util: Introduce virStorageFileGetNPIVKey (rhbz#1687715) +- storage: Fetch a unique key for vHBA/NPIV LUNs (rhbz#1687715) + * Thu Feb 21 2019 Jiri Denemark - 4.5.0-10.el7_6.6 - RHEL: spec: Require new enough librbd1 (rhbz#1679569)