|
 |
99cbc7 |
From 95f014690bab53caa5eac8859c03917ba96466dc Mon Sep 17 00:00:00 2001
|
|
|
99cbc7 |
Message-Id: <95f014690bab53caa5eac8859c03917ba96466dc@dist-git>
|
|
|
99cbc7 |
From: Bing Niu <bing.niu@intel.com>
|
|
|
99cbc7 |
Date: Mon, 15 Apr 2019 17:32:48 +0200
|
|
|
99cbc7 |
Subject: [PATCH] util: Add MBA check to virResctrlInfoGetCache
|
|
|
99cbc7 |
MIME-Version: 1.0
|
|
|
99cbc7 |
Content-Type: text/plain; charset=UTF-8
|
|
|
99cbc7 |
Content-Transfer-Encoding: 8bit
|
|
|
99cbc7 |
|
|
|
99cbc7 |
If we have some membw_info data, then we need to calculate the number
|
|
|
99cbc7 |
of MBA controllers on the system. The value cannot be obtained from a
|
|
|
99cbc7 |
direct query to the RDT kernel module, but it is the same as the last
|
|
|
99cbc7 |
level cache value which is calculated by traversing the cache hierarchy
|
|
|
99cbc7 |
of host(/sys/bus/cpu/devices/cpuX/cache/).
|
|
|
99cbc7 |
|
|
|
99cbc7 |
Signed-off-by: Bing Niu <bing.niu@intel.com>
|
|
|
99cbc7 |
Reviewed-by: John Ferlan <jferlan@redhat.com>
|
|
|
99cbc7 |
(cherry picked from commit 5aae2b3968c3e474e288cff68547f7aedac86921)
|
|
|
99cbc7 |
|
|
|
99cbc7 |
Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1468650
|
|
|
99cbc7 |
|
|
|
99cbc7 |
Signed-off-by: Pavel Hrdina <phrdina@redhat.com>
|
|
|
99cbc7 |
Message-Id: <bbacef44dd5c6d0a2d3760f4414e6e2701bd5175.1555342313.git.phrdina@redhat.com>
|
|
|
99cbc7 |
Reviewed-by: Ján Tomko <jtomko@redhat.com>
|
|
|
99cbc7 |
---
|
|
|
99cbc7 |
src/util/virresctrl.c | 14 ++++++++++++++
|
|
|
99cbc7 |
1 file changed, 14 insertions(+)
|
|
|
99cbc7 |
|
|
|
99cbc7 |
diff --git a/src/util/virresctrl.c b/src/util/virresctrl.c
|
|
|
99cbc7 |
index b12a05cb0f..f454868f1e 100644
|
|
|
99cbc7 |
--- a/src/util/virresctrl.c
|
|
|
99cbc7 |
+++ b/src/util/virresctrl.c
|
|
|
99cbc7 |
@@ -608,6 +608,20 @@ virResctrlInfoGetCache(virResctrlInfoPtr resctrl,
|
|
|
99cbc7 |
if (virResctrlInfoIsEmpty(resctrl))
|
|
|
99cbc7 |
return 0;
|
|
|
99cbc7 |
|
|
|
99cbc7 |
+ /* Let's take the opportunity to update the number of last level
|
|
|
99cbc7 |
+ * cache. This number of memory bandwidth controller is same with
|
|
|
99cbc7 |
+ * last level cache */
|
|
|
99cbc7 |
+ if (resctrl->membw_info) {
|
|
|
99cbc7 |
+ virResctrlInfoMemBWPtr membw_info = resctrl->membw_info;
|
|
|
99cbc7 |
+
|
|
|
99cbc7 |
+ if (level > membw_info->last_level_cache) {
|
|
|
99cbc7 |
+ membw_info->last_level_cache = level;
|
|
|
99cbc7 |
+ membw_info->max_id = 0;
|
|
|
99cbc7 |
+ } else if (membw_info->last_level_cache == level) {
|
|
|
99cbc7 |
+ membw_info->max_id++;
|
|
|
99cbc7 |
+ }
|
|
|
99cbc7 |
+ }
|
|
|
99cbc7 |
+
|
|
|
99cbc7 |
if (level >= resctrl->nlevels)
|
|
|
99cbc7 |
return 0;
|
|
|
99cbc7 |
|
|
|
99cbc7 |
--
|
|
|
99cbc7 |
2.21.0
|
|
|
99cbc7 |
|