|
|
902636 |
From eb0fc0ae2750a0462698d6d21ebb56a4249539f9 Mon Sep 17 00:00:00 2001
|
|
|
016a62 |
From: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
902636 |
Date: Mon, 17 Feb 2020 16:23:11 +0000
|
|
|
902636 |
Subject: [PATCH 1/9] target/i386: kvm: initialize feature MSRs very early
|
|
|
902636 |
MIME-Version: 1.0
|
|
|
902636 |
Content-Type: text/plain; charset=UTF-8
|
|
|
902636 |
Content-Transfer-Encoding: 8bit
|
|
|
016a62 |
|
|
|
016a62 |
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
902636 |
Message-id: <20200217162316.2464-2-pbonzini@redhat.com>
|
|
|
902636 |
Patchwork-id: 93899
|
|
|
902636 |
O-Subject: [RHEL-AV-8.2.0 qemu-kvm PATCH 1/6] target/i386: kvm: initialize feature MSRs very early
|
|
|
902636 |
Bugzilla: 1791648
|
|
|
902636 |
RH-Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
|
|
|
902636 |
RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
|
|
|
902636 |
RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
|
|
|
016a62 |
|
|
|
016a62 |
Some read-only MSRs affect the behavior of ioctls such as
|
|
|
016a62 |
KVM_SET_NESTED_STATE. We can initialize them once and for all
|
|
|
016a62 |
right after the CPU is realized, since they will never be modified
|
|
|
016a62 |
by the guest.
|
|
|
016a62 |
|
|
|
016a62 |
Reported-by: Qingua Cheng <qcheng@redhat.com>
|
|
|
016a62 |
Cc: qemu-stable@nongnu.org
|
|
|
016a62 |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
016a62 |
Message-Id: <1579544504-3616-2-git-send-email-pbonzini@redhat.com>
|
|
|
016a62 |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
016a62 |
(cherry picked from commit 420ae1fc51c99abfd03b1c590f55617edd2a2bed)
|
|
|
016a62 |
Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
|
|
|
016a62 |
---
|
|
|
016a62 |
target/i386/kvm.c | 81 ++++++++++++++++++++++++++++++--------------------
|
|
|
016a62 |
target/i386/kvm_i386.h | 1 +
|
|
|
016a62 |
2 files changed, 49 insertions(+), 33 deletions(-)
|
|
|
016a62 |
|
|
|
016a62 |
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
|
|
|
902636 |
index 86d9a1f..f41605b 100644
|
|
|
016a62 |
--- a/target/i386/kvm.c
|
|
|
016a62 |
+++ b/target/i386/kvm.c
|
|
|
902636 |
@@ -67,6 +67,8 @@
|
|
|
016a62 |
* 255 kvm_msr_entry structs */
|
|
|
016a62 |
#define MSR_BUF_SIZE 4096
|
|
|
016a62 |
|
|
|
016a62 |
+static void kvm_init_msrs(X86CPU *cpu);
|
|
|
016a62 |
+
|
|
|
016a62 |
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
|
|
|
016a62 |
KVM_CAP_INFO(SET_TSS_ADDR),
|
|
|
016a62 |
KVM_CAP_INFO(EXT_CPUID),
|
|
|
902636 |
@@ -1842,6 +1844,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
|
|
|
016a62 |
has_msr_tsc_aux = false;
|
|
|
016a62 |
}
|
|
|
016a62 |
|
|
|
016a62 |
+ kvm_init_msrs(cpu);
|
|
|
016a62 |
+
|
|
|
902636 |
r = hyperv_init_vcpu(cpu);
|
|
|
902636 |
if (r) {
|
|
|
902636 |
goto fail;
|
|
|
902636 |
@@ -2660,11 +2664,53 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
|
|
|
016a62 |
VMCS12_MAX_FIELD_INDEX << 1);
|
|
|
016a62 |
}
|
|
|
016a62 |
|
|
|
016a62 |
+static int kvm_buf_set_msrs(X86CPU *cpu)
|
|
|
016a62 |
+{
|
|
|
016a62 |
+ int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
|
|
|
016a62 |
+ if (ret < 0) {
|
|
|
016a62 |
+ return ret;
|
|
|
016a62 |
+ }
|
|
|
016a62 |
+
|
|
|
016a62 |
+ if (ret < cpu->kvm_msr_buf->nmsrs) {
|
|
|
016a62 |
+ struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
|
|
|
016a62 |
+ error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
|
|
|
016a62 |
+ (uint32_t)e->index, (uint64_t)e->data);
|
|
|
016a62 |
+ }
|
|
|
016a62 |
+
|
|
|
016a62 |
+ assert(ret == cpu->kvm_msr_buf->nmsrs);
|
|
|
016a62 |
+ return 0;
|
|
|
016a62 |
+}
|
|
|
016a62 |
+
|
|
|
016a62 |
+static void kvm_init_msrs(X86CPU *cpu)
|
|
|
016a62 |
+{
|
|
|
016a62 |
+ CPUX86State *env = &cpu->env;
|
|
|
016a62 |
+
|
|
|
016a62 |
+ kvm_msr_buf_reset(cpu);
|
|
|
016a62 |
+ if (has_msr_arch_capabs) {
|
|
|
016a62 |
+ kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
|
|
|
016a62 |
+ env->features[FEAT_ARCH_CAPABILITIES]);
|
|
|
016a62 |
+ }
|
|
|
016a62 |
+
|
|
|
016a62 |
+ if (has_msr_core_capabs) {
|
|
|
016a62 |
+ kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
|
|
|
016a62 |
+ env->features[FEAT_CORE_CAPABILITY]);
|
|
|
016a62 |
+ }
|
|
|
016a62 |
+
|
|
|
016a62 |
+ /*
|
|
|
016a62 |
+ * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
|
|
|
016a62 |
+ * all kernels with MSR features should have them.
|
|
|
016a62 |
+ */
|
|
|
016a62 |
+ if (kvm_feature_msrs && cpu_has_vmx(env)) {
|
|
|
016a62 |
+ kvm_msr_entry_add_vmx(cpu, env->features);
|
|
|
016a62 |
+ }
|
|
|
016a62 |
+
|
|
|
016a62 |
+ assert(kvm_buf_set_msrs(cpu) == 0);
|
|
|
016a62 |
+}
|
|
|
016a62 |
+
|
|
|
016a62 |
static int kvm_put_msrs(X86CPU *cpu, int level)
|
|
|
016a62 |
{
|
|
|
016a62 |
CPUX86State *env = &cpu->env;
|
|
|
016a62 |
int i;
|
|
|
016a62 |
- int ret;
|
|
|
016a62 |
|
|
|
016a62 |
kvm_msr_buf_reset(cpu);
|
|
|
016a62 |
|
|
|
902636 |
@@ -2722,17 +2768,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
|
|
|
016a62 |
}
|
|
|
016a62 |
#endif
|
|
|
016a62 |
|
|
|
016a62 |
- /* If host supports feature MSR, write down. */
|
|
|
016a62 |
- if (has_msr_arch_capabs) {
|
|
|
016a62 |
- kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
|
|
|
016a62 |
- env->features[FEAT_ARCH_CAPABILITIES]);
|
|
|
016a62 |
- }
|
|
|
016a62 |
-
|
|
|
016a62 |
- if (has_msr_core_capabs) {
|
|
|
016a62 |
- kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
|
|
|
016a62 |
- env->features[FEAT_CORE_CAPABILITY]);
|
|
|
016a62 |
- }
|
|
|
016a62 |
-
|
|
|
016a62 |
/*
|
|
|
016a62 |
* The following MSRs have side effects on the guest or are too heavy
|
|
|
016a62 |
* for normal writeback. Limit them to reset or full state updates.
|
|
|
902636 |
@@ -2910,14 +2945,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
|
|
|
016a62 |
|
|
|
016a62 |
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
|
|
|
016a62 |
* kvm_put_msr_feature_control. */
|
|
|
016a62 |
-
|
|
|
016a62 |
- /*
|
|
|
016a62 |
- * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
|
|
|
016a62 |
- * all kernels with MSR features should have them.
|
|
|
016a62 |
- */
|
|
|
016a62 |
- if (kvm_feature_msrs && cpu_has_vmx(env)) {
|
|
|
016a62 |
- kvm_msr_entry_add_vmx(cpu, env->features);
|
|
|
016a62 |
- }
|
|
|
016a62 |
}
|
|
|
016a62 |
|
|
|
016a62 |
if (env->mcg_cap) {
|
|
|
902636 |
@@ -2933,19 +2960,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
|
|
|
016a62 |
}
|
|
|
016a62 |
}
|
|
|
016a62 |
|
|
|
016a62 |
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
|
|
|
016a62 |
- if (ret < 0) {
|
|
|
016a62 |
- return ret;
|
|
|
016a62 |
- }
|
|
|
016a62 |
-
|
|
|
016a62 |
- if (ret < cpu->kvm_msr_buf->nmsrs) {
|
|
|
016a62 |
- struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
|
|
|
016a62 |
- error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
|
|
|
016a62 |
- (uint32_t)e->index, (uint64_t)e->data);
|
|
|
016a62 |
- }
|
|
|
016a62 |
-
|
|
|
016a62 |
- assert(ret == cpu->kvm_msr_buf->nmsrs);
|
|
|
016a62 |
- return 0;
|
|
|
016a62 |
+ return kvm_buf_set_msrs(cpu);
|
|
|
016a62 |
}
|
|
|
016a62 |
|
|
|
016a62 |
|
|
|
016a62 |
diff --git a/target/i386/kvm_i386.h b/target/i386/kvm_i386.h
|
|
|
902636 |
index 06fe06b..d98c6f6 100644
|
|
|
016a62 |
--- a/target/i386/kvm_i386.h
|
|
|
016a62 |
+++ b/target/i386/kvm_i386.h
|
|
|
902636 |
@@ -66,4 +66,5 @@ bool kvm_enable_x2apic(void);
|
|
|
016a62 |
bool kvm_has_x2apic_api(void);
|
|
|
902636 |
|
|
|
902636 |
bool kvm_hv_vpindex_settable(void);
|
|
|
016a62 |
+
|
|
|
016a62 |
#endif
|
|
|
016a62 |
--
|
|
|
016a62 |
1.8.3.1
|
|
|
016a62 |
|