From 5567938d29bf8a0ce451e59a8db009c12ab3444c Mon Sep 17 00:00:00 2001

From: Eduardo Habkost <ehabkost@redhat.com>

Date: Thu, 25 Jun 2015 19:31:29 +0200

Subject: [PATCH 09/10] target-i386: add Intel AVX-512 support

Message-id: <1435260689-9556-9-git-send-email-ehabkost@redhat.com>

Patchwork-id: 66506

O-Subject: [RHEL-7.2 qemu-kvm PATCH 8/8] target-i386: add Intel AVX-512 support

Bugzilla: 1233350

RH-Acked-by: Igor Mammedov <imammedo@redhat.com>

RH-Acked-by: Bandan Das <bsd@redhat.com>

RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>

Add AVX512 feature bits, register definition and corresponding

xsave/vmstate support.

Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

(cherry picked from commit 9aecd6f8aef653cea58932f06a2740299dbe5fd3)

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>

Conflicts:

	target-i386/cpu.h

	target-i386/machine.c

---

 target-i386/cpu.c     | 10 ++++--

 target-i386/cpu.h     | 61 ++++++++++++++++++++++++++++++++++++

 target-i386/kvm.c     | 19 +++++++++++

 target-i386/machine.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++

 4 files changed, 175 insertions(+), 2 deletions(-)

diff --git a/target-i386/cpu.c b/target-i386/cpu.c

index fe60c33..06efe17 100644

--- a/target-i386/cpu.c

+++ b/target-i386/cpu.c

@@ -146,8 +146,8 @@ static const char *svm_feature_name[] = {

 static const char *cpuid_7_0_ebx_feature_name[] = {

     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",

     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,

-    NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,

-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

+    "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,

+    NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,

 };

 typedef struct FeatureWordInfo {

@@ -228,6 +228,12 @@ static const ExtSaveArea ext_save_areas[] = {

             .offset = 0x3c0, .size = 0x40  },

     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,

             .offset = 0x400, .size = 0x40  },

+    [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,

+            .offset = 0x440, .size = 0x40 },

+    [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,

+            .offset = 0x480, .size = 0x200 },

+    [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,

+            .offset = 0x680, .size = 0x400 },

 };

 const char *get_register_name_32(unsigned int reg)

diff --git a/target-i386/cpu.h b/target-i386/cpu.h

index fc1e42e..61e9b86 100644

--- a/target-i386/cpu.h

+++ b/target-i386/cpu.h

@@ -390,6 +390,9 @@

 #define XSTATE_YMM                      (1ULL << 2)

 #define XSTATE_BNDREGS                  (1ULL << 3)

 #define XSTATE_BNDCSR                   (1ULL << 4)

+#define XSTATE_OPMASK                   (1ULL << 5)

+#define XSTATE_ZMM_Hi256                (1ULL << 6)

+#define XSTATE_Hi16_ZMM                 (1ULL << 7)

 /* CPUID feature words */

@@ -554,9 +557,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];

 #define CPUID_7_0_EBX_INVPCID  (1U << 10)

 #define CPUID_7_0_EBX_RTM      (1U << 11)

 #define CPUID_7_0_EBX_MPX      (1U << 14)

+#define CPUID_7_0_EBX_AVX512F  (1U << 16) /* AVX-512 Foundation */

 #define CPUID_7_0_EBX_RDSEED   (1U << 18)

 #define CPUID_7_0_EBX_ADX      (1U << 19)

 #define CPUID_7_0_EBX_SMAP     (1U << 20)

+#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */

+#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */

+#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */

 #define CPUID_VENDOR_SZ      12

@@ -697,6 +704,24 @@ typedef union {

 } XMMReg;

 typedef union {

+    uint8_t _b[32];

+    uint16_t _w[16];

+    uint32_t _l[8];

+    uint64_t _q[4];

+    float32 _s[8];

+    float64 _d[4];

+} YMMReg;

+

+typedef union {

+    uint8_t _b[64];

+    uint16_t _w[32];

+    uint32_t _l[16];

+    uint64_t _q[8];

+    float32 _s[16];

+    float64 _d[8];

+} ZMMReg;

+

+typedef union {

     uint8_t _b[8];

     uint16_t _w[4];

     uint32_t _l[2];

@@ -715,6 +740,20 @@ typedef struct BNDCSReg {

 } BNDCSReg;

 #ifdef HOST_WORDS_BIGENDIAN

+#define ZMM_B(n) _b[63 - (n)]

+#define ZMM_W(n) _w[31 - (n)]

+#define ZMM_L(n) _l[15 - (n)]

+#define ZMM_S(n) _s[15 - (n)]

+#define ZMM_Q(n) _q[7 - (n)]

+#define ZMM_D(n) _d[7 - (n)]

+

+#define YMM_B(n) _b[31 - (n)]

+#define YMM_W(n) _w[15 - (n)]

+#define YMM_L(n) _l[7 - (n)]

+#define YMM_S(n) _s[7 - (n)]

+#define YMM_Q(n) _q[3 - (n)]

+#define YMM_D(n) _d[3 - (n)]

+

 #define XMM_B(n) _b[15 - (n)]

 #define XMM_W(n) _w[7 - (n)]

 #define XMM_L(n) _l[3 - (n)]

@@ -727,6 +766,20 @@ typedef struct BNDCSReg {

 #define MMX_L(n) _l[1 - (n)]

 #define MMX_S(n) _s[1 - (n)]

 #else

+#define ZMM_B(n) _b[n]

+#define ZMM_W(n) _w[n]

+#define ZMM_L(n) _l[n]

+#define ZMM_S(n) _s[n]

+#define ZMM_Q(n) _q[n]

+#define ZMM_D(n) _d[n]

+

+#define YMM_B(n) _b[n]

+#define YMM_W(n) _w[n]

+#define YMM_L(n) _l[n]

+#define YMM_S(n) _s[n]

+#define YMM_Q(n) _q[n]

+#define YMM_D(n) _d[n]

+

 #define XMM_B(n) _b[n]

 #define XMM_W(n) _w[n]

 #define XMM_L(n) _l[n]

@@ -765,6 +818,8 @@ typedef struct {

 #define NB_MMU_MODES 3

+#define NB_OPMASK_REGS 8

+

 typedef enum TPRAccess {

     TPR_ACCESS_READ,

     TPR_ACCESS_WRITE,

@@ -826,6 +881,12 @@ typedef struct CPUX86State {

     XMMReg ymmh_regs[CPU_NB_REGS];

+    uint64_t opmask_regs[NB_OPMASK_REGS];

+    YMMReg zmmh_regs[CPU_NB_REGS];

+#ifdef TARGET_X86_64

+    ZMMReg hi16_zmm_regs[CPU_NB_REGS];

+#endif

+

     /* sysenter registers */

     uint32_t sysenter_cs;

     target_ulong sysenter_esp;

diff --git a/target-i386/kvm.c b/target-i386/kvm.c

index bbbbac0..c91bfb8 100644

--- a/target-i386/kvm.c

+++ b/target-i386/kvm.c

@@ -995,6 +995,9 @@ static int kvm_put_fpu(X86CPU *cpu)

 #define XSAVE_YMMH_SPACE  144

 #define XSAVE_BNDREGS     240

 #define XSAVE_BNDCSR      256

+#define XSAVE_OPMASK      272

+#define XSAVE_ZMM_Hi256   288

+#define XSAVE_Hi16_ZMM    416

 static int kvm_put_xsave(X86CPU *cpu)

 {

@@ -1031,6 +1034,14 @@ static int kvm_put_xsave(X86CPU *cpu)

             sizeof env->bnd_regs);

     memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,

             sizeof(env->bndcs_regs));

+    memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,

+            sizeof env->opmask_regs);

+    memcpy(&xsave->region[XSAVE_ZMM_Hi256], env->zmmh_regs,

+            sizeof env->zmmh_regs);

+#ifdef TARGET_X86_64

+    memcpy(&xsave->region[XSAVE_Hi16_ZMM], env->hi16_zmm_regs,

+            sizeof env->hi16_zmm_regs);

+#endif

     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);

     return r;

 }

@@ -1354,6 +1365,14 @@ static int kvm_get_xsave(X86CPU *cpu)

             sizeof env->bnd_regs);

     memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],

             sizeof(env->bndcs_regs));

+    memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],

+            sizeof env->opmask_regs);

+    memcpy(env->zmmh_regs, &xsave->region[XSAVE_ZMM_Hi256],

+            sizeof env->zmmh_regs);

+#ifdef TARGET_X86_64

+    memcpy(env->hi16_zmm_regs, &xsave->region[XSAVE_Hi16_ZMM],

+            sizeof env->hi16_zmm_regs);

+#endif

     return 0;

 }

diff --git a/target-i386/machine.c b/target-i386/machine.c

index b6be606..2c97002 100644

--- a/target-i386/machine.c

+++ b/target-i386/machine.c

@@ -63,6 +63,44 @@ static const VMStateDescription vmstate_ymmh_reg = {

 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \

     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)

+static const VMStateDescription vmstate_zmmh_reg = {

+    .name = "zmmh_reg",

+    .version_id = 1,

+    .minimum_version_id = 1,

+    .fields = (VMStateField[]) {

+        VMSTATE_UINT64(YMM_Q(0), YMMReg),

+        VMSTATE_UINT64(YMM_Q(1), YMMReg),

+        VMSTATE_UINT64(YMM_Q(2), YMMReg),

+        VMSTATE_UINT64(YMM_Q(3), YMMReg),

+        VMSTATE_END_OF_LIST()

+    }

+};

+

+#define VMSTATE_ZMMH_REGS_VARS(_field, _state, _n)                             \

+    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_zmmh_reg, YMMReg)

+

+#ifdef TARGET_X86_64

+static const VMStateDescription vmstate_hi16_zmm_reg = {

+    .name = "hi16_zmm_reg",

+    .version_id = 1,

+    .minimum_version_id = 1,

+    .fields = (VMStateField[]) {

+        VMSTATE_UINT64(ZMM_Q(0), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(1), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(2), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(3), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(4), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(5), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(6), ZMMReg),

+        VMSTATE_UINT64(ZMM_Q(7), ZMMReg),

+        VMSTATE_END_OF_LIST()

+    }

+};

+

+#define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _n)                         \

+    VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_hi16_zmm_reg, ZMMReg)

+#endif

+

 static const VMStateDescription vmstate_bnd_regs = {

     .name = "bnd_regs",

     .version_id = 1,

@@ -620,6 +658,52 @@ static const VMStateDescription vmstate_mpx = {

     }

 };

+static bool avx512_needed(void *opaque)

+{

+    X86CPU *cpu = opaque;

+    CPUX86State *env = &cpu->env;

+    unsigned int i;

+

+    for (i = 0; i < NB_OPMASK_REGS; i++) {

+        if (env->opmask_regs[i]) {

+            return true;

+        }

+    }

+

+    for (i = 0; i < CPU_NB_REGS; i++) {

+#define ENV_ZMMH(reg, field) (env->zmmh_regs[reg].YMM_Q(field))

+        if (ENV_ZMMH(i, 0) || ENV_ZMMH(i, 1) ||

+            ENV_ZMMH(i, 2) || ENV_ZMMH(i, 3)) {

+            return true;

+        }

+#ifdef TARGET_X86_64

+#define ENV_Hi16_ZMM(reg, field) (env->hi16_zmm_regs[reg].ZMM_Q(field))

+        if (ENV_Hi16_ZMM(i, 0) || ENV_Hi16_ZMM(i, 1) ||

+            ENV_Hi16_ZMM(i, 2) || ENV_Hi16_ZMM(i, 3) ||

+            ENV_Hi16_ZMM(i, 4) || ENV_Hi16_ZMM(i, 5) ||

+            ENV_Hi16_ZMM(i, 6) || ENV_Hi16_ZMM(i, 7)) {

+            return true;

+        }

+#endif

+    }

+

+    return false;

+}

+

+static const VMStateDescription vmstate_avx512 = {

+    .name = "cpu/avx512",

+    .version_id = 1,

+    .minimum_version_id = 1,

+    .fields = (VMStateField[]) {

+        VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),

+        VMSTATE_ZMMH_REGS_VARS(env.zmmh_regs, X86CPU, CPU_NB_REGS),

+#ifdef TARGET_X86_64

+        VMSTATE_Hi16_ZMM_REGS_VARS(env.hi16_zmm_regs, X86CPU, CPU_NB_REGS),

+#endif

+        VMSTATE_END_OF_LIST()

+    }

+};

+

 const VMStateDescription vmstate_x86_cpu = {

     .name = "cpu",

     .version_id = 12,

@@ -763,6 +847,9 @@ const VMStateDescription vmstate_x86_cpu = {

         } , {

             .vmsd = &vmstate_mpx,

             .needed = mpx_needed,

+        }, {

+            .vmsd = &vmstate_avx512,

+            .needed = avx512_needed,

         } , {

             /* empty */

         }

-- 

1.8.3.1