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From 0a8e2990b83c805fc6cc2421950a938caa9ba8a5 Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Wed, 3 Apr 2019 15:54:29 +0100
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Subject: [PATCH 05/10] i386: Add new CPU model Icelake-{Server, Client}
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RH-Author: plai@redhat.com
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Message-id: <1554306874-28796-6-git-send-email-plai@redhat.com>
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Patchwork-id: 85383
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O-Subject: [RHEL8.1 qemu-kvm PATCH resend 05/10] i386: Add new CPU model Icelake-{Server, Client}
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Bugzilla: 1561761
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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From: Robert Hoo <robert.hu@linux.intel.com>
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New CPU models mostly inherit features from ancestor Skylake, while addin new
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features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD,
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AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG),
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Intel PT and 5-level paging (Server only). As well as
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IA32_PRED_CMD, SSBD support for speculative execution
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side channel mitigations.
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Note:
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For 5-level paging, Guest physical address width can be configured, with
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parameter "phys-bits". Unless explicitly specified, we still use its default
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value, even for Icelake-Server cpu model.
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At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR
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actually presents more than 1 'feature', maintainers are considering expanding current
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features presentation of only CPUIDs to MSR bits; 2) a reasonable default value
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for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully
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beyond Icelake CPU model itself but fundamental. So split these work apart
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and do it later.
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https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
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https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
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Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
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Message-Id: <1530781798-183214-6-git-send-email-robert.hu@linux.intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit 8a11c62da9146dd89aee98947e6bd831e65a970d)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Resovled Conflicts:
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target/i386/cpu.c
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 115 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 8b9a9f6..d86b744 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -2414,6 +2414,121 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "Intel Xeon Processor (Skylake, IBRS)",
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},
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{
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+ .name = "Icelake-Client",
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+ .level = 0xd,
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+ .vendor = CPUID_VENDOR_INTEL,
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+ .family = 6,
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+ .model = 126,
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+ .stepping = 0,
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+ .features[FEAT_1_EDX] =
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+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+ CPUID_DE | CPUID_FP87,
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+ .features[FEAT_1_ECX] =
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+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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+ .features[FEAT_8000_0001_EDX] =
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+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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+ CPUID_EXT2_SYSCALL,
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+ .features[FEAT_8000_0001_ECX] =
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+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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+ .features[FEAT_8000_0008_EBX] =
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+ CPUID_8000_0008_EBX_WBNOINVD,
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+ .features[FEAT_7_0_EBX] =
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+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,
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+ .features[FEAT_7_0_ECX] =
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+ CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
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+ CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
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+ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
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+ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
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+ CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
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+ .features[FEAT_7_0_EDX] =
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+ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
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+ /* Missing: XSAVES (not supported by some Linux versions,
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+ * including v4.1 to v4.12).
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+ * KVM doesn't yet expose any XSAVES state save component,
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+ * and the only one defined in Skylake (processor tracing)
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+ * probably will block migration anyway.
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+ */
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+ .features[FEAT_XSAVE] =
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+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+ CPUID_XSAVE_XGETBV1,
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+ .features[FEAT_6_EAX] =
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+ CPUID_6_EAX_ARAT,
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+ .xlevel = 0x80000008,
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+ .model_id = "Intel Core Processor (Icelake)",
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+ },
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+ {
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+ .name = "Icelake-Server",
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+ .level = 0xd,
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+ .vendor = CPUID_VENDOR_INTEL,
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+ .family = 6,
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+ .model = 134,
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+ .stepping = 0,
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+ .features[FEAT_1_EDX] =
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+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+ CPUID_DE | CPUID_FP87,
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+ .features[FEAT_1_ECX] =
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+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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+ .features[FEAT_8000_0001_EDX] =
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+ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
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+ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
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+ .features[FEAT_8000_0001_ECX] =
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+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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+ .features[FEAT_8000_0008_EBX] =
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+ CPUID_8000_0008_EBX_WBNOINVD,
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+ .features[FEAT_7_0_EBX] =
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+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
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+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
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+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
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+ CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
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+ CPUID_7_0_EBX_INTEL_PT,
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+ .features[FEAT_7_0_ECX] =
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+ CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
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+ CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
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+ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
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+ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
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+ CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
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+ .features[FEAT_7_0_EDX] =
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+ CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |
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+ CPUID_7_0_EDX_SPEC_CTRL_SSBD,
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+ /* Missing: XSAVES (not supported by some Linux versions,
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+ * including v4.1 to v4.12).
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+ * KVM doesn't yet expose any XSAVES state save component,
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+ * and the only one defined in Skylake (processor tracing)
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+ * probably will block migration anyway.
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+ */
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+ .features[FEAT_XSAVE] =
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+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+ CPUID_XSAVE_XGETBV1,
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+ .features[FEAT_6_EAX] =
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+ CPUID_6_EAX_ARAT,
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+ .xlevel = 0x80000008,
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+ .model_id = "Intel Xeon Processor (Icelake)",
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+ },
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+ {
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.name = "Opteron_G1",
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.level = 5,
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.vendor = CPUID_VENDOR_AMD,
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--
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1.8.3.1
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